; -------------------------------------------------------------------------------- ; @Title: NUC029 On-Chip Peripherals ; @Props: Released ; @Author: NEJ ; @Changelog: 2024-01-16 NEJ ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: Generated (TRACE32, build: 165992.), based on: ; NUC029AE_v1_fixed.svd (Ver. 1.0), NUC029AN_v1_fixed.svd (Ver. 1.0), ; NUC029DE_v1_fixed.svd (Ver. 1.0), NUC029EE_v1_fixed.svd (Ver. 1.0), ; NUC029GE_v1_fixed.svd (Ver. 1.0) ; @Core: Cortex-M0 ; @Chip: NUC029FAE, NUC029KGE, NUC029LAN, NUC029LDE, ; NUC029LEE, NUC029LGE, NUC029NAN, NUC029SDE, ; NUC029SEE, NUC029SGE, NUC029TAN, NUC029ZAN ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pernuc029.per 17349 2024-01-19 09:59:04Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end sif (cpuis("NUC029?AE")||cpuis("NUC029?GE")) base ad:0x400D0000 elif (cpuis("NUC029?AN")) base ad:0x0 endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?GE")) tree "ACMP (Analog Comparator Contoller)" sif (cpuis("NUC029?AE")) group.long 0x0++0xF line.long 0x0 "ACMP_CR0,Analog Comparator 0 Control Register" bitfld.long 0x0 29.--30. "CPP0SEL,Analog Comparator 0 Positive Input Selection" "0: CPP0 is from P1.5 pin,1: CPP0 is from P1.0 pin,?,?" bitfld.long 0x0 9. "FALLING,Analog Comparator 0 Falling Edge Trigger Enable Control.Note: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 falling edge trigger PWM or..,1: Analog comparator 0 falling edge trigger Disabled" newline bitfld.long 0x0 8. "RISING,Analog Comparator 0 Rising Edge Trigger Enable Control.Note: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 rising edge trigger PWM or..,1: Analog comparator 0 rising edge trigger Disabled" bitfld.long 0x0 4. "NEGSEL,Analog Comparator 0 Negative Input Selection" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.." newline bitfld.long 0x0 2. "HYSEN,Analog Comparator 0 Hysteresis Enable Control" "0: Hysteresis function Disabled,1: Hysteresis function Enabled" bitfld.long 0x0 1. "ACMPIE,Analog Comparator 0 Interrupt Enable Control" "0: Interrupt function Disabled,1: Interrupt function Enabled" newline bitfld.long 0x0 0. "ACMPEN,Analog Comparator 0 Enable Control.Note: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 0 Disabled,1: Analog Comparator 1 Enabled" line.long 0x4 "ACMP_CR1,Analog Comparator 1 Control Register" bitfld.long 0x4 29.--30. "CPP1SEL,Analog Comparator 1 Positive Input Selection" "0: CPP1 is from P3.1 pin,1: CPP1 is from P3.2 pin,?,?" bitfld.long 0x4 9. "FALLING,Analog Comparator 1 Falling Edge Trigger Enable Control.Note: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 falling edge trigger PWM or..,1: Analog comparator 1 falling edge trigger Disabled" newline bitfld.long 0x4 8. "RISING,Analog Comparator 1 Rising Edge Trigger Enable Control.Note: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 rising edge trigger PWM or..,1: Analog comparator 1 rising edge trigger Disabled" bitfld.long 0x4 4. "NEGSEL,Analog Comparator 1 Negative Input Selection" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.." newline bitfld.long 0x4 2. "HYSEN,Analog Comparator 1 Hysteresis Enable Control" "0: Hysteresis function Disabled,1: Hysteresis function Enabled" bitfld.long 0x4 1. "ACMPIE,Analog Comparator 1 Interrupt Enable Control" "0: Interrupt function Disabled,1: Interrupt function Enabled" newline bitfld.long 0x4 0. "ACMPEN,Analog Comparator 1 Enable Control.Note: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 1 Disabled,1: Analog Comparator 1 Enabled" line.long 0x8 "ACMP_SR01,Analog Comparator 0/1 Status Register" bitfld.long 0x8 3. "ACMPO1,Analog Comparator 1 Output" "0: Analog comparator 1 outputs 0,1: Analog comparator 1 outputs 1" bitfld.long 0x8 2. "ACMPO0,Analog Comparator 0 Output" "0: Analog comparator 0 outputs 0,1: Analog comparator 0 outputs 1" newline bitfld.long 0x8 1. "ACMPF1,Analog Comparator 1 Flag.Note: Software can write 1 to clear this bit to 0." "0: Analog comparator 1 output does not change,1: Analog comparator 1 output changed" bitfld.long 0x8 0. "ACMPF0,Analog Comparator 0 Flag.Note: Software can write 1 to clear this bit to 0." "0: Analog comparator 0 output does not change,1: Analog comparator 0 output changed" line.long 0xC "ACMP_RVCR,Analog Comparator Reference Voltage Control Register" bitfld.long 0xC 7. "OUT_SEL,CRV Module Output Selection" "0: Band-gap voltage,1: Internal comparator reference voltage" hexmask.long.byte 0xC 0.--3. 1. "CRVS,Comparator Reference Voltage Setting" endif sif (cpuis("NUC029?AN")) tree "ACMPA" base ad:0x400D0000 group.long 0x0++0xB line.long 0x0 "CMPCR0,Comparator Control Register 0" bitfld.long 0x0 4. "CMPCN,Comparator negative input selection" "0: The ACMPx_N x=0 1 2 or 3 is selected as the..,1: The internal band-gap reference voltage is.." bitfld.long 0x0 2. "CMP_HYSEN,Comparator Hysteresis Enable" "0: Hysteresis function Disabled (Default),1: Hysteresis function Enabled. The typical range.." newline bitfld.long 0x0 1. "CMPIE,Comparator Interrupt Enable" "0: Interrupt function Disabled,1: Interrupt function Enabled" bitfld.long 0x0 0. "CMPEN,Comparator Enable.Comparator output needs to wait 2 us stable time after CMPEN is set." "0: Disabled,1: Enabled" line.long 0x4 "CMPCR1,Comparator Control Register 1" bitfld.long 0x4 4. "CMPCN,Comparator negative input selection" "0: The ACMPx_N x=0 1 2 or 3 is selected as the..,1: The internal band-gap reference voltage is.." bitfld.long 0x4 2. "CMP_HYSEN,Comparator Hysteresis Enable" "0: Hysteresis function Disabled (Default),1: Hysteresis function Enabled. The typical range.." newline bitfld.long 0x4 1. "CMPIE,Comparator Interrupt Enable" "0: Interrupt function Disabled,1: Interrupt function Enabled" bitfld.long 0x4 0. "CMPEN,Comparator Enable.Comparator output needs to wait 2 us stable time after CMPEN is set." "0: Disabled,1: Enabled" line.long 0x8 "CMPSR,Comparator Status Register" tree.end tree "ACMPB" base ad:0x401D0000 group.long 0x0++0xB line.long 0x0 "CMPCR0,Comparator Control Register 0" bitfld.long 0x0 4. "CMPCN,Comparator negative input selection" "0: The ACMPx_N x=0 1 2 or 3 is selected as the..,1: The internal band-gap reference voltage is.." bitfld.long 0x0 2. "CMP_HYSEN,Comparator Hysteresis Enable" "0: Hysteresis function Disabled (Default),1: Hysteresis function Enabled. The typical range.." newline bitfld.long 0x0 1. "CMPIE,Comparator Interrupt Enable" "0: Interrupt function Disabled,1: Interrupt function Enabled" bitfld.long 0x0 0. "CMPEN,Comparator Enable.Comparator output needs to wait 2 us stable time after CMPEN is set." "0: Disabled,1: Enabled" line.long 0x4 "CMPCR1,Comparator Control Register 1" bitfld.long 0x4 4. "CMPCN,Comparator negative input selection" "0: The ACMPx_N x=0 1 2 or 3 is selected as the..,1: The internal band-gap reference voltage is.." bitfld.long 0x4 2. "CMP_HYSEN,Comparator Hysteresis Enable" "0: Hysteresis function Disabled (Default),1: Hysteresis function Enabled. The typical range.." newline bitfld.long 0x4 1. "CMPIE,Comparator Interrupt Enable" "0: Interrupt function Disabled,1: Interrupt function Enabled" bitfld.long 0x4 0. "CMPEN,Comparator Enable.Comparator output needs to wait 2 us stable time after CMPEN is set." "0: Disabled,1: Enabled" line.long 0x8 "CMPSR,Comparator Status Register" tree.end endif sif (cpuis("NUC029?GE")) group.long 0x0++0xF line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register" bitfld.long 0x0 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected" bitfld.long 0x0 17. "WLATEN,Window Latch Function Enable Bit" "0: Window Latch Function Disabled,1: Window Latch Function Enabled" newline bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,?,?,?,?,?,?" newline bitfld.long 0x0 12. "OUTSEL,Comparator Output Selection" "0: Comparator 0 output to ACMP0_O pin is unfiltered..,1: Comparator 0 output to ACMP0_O pin is from.." bitfld.long 0x0 8.--9. "INTPOL,Interrupt Condition Polarity Selection.ACMPIF0 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?" newline bitfld.long 0x0 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,?,?" bitfld.long 0x0 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),?,?" newline bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled" bitfld.long 0x0 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 0 hysteresis Disabled,1: Comparator 0 hysteresis Enabled" newline bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled. If WKEN.." bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled" line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register" bitfld.long 0x4 18. "WCMPSEL,Window Compare Mode Selection" "0: Window compare mode Disabled,1: Window compare mode Selected" bitfld.long 0x4 17. "WLATEN,Window Latch Function Enable Bit" "0: Window Latch function Disabled,1: Window Latch function Enabled" newline bitfld.long 0x4 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x4 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,?,?,?,?,?,?" newline bitfld.long 0x4 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is unfiltered..,1: Comparator 1 output to ACMP1_O pin is from.." bitfld.long 0x4 8.--9. "INTPOL,Interrupt Condition Polarity Selection.ACMPIF1 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?" newline bitfld.long 0x4 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,?,?" bitfld.long 0x4 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV),?,?" newline bitfld.long 0x4 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled" bitfld.long 0x4 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 1 hysteresis Disabled,1: Comparator 1 hysteresis Enabled" newline bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled. If WKEN.." bitfld.long 0x4 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled" line.long 0x8 "ACMP_STATUS,Analog Comparator Status Register" bitfld.long 0x8 16. "ACMPWO,Comparator Window Output.This bit shows the output status of window compare mode" "0: The positvie input voltage is outside the window,1: The positive input voltage is in the window" bitfld.long 0x8 13. "ACMPS1,Comparator 1 Status.Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1" newline bitfld.long 0x8 12. "ACMPS0,Comparator 0 Status .Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1" bitfld.long 0x8 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag.This bit will be set to 1 when ACMP1 wake-up interrupt event occurs..Note: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred" newline bitfld.long 0x8 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag.This bit will be set to 1 when ACMP0 wake-up interrupt event occurs..Note: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred" bitfld.long 0x8 5. "ACMPO1,Comparator 1 Output.Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1" newline bitfld.long 0x8 4. "ACMPO0,Comparator 0 Output.Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1" bitfld.long 0x8 1. "ACMPIF1,Comparator 1 Interrupt Flag.This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1..Note: Write 1 to clear.." "0,1" newline bitfld.long 0x8 0. "ACMPIF0,Comparator 0 Interrupt Flag.This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1..Note: Write 1 to clear.." "0,1" line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register" bitfld.long 0xC 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV voltage source,1: The reference voltage defined by SYS_VREFCTL.." hexmask.long.byte 0xC 0.--3. 1. "CRVCTL,Comparator Reference Voltage Setting" endif tree.end endif tree "ADC (Analog-to-Digital Converter)" base ad:0x400E0000 sif (cpuis("NUC029?AE")) rgroup.long 0x0++0x3 line.long 0x0 "ADDR,ADC Data Register" bitfld.long 0x0 17. "VALID,Valid Flag.This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read." "0: Data in RSLT (ADDR[9:0]) bits not valid,1: Data in RSLT (ADDR[9:0]) bits valid" bitfld.long 0x0 16. "OVERRUN,Over Run Flag.If converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read." "0: Data in RSLT (ADDR[9:0])is recent conversion..,1: Data in RSLT (ADDR[9:0])overwrote" newline hexmask.long.word 0x0 0.--9. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." group.long 0x48++0x3 line.long 0x0 "ADSAMP,ADC Sampling Time Counter Register" hexmask.long.byte 0x0 0.--3. 1. "ADSAMPCNT,ADC Sampling Counter.If the ADC input is unstable user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clock. The additional clock number will be inserted to lengthen.." endif sif (cpuis("NUC029?AN")) rgroup.long 0x0++0x1F line.long 0x0 "ADDR0,ADC Data Register 0" bitfld.long 0x0 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x0 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x4 "ADDR1,ADC Data Register 1" bitfld.long 0x4 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x4 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x8 "ADDR2,ADC Data Register 2" bitfld.long 0x8 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x8 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0xC "ADDR3,ADC Data Register 3" bitfld.long 0xC 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0xC 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x10 "ADDR4,ADC Data Register 4" bitfld.long 0x10 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x10 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x14 "ADDR5,ADC Data Register 5" bitfld.long 0x14 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x14 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x18 "ADDR6,ADC Data Register 6" bitfld.long 0x18 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x18 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x1C "ADDR7,ADC Data Register 7" bitfld.long 0x1C 17. "VALID,Valid Flag .This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x1C 16. "OVERRUN,Over Run Flag (Read Only).If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT is recent conversion result,1: Data in RSLT is overwrite" newline hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." endif sif (cpuis("NUC029?DE")) rgroup.long 0x0++0x1F line.long 0x0 "ADDR0,ADC Data Register 0" bitfld.long 0x0 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x0 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0x4 "ADDR1,ADC Data Register 1" bitfld.long 0x4 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x4 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0x8 "ADDR2,ADC Data Register 2" bitfld.long 0x8 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x8 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0xC "ADDR3,ADC Data Register 3" bitfld.long 0xC 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0xC 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0x10 "ADDR4,ADC Data Register 4" bitfld.long 0x10 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x10 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0x14 "ADDR5,ADC Data Register 5" bitfld.long 0x14 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x14 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0x18 "ADDR6,ADC Data Register 6" bitfld.long 0x18 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x18 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." line.long 0x1C "ADDR7,ADC Data Register 7" bitfld.long 0x1C 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit." "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x1C 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~7) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~7) is overwritten" newline hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC.." endif sif (cpuis("NUC029?EE")) rgroup.long 0x0++0x1F line.long 0x0 "ADDR0,ADC Data Register 0" bitfld.long 0x0 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x0 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x4 "ADDR1,ADC Data Register 1" bitfld.long 0x4 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x4 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x8 "ADDR2,ADC Data Register 2" bitfld.long 0x8 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x8 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0xC "ADDR3,ADC Data Register 3" bitfld.long 0xC 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0xC 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x10 "ADDR4,ADC Data Register 4" bitfld.long 0x10 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x10 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x14 "ADDR5,ADC Data Register 5" bitfld.long 0x14 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x14 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x18 "ADDR6,ADC Data Register 6" bitfld.long 0x18 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x18 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x1C "ADDR7,ADC Data Register 7" bitfld.long 0x1C 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x1C 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." rgroup.long 0x40++0x3 line.long 0x0 "ADPDMA,ADC PDMA Current Transfer Data Register" hexmask.long.tbyte 0x0 0.--17. 1. "AD_PDMA,ADC PDMA Current Transfer Data Register.When PDMA transferring read this register can monitor current PDMA transfer data..Current PDMA transfer data is the content of ADDR0 ~ ADDR11..This is a read only register." endif sif (cpuis("NUC029?GE")) rgroup.long 0x0++0x4F line.long 0x0 "ADC_ADDR0,ADC Data Register 0" bitfld.long 0x0 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x4 "ADC_ADDR1,ADC Data Register 1" bitfld.long 0x4 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x8 "ADC_ADDR2,ADC Data Register 2" bitfld.long 0x8 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0xC "ADC_ADDR3,ADC Data Register 3" bitfld.long 0xC 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0xC 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x10 "ADC_ADDR4,ADC Data Register 4" bitfld.long 0x10 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x14 "ADC_ADDR5,ADC Data Register 5" bitfld.long 0x14 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x14 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x18 "ADC_ADDR6,ADC Data Register 6" bitfld.long 0x18 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x18 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x1C "ADC_ADDR7,ADC Data Register 7" bitfld.long 0x1C 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x1C 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x20 "ADC_ADDR8,ADC Data Register 8" bitfld.long 0x20 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x20 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x20 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x24 "ADC_ADDR9,ADC Data Register 9" bitfld.long 0x24 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x24 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x24 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x28 "ADC_ADDR10,ADC Data Register 10" bitfld.long 0x28 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x28 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x28 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x2C "ADC_ADDR11,ADC Data Register 11" bitfld.long 0x2C 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x2C 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x2C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x30 "ADC_ADDR12,ADC Data Register 12" bitfld.long 0x30 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x30 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x30 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x34 "ADC_ADDR13,ADC Data Register 13" bitfld.long 0x34 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x34 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x34 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x38 "ADC_ADDR14,ADC Data Register 14" bitfld.long 0x38 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x38 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x38 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x3C "ADC_ADDR15,ADC Data Register 15" bitfld.long 0x3C 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x3C 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x3C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x40 "ADC_ADDR16,ADC Data Register 16" bitfld.long 0x40 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x40 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x40 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x44 "ADC_ADDR17,ADC Data Register 17" bitfld.long 0x44 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x44 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x44 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x48 "ADC_ADDR18,ADC Data Register 18" bitfld.long 0x48 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x48 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x48 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x4C "ADC_ADDR19,ADC Data Register 19" bitfld.long 0x4C 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x4C 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x4C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) group.long 0x20++0x13 line.long 0x0 "ADCR,ADC Control Register" sif (cpuis("NUC029?AN")) bitfld.long 0x0 31. "DMOF,A/D differential input Mode Output Format" "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.." endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 31. "DMOF,A/D Differential Input Mode Output Format." "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.." newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 31. "DMOF,A/D Differential Input Mode Output Format" "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.." endif bitfld.long 0x0 11. "ADST,A/D Conversion Start.ADST bit can be set to 1 from three sources: software or PWM trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically after conversion complete." "0: Conversion stopped and A/D converter entered..,1: Conversion start" newline sif (cpuis("NUC029?AN")) bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Enable" "0: single-end analog input mode,1: differential analog input mode" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Control." "0: Single-end analog input mode,1: Differential analog input mode" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Control" "0: Single-end analog input mode,1: Differential analog input mode" bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable Bit" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR 0~11 Enabled" newline endif bitfld.long 0x0 8. "TRGEN,External Trigger Enable Control.Enable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled the ADST bit can be set to 1 by the selected hardware trigger source." "0: External trigger Disabled,1: External trigger Enabled" newline sif (cpuis("NUC029?AE")) bitfld.long 0x0 6. "TRGCOND,External Trigger Condition.This bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger." "0: Falling edge,1: Raising edge" endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition.These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger." "0: Low level,1: High level,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition.These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.." "0: Low level,1: High level,?,?" endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition.These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger." "0: Low level,1: High level,?,?" endif bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source.Note: Software should disable TRGEN and ADST before change TRGS." "0: A/D conversion is started by external STADC pin,?,?,?" newline sif (cpuis("NUC029?AN")) bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode.When changing the operation mode software should disable ADST bit firstly..Note: In Burst Mode the A/D result data always at Data Register 0." "0: Single conversion,1: Burst conversion,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode.When changing the operation mode software should disable ADST bit (ADCR[11]) firstly." "0: Single conversion,1: Reserved,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode.When changing the operation mode software should disable ADST bit (ADCR[11]) firstly." "0: Single conversion,1: Reserved.,?,?" endif bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Control.A/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" newline bitfld.long 0x0 0. "ADEN,A/D Converter Enable Control.Note: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D Converter Disabled,1: A/D Converter Enabled" line.long 0x4 "ADCHER,ADC Channel Enable Control Register" sif (cpuis("NUC029?EE")) hexmask.long.byte 0x4 10.--13. 1. "CHEN1,Analog Input Channel Enable Bit 1.Set CHEN[14:10] to enable the corresponding analog input channel 11 ~ 8. If DIFFEN bit (ADCR[10]) is set to 1 only the even number channels need to be enabled." bitfld.long 0x4 8.--9. "PRESEL,Analog Input Channel 7 Selection" "0: External analog input,1: Internal band-gap voltage,?,?" newline hexmask.long.byte 0x4 0.--7. 1. "CHEN,Analog Input Channel Enable Bit.Set CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit (ADCR[10]) is set to 1 only the even number channels need to be enabled." endif sif (cpuis("NUC029?AE")) bitfld.long 0x4 8. "PRESEL,Analog Input Channel 7 Selection.Note: When software selects the band-gap voltage as the analog input source of ADC channel 7 the ADC clock rate needs to be limited to lower than 300 kHz." "0: External analog input,1: Internal band-gap voltage (VBG)" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 8.--9. "PRESEL,Analog Input Channel 7 select.Note:.When software select the band-gap voltage as the analog input source of ADC channel 7 ADC clock rate needs to be limited to lower than 300 KHz." "0: External Analog Input,1: Internal Bandgap voltage,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 8.--9. "PRESEL,Analog Input Channel 7 Selection." "0: External analog input,1: Internal band-gap voltage,?,?" newline hexmask.long.byte 0x4 0.--7. 1. "CHEN,Analog Input Channel Enable Bit.Set CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit (ADCR[10]) is set to 1 only the even number channels need to be enabled.." endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable Control" "0: Channel 7 Disabled,1: Channel 7 Enabled" newline bitfld.long 0x4 6. "CHEN6,Analog Input Channel 6 Enable Control" "0: Channel 6 Disabled,1: Channel 6 Enabled" bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable Control" "0: Channel 5 Disabled,1: Channel 5 Enabled" newline bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable Control" "0: Channel 4 Disabled,1: Channel 4 Enabled" bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable Control" "0: Channel 3 Disabled,1: Channel 3 Enabled" newline bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable Control" "0: Channel 2 Disabled,1: Channel 2 Enabled" bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable Control" "0: Channel 1 Disabled,1: Channel 1 Enabled" newline bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable Control.Note: If software enables more than one channel the channel with the smallest number will be selected and the other enabled channels will be ignored." "0: Channel 0 Disabled,1: Channel 0 Enabled" endif line.long 0x8 "ADCMPR0,ADC Compare Register 0" sif (cpuis("NUC029?AE")) hexmask.long.word 0x8 16.--25. 1. "CMPD,Comparison Data.The 10-bit data is used to compare with conversion result of specified channel." endif sif (cpuis("NUC029?AN")) hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data.The 12 bits data is used to compare with conversion result of specified channel. .When DMOF bit is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format..When.." newline endif sif (cpuis("NUC029?DE")) hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data.The 12-bit data is used to compare with conversion result of specified channel..When DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned.." newline endif sif (cpuis("NUC029?EE")) hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data.The 12-bit data is used to compare with conversion result of specified channel..When DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned.." newline endif hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count.When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx.." newline sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")) bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x8 3.--6. 1. "CMPCH,Compare Channel Selection" newline endif bitfld.long 0x8 2. "CMPCOND,Compare Condition.Note: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.." newline bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Control.If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0x8 0. "CMPEN,Compare Enable Control.Set 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register." "0: Compare function Disabled,1: Compare function Enabled" line.long 0xC "ADCMPR1,ADC Compare Register 1" sif (cpuis("NUC029?AE")) hexmask.long.word 0xC 16.--25. 1. "CMPD,Comparison Data.The 10-bit data is used to compare with conversion result of specified channel." newline endif sif (cpuis("NUC029?AN")) hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data.The 12 bits data is used to compare with conversion result of specified channel. .When DMOF bit is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format..When.." newline endif sif (cpuis("NUC029?DE")) hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data.The 12-bit data is used to compare with conversion result of specified channel..When DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned.." endif sif (cpuis("NUC029?EE")) hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data.The 12-bit data is used to compare with conversion result of specified channel..When DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned.." newline endif hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count.When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx.." newline sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")) bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0xC 3.--6. 1. "CMPCH,Compare Channel Selection" newline endif bitfld.long 0xC 2. "CMPCOND,Compare Condition.Note: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.." newline bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Control.If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0xC 0. "CMPEN,Compare Enable Control.Set 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register." "0: Compare function Disabled,1: Compare function Enabled" line.long 0x10 "ADSR,ADC Status Register" sif (cpuis("NUC029?EE")) hexmask.long.byte 0x10 28.--31. 1. "OVERRUN1,Overrun Flag.It is a mirror to OVERRUN bit (ADDR8~11[16])..It is read only." hexmask.long.byte 0x10 24.--27. 1. "VALID1,Data Valid Flag.It is a mirror of VALID bit (ADDR8~11[17])..It is read only." newline hexmask.long.byte 0x10 16.--23. 1. "OVERRUN0,Overrun Flag.It is a mirror to OVERRUN bit (ADDR0~7[16])..It is read only." hexmask.long.byte 0x10 8.--15. 1. "VALID0,Data Valid Flag.It is a mirror of VALID bit (ADDR0~7[17])..It is read only." newline hexmask.long.byte 0x10 4.--7. 1. "CHANNEL,Current Conversion Channel.It is read only." bitfld.long 0x10 3. "BUSY,BUSY/IDLE.This bit is mirror of as ADST bit (ADCR[11])..It is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline endif sif (cpuis("NUC029?AE")) rbitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only).It is a mirror to OVERRUN (ADSR[16]) bit in ADDR register." "0,1" rbitfld.long 0x10 8. "VALID,Data Valid Flag (Read Only).It is a mirror of VALID (ADDR[17]) bit in ADDR register." "0,1" newline rbitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 3. "BUSY,BUSY/IDLE (Read Only).This bit is mirror of as ADST bit in ADCR" "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x10 16.--23. 1. "OVERRUN,Over Run flag (Read Only).It is a mirror to OVERRUN bit in ADDRx.When ADC in Burst Mode and the FIFO is overrun OVERRUN[7:0] will all set to 1." hexmask.long.byte 0x10 8.--15. 1. "VALID,Data Valid flag (Read Only).It is a mirror of VALID bit in ADDRx.When ADC in Burst Mode and the FIFO is valid VALID[7:0] will all set to 1." newline endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x10 16.--23. 1. "OVERRUN,Overrun Flag.It is a mirror to OVERRUN bit (ADDR0~7[16])..It is read only." hexmask.long.byte 0x10 8.--15. 1. "VALID,Data Valid Flag.It is a mirror of VALID bit (ADDR0~7[17])..It is read only." newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel.It is read only." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "BUSY,BUSY/IDLE.This bit is mirror of as ADST bit in ADCR..It is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel.It is read only." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "BUSY,BUSY/IDLE.This bit is mirror of as ADST bit (ADCR[11])..It is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline endif bitfld.long 0x10 2. "CMPF1,Compare Flag 1.When the selected channel A/D conversion result meets the setting condition in ADCMPR1 this bit is set to 1. Software can write 1 to clear this bit to 0." "0: Conversion result in ADDR does not meet the..,1: Conversion result in ADDR meets the ADCMPR1.." bitfld.long 0x10 1. "CMPF0,Compare Flag 0.When the selected channel A/D conversion result meets the setting condition in ADCMPR0 this bit is set to 1. Software can write 1 to clear this bit to 0." "0: Conversion result in ADDR does not meet the..,1: Conversion result in ADDR meets the ADCMPR0.." newline bitfld.long 0x10 0. "ADF,A/D Conversion End Flag.A status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends..Software can write 1 to clear this bit to 0." "0,1" endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) group.long 0x44++0x3 line.long 0x0 "ADTDCR,ADC Trigger Delay Control Register" hexmask.long.byte 0x0 0.--7. 1. "PTDT,PWM Trigger Delay Timer.Set this field will delay ADC start conversion time after PWM trigger..PWM trigger delay time is (4 * PTDT) * system clock." endif sif (cpuis("NUC029?EE")) rgroup.long 0x50++0xF line.long 0x0 "ADDR8,ADC Data Register 8" bitfld.long 0x0 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x0 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x4 "ADDR9,ADC Data Register 9" bitfld.long 0x4 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x4 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0x8 "ADDR10,ADC Data Register 10" bitfld.long 0x8 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0x8 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." line.long 0xC "ADDR11,ADC Data Register 11" bitfld.long 0xC 17. "VALID,Valid Flag.This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read..This is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not valid,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid" bitfld.long 0xC 16. "OVERRUN,Overrun Flag.If converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read..This is a read.." "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is overwritten" newline hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result.This field contains conversion result of ADC." endif sif (cpuis("NUC029?GE")) rgroup.long 0x74++0xB line.long 0x0 "ADC_ADDR29,ADC Data Register 29" bitfld.long 0x0 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x4 "ADC_ADDR30,ADC Data Register 30" bitfld.long 0x4 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." line.long 0x8 "ADC_ADDR31,ADC Data Register 31" bitfld.long 0x8 17. "VALID,Valid Flag (Read Only).This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only).If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only).This field contains conversion result of ADC." group.long 0x80++0x13 line.long 0x0 "ADC_ADCR,ADC Control Register" bitfld.long 0x0 31. "DMOF,Differential Input Mode Output Format.If user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)." "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.." bitfld.long 0x0 16.--18. "SMPTSEL,ADC Internal Sampling Time Selection" "0: 4 ADC clock for sampling; 16 ADC clock for..,1: 5 ADC clock for sampling; 17 ADC clock for..,?,?,?,?,?,?" newline bitfld.long 0x0 11. "ADST,A/D Conversion Start.ADST bit can be set to 1 from four sources: software external pin STADC PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In.." "0: Conversion stops and A/D converter enters idle..,1: Conversion starts" bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Control.Note1: differential input paired channel 3 5 8 cannot be used.Note2: In Differential Input mode only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion.." "0: Single-end analog input mode,1: Differential analog input mode" newline bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable Bit.When A/D conversion is completed the converted data is loaded into ADDR0~19 ADDR29~ADDR31. Software can enable this bit to generate a PDMA data transfer request." "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR0~19 ADDR29~ADDR31.." bitfld.long 0x0 8. "TRGEN,External Trigger Enable Bit.Enable or disable triggering of A/D conversion by external STADC pin PWM trigger and Timer trigger. If external trigger is enabled the ADST bit can be set to 1 by the selected hardware trigger source..Note: The ADC.." "0: External trigger Disabled,1: External trigger Enabled" newline bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition.These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger." "0: Low level,1: High level,?,?" bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source.Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits." "0: A/D conversion is started by external STADC pin,1: Timer0 ~ Timer3 overflow pulse trigger,?,?" newline bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode Control.Note1: When changing the operation mode software should clear ADST bit first..Note2: In Burst mode the A/D result data is always at ADC Data Register 0." "0: Single conversion,1: Burst conversion,?,?" bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Bit.A/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" newline bitfld.long 0x0 0. "ADEN,A/D Converter Enable Bit.Note: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D converter Disabled,1: A/D converter Enabled" line.long 0x4 "ADC_ADCHER,ADC Channel Enable Register" hexmask.long 0x4 0.--31. 1. "CHEN,Analog Input Channel Enable Control.Set ADCHER[19:0] bits to enable the corresponding analog input channel 19 ~ 0. If DIFFEN bit is set to 1 only the even number channel needs to be enabled..Besides set ADCHER[29] to ADCHER[31] bits will enable.." line.long 0x8 "ADC_ADCMPR0,ADC Compare Register 0" hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data.The 12-bit data is used to compare with conversion result of specified channel..Note: CMPD bits should be filled in unsigned format (straight binary format)." bitfld.long 0x8 15. "CMPWEN,Compare Window Mode Enable Bit.Note: This bit is only presented in ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled" newline hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count.When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.." hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection" newline bitfld.long 0x8 2. "CMPCOND,Compare Condition.Note: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.." bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Bit.If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" newline bitfld.long 0x8 0. "CMPEN,Compare Enable Bit.Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled" line.long 0xC "ADC_ADCMPR1,ADC Compare Register 1" hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data.The 12-bit data is used to compare with conversion result of specified channel..Note: CMPD bits should be filled in unsigned format (straight binary format)." bitfld.long 0xC 15. "CMPWEN,Compare Window Mode Enable Bit.Note: This bit is only presented in ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled" newline hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count.When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.." hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection" newline bitfld.long 0xC 2. "CMPCOND,Compare Condition.Note: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.." bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Bit.If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" newline bitfld.long 0xC 0. "CMPEN,Compare Enable Bit.Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled" line.long 0x10 "ADC_ADSR0,ADC Status Register0" hexmask.long.byte 0x10 27.--31. 1. "CHANNEL,Current Conversion Channel (Read Only)" rbitfld.long 0x10 16. "OVERRUNF,Overrun Flag (Read Only).If any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1..Note: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1." "0,1" newline rbitfld.long 0x10 8. "VALIDF,Data Valid Flag (Read Only).If any one of VALID (ADDRx[17]) is set this flag will be set to 1..Note: When ADC is in burst mode and any conversion result is valid this flag will be set to 1." "0,1" rbitfld.long 0x10 7. "BUSY,BUSY/IDLE (Read Only).This bit is a mirror of ADST bit in ADCR register." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline bitfld.long 0x10 2. "CMPF1,Compare Flag 1.When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1; it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet ADCMPR1..,1: Conversion result in ADDR meets ADCMPR1 setting" bitfld.long 0x10 1. "CMPF0,Compare Flag 0.When the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it." "0: Conversion result in ADDR does not meet ADCMPR0..,1: Conversion result in ADDR meets ADCMPR0 setting" newline bitfld.long 0x10 0. "ADF,A/D Conversion End Flag.A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit..ADF bit is set to 1 at the following three conditions:.When A/D conversion ends in Single mode..When A/D conversion ends on.." "0,1" rgroup.long 0x94++0x7 line.long 0x0 "ADC_ADSR1,ADC Status Register1" hexmask.long 0x0 0.--31. 1. "VALID,Data Valid Flag (Read Only).VALID[31:29 19:0] are the mirror of the VALID bits in ADDR31[17] ~ ADDR29[17] ADDR19[17]~ ADDR0[17]. The other bits are reserved. .Note: When ADC is in burst mode and any conversion result is valid VALID[31:29 .." line.long 0x4 "ADC_ADSR2,ADC Status Register2" hexmask.long 0x4 0.--31. 1. "OVERRUN,Overrun Flag (Read Only).OVERRUN[31:29 19:0] are the mirror of the OVERRUN bit in ADDR31[16] ~ADDR29[16] ADDR19[16] ~ ADDR0[16]. The other bits are reserved. .Note: When ADC is in burst mode and the FIFO is overrun OVERRUN[31:29 19:0] will.." group.long 0x9C++0x3 line.long 0x0 "ADC_ADTDCR,ADC Trigger Delay Control Register" hexmask.long.byte 0x0 0.--7. 1. "PTDT,PWM Trigger Delay Time.Set this field will delay ADC start conversion time after PWM trigger..PWM trigger delay time is (4 * PTDT) * system clock" rgroup.long 0x100++0x3 line.long 0x0 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register" hexmask.long.tbyte 0x0 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only).When PDMA transferring read this register can monitor current PDMA transfer data..Current PDMA transfer data could be the content of ADDR0 ~ ADDR19 and ADDR29 ~ ADDR31 registers." endif tree.end sif (cpuis("NUC029?DE")) tree "BPWM (Basic PWM Generator and Capture Timer)" base ad:0x0 tree "BPWM0" base ad:0x40044000 group.long 0x0++0x7 line.long 0x0 "BPWM_CTL0,BPWM Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect).BPWM pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable" newline hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Control.Each bit n controls the corresponding BPWM channel n..Note: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-Load.Each bit n controls the corresponding BPWM channel n..In up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." line.long 0x4 "BPWM_CTL1,BPWM Control Register 1" bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0.Each bit n controls corresponding BPWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" group.long 0x10++0x7 line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register" bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select." "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" line.long 0x4 "BPWM_CLKPSC,BPWM Clock Pre-scale Register" hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Pre-Scale .The clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)." group.long 0x20++0x7 line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register" bitfld.long 0x0 0. "CNTEN0,BPWM Counter Enable 0." "0: BPWM Counter and clock prescaler Stop Running,1: BPWM Counter and clock prescaler Start Running" line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register" bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit BPWM counter to 0000H" group.long 0x30++0x3 line.long 0x0 "BPWM_PERIOD,BPWM Period Register" hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register.Up-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x50++0x17 line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." rgroup.long 0x90++0x3 line.long 0x0 "BPWM_CNT0,BPWM Counter Register 0" bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." group.long 0xB0++0xF line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0" hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,BPWM Period (Center) Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter count to (PERIODn+1)..Note: This bit is center point control when BPWM counter operating in up-down.." hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,BPWM Zero Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter count to zero." line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1" hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,BPWM Compare Down Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter down count to CMPDAT..Note: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4." hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,BPWM Compare Up Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter up count to CMPDAT..Note: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4." line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register" hexmask.long.byte 0x8 0.--5. 1. "MSKENn,BPWM Mask Enable Control.Each bit n controls the corresponding BPWM channel n..The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. ." line.long 0xC "BPWM_MSK,BPWM Mask Data Register" hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,BPWM Mask Data Bit.This data bit control the state of BPWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.." group.long 0xD4++0x7 line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register" hexmask.long.byte 0x0 0.--5. 1. "PINVn,BPWM PIN Polar Inverse Control.The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.." line.long 0x4 "BPWM_POEN,BPWM Output Enable Register" hexmask.long.byte 0x4 0.--5. 1. "POENn,BPWM Pin Output Enable Control.Each bit n controls the corresponding BPWM channel n.." group.long 0xE0++0x3 line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register" hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,BPWM Compare Down Count Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n..Note: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4." hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,BPWM Compare Up Count Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n..Note: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4." newline bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt Enable 0.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt Enable 0.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" group.long 0xE8++0x3 line.long 0x0 "BPWM_INTSTS0,BPWM Interrupt Flag Register" hexmask.long.byte 0x0 24.--29. 1. "CMPDIFn,BPWM Compare Down Count Interrupt Flag.Each bit n controls the corresponding BPWM channel n..Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it..Note1: If CMPDAT equal.." hexmask.long.byte 0x0 16.--21. 1. "CMPUIFn,BPWM Compare Up Count Interrupt Flag.Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n..Note1: If CMPDAT equal to.." newline bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0.This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0.This bit is set by hardware when BPWM_CH0 counter reaches zero software can write 1 to clear this bit to zero." "0,1" group.long 0xF8++0x7 line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select." newline bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select.Others reserved." newline bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select." newline bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select." line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select." newline bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select." group.long 0x110++0x3 line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register" bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select." "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,?,?" bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function Enable 0.When synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). ." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled" wgroup.long 0x114++0x3 line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register" bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable (Write Only).PMW counter synchronous enable function is used to make selected BPWM channels (include BPWM0_CHx and BPWM1_CHx) start counting at the same time..Writing this bit to 1 will also set the counter.." "0,1" group.long 0x120++0x3 line.long 0x0 "BPWM_STATUS,BPWM Status Register" hexmask.long.byte 0x0 16.--21. 1. "ADCTRGn,ADC Start Of Conversion Status.Each bit n controls the corresponding BPWM channel n.." bitfld.long 0x0 0. "CNTMAX0,Time-Base Counter 0 Equal To 0xFFFF Latched Status." "0: Indicates the time-base counter never reached..,1: Indicates the time-base counter reached its.." group.long 0x200++0x7 line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register" hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Control.Each bit n controls the corresponding BPWM channel n.." line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register" hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload Enable Control.Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Control.Each bit n controls the corresponding BPWM channel n.." newline hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Control.Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Control.Each bit n controls the corresponding BPWM channel n.." rgroup.long 0x208++0x33 line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register" hexmask.long.byte 0x0 8.--13. 1. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n..Note: This bit will be cleared automatically.." hexmask.long.byte 0x0 0.--5. 1. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n..Note: This bit will be cleared automatically.." line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." group.long 0x250++0x7 line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register" hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n.." line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register" hexmask.long.byte 0x4 8.--13. 1. "CFLIFn,BPWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CRLIFn,BPWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.." rgroup.long 0x304++0x3 line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x31C++0x17 line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT0 Buffer" hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT1 Buffer" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT2 Buffer" hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT3 Buffer" hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT4 Buffer" hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT5 Buffer" hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." tree.end tree "BPWM1" base ad:0x40144000 group.long 0x0++0x7 line.long 0x0 "BPWM_CTL0,BPWM Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect).BPWM pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable" newline hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Control.Each bit n controls the corresponding BPWM channel n..Note: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-Load.Each bit n controls the corresponding BPWM channel n..In up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." line.long 0x4 "BPWM_CTL1,BPWM Control Register 1" bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0.Each bit n controls corresponding BPWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" group.long 0x10++0x7 line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register" bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select." "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" line.long 0x4 "BPWM_CLKPSC,BPWM Clock Pre-scale Register" hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Pre-Scale .The clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)." group.long 0x20++0x7 line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register" bitfld.long 0x0 0. "CNTEN0,BPWM Counter Enable 0." "0: BPWM Counter and clock prescaler Stop Running,1: BPWM Counter and clock prescaler Start Running" line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register" bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit BPWM counter to 0000H" group.long 0x30++0x3 line.long 0x0 "BPWM_PERIOD,BPWM Period Register" hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register.Up-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x50++0x17 line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMP,BPWM Comparator Register.CMP use to compare with CNT to generate BPWM waveform interrupt and trigger ADC..In independent mode BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point..In complementary mode BPWM_CMPDAT0 2 4 denote as.." rgroup.long 0x90++0x3 line.long 0x0 "BPWM_CNT0,BPWM Counter Register 0" bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." group.long 0xB0++0xF line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0" hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,BPWM Period (Center) Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter count to (PERIODn+1)..Note: This bit is center point control when BPWM counter operating in up-down.." hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,BPWM Zero Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter count to zero." line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1" hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,BPWM Compare Down Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter down count to CMPDAT..Note: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4." hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,BPWM Compare Up Point Control.Each bit n controls the corresponding BPWM channel n..BPWM can control output level when BPWM counter up count to CMPDAT..Note: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4." line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register" hexmask.long.byte 0x8 0.--5. 1. "MSKENn,BPWM Mask Enable Control.Each bit n controls the corresponding BPWM channel n..The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. ." line.long 0xC "BPWM_MSK,BPWM Mask Data Register" hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,BPWM Mask Data Bit.This data bit control the state of BPWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.." group.long 0xD4++0x7 line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register" hexmask.long.byte 0x0 0.--5. 1. "PINVn,BPWM PIN Polar Inverse Control.The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.." line.long 0x4 "BPWM_POEN,BPWM Output Enable Register" hexmask.long.byte 0x4 0.--5. 1. "POENn,BPWM Pin Output Enable Control.Each bit n controls the corresponding BPWM channel n.." group.long 0xE0++0x3 line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register" hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,BPWM Compare Down Count Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n..Note: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4." hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,BPWM Compare Up Count Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n..Note: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4." newline bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt Enable 0.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt Enable 0.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" group.long 0xE8++0x3 line.long 0x0 "BPWM_INTSTS0,BPWM Interrupt Flag Register" hexmask.long.byte 0x0 24.--29. 1. "CMPDIFn,BPWM Compare Down Count Interrupt Flag.Each bit n controls the corresponding BPWM channel n..Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it..Note1: If CMPDAT equal.." hexmask.long.byte 0x0 16.--21. 1. "CMPUIFn,BPWM Compare Up Count Interrupt Flag.Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n..Note1: If CMPDAT equal to.." newline bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0.This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0.This bit is set by hardware when BPWM_CH0 counter reaches zero software can write 1 to clear this bit to zero." "0,1" group.long 0xF8++0x7 line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select." newline bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select.Others reserved." newline bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select." newline bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select." line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select." newline bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select." group.long 0x110++0x3 line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register" bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select." "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,?,?" bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function Enable 0.When synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). ." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled" wgroup.long 0x114++0x3 line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register" bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable (Write Only).PMW counter synchronous enable function is used to make selected BPWM channels (include BPWM0_CHx and BPWM1_CHx) start counting at the same time..Writing this bit to 1 will also set the counter.." "0,1" group.long 0x120++0x3 line.long 0x0 "BPWM_STATUS,BPWM Status Register" hexmask.long.byte 0x0 16.--21. 1. "ADCTRGn,ADC Start Of Conversion Status.Each bit n controls the corresponding BPWM channel n.." bitfld.long 0x0 0. "CNTMAX0,Time-Base Counter 0 Equal To 0xFFFF Latched Status." "0: Indicates the time-base counter never reached..,1: Indicates the time-base counter reached its.." group.long 0x200++0x7 line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register" hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Control.Each bit n controls the corresponding BPWM channel n.." line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register" hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload Enable Control.Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Control.Each bit n controls the corresponding BPWM channel n.." newline hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Control.Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Control.Each bit n controls the corresponding BPWM channel n.." rgroup.long 0x208++0x33 line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register" hexmask.long.byte 0x0 8.--13. 1. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n..Note: This bit will be cleared automatically.." hexmask.long.byte 0x0 0.--5. 1. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n..Note: This bit will be cleared automatically.." line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data Register (Read Only).When rising capture condition happened the BPWM counter value will be saved in this register." line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data Register (Read Only).When falling capture condition happened the BPWM counter value will be saved in this register." group.long 0x250++0x7 line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register" hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Control.Each bit n controls the corresponding BPWM channel n.." line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register" hexmask.long.byte 0x4 8.--13. 1. "CFLIFn,BPWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CRLIFn,BPWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.." rgroup.long 0x304++0x3 line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x31C++0x17 line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT0 Buffer" hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT1 Buffer" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT2 Buffer" hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT3 Buffer" hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT4 Buffer" hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT5 Buffer" hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Register Buffer (Read Only).Used as CMP active register." tree.end tree.end endif tree "CLK (Clock Controller)" base ad:0x50000200 sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) group.long 0x0++0xB line.long 0x0 "PWRCON,System Power-down Control Register" sif (cpuis("NUC029?EE")) bitfld.long 0x0 12. "OSC48M_EN,48 MHz Internal High Speed RC Oscillator (HIRC48) Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.." endif sif (cpuis("NUC029?AE")) bitfld.long 0x0 9. "PD_32K,Enable LXT in Power-down Mode.This bit controls the crystal oscillator active or not in Power-down mode." "0: No effect to Power-down mode,1: If XTLCLK_EN[1:0] = 10 LXT is still active in.." bitfld.long 0x0 0.--1. "XTLCLK_EN,External Crystal HXT or LXT Enable Control (Write Protect).The default clock source is from HIRC. These two bits are default set to '00' and the XTAL1 and XTAL2 pins are GPIO..Note: To enable the external XTAL function the P5_ALT[1:0] and.." "0: XTAL1 and XTAL2 are GPIO disable both LXT HXT..,1: HXT Enabled,?,?" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 8. "PD_WAIT_CPU,This bit control the power down entry condition (write-protected)" "0: Chip entry power down mode when the PWR_DOWN_EN..,1: Chip enter power down mode when the both.." newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 8. "PD_WAIT_CPU,Power-Down Entry Condition Control (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at.." "0: Chip enters Power-down mode when the PWR_DOWN_EN..,1: Chip enters Power- down mode when the both.." endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 8. "PD_WAIT_CPU,Power-Down Entry Condition Control (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at.." "0: Chip enters Power-down mode when the PWR_DOWN_EN..,1: Chip enters Power- down mode when the both.." newline endif bitfld.long 0x0 7. "PWR_DOWN_EN,System Power-down Enable Bit (Write Protect).When chip wakes up from Power-down mode this bit is cleared by hardware. User needs to set this bit again for next Power-down..In Power-down mode 4~24 MHz external high speed crystal oscillator.." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or waits.." bitfld.long 0x0 6. "PD_WU_STS,Power-down Mode Wake-up Interrupt Status.Set by 'Power-down wake-up event' which indicates that resume from Power-down mode'.The flag is set if the GPIO UART WDT I2C ACMP Timer or BOD wake-up occurred..Note: This bit works only if.." "0,1" newline bitfld.long 0x0 5. "PD_WU_INT_EN,Power-down Mode Wake-up Interrupt Enable Control (Write Protect).Note: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high." "0: Disabled,1: Enabled" bitfld.long 0x0 4. "PD_WU_DLY,Wake-up Delay Counter Enable Control (Write Protect).When the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable..The delayed clock cycle is 4096 clock cycles when chip work at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled" newline bitfld.long 0x0 3. "OSC10K_EN,10 kHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).." bitfld.long 0x0 2. "OSC22M_EN,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect).Note: The default of OSC22M_EN bit is 1." "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.." newline sif (cpuis("NUC029?EE")) bitfld.long 0x0 1. "XTL32K_EN,32.768 KHz External Low Speed Crystal Oscillator (LXT) Enable Bit (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to.." "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." bitfld.long 0x0 0. "XTL12M_EN,4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect).The bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from 4~24 MHz external high speed.." "0: 4 ~ 24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal oscillator.." newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "XTL12M_EN,External Crystal Oscillator enable (write-protected).The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external crystal the bit is automatically set to '1'" "0: Crystal oscillation disable,1: Crystal oscillation enable" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 0. "XTL12M_EN,4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect).The bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from 4~24 MHz external high speed.." "0: 4 ~ 24 MHz external high speed crystal..,1: 4 ~ 24 MHz external high speed crystal.." endif line.long 0x4 "AHBCLK,AHB Devices Clock Enable Control Register" sif (cpuis("NUC029?AN")) bitfld.long 0x4 4. "DIV_EN,Hardware Divider Controller Clock Enable Control" "0: Hardware Divider engine clock Disabled,1: Hardware Divider engine clock Enabled" bitfld.long 0x4 3. "EBI_EN,EBI Controller Clock Enable Control." "0: Disable the EBI controller clock,1: Enable the EBI controller clock" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 3. "EBI_EN,EBI Controller Clock Enable Control" "0: EBI engine clock Disabled,1: EBI engine clock Enabled" endif bitfld.long 0x4 2. "ISP_EN,Flash ISP Controller Clock Enable Control" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled" newline sif (cpuis("NUC029?EE")) bitfld.long 0x4 1. "PDMA_EN,PDMA Controller Clock Enable Bit" "0: PDMA peripherial clock Disabled,1: PDMA peripherial clock Enabled" endif line.long 0x8 "APBCLK,APB Devices Clock Enable Control Register" sif (cpuis("NUC029?AN")) bitfld.long 0x8 31. "ACMPB_EN,Analog Comparator B Clock Enable" "0: Disable the Analog Comparator B Clock,1: Enable the Analog Comparator B Clock" bitfld.long 0x8 30. "ACMPA_EN,Analog Comparator A Clock Enable" "0: Disable the Analog Comparator A Clock,1: Enable the Analog Comparator A Clock" newline endif sif (cpuis("NUC029?AE")) bitfld.long 0x8 30. "ACMP_EN,Analog Comparator Clock Enable Control" "0: Analog Comparator clock Disabled,1: Analog Comparator clock Enabled" bitfld.long 0x8 16. "UART_EN,UART Clock Enable Control" "0: UART clock Disabled,1: UART clock Enabled" newline bitfld.long 0x8 12. "SPI_EN,SPI Peripheral Clock Enable Control" "0: SPI peripheral clock Disabled,1: SPI peripheral clock Enabled" endif bitfld.long 0x8 28. "ADC_EN,Analog-Digital-Converter (ADC) Clock Enable Control" "0: ADC peripheral clock Disabled,1: ADC peripheral clock Enabled" newline sif (cpuis("NUC029?EE")) bitfld.long 0x8 27. "USBD_EN,USB 2.0 FS Device Controller Clock Enable Bit" "0: USB clock Disabled,1: USB clock Enabled" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "PWM67_EN,PWM_67 Clock Enable" "0: Disable PWM67 clock,1: Enable PWM67 clock" newline endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x8 22. "PWM45_EN,PWM_45 Clock Enable Control" "0: PWM45 clock Disabled,1: PWM45 clock Enabled" bitfld.long 0x8 21. "PWM23_EN,PWM_23 Clock Enable Control" "0: PWM23 clock Disabled,1: PWM23 clock Enabled" newline bitfld.long 0x8 20. "PWM01_EN,PWM_01 Clock Enable Control" "0: PWM01 clock Disabled,1: PWM01 clock Enabled" bitfld.long 0x8 8. "I2C_EN,I2C Clock Enable Control" "0: I2C clock Disabled,1: I2C clock Enabled" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 22. "PWM45_EN,PWM_45 Clock Enable Bit" "0: PWM45 clock Disabled,1: PWM45 clock Enabled" bitfld.long 0x8 21. "PWM23_EN,PWM_23 Clock Enable Bit" "0: PWM23 clock Disabled,1: PWM23 clock Enabled" newline bitfld.long 0x8 20. "PWM01_EN,PWM_01 Clock Enable Bit" "0: PWM01 clock Disabled,1: PWM01 clock Enabled" endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 18. "UART2_EN,UART2 Clock Enable Bit." "0: UART2 clock Disabled,1: UART2 clock Enabled" newline bitfld.long 0x8 17. "UART1_EN,UART1 Clock Enable Bit." "0: UART1 clock Disabled,1: UART1 clock Enabled" bitfld.long 0x8 16. "UART0_EN,UART0 Clock Enable Bit." "0: UART0 clock Disabled,1: UART0 clock Enabled" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 18. "UART2_EN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled" newline bitfld.long 0x8 17. "UART1_EN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled" bitfld.long 0x8 16. "UART0_EN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 17. "UART1_EN,UART1 Clock Enable" "0: Disable UART1 clock,1: Enable UART1 clock" newline bitfld.long 0x8 16. "UART0_EN,UART0 Clock Enable" "0: Disable UART0 clock,1: Enable UART0 clock" endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 13. "SPI1_EN,SPI1 Clock Enable" "0: Disable SPI1 Clock,1: Enable SPI1 Clock" newline bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable" "0: Disable SPI0 Clock,1: Enable SPI0 Clock" endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 13. "SPI1_EN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled" newline bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled" endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable Bit." "0: SPI0 clock Disabled,1: SPI0 clock Enabled" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 9. "I2C1_EN,I2C1 Clock Enable" "0: Disable I2C1 Clock,1: Enable I2C1 Clock" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 9. "I2C1_EN,I2C1 Clock Enable Bit." "0: I2C1 clock Disabled,1: I2C1 clock Enabled" newline bitfld.long 0x8 8. "I2C0_EN,I2C0 Clock Enable Bit." "0: I2C0 clock Disabled,1: I2C0 clock Enabled" endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 9. "I2C1_EN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled" newline bitfld.long 0x8 8. "I2C0_EN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled" endif bitfld.long 0x8 6. "FDIV_EN,Frequency Divider Output Clock Enable Control" "0: FDIV clock Disabled,1: FDIV clock Enabled" newline sif (cpuis("NUC029?AN")) bitfld.long 0x8 5. "TMR3_EN,Timer3 Clock Enable" "0: Disable Timer3 Clock,1: Enable Timer3 Clock" bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable" "0: Disable Timer2 Clock,1: Enable Timer2 Clock" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 5. "TMR3_EN,Timer3 Clock Enable Bit." "0: Timer3 clock Disabled,1: Timer3 clock Enabled" bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable Bit." "0: Timer2 clock Disabled,1: Timer2 clock Enabled" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 5. "TMR3_EN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled" bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled" newline endif bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable Control" "0: Timer1 clock Disabled,1: Timer1 clock Enabled" bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable Control" "0: Timer0 clock Disabled,1: Timer0 clock Enabled" newline sif (cpuis("NUC029?EE")) bitfld.long 0x8 1. "RTC_EN,Real-Time-Clock APB Interface Clock Enable Bit.This bit is used to control the RTC APB clock only The RTC peripheral clock source is selected from RTC_SEL_10K(CLKSEL2[18]). It can be selected to the 32.768 kHz external low speed crystal.." "0: RTC clock Disabled,1: RTC clock Enabled" endif bitfld.long 0x8 0. "WDT_EN,Watchdog Timer Clock Enable Control (Write Protect).Note: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled" rgroup.long 0xC++0x3 line.long 0x0 "CLKSTATUS,Clock Status Monitor Register" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x0 7. "CLK_SW_FAIL,Clock Switch Fail Flag.Note1: This bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1..Note2: This bit is.." "0: Clock switching success,1: Clock switching failed" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 7. "CLK_SW_FAIL,Clock Switching Fail Flag (Read Only).This bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switchs system clock the system clock source will keep old clock until the new clock.." "0: Clock switching success,1: Clock switching failure" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 7. "CLK_SW_FAIL,Clock Switching Fail Flag (Read Only).This bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switch system clock the system clock source will keep old clock until the new clock.." "0: Clock switching success,1: Clock switching failure" endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 5. "OSC48M_STB,48 MHz Internal High Speed RC Oscillator (HIRC48) Clock Source Stable Flag (Read Only)" "0: 48MHz internal high speed RC oscillator (HIRC48)..,1: 48MHz internal high speed RC oscillator (HIRC48).." newline endif bitfld.long 0x0 4. "OSC22M_STB,HIRC Clock Source Stable Flag (Read Only)" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable" newline bitfld.long 0x0 3. "OSC10K_STB,LIRC Clock Source Stable Flag (Read Only)" "0: LIRC clock is not stable or disabled,1: LIRC clock is stable" sif (cpuis("NUC029?AN")) bitfld.long 0x0 2. "PLL_STB,PLL clock source stable flag (Read Only)" "0: PLL clock is not stable or disable,1: PLL clock is stable" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 2. "PLL_STB,Internal PLL Clock Source Stable Flag (Read Only)." "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable in normal mode" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 2. "PLL_STB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable in normal mode" newline bitfld.long 0x0 1. "XTL32K_STB,32.768 KHz External Low Speed Crystallator Oscillator (LXT) Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." bitfld.long 0x0 0. "XTL12M_STB,4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." newline endif sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "XTL_STB,HXT or LXT Clock Source Stable Flag" "0: HXT or LXT clock is not stable or disabled,1: HXT or LXT clock is stable" endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "XTL12M_STB,External Crystal clock source stable flag (Read Only)" "0: External Crystal clock is not stable or disable,1: External Crystal clock is stable" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 0. "XTL12M_STB,4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)." "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." endif group.long 0x10++0xF line.long 0x0 "CLKSEL0,Clock Source Select Control Register 0" sif (cpuis("NUC029?EE")) bitfld.long 0x0 8. "USB_S,USB Clock Source Selection" "0: Clock source from PLL clock,1: Clock source from 48 MHz high speed RC.." endif bitfld.long 0x0 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Selection from Reference Clock (Write Protect).Note3: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "HCLK_S,HCLK Clock Source Selection (Write Protect).Note1: Before clock switching the related clock sources (both pre-select and new-select) must be turn-on and stable..Note2: These bits are protected bit and programming them needs to write 0x59 .." "0: Clock source is from HXT or LXT,1: Reserved,?,?,?,?,?,?" line.long 0x4 "CLKSEL1,Clock Source Select Control Register 1" sif (cpuis("NUC029?AN")) bitfld.long 0x4 30.--31. "PWM23_S,PWM2 and PWM3 clock source select..PWM2 and PWM3 uses the same Engine clock source both of them use the same pre-scalar" "0: Clock source from external crystal clock (4 ~..,1: Clock source from internal 10 kHz low speed..,?,?" bitfld.long 0x4 28.--29. "PWM01_S,PWM0 and PWM1 clock source select..PWM0 and PWM1 uses the same Engine clock source both of them use the same pre-scalar" "0: Clock source from external crystal clock ( 4 ~..,1: Clock source from internal 10 kHz low speed..,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 30.--31. "PWM23_S,PWM2 And PWM3 Clock Source Selection.PWM2 and PWM3 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9])." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?" bitfld.long 0x4 28.--29. "PWM01_S,PWM0 And PWM1 Clock Source Selection.PWM0 and PWM1 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8])." "0,1,2,3" newline endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x4 24.--25. "UART_S,UART Clock Source Selection.Note: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?" bitfld.long 0x4 12.--14. "TMR1_S,TIMER1 Clock Source Selection.Note: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "TMR0_S,TIMER0 Clock Source Selection.Note: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 24.--25. "UART_S,UART Clock Source Selection." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 24.--25. "UART_S,UART Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?" endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 20.--22. "TMR3_S,TIMER3 clock source select." "0: Clock source from external crystal clock (4 ~..,?,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 20.--22. "TMR3_S,TIMER3 Clock Source Selection." "0: Clock source from 4~24 MHz external high speed..,1: Reserved,?,?,?,?,?,?" endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 20.--22. "TMR3_S,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 16.--18. "TMR2_S,TIMER2 clock source select." "0: Clock source from external crystal clock (4 ~..,?,?,?,?,?,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 16.--18. "TMR2_S,TIMER2 Clock Source Selection." "0: Clock source from external 4~24 MHz high speed..,1: Reserved,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 16.--18. "TMR2_S,TIMER2 Clock Source Selection" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 12.--14. "TMR1_S,TIMER1 Clock Source Selection." "0: Clock source from 4~24 MHz external high speed..,1: Reserved,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 12.--14. "TMR1_S,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 8.--10. "TMR0_S,TIMER0 Clock Source Selection." "0: Clock source from 4~24 MHz external high speed..,1: Reserved,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 8.--10. "TMR0_S,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 5. "SPI1_S,SPI1 clock source select" "0: Clock source from PLL clock,1: Clock source from HCLK" newline bitfld.long 0x4 4. "SPI0_S,SPI0 clock source select" "0: Clock source from PLL clock,1: Clock source from HCLK" endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 5. "SPI1_S,SPI1 Clock Source Selection" "0: Clock source from PLL clock,1: Clock source from HCLK" newline bitfld.long 0x4 4. "SPI0_S,SPI0 Clock Source Selection" "0: Clock source from PLL clock,1: Clock source from HCLK" endif sif (cpuis("NUC029?AE")) bitfld.long 0x4 4. "SPI_S,SPI Clock Source Selection.Note: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from HCLK" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 4. "SPI0_S,SPI0 Clock Source Selection." "0: Clock source from PLL,1: Clock source from HCLK" endif bitfld.long 0x4 2.--3. "ADC_S,ADC Peripheral Clock Source Selection.Note: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?" newline bitfld.long 0x4 0.--1. "WDT_S,WDT CLK Clock Source Selection (Write Protect).Note1: These bits are the protected bit and programming them needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Clock source is from HXT or LXT,1: Reserved,?,?" line.long 0x8 "CLKDIV,Clock Divider Number Register" hexmask.long.byte 0x8 16.--23. 1. "ADC_N,ADC Peripheral Clock Divide Number from ADC Peripheral Clock Source" hexmask.long.byte 0x8 8.--11. 1. "UART_N,UART Clock Divide Number from UART Clock Source" newline sif (cpuis("NUC029?EE")) hexmask.long.byte 0x8 4.--7. 1. "USB_N,USB Clock Divide Number From PLL Clock" endif hexmask.long.byte 0x8 0.--3. 1. "HCLK_N,HCLK Clock Divide Number from HCLK Clock Source" line.long 0xC "CLKSEL2,Clock Source Select Control Register 2" sif (cpuis("NUC029?EE")) bitfld.long 0xC 18. "RTC_SEL_10K,RTC Clock Source Selection" "0: Clock source from 32.768 kHz external low speed..,1: Clock source from 10 kHz internal low speed RC.." bitfld.long 0xC 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection" "?,?,?,?" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0xC 16.--17. "WWDT_S,Window Watchdog Timer clock source select" "?,?,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0xC 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection." "?,?,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0xC 10. "PWM45_S_E,PWM4 And PWM5 Clock Source Selection Extend.PWM4 and PWM5 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10])." "0,1" bitfld.long 0xC 9. "PWM23_S_E,PWM2 And PWM3 Clock Source Selection Extend.PWM2 and PWM3 used the same peripheral clock source; both of them used the same prescaler. The perpherial clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E.." "0,1" newline bitfld.long 0xC 8. "PWM01_S_E,PWM0 And PWM1 Clock Source Selection Extend.PWM0 and PWM1 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E.." "0,1" endif sif (cpuis("NUC029?AN")) bitfld.long 0xC 6.--7. "PWM67_S,PWM6 and PWM7 clock source select.PWM6 and PWM7 used the same Engine clock source both of them use the same pre-scalar" "0: Clock source from external crystal clock (4 ~..,1: Clock source from internal 10 kHz low speed..,?,?" newline bitfld.long 0xC 4.--5. "PWM45_S,PWM4 and PWM5 clock source select.PWM4 and PWM5 used the same Engine clock source both of them use the same pre-scalar" "0: Clock source from external crystal clock (4 ~ 24..,1: Clock source from internal 10 kHz low speed..,?,?" endif sif (cpuis("NUC029?EE")) bitfld.long 0xC 4.--5. "PWM45_S,PWM4 And PWM5 Clock Source Selection.PWM4 and PWM5 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10])." "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?" newline endif bitfld.long 0xC 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection.Note: To set PWRCON[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,?" group.long 0x24++0x3 line.long 0x0 "FRQDIV,Frequency Divider Control Register" sif (cpuis("NUC029?EE")) bitfld.long 0x0 6. "CLKO_1HZ_EN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz external low..,1: 1 Hz clock output for 32.768 kHz external low.." bitfld.long 0x0 5. "DIVIDER1,Frequency Divider One Enable Bit" "0: Frequency divider will output clock with source..,1: Frequency divider will output clock with source.." newline endif sif (cpuis("NUC029?AE")) bitfld.long 0x0 5. "DIVIDER1,Frequency Divider 1 Enable Control" "0: Divider output frequency is depended on FSEL value,1: Divider output frequency is the same as input.." newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 5. "DIVIDER1,Frequency Divider One Enable Bit." "0: Frequency divider will output clock with source..,1: Frequency divider will output clock with source.." newline endif bitfld.long 0x0 4. "DIVIDER_EN,Frequency Divider Enable Control" "0: Frequency Divider Disabled,1: Frequency Divider Enabled" hexmask.long.byte 0x0 0.--3. 1. "FSEL,Divider Output Frequency Selection.The formula of output frequency is.Fin is the input clock frequency..Fout is the frequency of divider output clock..N is the 4-bit value of FSEL[3:0]." endif sif (cpuis("NUC029?GE")) group.long 0x0++0xB line.long 0x0 "CLK_PWRCTL,System Power-down Control Register" bitfld.long 0x0 13. "HIRC48EN,HIRC48 Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.." bitfld.long 0x0 12. "HXTSELTYP,HXT Crystal Type Select Bit (Write Protect).This is a protected register. Please refer to open lock sequence to program it..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Select INV type,1: Select GM type" newline bitfld.long 0x0 10.--11. "HXTGAIN,HXT Gain Control Bit (Write Protect).Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled crystal will consume more power than gain control off. .Note: This bit is write protected." "0: HXT frequency is lower than from 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?" bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect).When this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode..When chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip waits CPU sleep command WFI and then enters.." newline bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status.Set by 'Power-down wake-up event' it indicates that resume from Power-down mode' .The flag is set if the EINT0~5 GPIO USBD UART0~2 WDT ACMP01 BOD EBOD RTC TMR0~3 I2C0~1 or USCI0~2 wake-up.." "0,1" bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect).Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high..Note2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled" newline bitfld.long 0x0 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect).When the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable..The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled" bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).." newline bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.." bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz External Low Speed Crystal (LXT)..,1: 32.768 kHz External Low Speed Crystal (LXT).." newline bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect).The bit default value is set by Flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from HXT this bit is set to 1 automatically..Note: This bit is write protected. Refer.." "0: 4~24 MHz External High Speed Crystal (HXT)..,1: 4~24 MHz External High Speed Crystal (HXT) Enabled" line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register" bitfld.long 0x4 21. "GPIOFCKEN,General Purpose I/O PF Group Clock Enable Bit" "0: GPIO PF group clock Disabled,1: GPIO PF group clock Enabled" bitfld.long 0x4 20. "GPIOECKEN,General Purpose I/O PE Group Clock Enable Bit" "0: GPIO PE group clock Disabled,1: GPIO PE group clock Enabled" newline bitfld.long 0x4 19. "GPIODCKEN,General Purpose I/O PD Group Clock Enable Bit" "0: GPIO PD group clock Disabled,1: GPIO PD group clock Enabled" bitfld.long 0x4 18. "GPIOCCKEN,General Purpose I/O PC Group Clock Enable Bit" "0: GPIO PC group clock Disabled,1: GPIO PC group clock Enabled" newline bitfld.long 0x4 17. "GPIOBCKEN,General Purpose I/O PB Group Clock Enable Bit" "0: GPIO PB group clock Disabled,1: GPIO PB group clock Enabled" bitfld.long 0x4 16. "GPIOACKEN,General Purpose I/O PA Group Clock Enable Bit" "0: GPIO PA group clock Disabled,1: GPIO PA group clock Enabled" newline bitfld.long 0x4 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC peripheral clock Disabled when chip..,1: FMC peripheral clock Enabled when chip operating.." bitfld.long 0x4 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled" newline bitfld.long 0x4 4. "HDIVCKEN,Hardware Divider Controller Clock Enable Bit" "0: Hardware divider peripheral clock Disabled,1: Hardware divider peripheral clock Enabled" bitfld.long 0x4 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled" newline bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled" bitfld.long 0x4 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled" line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0" bitfld.long 0x8 30. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog Comparator 0/1 clock Disabled,1: Analog Comparator 0/1 clock Enabled" bitfld.long 0x8 28. "ADCCKEN,Analog-digital-converter (ADC) Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled" newline bitfld.long 0x8 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB Device clock Disabled,1: USB Device clock Enabled" bitfld.long 0x8 21. "PWM1CKEN,PWM1 Clock Enable Bit" "0: PWM1 clock Disabled,1: PWM1 clock Enabled" newline bitfld.long 0x8 20. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled" bitfld.long 0x8 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled" newline bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled" bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled" newline bitfld.long 0x8 13. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 Clock Disabled,1: SPI1 Clock Enabled" bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled" newline bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 Clock Disabled,1: I2C1 Clock Enabled" bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled" newline bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO Clock Disabled,1: CLKO Clock Enabled" bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 Clock Disabled,1: Timer3 Clock Enabled" newline bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 Clock Disabled,1: Timer2 Clock Enabled" bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 Clock Disabled,1: Timer1 Clock Enabled" newline bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 Clock Disabled,1: Timer0 Clock Enabled" bitfld.long 0x8 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit.This bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL2[18]). It can be selected to external 32.768 kHz low speed crystal (LXT) or 10.." "0: RTC Clock Disabled,1: RTC Clock Enabled" newline bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled" rgroup.long 0xC++0x3 line.long 0x0 "CLK_STATUS,Clock Status Monitor Register" bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) .This bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1..Note: After.." "0: Clock switching success,1: Clock switching failure" bitfld.long 0x0 5. "HIRC48STB,HIRC48 Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.." newline bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.." bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).." newline bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled" bitfld.long 0x0 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." newline bitfld.long 0x0 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." group.long 0x10++0x17 line.long 0x0 "CLK_CLKSEL0,Clock Source Select Control Register 0" bitfld.long 0x0 7. "PCLK1SEL,PCLK1 Clock Source Selection (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APB1 BUS clock source from HCLK,1: APB1 BUS clock source from HCLK/2" bitfld.long 0x0 6. "PCLK0SEL,PCLK0 Clock Source Selection (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APB0 BUS clock source from HCLK,1: APB0 BUS clock source from HCLK/2" newline bitfld.long 0x0 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect).Note2: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?" bitfld.long 0x0 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect).Before clock switching the related clock sources (both pre-select and new-select) must be turned on..The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration.." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?" line.long 0x4 "CLK_CLKSEL1,Clock Source Select Control Register 1" bitfld.long 0x4 29. "PWM1SEL,PWM1 Clock Source Selection.The peripheral clock source of PWM1 is defined by PWM1SEL." "0: Clock source from PLL clock,1: Clock source from PCLK1" bitfld.long 0x4 28. "PWM0SEL,PWM0 Clock Source Selection.The peripheral clock source of PWM0 is defined by PWM0SEL." "0: Clock source from PLL clock,1: Clock source from PCLK0" newline bitfld.long 0x4 24.--25. "UARTSEL,UART Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?" bitfld.long 0x4 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline bitfld.long 0x4 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" bitfld.long 0x4 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" bitfld.long 0x4 2.--3. "ADCSEL,ADC Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL,?,?" newline bitfld.long 0x4 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect).Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Reserved.,1: Clock source from 32.768 kHz external low speed..,?,?" line.long 0x8 "CLK_CLKDIV0,Clock Divider Number Register 0" hexmask.long.byte 0x8 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source" hexmask.long.byte 0x8 8.--11. 1. "UARTDIV,UART Clock Divide Number From UART Clock Source" newline hexmask.long.byte 0x8 4.--7. 1. "USBDIV,USB Clock Divide Number From PLL Source.Note: If the HIRC48 is selected it is delivery to USB clock directly." hexmask.long.byte 0x8 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" line.long 0xC "CLK_CLKSEL2,Clock Source Select Control Register 2" bitfld.long 0xC 26.--27. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?" bitfld.long 0xC 24.--25. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?" newline bitfld.long 0xC 18. "RTCSEL,RTC Clock Source Selection" "0: Clock source from 32.768 kHz external low speed..,1: Clock source from 10 kHz internal low speed RC.." bitfld.long 0xC 16.--17. "WWDTSEL,Window Watchdog Timer Clock Source Selection" "?,?,?,?" newline bitfld.long 0xC 2.--4. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" line.long 0x10 "CLK_PLLCTL,PLL Control Register" bitfld.long 0x10 23. "STBSEL,PLL Stable Counter Selection" "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 12288 PLL source clock.." bitfld.long 0x10 19. "PLLSRC,PLL Source Clock Selection" "0: PLL source clock from external 4~24 MHz..,1: PLL source clock from internal 22.1184 MHz.." newline bitfld.long 0x10 18. "OE,PLL OE (FOUT Enable) Control" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low" bitfld.long 0x10 17. "BP,PLL Bypass Control" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN" newline bitfld.long 0x10 16. "PD,Power-down Mode .If set PDEN(CLK_PWRCTL[7]) bit to 1 the PLL will enter Power-down mode too." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)" bitfld.long 0x10 14.--15. "OUTDIV,PLL Output Divider Control .Refer to the formulas below the table." "0,1,2,3" newline hexmask.long.byte 0x10 9.--13. 1. "INDIV,PLL Input Divider Control .Refer to the formulas below the table." hexmask.long.word 0x10 0.--8. 1. "FBDIV,PLL Feedback Divider Control .Refer to the formulas below the table." line.long 0x14 "CLK_CLKOCTL,Clock Output Control Register" bitfld.long 0x14 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz external low..,1: 1 Hz clock output for 32.768 kHz external low.." bitfld.long 0x14 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.." newline bitfld.long 0x14 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled" hexmask.long.byte 0x14 0.--3. 1. "FREQSEL,Clock Output Frequency Selection.The formula of output frequency is.Fin is the input clock frequency..Fout is the frequency of divider output clock..N is the 4-bit value of FREQSEL[3:0]." group.long 0x30++0xB line.long 0x0 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1" bitfld.long 0x0 10. "USCI2CKEN,USCI2 Clock Enable Bit" "0: USCI2 clock Disabled,1: USCI2 clock Enabled" bitfld.long 0x0 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled" newline bitfld.long 0x0 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled" bitfld.long 0x0 1. "SC1CKEN,SC1 Clock Enable Bit" "0: SC1 clock Disabled,1: SC1 clock Enabled" newline bitfld.long 0x0 0. "SC0CKEN,SC0 Clock Enable Bit" "0: SC0 Clock Disabled,1: SC0 Clock Enabled" line.long 0x4 "CLK_CLKSEL3,Clock Source Select Control Register 3" bitfld.long 0x4 8. "USBDSEL,USBD Clock Source Selection(Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 48 MHz internal hight speed RC..,1: Clock source from PLL clock" bitfld.long 0x4 2.--3. "SC1SEL,SC1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?" newline bitfld.long 0x4 0.--1. "SC0SEL,SC0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL clock,?,?" line.long 0x8 "CLK_CLKDIV1,Clock Divider Number Register 1" hexmask.long.byte 0x8 8.--15. 1. "SC1DIV,SC1 Clock Divide Number From SC1 Clock Source" hexmask.long.byte 0x8 0.--7. 1. "SC0DIV,SC0 Clock Divide Number From SC0 Clock Source" group.long 0x40++0x3 line.long 0x0 "CLK_BODCLK,Clock Source Select for BOD Control Register" bitfld.long 0x0 0. "VDETCKSEL,Clock Source Selection for Voltage Detector.The Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL..Note1: If LIRC is selected LIRCEN (CLK_PWRCTL[3]) must be enabled..Note2: If LXT is selected LXTEN.." "0: Clock source is from 10 kHz internal low speed..,1: Clock source is from 32.768 kHz external low.." group.long 0x70++0xB line.long 0x0 "CLK_CLKDCTL,Clock Fail Detector Control Register" bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." newline bitfld.long 0x0 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." bitfld.long 0x0 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." newline bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." line.long 0x4 "CLK_CLKDSTS,Clock Fail Detector Status Register" bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag (Write Protect).Note1: This bit can be cleared to 0 by software writing '1'..Note2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." bitfld.long 0x4 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect).Note1: This bit can be cleared to 0 by software writing '1'. .Note2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." newline bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect).Note1: This bit can be cleared to 0 by software writing '1'..Note2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.." line.long 0x8 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register" hexmask.long.word 0x8 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary.The bits define the high value of frequency monitor window..When HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1." endif sif (cpuis("NUC029?AN")) group.long 0x20++0x3 line.long 0x0 "PLLCON,PLL Control Register" bitfld.long 0x0 19. "PLL_SRC,PLL Source Clock Select" "0: PLL source clock from external crystal (4 ~ 24..,1: PLL source clock from 22.1184 MHz oscillator" bitfld.long 0x0 18. "OE,PLL OE (FOUT enable) pin Control" "0: PLL FOUT enable,1: PLL FOUT is fixed low" newline bitfld.long 0x0 17. "BP,PLL Bypass Control" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock input" bitfld.long 0x0 16. "PD,Power down Mode.If the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too." "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)" newline bitfld.long 0x0 14.--15. "OUT_DV,PLL Output Divider Control" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "IN_DV,PLL Input Divider Control" newline hexmask.long.word 0x0 0.--8. 1. "FB_DV,PLL Feedback Divider Control" endif sif (cpuis("NUC029?DE")) group.long 0x20++0x3 line.long 0x0 "PLLCON,PLL Control Register" bitfld.long 0x0 19. "PLL_SRC,PLL Source Clock Selection." "0: PLL source clock from 4~24 MHz external high..,1: PLL source clock from 22.1184 MHz internal high.." bitfld.long 0x0 18. "OE,PLL OE (FOUT Enable) Pin Control." "0: PLL FOUT Enabled,1: PLL FOUT is fixed low" newline bitfld.long 0x0 17. "BP,PLL Bypass Control." "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock input" bitfld.long 0x0 16. "PD,Power-Down Mode.If the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too.." "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)" newline bitfld.long 0x0 14.--15. "OUT_DV,PLL Output Divider Control Bits.Refer to the formulas below the table." "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "IN_DV,PLL Input Divider Control Bits.Refer to the formulas below the table." newline hexmask.long.word 0x0 0.--8. 1. "FB_DV,PLL Feedback Divider Control Bits.Refer to the formulas below the table." endif sif (cpuis("NUC029?EE")) group.long 0x20++0x3 line.long 0x0 "PLLCON,PLL Control Register" bitfld.long 0x0 19. "PLL_SRC,PLL Source Clock Selection" "0: PLL source clock from 4~24 MHz external high..,1: PLL source clock from 22.1184 MHz internal high.." bitfld.long 0x0 18. "OE,PLL OE (FOUT Enable) Pin Control" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low" newline bitfld.long 0x0 17. "BP,PLL Bypass Control" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock input" bitfld.long 0x0 16. "PD,Power-Down Mode.If the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too." "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)" newline bitfld.long 0x0 14.--15. "OUT_DV,PLL Output Divider Control Bits.Refer to the formulas below the table." "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "IN_DV,PLL Input Divider Control Bits.Refer to the formulas below the table." newline hexmask.long.word 0x0 0.--8. 1. "FB_DV,PLL Feedback Divider Control Bits.Refer to the formulas below the table." endif sif (cpuis("NUC029?DE")) group.long 0x30++0x7 line.long 0x0 "APBCLK1,APB Devices Clock Enable Control Register 1" bitfld.long 0x0 19. "BPWM1_EN,BPWM1 Clock Enable Bit." "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled" bitfld.long 0x0 18. "BPWM0_EN,BPWM0 Clock Enable Bit." "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled" newline bitfld.long 0x0 17. "PWM1_EN,PWM1 Clock Enable Bit." "0: PWM1 clock Disabled,1: PWM1 clock Enabled" bitfld.long 0x0 16. "PWM0_EN,PWM0 Clock Enable Bit." "0: PWM0 clock Disabled,1: PWM0 clock Enabled" newline bitfld.long 0x0 10. "UART5_EN,UART5 Clock Enable Bit." "0: UART5 clock Disabled,1: UART5 clock Enabled" bitfld.long 0x0 9. "UART4_EN,UART4 Clock Enable Bit." "0: UART4 clock Disabled,1: UART4 clock Enabled" newline bitfld.long 0x0 8. "UART3_EN,UART3 Clock Enable Bit." "0: UART3 clock Disabled,1: UART3 clock Enabled" line.long 0x4 "CLKSEL3,Clock Source Select Control Register 3" bitfld.long 0x4 19. "BPWM1_S,BPWM1 Clock Source Selection.The Engine clock source of BPWM1 is defined by BPWM1_S.." "0: Clock source from PLL,1: Clock source from PCLK" bitfld.long 0x4 18. "BPWM0_S,BPWM0 Clock Source Selection.The Engine clock source of BPWM0 is defined by BPWM0_S.." "0: Clock source from PLL,1: Clock source from PCLK" newline bitfld.long 0x4 17. "PWM1_S,PWM1 Clock Source Selection.The Engine clock source of PWM1 is defined by PWM1_S.." "0: Clock source from PLL,1: Clock source from PCLK" bitfld.long 0x4 16. "PWM0_S,PWM0 Clock Source Selection.The Engine clock source of PWM0 is defined by PWM0_S.." "0: Clock source from PLL,1: Clock source from PCLK" group.long 0x70++0xF line.long 0x0 "CLKDCTL,Clock Fail Detector Control Register" bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit." "0: HXT clock frequency monitor fail interrupt..,1: HXT clock frequency monitor fail interrupt Enabled" bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit." "0: HXT clock frequency monitor Disabled,1: HXT clock frequency monitor Enabled" newline bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit." "0: HXT clock Fail interrupt Disabled,1: HXT clock Fail interrupt Enabled" bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit." "0: HXT clock Fail detector Disabled,1: HXT clock Fail detector Enabled" line.long 0x4 "CLKDSTS,Clock Fail Detector Status Register" bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag." "0: HXT clock normal,1: HXT clock frequency abnormal (write '1' to clear)" bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag." "0: HXT clock normal,1: HXT clock stop (write '1' to clear)" line.long 0x8 "CDUPB,Clock Frequency Detector Upper Boundary Register" hexmask.long.word 0x8 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary.The bits define the high value of frequency monitor window..When HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1." line.long 0xC "CDLOWB,Clock Frequency Detector Lower Boundary Register" hexmask.long.word 0xC 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Lower Boundary.The bits define the low value of frequency monitor window..When HXT frequency monitor values lower than this register the HXT frequency detect fail interrupt flag will set to 1." endif sif (cpuis("NUC029?GE")) group.long 0x7C++0x3 line.long 0x0 "CLK_CDLOWB,Clock Frequency Detector Low Boundary Register" hexmask.long.word 0x0 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Low Boundary.The bits define the low value of frequency monitor window..When HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will set to 1." endif tree.end sif (cpuis("NUC029?GE")) tree "CRC (Cyclic Redundancy Check)" base ad:0x50018000 group.long 0x0++0xB line.long 0x0 "CRC_CTL,CRC Control Register" bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode.This field indicates the CRC operation polynomial mode." "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,?,?" bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length.This field indicates the valid write data length of DATA (CRC_DAT[31:0])..Note: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode .." "0: Data length is 8-bit mode,1: Data length is 16-bit mode..Data length is..,?,?" newline bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement Enable Bit.This bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0])." "0: 1's complement for CRC CHECKSUM Disabled,1: 1's complement for CRC CHECKSUM Enabled" bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement Enable Bit.This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0])." "0: 1's complement for CRC DATA Disabled,1: 1's complement for CRC DATA Enabled" newline bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse Enable Bit.This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0])..Note: If the checksum result is 0xDD7B0F2E the bit order reverse result for CRC checksum is.." "0: Bit order reverse for CRC CHECKSUM Disabled,1: Bit order reverse for CRC CHECKSUM Enabled" bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse Enable Bit.This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0])..Note: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is.." "0: Bit order reversed for CRC DATA Disabled,1: Bit order reversed for CRC DATA Enabled (per byte)" newline bitfld.long 0x0 1. "CHKSINIT,Checksum Initialization.Set this bit will auto reolad SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value..Note: This bit will be cleared automatically." "0: No effect,1: Reolad SEED value to CHECKSUM as CRC operation.." bitfld.long 0x0 0. "CRCEN,CRC Generator Enable Bit.Set this bit 1 to enable CRC generator for CRC operation." "0: No effect,1: CRC generator is active" line.long 0x4 "CRC_DAT,CRC Write Data Register" hexmask.long 0x4 0.--31. 1. "DATA,CRC Write Data Bits.User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation..Note: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if.." line.long 0x8 "CRC_SEED,CRC Seed Register" hexmask.long 0x8 0.--31. 1. "SEED,CRC Seed Value.This field indicates the CRC seed value..Note1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1..Note2: The valid bits of CRC_SEED[31:0] is correlated to.." rgroup.long 0xC++0x3 line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register" hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results.This field indicates the CRC checksum result..Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30])." tree.end endif sif (cpuis("NUC029?AN")) tree "DIV (Divider Control)" base ad:0x50014000 group.long 0x0++0x13 line.long 0x0 "DIVIDEND,Dividend Source Register" hexmask.long 0x0 0.--31. 1. "Dividend,Dividend Source..This register is given the dividend of divider before calculation starts." line.long 0x4 "DIVISOR,Divisor Source Resister" hexmask.long.word 0x4 0.--15. 1. "Divisor,Divisor Source..This register is given the divisor of divider before calculation starts..Note: when this register is written hardware divider will start calculate" line.long 0x8 "DIVQUO,Quotient Result Resister" hexmask.long 0x8 0.--31. 1. "Quotient,Quotient Result.This register holds the quotient result of divider after calculation complete." line.long 0xC "DIVREM,Reminder Result Register" hexmask.long.word 0xC 0.--15. 1. "Reminder,Reminder Result.This register holds the reminder result of divider after calculation complete." line.long 0x10 "DIVSTS,Divider Status Register" bitfld.long 0x10 1. "DIV0,Divisor zero warning..1: The divisor is 0..0: The divisor is not 0..This register is read only." "0,1" bitfld.long 0x10 0. "DIV_FINISH,Divider operation finished..This register is read only." "0: The divider calculation is not yet,1: The divider calculation is finished" tree.end endif sif (cpuis("NUC029?AN")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) tree "EBI (External Bus Interface)" base ad:0x50010000 sif (cpuis("NUC029?AN")||cpuis("NUC029?EE")) group.long 0x0++0x7 line.long 0x0 "EBICON,External Bus Interface General Control Register" bitfld.long 0x0 16.--18. "ExttALE,Expand Time of ALE.The ALE width (tALE) to latch the address can be controlled by ExttALE." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "ExtBW16,EBI data width 16 bit.This bit defines if the data bus is 8-bit or 16-bit." "0: EBI data width is 8 bit,1: EBI data width is 16 bit" bitfld.long 0x0 0. "ExtEN,EBI Enable.This bit is the functional enable bit for EBI." "0: EBI function is disabled,1: EBI function is enabled" line.long 0x4 "EXTIME,External Bus Interface Timing Control Register" hexmask.long.byte 0x4 24.--27. 1. "ExtIR2R,Idle State Cycle Between Read-Read.When read action is finish and next action is going to read idle state is inserted and nCS return to high if ExtIR2R is not zero." hexmask.long.byte 0x4 12.--15. 1. "ExtIW2X,Idle State Cycle After Write.When write action is finish idle state is inserted and nCS return to high if ExtIW2X is not zero." newline bitfld.long 0x4 8.--10. "ExttAHD,EBI Data Access Hold Time.ExttAHD define data access hold time (tAHD)." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 3.--7. 1. "ExttACC,EBI Data Access Time.ExttACC define data access time (tACC)." endif sif (cpuis("NUC029?GE")) group.long 0x0++0x7 line.long 0x0 "EBI_CTL0,External Bus Interface Bank0 Control Register" bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE.The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE..Note: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider.The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?" newline bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode.When continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled" bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse" "0: Chip select pin (EBI_nCSx) is active low,1: Chip select pin (EBI_nCSx) is active high" newline bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select.This bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit" bitfld.long 0x0 0. "EN,EBI Enable Bit.This bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled" line.long 0x4 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register" hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read.This field defines the number of R2R idle cycle." bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.." newline bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.." hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write.This field defines the number of W2X idle cycle." newline bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time.TAHD define data access hold time (tAHD)." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time.TACC define data access time (tACC)." endif sif (cpuis("NUC029?EE")) group.long 0x8++0x3 line.long 0x0 "EBICON2,External Bus Interface General Control Register 2" bitfld.long 0x0 2. "WAHD_OFF,Access Hold Time Disable Control When Write" "0: tAHD is controlled by ExttAHD when write through..,1: No tAHD when write through EBI" bitfld.long 0x0 1. "RAHD_OFF,Access Hold Time Disable Control When Read" "0: tAHD is controlled by ExttAHD when read through..,1: No tAHD when read through EBI" newline bitfld.long 0x0 0. "WBUFF_EN,EBI Write Buffer Enable" "0: EBI write buffer disable,1: EBI write buffer enable" endif sif (cpuis("NUC029?GE")) group.long 0x10++0x7 line.long 0x0 "EBI_CTL1,External Bus Interface Bank1 Control Register" bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE.The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE..Note: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider.The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?" newline bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode.When continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled" bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse" "0: Chip select pin (EBI_nCSx) is active low,1: Chip select pin (EBI_nCSx) is active high" newline bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select.This bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit" bitfld.long 0x0 0. "EN,EBI Enable Bit.This bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled" line.long 0x4 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register" hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read.This field defines the number of R2R idle cycle." bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.." newline bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.." hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write.This field defines the number of W2X idle cycle." newline bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time.TAHD define data access hold time (tAHD)." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time.TACC define data access time (tACC)." endif tree.end endif tree "FMC (Flash Memory Controller)" base ad:0x5000C000 sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) group.long 0x0++0x13 line.long 0x0 "ISPCON,ISP Control Register" bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect).This bit is set by hardware when a triggered ISP meets any of the following conditions:.(3) User Configuration is erased/programmed when CFGUEN is 0..(4) Destination address is illegal such as over an available.." "0,1" bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Control (Write Protect)" "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM" newline bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Control (Write Protect).Writing this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM." "0: ISP update User Configuration Disabled,1: ISP update User Configuration Enabled" bitfld.long 0x0 3. "APUEN,APROM Update Enable Control (Write Protect)" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM" newline bitfld.long 0x0 1. "BS,Boot Select (Write Protect).Set/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Boot from APROM,1: Boot from LDROM" bitfld.long 0x0 0. "ISPEN,ISP Enable Control (Write Protect).Set this bit to enable ISP function." "0: ISP function Disabled,1: ISP function Enabled" line.long 0x4 "ISPADR,ISP Address Register" hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address.The NuMicro NUC029 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation." line.long 0x8 "ISPDAT,ISP Data Register" hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data.Write data to this register before ISP program operation..Read data from this register after ISP read operation." line.long 0xC "ISPCMD,ISP Command Register" sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--5. 1. "ISPCMD,ISP Command .ISP commands are shown below:" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0xC 0.--5. 1. "ISPCMD,ISP Command.ISP command table is shown below:." newline endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0xC 0.--5. 1. "ISPCMD,ISP Command.ISP command table is shown below:" endif line.long 0x10 "ISPTRG,ISP Trigger Register" bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect).Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished." "0: ISP operation is finished,1: ISP operation is progressed" endif sif (cpuis("NUC029?GE")) group.long 0x0++0x13 line.long 0x0 "FMC_ISPCTL,ISP Control Register" bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect).This bit is set by hardware when a triggered ISP meets any of the following conditions:.This bit needs to be cleared by writing 1 to it..(1) APROM writes to itself if APUEN is set to 0..(2) LDROM writes to itself.." "0,1" bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect).LDROM update enable bit..Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated" newline bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect).Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated" bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect).Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM" newline bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Bit (Write Protect).Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: SPROM cannot be updated,1: SPROM can be updated" bitfld.long 0x0 1. "BS,Boot Select (Write Protect).Set/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Booting from APROM,1: Booting from LDROM" newline bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect).ISP function enable bit. Set this bit to enable ISP function..Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled" line.long 0x4 "FMC_ISPADDR,ISP Address Register" hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address.The NuMicro NUC029GE series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation..For Checksum Calculation command this field is the Flash.." line.long 0x8 "FMC_ISPDAT,ISP Data Register" hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data.Write data to this register before ISP program operation..Read data from this register after ISP read operation." line.long 0xC "FMC_ISPCMD,ISP CMD Register" hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP CMD.ISP command table is shown below:.The other commands are invalid." line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register" bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect).Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished..Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed" rgroup.long 0x14++0x3 line.long 0x0 "FMC_DFBA,Data Flash Base Address" hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address.This register indicates Data Flash start address. It is a read only register..The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1" group.long 0x18++0x3 line.long 0x0 "FMC_FTCTL,Flash Access Time Control Register" bitfld.long 0x0 7. "CACHEOFF,Flash Cache Disable Bit (Write Protect).Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: Flash Cache function Enabled (default),1: Flash Cache function Disabled" bitfld.long 0x0 4.--6. "FOM,Frequency Optimization Mode (Write Protect).The NUC029GE series supports adjustable Flash access timing to optimize the Flash access cycles in different working frequency..Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "?,1: Frequency 24 MHz..Frequency 72 MHz,?,?,?,?,?,?" endif sif (cpuis("NUC029?AE")) rgroup.long 0x14++0x3 line.long 0x0 "DFBA,Data Flash Start Address" hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address.This register indicates data flash start address. It is a read only register..The data flash start address is defined by user. Since on chip flash erase unit is 512 bytes it is mandatory to keep bit 8-0 as 0." group.long 0x40++0x3 line.long 0x0 "ISPSTA,ISP Status Register" hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only).The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}." bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect).This bit is set by hardware when a triggered ISP meets any of the following conditions:.(3) User Configuration is erased/programmed when CFGUEN is 0..(4) Destination address is illegal such as over an available.." "0,1" newline rbitfld.long 0x0 1.--2. "CBS,Config Boot Selection (Read only).This is a mirror of CBS in CONFIG0." "0,1,2,3" rbitfld.long 0x0 0. "ISPGO,ISP Start Trigger (Read only).Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished..Note: This bit is the same with ISPTRG bit 0." "0: ISP operation is finished,1: ISP operation is progressed" endif sif (cpuis("NUC029?AN")) rgroup.long 0x14++0x3 line.long 0x0 "DFBADR,Data Flash Base Address" hexmask.long 0x0 0.--31. 1. "DFBADR,Data Flash Base Address.This register indicates data flash start address. It is a read only register..For 8/16/32/64KB flash memory device the data flash size is 4KB and it start address is fixed at 0x0001_F000 by hardware internally." group.long 0x18++0x3 line.long 0x0 "FATCON,Flash Access Time Control Register" bitfld.long 0x0 4. "LFOM,Low Frequency Optimization Mode (write-protected).When chip operation frequency is lower than 25 MHz chip can work more efficiently by setting this bit to 1" "0: Disable low frequency optimization mode,1: Enable low frequency optimization mode" endif sif (cpuis("NUC029?DE")) rgroup.long 0x14++0x3 line.long 0x0 "DFBADR,Data Flash Base Address" hexmask.long 0x0 0.--31. 1. "DFBADR,Data Flash Base Address.This register indicates Data Flash start address. It is read only..When DFVSEN is set to 0 the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is.." group.long 0x18++0x3 line.long 0x0 "FATCON,Flash Access Time Control Register" bitfld.long 0x0 6. "FOMSEL1,Chip Frequency Optimization Mode Select1 (Write-protection Bit)" "0,1" bitfld.long 0x0 4. "FOMSEL0,Chip Frequency Optimization Mode Select 0 (Write-Protection Bit).When CPU frequency is lower than 25 MHz user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance.." "0,1" group.long 0x40++0x3 line.long 0x0 "ISPSTA,ISP Status Register" hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only).The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}." bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write-Protection Bit).This bit is set by hardware when a triggered ISP meets any of the following conditions:.(1) APROM writes to itself.(2) LDROM writes to itself.(3) CONFIG is erased/programmed if CFGUEN is set to 0.(4).." "0,1" newline rbitfld.long 0x0 1.--2. "CBS,Chip Boot Selection (Read Only).This is a mirror of CBS in CONFIG0." "0,1,2,3" rbitfld.long 0x0 0. "ISPGO,ISP Start Trigger (Read Only).Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished..Note: This bit is the same as ISPTRG bit0." "0: ISP operation finished,1: ISP operation progressed" endif sif (cpuis("NUC029?EE")) rgroup.long 0x14++0x3 line.long 0x0 "DFBADR,Data Flash Base Address" hexmask.long 0x0 0.--31. 1. "DFBADR,Data Flash Base Address.This register indicates Data Flash start address. It is read only..Tthe Data Flash size is defined by user configuration register content is loaded from CONFIG1 when chip is powered on." group.long 0x18++0x3 line.long 0x0 "FATCON,Flash Access Time Control Register" bitfld.long 0x0 6. "FOMSEL1,Chip Frequency Optimization Mode Select1 (Write-protection Bit)" "0,1" bitfld.long 0x0 4. "FOMSEL0,Chip Frequency Optimization Mode Select 0 (Write-Protection Bit).When CPU frequency is lower than 72 MHz user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance." "0,1" group.long 0x40++0x3 line.long 0x0 "ISPSTA,ISP Status Register" hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only).The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}" bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write-Protection Bit).This bit is set by hardware when a triggered ISP meets any of the following conditions:.(1) APROM writes to itself.(2) LDROM writes to itself.(3) CONFIG is erased/programmed if CFGUEN is set to 0.(4).." "0,1" newline rbitfld.long 0x0 1.--2. "CBS,Chip Boot Selection (Read Only).This is a mirror of CBS in CONFIG0." "0,1,2,3" rbitfld.long 0x0 0. "ISPGO,ISP Start Trigger (Read Only).Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished..Note: This bit is the same as ISPTRG bit0" "0: ISP operation finished,1: ISP operation progressed" endif sif (cpuis("NUC029?GE")) group.long 0x40++0x3 line.long 0x0 "FMC_ISPSTS,ISP Status Register" bitfld.long 0x0 31. "SCODE,Security Code Active Flag.This bit is set by hardware when detecting SPROM secured code is active at Flash initiation or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation." "0: Secured code is inactive,1: Secured code is active" hexmask.long.tbyte 0x0 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only).All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF} except SPROM..VECMAP [18:12] should be 0." newline bitfld.long 0x0 7. "ALLONE,Flash All-one Verification Flag .This bit is set by hardware if all of Flash bits are 1 and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit can also be cleared by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash All-One.." bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect).This bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:.(1).." "0,1" newline rbitfld.long 0x0 1.--2. "CBS,Boot Selection of CONFIG (Read Only).This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?" rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only).Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished..This bit is the mirror of ISPGO(FMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed" group.long 0x80++0xF line.long 0x0 "FMC_MPDAT0,ISP Data0 Register" hexmask.long 0x0 0.--31. 1. "ISPDAT0,ISP Data 0.This register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data." line.long 0x4 "FMC_MPDAT1,ISP Data1 Register" hexmask.long 0x4 0.--31. 1. "ISPDAT1,ISP Data 1.This register is the second 32-bit data for 64-bit/multi-word programming." line.long 0x8 "FMC_MPDAT2,ISP Data2 Register" hexmask.long 0x8 0.--31. 1. "ISPDAT2,ISP Data 2.This register is the third 32-bit data for multi-word programming." line.long 0xC "FMC_MPDAT3,ISP Data3 Register" hexmask.long 0xC 0.--31. 1. "ISPDAT3,ISP Data 3.This register is the fourth 32-bit data for multi-word programming." rgroup.long 0xC0++0x7 line.long 0x0 "FMC_MPSTS,ISP Multi-program Status Register" bitfld.long 0x0 7. "D3,ISP DATA 3 Flag (Read Only).This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete." "0: FMC_MPDAT3 register is empty or program to Flash..,1: FMC_MPDAT3 register has been written and not.." bitfld.long 0x0 6. "D2,ISP DATA 2 Flag (Read Only).This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete." "0: FMC_MPDAT2 register is empty or program to Flash..,1: FMC_MPDAT2 register has been written and not.." newline bitfld.long 0x0 5. "D1,ISP DATA 1 Flag (Read Only).This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete." "0: FMC_MPDAT1 register is empty or program to Flash..,1: FMC_MPDAT1 register has been written and not.." bitfld.long 0x0 4. "D0,ISP DATA 0 Flag (Read Only).This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete." "0: FMC_MPDAT0 register is empty or program to Flash..,1: FMC_MPDAT0 register has been written and not.." newline bitfld.long 0x0 2. "ISPFF,ISP Fail Flag (Read Only).This bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:.(1) APROM.." "0,1" bitfld.long 0x0 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress" newline bitfld.long 0x0 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only).Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished..This bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed" line.long 0x4 "FMC_MPADDR,ISP Multi-program Address Register" hexmask.long 0x4 0.--31. 1. "MPADDR,ISP Multi-word Program Address.MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1..MPADDR will keep the final ISP address when ISP multi-word program is complete." endif tree.end sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) tree "GCR (System Global Control Registers)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "PDID,Part Device Identification Number Register" hexmask.long 0x0 0.--31. 1. "PDID,Product Device Identification Number.This register reflects the device part number code. Software can read this register to identify which device is used." group.long 0x4++0xB line.long 0x0 "RSTSRC,System Reset Source Register" bitfld.long 0x0 7. "RSTS_CPU,CPU Reset Flag.The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC)..Note: Software can write 1 to clear this bit to 0." "0: No reset from CPU,1: Cortex-M0 core and FMC are reset by software.." sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x0 5. "RSTS_MCU,MCU Reset Flag.The RSTS_MCU flag is set by the 'reset signal' from the Cortex-M0 core to indicate the previous reset source..Note: Software can write 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 5. "RSTS_SYS,SYS Reset Flag.The RSTS_SYS flag Is set by the 'Reset Signal' from the Cortex-M0 core to indicate the previous reset source..Note: Write 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 5. "RSTS_SYS,SYS Reset Flag.The RSTS_SYS flag Is set by the 'Reset Signal' from the Cortex-M0 kernel to indicate the previous reset source..Note: Write 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." newline endif bitfld.long 0x0 4. "RSTS_BOD,Brown-out Detector Reset Flag.The RSTS_BOD flag is set by the 'reset signal' from the Brown-out Detector to indicate the previous reset source..Note: Software can write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.." sif (cpuis("NUC029?AN")) bitfld.long 0x0 3. "RSTS_LVR,The RSTS_LVR flag is set by the 'reset signal' from the Low-Voltage-Reset controller to indicate the previous reset source..Software can write 1 to clear this bit to zero." "0: No reset from LVR,1: The LVR module had issued the reset signal to.." newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 3. "RSTS_LVR,Low Voltage Reset Flag.The RSTS_LVR flag is set by the 'Reset Signal' from the Low-Voltage-Reset controller to indicate the previous reset source..Note: Write 1 to clear this bit to 0." "0: No reset from LVR,1: The LVR controller had issued the reset signal.." newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 3. "RSTS_LVR,Low Voltage Reset Flag.The RSTS_LVR flag is set by the 'Reset Signal' from the Low-Voltage-Reset controller to indicate the previous reset source..Note: Write 1 to clear this bit to 0." "0: No reset from LVR,1: The LVR controller had issued the reset signal.." newline endif bitfld.long 0x0 2. "RSTS_WDT,Watchdog Reset Flag.The RSTS_WDT flag is set by the 'reset signal' from the Watchdog timer to indicate the previous reset source..Note: Software can write 1 to clear this bit to 0." "0: No reset from Watchdog timer,1: The Watchdog timer had issued the reset signal.." newline bitfld.long 0x0 1. "RSTS_RESET,Reset Pin Reset Flag.The RSTS_RESET flag is set by the 'reset signal' from the /RESET pin to indicate the previous reset source..Note: Software can write 1 to clear this bit to 0." "0: No reset from pin /RESET pin,1: The /RESET pin had issued the reset signal to.." bitfld.long 0x0 0. "RSTS_POR,Power-on Reset Flag.The RSTS_POR flag is set by the 'reset signal' which is from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source..Note: Software can write 1 to clear this bit to 0." "0: No reset from POR or CHIP_RST,1: Power-on-Reset (POR) or CHIP_RST had issued the.." line.long 0x4 "IPRSTC1,Peripheral Reset Control Resister 1" sif (cpuis("NUC029?AN")) bitfld.long 0x4 4. "DIV_RST,DIV Controller Reset (write-protection bit).Set this bit to 1 will generate a reset signal to the DIVIDER. User need to set this bit to 0 to release from the reset state..This bit is the protected bit It means programming this bit needs to.." "0: DIVIDER controller normal operation,1: DIVIDER controller reset" bitfld.long 0x4 3. "EBI_RST,EBI Controller Reset (write-protected).Set these bit '1' will generate a reset signal to the EBI. User need to set this bit to '0' to release from the reset state" "0: EBI controller normal operation,1: EBI controller reset" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 3. "EBI_RST,EBI Controller Reset (Write-protection Bit).Set this bit to 1 will generate a reset signal to the EBI. User need to set this bit to 0 to release from the reset state..This bit is the protected bit It means programming this bit needs to write.." "0: EBI controller normal operation,1: EBI controller reset" bitfld.long 0x4 2. "PDMA_RST,PDMA Controller Reset (Write Protect).Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state..Note1: This bit is the protected bit and programming it needs to write '59h' .." "0: PDMA controller normal operation,1: PDMA controller reset" newline endif bitfld.long 0x4 1. "CPU_RST,CPU Kernel Reset.Setting this bit will reset the CPU kernel and this bit will automatically return to 0 after the 2 clock cycles..Note: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address.." "0: CPU normal operation,1: Reset CPU Kernel" bitfld.long 0x4 0. "CHIP_RST,CHIP One-shot Reset (Write Protect).Setting this bit will reset the CHIP including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles..The CHIP_RST is the same as the POR reset and all the.." "0: Chip normal operation,1: CHIP one-shot reset" line.long 0x8 "IPRSTC2,Peripheral Reset Control Resister 2" bitfld.long 0x8 28. "ADC_RST,ADC Controller Reset" "0: ADC module normal operation,1: ADC module reset" sif (cpuis("NUC029?EE")) bitfld.long 0x8 27. "USBD_RST,USB Device Controller Reset" "0: USB device controller normal operation,1: USB device controller reset" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "ACMPB_RST,Analog Comparator 1 Controller Reset" "0: Analog Comparator controller 1 normal operation,1: Analog Comparator controller 1 reset" newline endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x8 22. "ACMP_RST,ACMP Controller Reset" "0: ACMP module normal operation,1: ACMP module reset" newline bitfld.long 0x8 8. "I2C_RST,I2C Controller Reset" "0: I2C module normal operation,1: I2C module reset" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 21. "PWM47_RST,PWM4~7 controller Reset" "0: PWM4~7 controller normal operation,1: PWM4~7 controller reset" bitfld.long 0x8 20. "PWM03_RST,PWM0~3 controller Reset" "0: PWM0~3 controller normal operation,1: PWM0~3 controller reset" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 21. "PWM45_RST,PWM45 Controller Reset" "0: PWM45 controller normal operation,1: PWM45 controller reset" newline bitfld.long 0x8 20. "PWM03_RST,PWM03 Controller Reset" "0: PWM03 controller normal operation,1: PWM03 controller reset" endif sif (cpuis("NUC029?AE")) bitfld.long 0x8 20. "PWM_RST,PWM Controller Reset" "0: PWM module normal operation,1: PWM module reset" newline bitfld.long 0x8 16. "UART_RST,UART Controller Reset" "0: UART module normal operation,1: UART module reset" bitfld.long 0x8 12. "SPI_RST,SPI Controller Reset" "0: SPI module normal operation,1: SPI module reset" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 18. "UART2_RST,UART2 Controller Reset ." "0: UART2 controller normal operation,1: UART2 controller reset" newline bitfld.long 0x8 17. "UART1_RST,UART1 Controller Reset." "0: UART1 controller normal operation,1: UART1 controller reset" bitfld.long 0x8 16. "UART0_RST,UART0 Controller Reset." "0: UART0 controller normal operation,1: UART0 controller reset" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 18. "UART2_RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset" newline bitfld.long 0x8 17. "UART1_RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset" bitfld.long 0x8 16. "UART0_RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 17. "UART1_RST,UART1 controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset" bitfld.long 0x8 16. "UART0_RST,UART0 controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 13. "SPI1_RST,SPI1 controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset" bitfld.long 0x8 12. "SPI0_RST,SPI0 controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 13. "SPI1_RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset" bitfld.long 0x8 12. "SPI0_RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 12. "SPI0_RST,SPI0 Controller Reset." "0: SPI0 controller normal operation,1: SPI0 controller reset" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 9. "I2C1_RST,I2C1 controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 9. "I2C1_RST,I2C1 Controller Reset." "0: I2C1 controller normal operation,1: I2C1 controller reset" bitfld.long 0x8 8. "I2C0_RST,I2C0 Controller Reset." "0: I2C0 controller normal operation,1: I2C0 controller reset" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 9. "I2C1_RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset" bitfld.long 0x8 8. "I2C0_RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 5. "TMR3_RST,Timer3 controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset" bitfld.long 0x8 4. "TMR2_RST,Timer2 controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x8 5. "TMR3_RST,Timer3 Controller Reset." "0: Timer3 controller normal operation,1: Timer3 controller reset" bitfld.long 0x8 4. "TMR2_RST,Timer2 Controller Reset." "0: Timer2 controller normal operation,1: Timer2 controller reset" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x8 5. "TMR3_RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset" bitfld.long 0x8 4. "TMR2_RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset" newline endif bitfld.long 0x8 3. "TMR1_RST,Timer1 Controller Reset" "0: Timer1 module normal operation,1: Timer1 module reset" bitfld.long 0x8 2. "TMR0_RST,Timer0 Controller Reset" "0: Timer0 module normal operation,1: Timer0 module reset" newline bitfld.long 0x8 1. "GPIO_RST,GPIO (P0~P5) Controller Reset" "0: GPIO module normal operation,1: GPIO module reset" sif (cpuis("NUC029?DE")) group.long 0x10++0x3 line.long 0x0 "IPRSTC3,Peripheral Reset Control Register 3" bitfld.long 0x0 19. "BPWM1_RST,BPWM1 Controller Reset." "0: BPWM1 controller normal operation,1: BPWM1 controller reset" bitfld.long 0x0 18. "BPWM0_RST,BPWM0 Controller Reset." "0: BPWM0 controller normal operation,1: BPWM0 controller reset" newline bitfld.long 0x0 17. "PWM1_RST,PWM1 Controller Reset." "0: PWM1 controller normal operation,1: PWM1 controller reset" bitfld.long 0x0 16. "PWM0_RST,PWM0 Controller Reset." "0: PWM0 controller normal operation,1: PWM0 controller reset" newline bitfld.long 0x0 10. "UART5_RST,UART5 Controller Reset." "0: UART5 controller normal operation,1: UART5 controller reset" bitfld.long 0x0 9. "UART4_RST,UART4 Controller Reset." "0: UART4 controller normal operation,1: UART4 controller reset" newline bitfld.long 0x0 8. "UART3_RST,UART3 Controller Reset." "0: UART3 controller normal operation,1: UART3 controller reset" group.long 0x24++0x7 line.long 0x0 "PORCR,Power-on-reset Controller Register" hexmask.long.word 0x0 0.--15. 1. "POR_DIS_CODE,Power-On-Reset Enable Bit (Write Protect).When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.." line.long 0x4 "VREFCR,VREF Controller Register" bitfld.long 0x4 4. "ADC_VREFSEL,ADC VREF Path Control (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: ADC VREF is from VREF pin,1: ADC VREF is from AVDD" group.long 0x30++0x17 line.long 0x0 "GPA_MFP,GPIOA Multiple Function and Input Type Control Register" hexmask.long.word 0x0 16.--31. 1. "GPA_TYPEn,Trigger Function Selection." bitfld.long 0x0 15. "GPA_MFP15,PA.15 Pin Function Selection.Bit GPA_MFP15 determines the PA.15 function.." "0: GPIO function is selected,1: PWM0_CH3 function is selected" newline bitfld.long 0x0 14. "GPA_MFP14,PA.14 Pin Function Selection.Bit GPA_MFP14 determines the PA.14 function.." "0: GPIO function is selected,1: PWM0_CH2 function is selected" bitfld.long 0x0 13. "GPA_MFP13,PA.13 Pin Function Selection.Bits PA13_UR5TXD (ALT_MFP4[9]) and GPA_MFP13 determine the PA.13 function..(PA13_UR5TXD GPA_MFP13) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 12. "GPA_MFP12,PA.12 Pin Function Selection.Bits PA12_UR5RXD (ALT_MFP4[8]) and GPA_MFP12 determine the PA.12 function..(PA12_UR5RXD GPA_MFP12) value and function mapping is as following list.." "0,1" bitfld.long 0x0 11. "GPA_MFP11,PA.11 Pin Function Selection.Bits PA11_PWM13 (ALT_MFP3[9]) and GPA_MFP11 determine the PA.11 function..(PA11_PWM13 GPA_MFP11) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 10. "GPA_MFP10,PA.10 Pin Function Selection.Bits PA10_PWM12 (ALT_MFP3[8]) and GPA_MFP10 determine the PA.10 function..(PA10_PWM12 GPA_MFP10) value and function mapping is as following list.." "0,1" bitfld.long 0x0 9. "GPA_MFP9,PA.9 Pin Function Selection.Bits PA9_UR1CTS (ALT_MFP4[1]) and GPA_MFP9 determine the PA.9 function..(PA9_UR1CTS GPA_MFP9) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 8. "GPA_MFP8,PA.8 Pin Function Selection.Bits PA8_UR1RTS (ALT_MFP4[0]) and GPA_MFP8 determine the PA.8 function..(PA8_UR1RTS GPA_MFP8) value and function mapping is as following list.." "0,1" bitfld.long 0x0 7. "GPA_MFP7,PA.7 Pin Function Selection.Bits PA7_VREF (ALT_MFP4[14]) and GPA_MFP7 determine the PA.7 function..(PA7_VREF GPA_MFP7) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 6. "GPA_MFP6,PA.6 Pin Function Selection.Bits PA6_UR3TXD (ALT_MFP4[5]) and GPA_MFP6 determine the PA.6 function..(PA6_UR3TXD GPA_MFP6) value and function mapping is as following list.." "0,1" bitfld.long 0x0 5. "GPA_MFP5,PA.5 Pin Function Selection.Bits PA5_UR3RXD (ALT_MFP4[4]) and GPA_MFP5 determine the PA.5 function..(PA5_UR3RXD GPA_MFP5) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 4. "GPA_MFP4,PA.4 Pin Function Selection.Bit GPA_MFP4 determines the PA.4 function.." "0: GPIO function is selected,1: ADC4 function is selected" bitfld.long 0x0 3. "GPA_MFP3,PA.3 Pin Function Selection.Bits PA3_PWM11 (ALT_MFP3[7]) PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function..(PA3_PWM11 PA3_UR3RXD GPA_MFP3) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 2. "GPA_MFP2,PA.2 Pin Function Selection.Bits PA2_PWM10 (ALT_MFP3[6]) PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function..(PA2_PWM10 PA2_UR3TXD GPA_MFP2) value and function mapping is as following list.." "0,1" bitfld.long 0x0 1. "GPA_MFP1,PA.1 Pin Function Selection.Bits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function..(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is as following.." "0,1" newline bitfld.long 0x0 0. "GPA_MFP0,PA.0 Pin Function Selection.Bits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function..(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is as following.." "0,1" line.long 0x4 "GPB_MFP,GPIOB Multiple Function and Input Type Control Register" hexmask.long.word 0x4 16.--31. 1. "GPB_TYPEn,Trigger Function Selection." bitfld.long 0x4 15. "GPB_MFP15,PB.15 Pin Function Selection.Bits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function..(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as following.." "0,1" newline bitfld.long 0x4 14. "GPB_MFP14,PB.14 Pin Function Selection.Bit GPB_MFP14 determines the PB.14 function.." "0: GPIO function is selected,1: INT0 function is selected" bitfld.long 0x4 12. "GPB_MFP12,PB.12 Pin Function Selection.Bits PB12_BPWM13 (ALT_MFP3[21]) and GPB_MFP12 determine the PB.12 function..(PB12_BPWM13 GPB_MFP12) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 11. "GPB_MFP11,PB.11 Pin Function Selection.Bits PB11_PWM04 (ALT_MFP3[24]) and GPB_MFP11 determine the PB.11 function..(PB11_PWM04 GPB_MFP11) value and function mapping is as following list.." "0,1" bitfld.long 0x4 10. "GPB_MFP10,PB.10 Pin Function Selection.Bit GPB_MFP10 determines the PB.10 function.." "0: GPIO function is selected,1: TM2 function is selected" newline bitfld.long 0x4 9. "GPB_MFP9,PB.9 Pin Function Selection.Bit GPB_MFP9 determines the PB.9 function.." "0: GPIO function is selected,1: TM1 function is selected" bitfld.long 0x4 8. "GPB_MFP8,PB.8 Pin Function Selection.Bits PB8_BPWM12 (ALT_MFP3[20]) PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function..(PB8_BPWM12 PB8_CLKO GPB_MFP8) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 7. "GPB_MFP7,PB.7 Pin Function Selection.Bit GPB_MFP7 determines the PB.7 function.." "0: GPIO function is selected,1: UART1_nCTS function is selected" bitfld.long 0x4 6. "GPB_MFP6,PB.6 Pin Function Selection.Bit GPB_MFP6 determines the PB.6 function.." "0: GPIO function is selected,1: UART1_nRTS function is selected" newline bitfld.long 0x4 5. "GPB_MFP5,PB 5 Pin Function Selection.Bit GPB_MFP5 determines the PB.5 function.." "0: GPIO function is selected,1: UART1_TXD function is selected" bitfld.long 0x4 4. "GPB_MFP4,PB.4 Pin Function Selection.Bit GPB_MFP4 determines the PB.4 function.." "0: GPIO function is selected,1: UART1_RXD function is selected" newline bitfld.long 0x4 3. "GPB_MFP3,PB.3 Pin Function Selection.Bits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function..(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as following list.." "0,1" bitfld.long 0x4 2. "GPB_MFP2,PB.2 Pin Function Selection.Bits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function..(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 1. "GPB_MFP1,PB.1 Pin Function Selection.Bit GPB_MFP1 determines the PB.1 function.." "0: GPIO function is selected,1: UART0_TXD function is selected" bitfld.long 0x4 0. "GPB_MFP0,PB.0 Pin Function Selection.Bit GPB_MFP0 determines the PB.0 function.." "0: GPIO function is selected,1: UART0_RXD function is selected" line.long 0x8 "GPC_MFP,GPIOC Multiple Function and Input Type Control Register" hexmask.long.word 0x8 16.--31. 1. "GPC_TYPEn,Trigger Function Selection." bitfld.long 0x8 11. "GPC_MFP11,PC.11 Pin Function Selection.Bit GPC_MFP11 determines the PC.11 function.." "0: GPIO function is selected,1: PWM1_BRAKE1 function is selected" newline bitfld.long 0x8 10. "GPC_MFP10,PC.10 Pin Function Selection.Bit GPC_MFP10 determines the PC.10 function.." "0: GPIO function is selected,1: PWM1_BRAKE0 function is selected" bitfld.long 0x8 9. "GPC_MFP9,PC.9 Pin Function Selection.Bit GPC_MFP9 determines the PC.9 function.." "0: GPIO function is selected,1: PWM0_BRAKE1 function is selected" newline bitfld.long 0x8 8. "GPC_MFP8,PC.8 Pin Function Selection.Bit GPC_MFP8 determines the PC.8 function.." "0: GPIO function is selected,1: PWM0_BRAKE0 function is selected" bitfld.long 0x8 7. "GPC_MFP7,PC.7 Pin Function Selection.Bits PC7_PWM0BK1 (ALT_MFP3[29]) PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function..(PC7_PWM0BK1 PC7_I2C0SCL GPC_MFP7) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 6. "GPC_MFP6,PC.6 Pin Function Selection.Bits PC6_PWM0BK0 (ALT_MFP3[28]) PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function..(PC6_PWM0BK0 PC6_I2C0SDA GPC_MFP6) value and function mapping is as following list.." "0,1" bitfld.long 0x8 3. "GPC_MFP3,PC.3 Pin Function Selection.Bits PC3_BPWM03 (ALT_MFP3[15]) and GPC_MFP3 determine the PC.3 function..(PC3_BPWM03 GPC_MFP3) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 2. "GPC_MFP2,PC.2 Pin Function Selection.Bits PC2_BPWM02 (ALT_MFP3[14]) and GPC_MFP2 determine the PC.2 function..(PC2_BPWM02 GPC_MFP2) value and function mapping is as following list.." "0,1" bitfld.long 0x8 1. "GPC_MFP1,PC.1 Pin Function Selection.Bits PC1_BPWM01 (ALT_MFP3[13]) and GPC_MFP1 determine the PC.1 function..(PC1_BPWM01 GPC_MFP1) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 0. "GPC_MFP0,PC.0 Pin Function Selection.Bits PC0_BPWM00 (ALT_MFP3[12]) and GPC_MFP0 determine the PC.0 function..(PC0_BPWM00 GPC_MFP0) value and function mapping is as following list.." "0,1" line.long 0xC "GPD_MFP,GPIOD Multiple Function and Input Type Control Register" hexmask.long.word 0xC 16.--31. 1. "GPD_TYPEn,Trigger Function Selection." bitfld.long 0xC 15. "GPD_MFP15,PD.15 Pin Function Selection .Bits PD15_BPWM04 (ALT_MFP3[16]) and GPD_MFP15 determine the PD.15 function..(PD15_BPWM04 GPD_MFP15) value and function mapping is as following list.." "0,1" newline bitfld.long 0xC 14. "GPD_MFP14,PD.14 Pin Function Selection .Bits PD14_BPWM05 (ALT_MFP3[17]) and GPD_MFP14 determine the PD.14 function..(PD14_BPWM05 GPD_MFP14) value and function mapping is as following list.." "0,1" bitfld.long 0xC 7. "GPD_MFP7,PD.7 Pin Function Selection .Bits PD7_BPWM10 (ALT_MFP3[18]) and GPD_MFP7 determine the PD.7 function..(PD7_BPWM10 GPD_MFP7) value and function mapping is as following list.." "0,1" newline bitfld.long 0xC 6. "GPD_MFP6,PD.6 Pin Function Selection.Bits PD6_BPWM11 (ALT_MFP3[19]) and GPD_MFP6 determine the PD.6 function..(PD6_BPWM11 GPD_MFP6) value and function mapping is as following list.." "0,1" line.long 0x10 "GPE_MFP,GPIOE Multiple Function and Input Type Control Register" bitfld.long 0x10 21. "GPE_TYPE5,Trigger Function Selection." "0: GPIOE[5] I/O input Schmitt Trigger function..,1: GPIOE[5] I/O input Schmitt Trigger function.." bitfld.long 0x10 5. "GPE_MFP5,PE.5 Pin Function Selection.Bits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function..(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list.." "0,1" line.long 0x14 "GPF_MFP,GPIOF Multiple Function and Input Type Control Register" hexmask.long.word 0x14 16.--24. 1. "GPF_TYPEn,Trigger Function Selection." bitfld.long 0x14 8. "GPF_MFP8,PF.8 Pin Function Selection.Bit PF8_BPWM14 (ALT_MFP3[22]) GPF_MFP8 determines the PF.8 function..(PF8_BPWM14 GPF_MFP8) value and function mapping is as following list.." "0,1" newline bitfld.long 0x14 7. "GPF_MFP7,PF.7 Pin Function Selection.Bit GPF_MFP7 determines the PF.7 function.." "0: GPIO function is selected,1: ICE_DAT function is selected" bitfld.long 0x14 6. "GPF_MFP6,PF.6 Pin Function Selection.Bit GPF_MFP6 determines the PF.6 function.." "0: GPIO function is selected,1: ICE_CLK function is selected" newline bitfld.long 0x14 5. "GPF_MFP5,PF.5 Pin Function Selection.Bits PF5_PWM15 (ALT_MFP3[11]) and GPF_MFP5 determine the PF.5 function..(PF5_PWM15 GPF_MFP5) value and function mapping is as following list.." "0,1" bitfld.long 0x14 4. "GPF_MFP4,PF.4 Pin Function Selection .Bits PF4_PWM14 (ALT_MFP3[10]) and GPF_MFP4 determine the PF.4 function..(PF4_PWM14 GPF_MFP4) value and function mapping is as following list.." "0,1" newline bitfld.long 0x14 1. "GPF_MFP1,PF.1 Pin Function Selection .Bit GPF_MFP1 determine the PF.1 function..Note: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])." "0: GPIO function is selected,1: XT1_IN function is selected" bitfld.long 0x14 0. "GPF_MFP0,PF.0 Pin Function Selection.Bit GPF_MFP0 determines the PF.0 function..Note: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])." "0: GPIO function is selected,1: XT1_OUT function is selected" group.long 0x50++0x3 line.long 0x0 "ALT_MFP,Alternative Multiple Function Pin Control Register" bitfld.long 0x0 29. "PB8_CLKO,PB.8 Pin Alternative Function Selection.Bits PB8_BPWM12 (ALT_MFP3[20]) PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function..(PB8_BPWM12 PB8_CLKO GPB_MFP8) value and function mapping is as following list.." "0,1" bitfld.long 0x0 27. "PB3_T3EX,PB.3 Pin Alternative Function Selection.Bits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function..(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as.." "0,1" newline bitfld.long 0x0 26. "PB2_T2EX,PB.2 Pin Alternative Function Selection.Bits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function..(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as.." "0,1" bitfld.long 0x0 25. "PE5_T1EX,PE.5 Pin Alternative Function Selection.Bits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function..(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list.." "0,1" newline bitfld.long 0x0 24. "PB15_T0EX,PB.15 Pin Alternative Function Selection.Bits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function..(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is.." "0,1" group.long 0x5C++0xB line.long 0x0 "ALT_MFP2,Alternative Multiple Function Pin Control Register 2" bitfld.long 0x0 5. "PB3_TM3,PB.3 Pin Alternative Function Selection.Bits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function..(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as.." "0,1" bitfld.long 0x0 4. "PB2_TM2,PB.2 Pin Alternative Function Selection.Bits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function..(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as.." "0,1" newline bitfld.long 0x0 3. "PE5_TM1,PE.5 Pin Alternative Function Selection.Bits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function..(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list.." "0,1" bitfld.long 0x0 2. "PB15_TM0,PB.15 Pin Alternative Function Selection.Bits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function..(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is.." "0,1" line.long 0x4 "ALT_MFP3,Alternative Multiple Function Pin Control Register 3" bitfld.long 0x4 31. "PB2_PWM1BK1,PB.2 Pin Alternative Function Selection.Bits PB2_TM2 (ALT_MFP2[4]) PB2_PWM1BK1 (ALT_MFP3[31]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function..(PB2_TM2 PB2_PWM1BK1 PB2_T2EX GPB_MFP2) value and function mapping is as.." "0,1" bitfld.long 0x4 30. "PB3_PWM1BK0,PB.3 Pin Alternative Function Selection.Bits PB3_TM3 (ALT_MFP2[5]) PB3_PWM1BK0 (ALT_MFP3[30]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function..(PB3_TM3 PB3_PWM1BK0 PB3_T3EX GPB_MFP3) value and function mapping is as.." "0,1" newline bitfld.long 0x4 29. "PC7_PWM0BK1,PC.7 Pin Alternative Function Selection.Bits PC7_PWM0BK1 (ALT_MFP3[29]) PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function..(PC7_PWM0BK1 PC7_I2C0SCL GPC_MFP7) value and function mapping is as following list.." "0,1" bitfld.long 0x4 28. "PC6_PWM0BK0,PC.6 Pin Alternative Function Selection.Bits PC6_PWM0BK0 (ALT_MFP3[28]) PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function..(PC6_PWM0BK0 PC6_I2C0SDA GPB_MFP6) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 24. "PB11_PWM04,PB.11 Pin Alternative Function Selection.Bits PB11_PWM04 (ALT_MFP3[24]) and GPB_MFP11 determine the PB.11 function..(PB11_PWM04 GPB_MFP11) value and function mapping is as following list.." "0,1" bitfld.long 0x4 23. "PB15_BPWM15,PB.15 Pin Function Selection.Bits PB15_BPWM15 (ALT_MFP3[23]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function..(PB15_BPWM15 PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as.." "0,1" newline bitfld.long 0x4 22. "PF8_BPWM14,PF.8 Pin Function Selection.Bit PF8_BPWM14 (ALT_MFP3[22]) GPF_MFP8 determines the PF.8 function..(PF8_BPWM14 GPF_MFP8) value and function mapping is as following list.." "0,1" bitfld.long 0x4 21. "PB12_BPWM13,PB.12 Pin Alternative Function Selection.Bits PB12_BPWM13 (ALT_MFP3[21]) and GPB_MFP12 determine the PB.12 function..(PB12_BPWM13 GPB_MFP12) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 20. "PB8_BPWM12,PB.8 Pin Alternative Function Selection.Bits PB8_BPWM12 (ALT_MFP3[20]) PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function..(PB8_BPWM12 PB8_CLKO GPB_MFP8) value and function mapping is as following list.." "0,1" bitfld.long 0x4 19. "PD6_BPWM11,PD.6 Pin Alternative Function Selection.Bits PD6_BPWM11 (ALT_MFP3[19]) and GPD_MFP6 determine the PD.6 function..(PD6_BPWM11 GPD_MFP6) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 18. "PD7_BPWM10,PD.7 Pin Alternative Function Selection .Bits PD7_BPWM10 (ALT_MFP3[18]) and GPD_MFP7 determine the PD.7 function..(PD7_BPWM10 GPD_MFP7) value and function mapping is as following list.." "0,1" bitfld.long 0x4 17. "PD14_BPWM05,PD.14 Pin Alternative Function Selection .Bits PD14_BPWM05 (ALT_MFP3[17]) and GPD_MFP14 determine the PD.14 function..(PD14_BPWM05 GPD_MFP14) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 16. "PD15_BPWM04,PD.15 Pin Alternative Function Selection .Bits PD15_BPWM04 (ALT_MFP3[16]) and GPD_MFP15 determine the PD.15 function..(PD15_BPWM04 GPD_MFP15) value and function mapping is as following list.." "0,1" bitfld.long 0x4 15. "PC3_BPWM03,PC.3 Pin Alternative Function Selection.Bits PC3_BPWM03 (ALT_MFP3[15]) and GPC_MFP3 determine the PC.3 function..(PC3_BPWM03 GPC_MFP3) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 14. "PC2_BPWM02,PC.2 Pin Alternative Function Selection.Bits PC2_BPWM02 (ALT_MFP3[14]) and GPC_MFP2 determine the PC.2 function..(PC2_BPWM02 GPC_MFP2) value and function mapping is as following list.." "0,1" bitfld.long 0x4 13. "PC1_BPWM01,PC.1 Pin Alternative Function Selection.Bits PC1_BPWM01 (ALT_MFP3[13]) and GPC_MFP1 determine the PC.1 function..(PC1_BPWM01 GPC_MFP1) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 12. "PC0_BPWM00,PC.0 Pin Alternative Function Selection.Bits PC0_BPWM00 (ALT_MFP3[12]) and GPC_MFP0 determine the PC.0 function..(PC0_BPWM00 GPC_MFP0) value and function mapping is as following list.." "0,1" bitfld.long 0x4 11. "PF5_PWM15,PF.5 Pin Alternative Function Selection.Bits PF5_PWM15 (ALT_MFP3[11]) and GPF_MFP5 determine the PF.5 function..(PF5_PWM15 GPF_MFP5) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 10. "PF4_PWM14,PF.4 Pin Alternative Function Selection .Bits PF4_PWM14 (ALT_MFP3[10]) and GPF_MFP4 determine the PF.4 function..(PF4_PWM14 GPF_MFP4) value and function mapping is as following list.." "0,1" bitfld.long 0x4 9. "PA11_PWM13,PA.11 Pin Alternative Function Selection.Bits PA11_PWM13 (ALT_MFP3[9]) and GPA_MFP11 determine the PA.11 function..(PA11_PWM13 GPA_MFP11) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 8. "PA10_PWM12,PA.10 Pin Alternative Function Selection.Bits PA10_PWM12 (ALT_MFP3[8]) and GPA_MFP10 determine the PA.10 function..(PA10_PWM12 GPA_MFP10) value and function mapping is as following list.." "0,1" bitfld.long 0x4 7. "PA3_PWM11,PA.3 Pin Alternative Function Selection.Bits PA3_PWM11 (ALT_MFP3[7]) PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function..(PA3_PWM11 PA3_UR3RXD GPA_MFP3) value and function mapping is as following list.." "0,1" newline bitfld.long 0x4 6. "PA2_PWM10,PA.2 Pin Alternative Function Selection.Bits PA2_PWM10 (ALT_MFP3[6]) PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function..(PA2_PWM10 PA2_UR3TXD GPA_MFP2) value and function mapping is as following list.." "0,1" bitfld.long 0x4 5. "PA1_PWM05,PA.1 Pin Alternative Function Selection.Bits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function..(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is.." "0,1" newline bitfld.long 0x4 4. "PA0_PWM04,PA.0 Pin Alternative Function Selection.Bits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function..(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is.." "0,1" line.long 0x8 "ALT_MFP4,Alternative Multiple Function Pin Control Register 4" bitfld.long 0x8 14. "PA7_VREF,PA.7 Pin Alternative Function Selection.Bits PA7_VREF (ALT_MFP4[14]) and GPA_MFP7 determine the PA.7 function..(PA7_VREF GPA_MFP7) value and function mapping is as following list.." "0,1" bitfld.long 0x8 13. "PA1_I2C1SDA,PA.1 Pin Alternative Function Selection.Bits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function..(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping.." "0,1" newline bitfld.long 0x8 12. "PA0_I2C1SCL,PA.0 Pin Alternative Function Selection.Bits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function..(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping.." "0,1" bitfld.long 0x8 11. "PC7_I2C0SCL,PC.7 Pin Alternative Function Selection.Bits PC7_PWM0BK1 (ALT_MFP3[29]) PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function..(PC7_PWM0BK1 PC7_I2C0SCL GPC_MFP7) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 10. "PC6_I2C0SDA,PC.6 Pin Alternative Function Selection.Bits PC6_PWM0BK0 (ALT_MFP3[28]) PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function..(PC6_PWM0BK0 PC6_I2C0SDA GPC_MFP6) value and function mapping is as following list.." "0,1" bitfld.long 0x8 9. "PA13_UR5TXD,PA.13 Pin Alternative Function Selection.Bits PA13_UR5TXD (ALT_MFP4[9]) and GPA_MFP13 determine the PA.13 function..(PA13_UR5TXD GPA_MFP13) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 8. "PA12_UR5RXD,PA.12 Pin Alternative Function Selection.Bits PA12_UR5RXD (ALT_MFP4[8]) and GPA_MFP12 determine the PA.12 function..(PA12_UR5RXD GPA_MFP12) value and function mapping is as following list.." "0,1" bitfld.long 0x8 7. "PA0_UR5TXD,PA.0 Pin Alternative Function Selection.Bits PA0_PWM04 (ALT_MFP3[4]) PA0_UR5TXD (ALT_MFP4[7]) PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function..(PA0_PWM04 PA0_UR5TXD PA0_I2C1SCL GPA_MFP0) value and function mapping is.." "0,1" newline bitfld.long 0x8 6. "PA1_UR5RXD,PA.1 Pin Alternative Function Selection.Bits PA1_PWM05 (ALT_MFP3[5]) PA1_UR5RXD (ALT_MFP4[6]) PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function..(PA1_PWM05 PA1_UR5RXD PA1_I2C1SDA GPA_MFP1) value and function mapping is.." "0,1" bitfld.long 0x8 5. "PA6_UR3TXD,PA.6 Pin Alternative Function Selection.Bits PA6_UR3TXD (ALT_MFP4[5]) and GPA_MFP6 determine the PA.6 function..(PA6_UR3TXD GPA_MFP6) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 4. "PA5_UR3RXD,PA.5 Pin Alternative Function Selection.Bits PA5_UR3RXD (ALT_MFP4[4]) and GPA_MFP5 determine the PA.5 function..(PA5_UR3RXD GPA_MFP5) value and function mapping is as following list.." "0,1" bitfld.long 0x8 3. "PA2_UR3TXD,PA.2 Pin Alternative Function Selection.Bits PA2_PWM10 (ALT_MFP3[6]) PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function..(PA2_PWM10 PA2_UR3TXD GPA_MFP2) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 2. "PA3_UR3RXD,PA.3 Pin Alternative Function Selection.Bits PA3_PWM11 (ALT_MFP3[7]) PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function..(PA3_PWM11 PA3_UR3RXD GPA_MFP3) value and function mapping is as following list.." "0,1" bitfld.long 0x8 1. "PA9_UR1CTS,PA.9 Pin Alternative Function Selection.Bits PA9_UR1CTS (ALT_MFP4[1]) and GPA_MFP9 determine the PA.9 function..(PA9_UR1CTS GPA_MFP9) value and function mapping is as following list.." "0,1" newline bitfld.long 0x8 0. "PA8_UR1RTS,PA.8 Pin Alternative Function Selection.Bits PA8_UR1RTS (ALT_MFP4[0]) and GPA_MFP8 determine the PA.8 function..(PA8_UR1RTS GPA_MFP8) value and function mapping is as following list.." "0,1" endif group.long 0x18++0x3 line.long 0x0 "BODCR,Brown-out Detector Control Register" sif (cpuis("NUC029?DE")) bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-Glitch Time Select (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?" endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 8.--10. "BODDGSEL,Brown-Out Detector Output De-Glitch Time Select (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register.." "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),?,?,?,?,?,?" newline bitfld.long 0x0 7. "LVR_EN,Low Voltage Reset Enable Bit (Write Protect).The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default..Note: This bit is the protected bit and programming it needs to.." "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 7. "LVR_EN,Low Voltage Reset Enable (write-protected).The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default." "0: Disabled Low Voltage Reset function,1: Enabled Low Voltage Reset function - After.." newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 7. "LVR_EN,Low Voltage Reset Enable Bit (Write Protect).The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default..Note: This bit is the protected bit and programming it needs to.." "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.." endif bitfld.long 0x0 6. "BOD_OUT,Brown-out Detector Output State" "0: Brown-out Detector status output is 0 the..,1: Brown-out Detector status output is 1 the.." newline bitfld.long 0x0 5. "BOD_LPM,Brown-Out Detector Low power Mode (Write Protect).The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1uA but slow the BOD response." "0: BOD operate in normal mode (default),1: Enable the BOD low power mode" bitfld.long 0x0 4. "BOD_INTF,Brown-out Detector Interrupt Flag" "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the AVDD is.." newline bitfld.long 0x0 3. "BOD_RSTEN,Brown-out Reset Enable Control (Initiated and Write-protected Bit).The default value is set by flash controller user configuration register config0 bit[20]..When the BOD_EN is enabled and the interrupt is asserted the interrupt will be kept.." "0: Brown-out 'INTERRUPT' function Enabled; when the..,1: Brown-out 'RESET' function Enabled; when the.." sif (cpuis("NUC029?DE")) bitfld.long 0x0 1.--2. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Write Protect).The default value is set by flash memory controller user configuration register CBOV (CONFIG0[22:21]) bit..Note: This bit is the protected bit. It means programming this needs to.." "0: Brown-out voltage is 2.2V,1: Brown-out voltage is 2.7V,?,?" newline bitfld.long 0x0 0. "BOD_EN,Brown-Out Detector Enable Bit (Write Protect).The default value is set by flash memory controller user configuration register CBODEN (CONFIG0[23]) bit..Note: This bit is the protected bit. It means programming this needs to write '59h' '16h' .." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled" endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x0 1.--2. "BOD_VL,Brown-out Detector Threshold Voltage Selection (Initiated Write-protected Bit)" "0,1,2,3" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 1.--2. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Write Protect).The default value is set by flash momory controller user configuration register CBOV(CONFIG0[22:21]) bit ..Note: This bit is the protected bit. It means programming this needs to.." "0: Brown-out voltage is 2.2V,1: Brown-out voltage is 2.7V,?,?" newline bitfld.long 0x0 0. "BOD_EN,Brown-Out Detector Enable Bit (Write Protect).The default value is set by flash memory controller user configuration register CBODEN(CONFIG0[23]) bit..Note: This bit is the protected bit. It means programming this needs to write '59h' '16h' .." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled" endif sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "BOD_VL_EXT,Brown-out Detector Selection Extension (Initiated Write-protected Bit)" "0: Brown-out detector threshold voltage is selected..,1: Brown-out detector threshold voltage is selected.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "BOD_EN,Brown-Out Detector Enable (write-protected).The default value is set by flash controller user configuration register config0 bit[23]" "0: Brown-Out Detector function is disabled,1: Brown-Out Detector function is enabled" endif sif (cpuis("NUC029?AN")) group.long 0x1C++0x3 line.long 0x0 "TEMPCR,Temperature Sensor Control Register" bitfld.long 0x0 0. "VTEMP_EN,Temperature sensor Enable.This bit is used to enable/disable temperature sensor function..After this bit is set to 1 the value of temperature can get from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer.." "0: Disabled temperature sensor function (default),1: Enabled temperature sensor function" group.long 0x24++0x7 line.long 0x0 "PORCR,Power-On-Reset Controller Register" hexmask.long.word 0x0 0.--15. 1. "POR_DIS_CODE,Power-On-Reset enable control (write-protected).When power on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. If set the POR_DIS_CODE equal to 0x5AA5 the.." line.long 0x4 "GPIO_2CKn,GPIO 2CK Strong Pull High Controller Register" bitfld.long 0x4 0. "GPIO_2CKn,GPIO two clock strong pull high disable" "0: GPIO two clock strong pull high is enabled if..,1: GPIO two clock strong pull high is disabled if.." endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) group.long 0x30++0x13 line.long 0x0 "P0_MFP,P0 Multiple Function and Input Type Control Register" sif (cpuis("NUC029?AN")) bitfld.long 0x0 25. "P0_ALT11,P0.1 alternate function Selection1.The pin function of P0.1 depends on P0_MFP[1] P0_ALT[1] and P0_ALT1[1]..Refer to P0_ALT[1] for details descriptions." "0,1" bitfld.long 0x0 24. "P0_ALT10,P0.0 alternate function Selection1.The pin function of P0.0 depends on P0_MFP[0] P0_ALT[0] and P0_ALT1[0]..Refer to P0_ALT[0] for details descriptions." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "P0_TYPEn,P0[7:0] input Schmitt Trigger function Enable" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 16.--23. 1. "P0_TYPE,P0[7:0] TTL or Schmitt Trigger Function Enable Control" newline endif bitfld.long 0x0 15. "P0_ALT7,P0.7 Alternate Function Selection" "0,1" bitfld.long 0x0 14. "P0_ALT6,P0.6 Alternate Function Selection" "0,1" newline bitfld.long 0x0 13. "P0_ALT5,P0.5 Alternate Function Selection" "0,1" bitfld.long 0x0 12. "P0_ALT4,P0.4 Alternate Function Selection" "0,1" newline sif (cpuis("NUC029?AN")) bitfld.long 0x0 11. "P0_ALT3,P0.3 alternate function Selection" "0,1" bitfld.long 0x0 10. "P0_ALT2,P0.2 alternate function Selection" "0,1" newline endif bitfld.long 0x0 9. "P0_ALT1,P0.1 Alternate Function Selection" "0,1" bitfld.long 0x0 8. "P0_ALT0,P0.0 Alternate Function Selection" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "P0_MFP,P0 Multiple Function Selection.The pin function of P0 depends on P0_MFP and P0_ALT..Refer to P0_ALT Description for details." line.long 0x4 "P1_MFP,P1 Multiple Function and Input Type Control Register" sif (cpuis("NUC029?AE")) hexmask.long.byte 0x4 16.--23. 1. "P1_TYPE,P1[7:0] TTL or Schmitt Trigger Function Enable Control" newline endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x4 16.--23. 1. "P1_TYPEn,P1[7:0] input Schmitt Trigger function Enable" newline bitfld.long 0x4 15. "P1_ALT7,P1.7 alternate function Selection" "0,1" bitfld.long 0x4 14. "P1_ALT6,P1.6 alternate function Selection" "0,1" newline endif bitfld.long 0x4 13. "P1_ALT5,P1.5 Alternate Function Selection" "0,1" bitfld.long 0x4 12. "P1_ALT4,P1.4 Alternate Function Selection" "0,1" newline bitfld.long 0x4 11. "P1_ALT3,P1.3 Alternate Function Selection" "0,1" bitfld.long 0x4 10. "P1_ALT2,P1.2 Alternate Function Selection" "0,1" newline sif (cpuis("NUC029?AN")) bitfld.long 0x4 9. "P1_ALT1,P1.1 alternate function Selection" "0,1" endif bitfld.long 0x4 8. "P1_ALT0,P1.0 Alternate Function Selection" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "P1_MFP,P1 Multiple Function Selection.The pin function of P1 depends on P1_MFP and P1_ALT..Refer to P1_ALT Description for details." line.long 0x8 "P2_MFP,P2 Multiple Function and Input Type Control Register" sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 16.--23. 1. "P2_TYPE,P2[7:0] TTL or Schmitt Trigger Function Enable Control" endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x8 16.--23. 1. "P2_TYPEn,P2[7:0] input Schmitt Trigger function Enable" newline bitfld.long 0x8 15. "P2_ALT7,P2.7 alternate function Selection" "0,1" endif bitfld.long 0x8 14. "P2_ALT6,P2.6 Alternate Function Selection" "0,1" newline bitfld.long 0x8 13. "P2_ALT5,P2.5 Alternate Function Selection" "0,1" bitfld.long 0x8 12. "P2_ALT4,P2.4 Alternate Function Selection" "0,1" newline bitfld.long 0x8 11. "P2_ALT3,P2.3 Alternate Function Selection" "0,1" bitfld.long 0x8 10. "P2_ALT2,P2.2 Alternate Function Selection" "0,1" newline sif (cpuis("NUC029?AN")) bitfld.long 0x8 9. "P2_ALT1,P2.1 alternate function Selection" "0,1" bitfld.long 0x8 8. "P2_ALT0,P2.0 alternate function Selection" "0,1" newline endif hexmask.long.byte 0x8 0.--7. 1. "P2_MFP,P2 Multiple Function Selection.The pin function of P2 depends on P2_MFP and P2_ALT..Refer to P2_ALT Description for details." line.long 0xC "P3_MFP,P3 Multiple Function and Input Type Control Register" sif (cpuis("NUC029?AE")) bitfld.long 0xC 24. "P32CPP1,P3.2 Alternate Function Selection Extension" "0: P3.2 is set by P3_ALT[2] and P3_MFP[2],1: P3.2 is set to CPP1 of ACMP1" hexmask.long.byte 0xC 16.--23. 1. "P3_TYPE,P3[7:0] TTL or Schmitt Trigger Function Enable Control" newline endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0xC 16.--23. 1. "P3_TYPEn,P3[7:0] input Schmitt Trigger function Enable" bitfld.long 0xC 15. "P3_ALT7,P3.7 alternate function Selection" "0,1" newline endif bitfld.long 0xC 14. "P3_ALT6,P3.6 Alternate Function Selection" "0,1" bitfld.long 0xC 13. "P3_ALT5,P3.5 Alternate Function Selection" "0,1" newline bitfld.long 0xC 12. "P3_ALT4,P3.4 Alternate Function Selection" "0,1" sif (cpuis("NUC029?AN")) bitfld.long 0xC 11. "P3_ALT3,P3.3 alternate function Selection" "0,1" newline endif bitfld.long 0xC 10. "P3_ALT2,P3.2 Alternate Function Selection" "0,1" newline bitfld.long 0xC 9. "P3_ALT1,P3.1 Alternate Function Selection" "0,1" newline bitfld.long 0xC 8. "P3_ALT0,P3.0 Alternate Function Selection" "0,1" hexmask.long.byte 0xC 0.--7. 1. "P3_MFP,P3 Multiple Function Selection.The pin function of P3 depends on P3_MFP and P3_ALT..Refer to P3_ALT Description for details." line.long 0x10 "P4_MFP,P4 Multiple Function and Input Type Control Register" sif (cpuis("NUC029?AE")) hexmask.long.byte 0x10 16.--23. 1. "P4_TYPE,P4[7:0] TTL or Schmitt Trigger Function Enable Control" newline endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x10 16.--23. 1. "P4_TYPEn,P4[7:0] input Schmitt Trigger function Enable" newline endif bitfld.long 0x10 15. "P4_ALT7,P4.7 Alternate Function Selection" "0,1" bitfld.long 0x10 14. "P4_ALT6,P4.6 Alternate Function Selection" "0,1" newline sif (cpuis("NUC029?AN")) bitfld.long 0x10 13. "P4_ALT5,P4.5 alternate function Selection" "0,1" bitfld.long 0x10 12. "P4_ALT4,P4.4 alternate function Selection" "0,1" newline bitfld.long 0x10 11. "P4_ALT3,P4.3 alternate function Selection" "0,1" bitfld.long 0x10 10. "P4_ALT2,P4.2 alternate function Selection" "0,1" newline bitfld.long 0x10 9. "P4_ALT1,P4.1 alternate function Selection" "0,1" bitfld.long 0x10 8. "P4_ALT0,P4.0 alternate function Selection" "0,1" newline endif hexmask.long.byte 0x10 0.--7. 1. "P4_MFP,P4 Multiple Function Selection.The pin function of P4 depends on P4_MFP and P4_ALT..Refer to P4_ALT Description for details." endif sif (cpuis("NUC029?AE")) group.long 0x44++0x3 line.long 0x0 "P5_MFP,P5 Multiple Function and Input Type Control Register" hexmask.long.byte 0x0 16.--23. 1. "P5_TYPE,P5[7:0] TTL or Schmitt Trigger Function Enable Control" bitfld.long 0x0 13. "P5_ALT5,P5.5 Alternate Function Selection" "0,1" newline bitfld.long 0x0 12. "P5_ALT4,P5.4 Alternate Function Selection" "0,1" bitfld.long 0x0 11. "P5_ALT3,P5.3 Alternate Function Selection" "0,1" newline bitfld.long 0x0 10. "P5_ALT2,P5.2 Alternate Function Selection" "0,1" bitfld.long 0x0 9. "P5_ALT1,P5.1 Alternate Function Selection" "0,1" newline bitfld.long 0x0 8. "P5_ALT0,P5.0 Alternate Function Selection" "0,1" hexmask.long.byte 0x0 0.--7. 1. "P5_MFP,P5 Multiple Function Selection.The pin function of P5 depends on P5_MFP and P5_ALT..Refer to P5_ALT Description for details." group.long 0x80++0xB line.long 0x0 "IRCTRIMCTL,HIRC Trim Control Register" bitfld.long 0x0 6.--7. "TRIM_RETRY_CNT,Trim Value Update Limitation Count" "0,1,2,3" bitfld.long 0x0 4.--5. "TRIM_LOOP,Trim Calculation Loop.This field defines that trim value calculation is based on how many LXT clocks in..For example if TRIM_LOOP is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" newline bitfld.long 0x0 0. "TRIM_SEL,Trim Frequency Selection.This bit is to enable the HIRC auto trim..When setting this bit to 1 the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock..During auto trim operation if LXT clock.." "0: HIRC auto trim function Disabled,1: HIRC auto trim function Enabled and HIRC trimmed.." line.long 0x4 "IRCTRIMIEN,HIRC Trim Interrupt Enable Control Register" bitfld.long 0x4 2. "_32K_ERR_IEN,LXT Clock Error Interrupt Enable Control.This bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation..If this bit is high and 32K_ERR_INT is set during auto trim operation an interrupt will be.." "0: 32K_ERR_INT status Disabled to trigger an..,1: 32K_ERR_INT status Enabled to trigger an.." bitfld.long 0x4 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable Control.This bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL..If this bit is.." "0: TRIM_FAIL_INT status Disabled to trigger an..,1: TRIM_FAIL_INT status Enabled to trigger an.." line.long 0x8 "IRCTRIMINT,HIRC Trim Interrupt Status Register" bitfld.long 0x8 2. "_32K_ERR_INT,LXT Clock Error Interrupt Status.This bit indicates that LXT clock frequency is inaccuracy. Once this bit is set the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically..If this bit is set and.." "0: LXT clock frequency is accuracy,1: LXT clock frequency is inaccuracy" bitfld.long 0x8 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status.This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set the auto trim operation stopped and TRIM_SEL will be cleared to 0 by.." "0: Trim value update limitation count is not reached,1: Trim value update limitation count is reached.." newline bitfld.long 0x8 0. "FREQ_LOCK,HIRC Frequency Lock Status.This bit indicates the HIRC frequency locked in 22.1184 MHz..This is a read only status bit and doesn't trigger any interrupt." "0,1" endif sif (cpuis("NUC029?EE")) group.long 0x1C++0x3 line.long 0x0 "TEMPCR,Temperature Sensor Control Register" bitfld.long 0x0 0. "VTEMP_EN,Temperature Sensor Enable Bit.This bit is used to enable/disable temperature sensor function..Note: After this bit is set to 1 the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled" group.long 0x24++0x3 line.long 0x0 "PORCR,Power-on-reset Controller Register" hexmask.long.word 0x0 0.--15. 1. "POR_DIS_CODE,Power-On-Reset Enable Bit (Write Protect).When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.." group.long 0x30++0xB line.long 0x0 "GPA_MFP,GPIOA Multiple Function and Input Type Control Register" hexmask.long.word 0x0 16.--31. 1. "GPA_TYPEn,Trigger Function Selection" bitfld.long 0x0 15. "GPA_MFP15,PA.15 Pin Function Selection" "0: GPIOA function is selected,1: PWM3 function is selected" newline bitfld.long 0x0 14. "GPA_MFP14,PA.14 Pin Function Selection.Bits EBI_HB_EN[7] (ALT_MFP[23]) EBI_EN (ALT_MFP[11]) and GPA_MFP[14] determine the PA.14 function..(EBI_HB_EN EBI_EN GPA_MFP14) value and function mapping is as following list." "0,1" bitfld.long 0x0 13. "GPA_MFP13,PA.13 Pin Function Selection.Bits EBI_HB_EN[6] (ALT_MFP[22]) EBI_EN (ALT_MFP[11]) and GPA_MFP[13] determine the PA.13 function..(EBI_HB_EN EBI_EN GPA_MFP13) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 12. "GPA_MFP12,PA.12 Pin Function Selection.Bits EBI_HB_EN[5] (ALT_MFP[21]) EBI_EN (ALT_MFP[11]) and GPA_MFP[12] determine the PA.12 function..(EBI_HB_EN EBI_EN GPA_MFP12) value and function mapping is as following list." "0,1" bitfld.long 0x0 11. "GPA_MFP11,PA.11 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPA_MFP[11] determine the PA.11 function..(EBI_EN GPA_MFP11) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 10. "GPA_MFP10,PA.10 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPA_MFP[10] determine the PA.10 function..(EBI_EN GPA_MFP10) value and function mapping is as following list." "0,1" bitfld.long 0x0 9. "GPA_MFP9,PA.9 Pin Function Selection.Bit GPA_MFP[9] determines the PA.9 function." "0: GPIO function is selected,1: I2C0_SCL function is selected" newline bitfld.long 0x0 8. "GPA_MFP8,PA.8 Pin Function Selection.Bit GPA_MFP[8] determines the PA.9 function." "0: GPIO function is selected to the pin PA.8,1: I2C0_SDA function is selected to the pin PA.8" bitfld.long 0x0 7. "GPA_MFP7,Reserved." "0,1" newline bitfld.long 0x0 6. "GPA_MFP6,PA.6 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPA_MFP[6] determine the PA.6 function..(EBI_EN GPA_MFP6) value and function mapping is as following list." "0,1" bitfld.long 0x0 5. "GPA_MFP5,PA.5 Pin Function Selection.Bits EBI_HB_EN[0] (ALT_MFP[16]) EBI_EN (ALT_MFP[11]) and GPA_MFP[5] determine the PA.5 function..(EBI_HB_EN EBI_EN GPA_MFP5) value and function mapping is as following list " "0,1" newline bitfld.long 0x0 4. "GPA_MFP4,PA.4 Pin Function Selection.Bits EBI_HB_EN[1] (ALT_MFP[17]) EBI_EN (ALT_MFP[11]) and GPA_MFP[4] determine the PA.4 function..(EBI_HB_EN EBI_EN GPA_MFP4) value and function mapping is as following list." "0,1" bitfld.long 0x0 3. "GPA_MFP3,PA.3 Pin Function Selection.Bits EBI_HB_EN[2] (ALT_MFP[18]) EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function..(EBI_HB_EN EBI_EN GPA_MFP3) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 2. "GPA_MFP2,PA.2 Pin Function Selection.Bits EBI_HB_EN[3] (ALT_MFP[19]) EBI_EN (ALT_MFP[11]) and GPA_MFP[2] determine the PA.2 function..(EBI_HB_EN EBI_EN GPA_MFP2) value and function mapping is as following list." "0,1" bitfld.long 0x0 1. "GPA_MFP1,PA.1 Pin Function Selection.Bit EBI_HB_EN[4] (ALT_MFP[20]) EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function..(EBI_HB_EN EBI_EN GPA_MFP1) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 0. "GPA_MFP0,PA.0 Pin Function Selection" "0: GPIO function is selected,1: ADC0 function is selected" line.long 0x4 "GPB_MFP,GPIOB Multiple Function and Input Type Control Register" hexmask.long.word 0x4 16.--31. 1. "GPB_TYPEn,Trigger Function Selection" bitfld.long 0x4 15. "GPB_MFP15,PB.15 Pin Function Selection.Bits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function..(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as.." "0,1" newline bitfld.long 0x4 14. "GPB_MFP14,PB.14 Pin Function Selection.Bits PB14_15_EBI (ALT_MFP2[1]) and GPB_MFP[14] determine the PB.14 function..(PB14_15_EBI GPB_MFP14) value and function mapping is as following list" "0,1" bitfld.long 0x4 13. "GPB_MFP13,PB.13 Pin Function Selection" "0: GPIO function is selected to the pin PB.13,1: AD1 function is selected" newline bitfld.long 0x4 12. "GPB_MFP12,Reserved." "0,1" bitfld.long 0x4 11. "GPB_MFP11,PB.11 Pin Function Selection.Bits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function..(PB11_PWM4 GPB_MFP11) value and function mapping is as following list." "0,1" newline bitfld.long 0x4 10. "GPB_MFP10,PB.10 Pin Function Selection.Bits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function..(PB10_S01 GPB_MFP10) value and function mapping is as following list." "0,1" bitfld.long 0x4 9. "GPB_MFP9,PB.9 Pin Function Selection.Bits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function..(PB9_S11 GPB_MFP9) value and function mapping is as following list." "0,1" newline bitfld.long 0x4 8. "GPB_MFP8,PB.8 Pin Function Selection.Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function..(PB8_CLKO GPB_MFP8) value and function mapping is as following list." "0,1" bitfld.long 0x4 7. "GPB_MFP7,PB.7 Pin Function Selection.Bit EBI_EN (ALT_MFP[11]) GPB_MFP[7] determines the PB.7 function..(EBI_EN GPB_MFP7) value and function mapping is as following list." "0,1" newline bitfld.long 0x4 6. "GPB_MFP6,PB.6 Pin Function Selection.Bit EBI_EN (ALT_MFP[11]) GPB_MFP[6] determines the PB.6 function..(EBI_EN GPB_MFP6) value and function mapping is as following list." "0,1" bitfld.long 0x4 5. "GPB_MFP5,PB 5 Pin Function Selection.Bit GPB_MFP[5] determines the PB.5 function." "0: GPIO function is selected to the pin PB.5,1: UART1_TXD function is selected to the pin PB.5" newline bitfld.long 0x4 4. "GPB_MFP4,PB.4 Pin Function Selection.Bit GPB_MFP[4] determines the PB.4 function." "0: GPIO function is selected to the pin PB.4,1: UART1_RXD function is selected to the pin PB.4" bitfld.long 0x4 3. "GPB_MFP3,PB.3 Pin Function Selection.Bits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function..(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value and function.." "0,1" newline bitfld.long 0x4 2. "GPB_MFP2,PB.2 Pin Function Selection.Bits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function..(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and function.." "0,1" bitfld.long 0x4 1. "GPB_MFP1,PB.1 Pin Function Selection.Bit GPB_MFP[1] determines the PB.1 function." "0: GPIO function is selected to the pin PB.1,1: UART0_TXD function is selected to the pin PB.1" newline bitfld.long 0x4 0. "GPB_MFP0,PB.0 Pin Function Selection.Bit GPB_MFP[0] determines the PB.0 function." "0: GPIO function is selected to the pin PB.0,1: UART0_RXD function is selected to the pin PB.0" line.long 0x8 "GPC_MFP,GPIOC Multiple Function and Input Type Control Register" hexmask.long.word 0x8 16.--31. 1. "GPC_TYPEn,Trigger Function Selection" bitfld.long 0x8 15. "GPC_MFP15,PC.15 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPC_MFP[15] determine the PC.15 function..(EBI_EN GPC_MFP15) value and function mapping is as following list" "0,1" newline bitfld.long 0x8 14. "GPC_MFP14,PC.14 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPC_MFP[14] determine the PC.14 function..(EBI_EN GPC_MFP14) value and function mapping is as following list" "0,1" bitfld.long 0x8 13. "GPC_MFP13,Reserved." "0,1" newline bitfld.long 0x8 12. "GPC_MFP12,Reserved." "0,1" bitfld.long 0x8 11. "GPC_MFP11,PC.11 Pin Function Selection.Bit GPC_MFP[11] determines the PC.11 function." "0: GPIO function is selected to the pin PC.11,1: SPI1_MOSI0 function is selected to the pin PC.11" newline bitfld.long 0x8 10. "GPC_MFP10,PC.10 Pin Function Selection.Bit GPC_MFP[10] determines the PC.10 function." "0: GPIO function is selected to the pin PC.10,1: SPI1_MISO0 function is selected to the pin PC.10" bitfld.long 0x8 9. "GPC_MFP9,PC.9 Pin Function Selection.Bit GPC_MFP[9] determines the PC.9 function." "0: GPIO function is selected to the pin PC.9,1: SPI1_CLK function is selected to the pin PC.9" newline bitfld.long 0x8 8. "GPC_MFP8,PC.8 Pin Function Selection.Bits EBI_MCLK_EN (ALT_MFP[12]) EBI_EN (ALT_MFP[11]) GPC_MFP[8] determine the PC.8 function..(EBI_MCLK_EN EBI_EN GPC_MFP8) value and function mapping is as following list." "0,1" bitfld.long 0x8 7. "GPC_MFP7,PC.7 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPC_MFP[7] determine the PC.7 function..(EBI_EN GPC_MFP7) value and function mapping is as following list." "0,1" newline bitfld.long 0x8 6. "GPC_MFP6,PC.6 Pin Function Selection.Bits EBI_EN (ALT_MFP[11]) and GPC_MFP[6] determine the PC.6 function..(EBI_EN GPB_MFP6) value and function mapping is as following list." "0,1" bitfld.long 0x8 5. "GPC_MFP5,Reserved." "0,1" newline bitfld.long 0x8 4. "GPC_MFP4,Reserved." "0,1" bitfld.long 0x8 3. "GPC_MFP3,PC.3 Pin Function Selection" "0: GPIO function is selected,1: SPI0_MOSI0 function is selected" newline bitfld.long 0x8 2. "GPC_MFP2,PC.2 Pin Function Selection" "0: GPIO function is selected,1: SPI0_MISO0 function is selected" bitfld.long 0x8 1. "GPC_MFP1,PC.1 Pin Function Selection" "0: GPIO function is selected,1: SPI0_CLK function is selected" newline bitfld.long 0x8 0. "GPC_MFP0,PC.0 Pin Function Selection" "0: GPIO function is selected,1: SPI0_SS0 function is selected" group.long 0x40++0x7 line.long 0x0 "GPE_MFP,GPIOE Multiple Function and Input Type Control Register" hexmask.long.word 0x0 16.--31. 1. "GPE_TYPEn,Trigger Function Selection" bitfld.long 0x0 5. "GPE_MFP5,PE.5 Pin Function Selection.Bits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function..(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list." "0,1" line.long 0x4 "GPF_MFP,GPIOF Multiple Function and Input Type Control Register" hexmask.long.byte 0x4 16.--19. 1. "GPF_TYPEn,Trigger Function Selection" bitfld.long 0x4 1. "GPF_MFP1,PF.1 Pin Function Selection .Bit GPF_MFP[1] determines the PF.1 function..Note: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])." "0: GPIO function is selected to the pin PF.1,1: XT1_IN function is selected to the pin PF.1" newline bitfld.long 0x4 0. "GPF_MFP0,PF.0 Pin Function Selection.Bit GPF_MFP[0] determines the PF.0 function.Note: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])." "0: GPIO function is selected to the pin PF.0,1: XT1_OUT function is selected to the pin PF.0" group.long 0x50++0x3 line.long 0x0 "ALT_MFP,Alternative Multiple Function Pin Control Register" bitfld.long 0x0 29. "PB8_CLKO,PB.8 Pin Alternative Function Selection.Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function..(PB8_CLKO GPB_MFP8) value and function mapping is as following list." "0,1" bitfld.long 0x0 27. "PB3_T3EX,PB.3 Pin Alternative Function Selection.Bits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function..(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value.." "0,1" newline bitfld.long 0x0 26. "PB2_T2EX,PB.2 Pin Alternative Function Selection.Bits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function..(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value.." "0,1" bitfld.long 0x0 25. "PE5_T1EX,PE.5 Pin Alternative Function Selection.Bits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function..(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 24. "PB15_T0EX,PB.15 Pin Alternative Function Selection.Bits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function..(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping.." "0,1" bitfld.long 0x0 23. "EBI_HB_EN7,Bits EBI_HB_EN[7] (ALT_MFP[23]) EBI_EN (ALT_MFP[11]) and GPA_MFP[14] determine the PA.14 function..(EBI_HB_EN EBI_EN GPA_MFP14) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 22. "EBI_HB_EN6,Bits EBI_HB_EN[6] (ALT_MFP[22]) EBI_EN (ALT_MFP[11]) and GPA_MFP[13] determine the PA.13 function..(EBI_HB_EN EBI_EN GPA_MFP13) value and function mapping is as following list." "0,1" bitfld.long 0x0 21. "EBI_HB_EN5,Bits EBI_HB_EN[5] (ALT_MFP[21]) EBI_EN (ALT_MFP[11]) and GPA_MFP[12] determine the PA.12 function..(EBI_HB_EN EBI_EN GPA_MFP12) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 20. "EBI_HB_EN4,Bit EBI_HB_EN[4] (ALT_MFP[20]) EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function..(EBI_HB_EN EBI_EN GPA_MFP1) value and function mapping is as following list." "0,1" bitfld.long 0x0 19. "EBI_HB_EN3,Bits EBI_HB_EN[3] (ALT_MFP[19]) EBI_EN (ALT_MFP[11]) and GPA_MFP[2] determine the PA.2 function..(EBI_HB_EN EBI_EN GPA_MFP2) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 18. "EBI_HB_EN2,Bits EBI_HB_EN[2] (ALT_MFP[18]) EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function..(EBI_HB_EN EBI_EN GPA_MFP3) value and function mapping is as following list." "0,1" bitfld.long 0x0 17. "EBI_HB_EN1,Bits EBI_HB_EN[1] (ALT_MFP[17]) EBI_EN (ALT_MFP[11]) and GPA_MFP[4] determine the PA.4 function..(EBI_HB_EN EBI_EN GPA_MFP4) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 16. "EBI_HB_EN0,Bits EBI_HB_EN[0] (ALT_MFP[16]) EBI_EN (ALT_MFP[11]) and GPA_MFP[5] determine the PA.5 function..(EBI_HB_EN EBI_EN GPA_MFP5) value and function mapping is as following list " "0,1" bitfld.long 0x0 14. "EBI_nWRH_EN,Bits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function..(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value and function mapping is as following.." "0,1" newline bitfld.long 0x0 13. "EBI_nWRL_EN,Bits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function..(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and function mapping is as following list." "0,1" bitfld.long 0x0 12. "EBI_MCLK_EN,Bits EBI_MCLK_EN (ALT_MFP[12]) EBI_EN (ALT_MFP[11]) GPC_MFP[8] determine the PC.8 function..(EBI_MCLK_EN EBI_EN GPC_MFP8) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 11. "EBI_EN,EBI_EN is use to switch GPIO function to EBI function (AD[15:0] ALE RE WE CS MCLK) it need additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8] MCLK)" "0,1" bitfld.long 0x0 4. "PB11_PWM4,PB.11 Pin Alternative Function Selection.Bits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function..(PB11_PWM4 GPB_MFP11) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 3. "PB14_S31,PB.14 Pin Alternative Function Selection.Bits PB14_15_EBI (ALT_MFP2[1]) and GPB_MFP[14] determine the PB.14 function..(PB14_15_EBI GPB_MFP14) value and function mapping is as following list" "0,1" bitfld.long 0x0 1. "PB9_S11,PB.9 Pin Alternative Function Selection.Bits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function..(PB9_S11 GPB_MFP9) value and function mapping is as following list." "0,1" newline bitfld.long 0x0 0. "PB10_S01,PB.10 Pin Alternative Function Selection.Bits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function..(PB10_S01 GPB_MFP10) value and function mapping is as following list." "0,1" group.long 0x5C++0x3 line.long 0x0 "ALT_MFP2,Alternative Multiple Function Pin Control Register 2" bitfld.long 0x0 5. "PB3_TM3,PB.3 Pin Alternative Function Selection.Bits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function..(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value.." "0,1" bitfld.long 0x0 4. "PB2_TM2,PB.2 Pin Alternative Function Selection.Bits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function..(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and.." "0,1" newline bitfld.long 0x0 3. "PE5_TM1,PE.5 Pin Alternative Function Selection.Bits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function..(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list." "0,1" bitfld.long 0x0 2. "PB15_TM0,PB.15 Pin Alternative Function Selection.Bits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function..(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is.." "0,1" newline bitfld.long 0x0 1. "PB14_15_EBI,PB .14 and PB.15 Pin Alternative Function Selection.Bits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function..(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and.." "0,1" group.long 0x80++0xB line.long 0x0 "IRCTCTL,IRC Trim Control Register" bitfld.long 0x0 8. "CLKERR_STOP_EN,Clock Error Stop Enable Bit" "0: The trim operation is kept going if clock is..,1: The trim operation is stopped if clock is.." bitfld.long 0x0 6.--7. "TRIM_RETRY_CNT,Trim Value Update Limitation Count.The field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked..Once the HIRC locked the internal trim value update counter will be reset..If.." "0: Trim retry count limitation is 64,1: Trim retry count limitation is 128,?,?" newline bitfld.long 0x0 4.--5. "TRIM_LOOP,Trim Calculation Loop.This field defines that trim value calculation is based on how many 32.768 kHz clocks in..For example if TRIM_LOOP is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" bitfld.long 0x0 0.--1. "TRIM_SEL,Trim Frequency Selection.This field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically..If no any target frequency is selected (TRIM_SEL is 00) the HIRC auto.." "0: HIRC auto trim function Disabled,1: HIRC auto trim function Enabled and HIRC trimmed..,?,?" line.long 0x4 "IRCTIEN,IRC Trim Interrupt Enable Register" bitfld.long 0x4 2. "CLKERR_IEN,Clock Error Interrupt Enable Bit.This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation..If this bit is set to1 and CLKERR_INT (IRCTRIMINT[2]) is set during auto trim operation. An interrupt.." "0: CLKERR_INT (IRCTRIMINT[2]) status to trigger an..,1: CLKERR_INT (IRCTRIMINT[2]) status to trigger an.." bitfld.long 0x4 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable Bit.This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTCTL[1:0])..If this.." "0: TRIM_FAIL_INT (IRCTRIMINT[1]) status to trigger..,1: TRIM_FAIL_INT (IRCTRIMINT[1]) status to trigger.." line.long 0x8 "IRCTSTS,IRC Trim Interrupt Status Register" bitfld.long 0x8 2. "CLKERR_INT,Clock Error Interrupt Status.When the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate" bitfld.long 0x8 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status.This bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. Once.." "0: Trim value update limitation count did not reach,1: Trim value update limitation count reached and.." newline bitfld.long 0x8 0. "FREQ_LOCK,HIRC Frequency Lock Status.This bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked..This is a status bit and doesn't trigger any interrupt." "0,1" group.long 0x90++0xB line.long 0x0 "HIRCTCTL,HIRC Trim Control Register" hexmask.long.byte 0x0 16.--20. 1. "BOUNDARY,Boundary Selection.Fill the boundary range from 1 to 31 0 is reserved..Note: This field is effective only when the BOUNDEN(SYS_HIRCTCTL[9]) is enable." bitfld.long 0x0 9. "BOUNDEN,Boundary Enable" "0: Boundary function is disable,1: Boundary function is enable" newline bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count.This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked..Once the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?" newline bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection.This field defines that trim value calculation is based on how many reference clocks..Note: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection.This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim..During auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?" line.long 0x4 "HIRCTIEN,HIRC Trim Interrupt Enable Register" bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit.This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation..If this bit is set to1 and CLKERRIF(SYS_HIRCTSTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_HIRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_HIRCTSTS[2]) status to.." bitfld.long 0x4 1. "TFALIEN,Trim Failure Interrupt Enable Bit.This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0])..If this bit.." "0: Disable TFAILIF(SYS_HIRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTSTS[1]) status to.." line.long 0x8 "HIRCTSTS,HIRC Trim Interrupt Status Register" bitfld.long 0x8 3. "OVBDIF,Over Boundary Status.When the over boundary function is set if there occurs the over boundary condition this flag will be set..Note: Write 1 to clear this flag." "0: Over boundary coundition did not occur,1: Over boundary coundition occurred" bitfld.long 0x8 2. "CLKERIF,Clock Error Interrupt Status.When the reference clock or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is inaccuracy.Once this bit is set to.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy" newline bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status.This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.." bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status.This bit indicates the HIRC frequency is locked..This is a status bit and doesn't trigger any interrupt.Write 1 to clear this to 0. This bit will be set automatically if the frequecy is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.." endif group.long 0x100++0x3 line.long 0x0 "REGWRPROT,Register Write-Protection Control Register" sif (cpuis("NUC029?DE")) hexmask.long.byte 0x0 1.--7. 1. "REGWRPROT,Register Write-Protection Code (Write Only).Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.." endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")) rbitfld.long 0x0 0. "REGPROTDIS,Register Write-Protection Disable index (Read Only)" "0: Write-protection Enabled for writing protected..,1: Write-protection Disabled for writing protected.." newline endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) hexmask.long.byte 0x0 0.--7. 1. "REGWRPROT,Register Write-Protection Code (Write Only).Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59 0x16 0x88 to this field. After this sequence is.." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x0 0.--7. 1. "REGWRPROT,Register Write-Protection Code (Write Only).Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.." endif tree.end endif tree "GPIO (General Purpose I/Os)" base ad:0x50004000 sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) group.long 0x0++0xF line.long 0x0 "P0_PMD,P0 I/O Mode Control" bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "P0_OFFD,P0 Digital Input Path Disable Control" hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [n] Digital Input Path Disable Control" line.long 0x8 "P0_DOUT,P0 Data Output Value" sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "DOUT7,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 6. "DOUT6,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 5. "DOUT5,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 4. "DOUT4,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 3. "DOUT3,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 2. "DOUT2,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 1. "DOUT1,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 0. "DOUT0,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 0.--7. 1. "DOUT,Port 0-5 Pin [n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode..Note2:.P0_DOUT[3:2] are reserved..P1_DOUT[7:6] [1] are.." endif line.long 0xC "P0_DMASK,P0 Data Output Write Mask" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "DMASK7,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 6. "DMASK6,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 5. "DMASK5,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 4. "DMASK4,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 3. "DMASK3,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 2. "DMASK2,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 1. "DMASK1,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 0. "DMASK0,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "DMASK,Port 0-5 Pin [n] Data Output Write Mask.These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.." endif rgroup.long 0x10++0x3 line.long 0x0 "P0_PIN,P0 Pin Value" sif (cpuis("NUC029?AN")) rbitfld.long 0x0 7. "PIN7,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 6. "PIN6,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 5. "PIN5,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 4. "PIN4,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 3. "PIN3,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 2. "PIN2,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 1. "PIN1,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 0. "PIN0,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note2:.P0_PIN[3:2] are.." endif group.long 0x14++0xF line.long 0x0 "P0_DBEN,P0 De-bounce Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x0 7. "DBEN7,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 6. "DBEN6,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 5. "DBEN5,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 4. "DBEN4,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 3. "DBEN3,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 2. "DBEN2,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 1. "DBEN1,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 0. "DBEN0,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [n] Input Signal De-bounce Enable Control.DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." endif line.long 0x4 "P0_IMD,P0 Interrupt Mode Control" sif (cpuis("NUC029?AN")) bitfld.long 0x4 7. "IMD7,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x4 0.--7. 1. "IMD,Port 0-5 Pin [n] Edge or Level Detection Interrupt Mode Control.IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.." endif line.long 0x8 "P0_IEN,P0 Interrupt Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "IR_EN7,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 22. "IR_EN6,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 21. "IR_EN5,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 20. "IR_EN4,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 19. "IR_EN3,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 18. "IR_EN2,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 17. "IR_EN1,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 16. "IR_EN0,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 16.--23. 1. "IR_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Rising Edge or Input Level High.IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." bitfld.long 0x8 0. "IF_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Falling Edge or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "IF_EN7,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 6. "IF_EN6,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 5. "IF_EN5,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 4. "IF_EN4,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 3. "IF_EN3,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 2. "IF_EN2,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 1. "IF_EN1,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 0. "IF_EN0,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." endif line.long 0xC "P0_ISRC,P0 Interrupt Source Flag" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "ISRC7,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 6. "ISRC6,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 4. "ISRC4,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 2. "ISRC2,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 0. "ISRC0,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "ISRC,Port 0-5 Pin [n] Interrupt Source Flag.Write :.Note2:.P0_ISRC[3:2] are reserved..P1_ISRC[7:6] [1] are reserved..P2_ISRC[7] [1:0] are reserved..P3_ISRC[7] [3] are reserved..P4_ISRC[5:0] are reserved..P5_ISRC[7:6] are reserved." endif group.long 0x40++0xF line.long 0x0 "P1_PMD,P1 I/O Mode Control" bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "P1_OFFD,P1 Digital Input Path Disable Control" hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [n] Digital Input Path Disable Control" line.long 0x8 "P1_DOUT,P1 Data Output Value" sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "DOUT7,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 6. "DOUT6,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 5. "DOUT5,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 4. "DOUT4,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 3. "DOUT3,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 2. "DOUT2,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 1. "DOUT1,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 0. "DOUT0,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 0.--7. 1. "DOUT,Port 0-5 Pin [n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode..Note2:.P0_DOUT[3:2] are reserved..P1_DOUT[7:6] [1] are.." endif line.long 0xC "P1_DMASK,P1 Data Output Write Mask" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "DMASK7,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 6. "DMASK6,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 5. "DMASK5,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 4. "DMASK4,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 3. "DMASK3,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 2. "DMASK2,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 1. "DMASK1,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 0. "DMASK0,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "DMASK,Port 0-5 Pin [n] Data Output Write Mask.These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.." endif rgroup.long 0x50++0x3 line.long 0x0 "P1_PIN,P1 Pin Value" sif (cpuis("NUC029?AN")) rbitfld.long 0x0 7. "PIN7,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 6. "PIN6,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 5. "PIN5,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 4. "PIN4,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 3. "PIN3,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 2. "PIN2,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 1. "PIN1,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 0. "PIN0,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note2:.P0_PIN[3:2] are.." endif group.long 0x54++0xF line.long 0x0 "P1_DBEN,P1 De-bounce Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x0 7. "DBEN7,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 6. "DBEN6,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 5. "DBEN5,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 4. "DBEN4,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 3. "DBEN3,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 2. "DBEN2,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 1. "DBEN1,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 0. "DBEN0,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [n] Input Signal De-bounce Enable Control.DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." endif line.long 0x4 "P1_IMD,P1 Interrupt Mode Control" sif (cpuis("NUC029?AN")) bitfld.long 0x4 7. "IMD7,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x4 0.--7. 1. "IMD,Port 0-5 Pin [n] Edge or Level Detection Interrupt Mode Control.IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.." endif line.long 0x8 "P1_IEN,P1 Interrupt Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "IR_EN7,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 22. "IR_EN6,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 21. "IR_EN5,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 20. "IR_EN4,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 19. "IR_EN3,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 18. "IR_EN2,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 17. "IR_EN1,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 16. "IR_EN0,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 16.--23. 1. "IR_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Rising Edge or Input Level High.IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." bitfld.long 0x8 0. "IF_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Falling Edge or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "IF_EN7,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 6. "IF_EN6,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 5. "IF_EN5,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 4. "IF_EN4,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 3. "IF_EN3,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 2. "IF_EN2,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 1. "IF_EN1,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 0. "IF_EN0,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." endif line.long 0xC "P1_ISRC,P1 Interrupt Source Flag" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "ISRC7,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 6. "ISRC6,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 4. "ISRC4,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 2. "ISRC2,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 0. "ISRC0,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "ISRC,Port 0-5 Pin [n] Interrupt Source Flag.Write :.Note2:.P0_ISRC[3:2] are reserved..P1_ISRC[7:6] [1] are reserved..P2_ISRC[7] [1:0] are reserved..P3_ISRC[7] [3] are reserved..P4_ISRC[5:0] are reserved..P5_ISRC[7:6] are reserved." endif group.long 0x80++0xF line.long 0x0 "P2_PMD,P2 I/O Mode Control" bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "P2_OFFD,P2 Digital Input Path Disable Control" hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [n] Digital Input Path Disable Control" line.long 0x8 "P2_DOUT,P2 Data Output Value" sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "DOUT7,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 6. "DOUT6,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 5. "DOUT5,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 4. "DOUT4,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 3. "DOUT3,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 2. "DOUT2,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 1. "DOUT1,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 0. "DOUT0,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 0.--7. 1. "DOUT,Port 0-5 Pin [n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode..Note2:.P0_DOUT[3:2] are reserved..P1_DOUT[7:6] [1] are.." endif line.long 0xC "P2_DMASK,P2 Data Output Write Mask" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "DMASK7,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 6. "DMASK6,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 5. "DMASK5,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 4. "DMASK4,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 3. "DMASK3,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 2. "DMASK2,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 1. "DMASK1,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 0. "DMASK0,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "DMASK,Port 0-5 Pin [n] Data Output Write Mask.These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.." endif rgroup.long 0x90++0x3 line.long 0x0 "P2_PIN,P2 Pin Value" sif (cpuis("NUC029?AN")) rbitfld.long 0x0 7. "PIN7,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 6. "PIN6,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 5. "PIN5,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 4. "PIN4,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 3. "PIN3,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 2. "PIN2,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 1. "PIN1,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 0. "PIN0,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note2:.P0_PIN[3:2] are.." endif group.long 0x94++0xF line.long 0x0 "P2_DBEN,P2 De-bounce Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x0 7. "DBEN7,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 6. "DBEN6,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 5. "DBEN5,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 4. "DBEN4,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 3. "DBEN3,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 2. "DBEN2,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 1. "DBEN1,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 0. "DBEN0,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [n] Input Signal De-bounce Enable Control.DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." endif line.long 0x4 "P2_IMD,P2 Interrupt Mode Control" sif (cpuis("NUC029?AN")) bitfld.long 0x4 7. "IMD7,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x4 0.--7. 1. "IMD,Port 0-5 Pin [n] Edge or Level Detection Interrupt Mode Control.IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.." endif line.long 0x8 "P2_IEN,P2 Interrupt Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "IR_EN7,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 22. "IR_EN6,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 21. "IR_EN5,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 20. "IR_EN4,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 19. "IR_EN3,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 18. "IR_EN2,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 17. "IR_EN1,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 16. "IR_EN0,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 16.--23. 1. "IR_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Rising Edge or Input Level High.IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." bitfld.long 0x8 0. "IF_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Falling Edge or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "IF_EN7,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 6. "IF_EN6,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 5. "IF_EN5,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 4. "IF_EN4,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 3. "IF_EN3,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 2. "IF_EN2,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 1. "IF_EN1,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 0. "IF_EN0,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." endif line.long 0xC "P2_ISRC,P2 Interrupt Source Flag" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "ISRC7,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 6. "ISRC6,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 4. "ISRC4,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 2. "ISRC2,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 0. "ISRC0,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "ISRC,Port 0-5 Pin [n] Interrupt Source Flag.Write :.Note2:.P0_ISRC[3:2] are reserved..P1_ISRC[7:6] [1] are reserved..P2_ISRC[7] [1:0] are reserved..P3_ISRC[7] [3] are reserved..P4_ISRC[5:0] are reserved..P5_ISRC[7:6] are reserved." endif group.long 0xC0++0xF line.long 0x0 "P3_PMD,P3 I/O Mode Control" bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "P3_OFFD,P3 Digital Input Path Disable Control" hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [n] Digital Input Path Disable Control" line.long 0x8 "P3_DOUT,P3 Data Output Value" sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "DOUT7,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 6. "DOUT6,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 5. "DOUT5,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 4. "DOUT4,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 3. "DOUT3,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 2. "DOUT2,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 1. "DOUT1,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 0. "DOUT0,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 0.--7. 1. "DOUT,Port 0-5 Pin [n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode..Note2:.P0_DOUT[3:2] are reserved..P1_DOUT[7:6] [1] are.." endif line.long 0xC "P3_DMASK,P3 Data Output Write Mask" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "DMASK7,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 6. "DMASK6,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 5. "DMASK5,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 4. "DMASK4,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 3. "DMASK3,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 2. "DMASK2,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 1. "DMASK1,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 0. "DMASK0,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "DMASK,Port 0-5 Pin [n] Data Output Write Mask.These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.." endif rgroup.long 0xD0++0x3 line.long 0x0 "P3_PIN,P3 Pin Value" sif (cpuis("NUC029?AN")) rbitfld.long 0x0 7. "PIN7,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 6. "PIN6,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 5. "PIN5,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 4. "PIN4,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 3. "PIN3,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 2. "PIN2,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 1. "PIN1,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 0. "PIN0,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note2:.P0_PIN[3:2] are.." endif group.long 0xD4++0xF line.long 0x0 "P3_DBEN,P3 De-bounce Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x0 7. "DBEN7,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 6. "DBEN6,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 5. "DBEN5,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 4. "DBEN4,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 3. "DBEN3,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 2. "DBEN2,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 1. "DBEN1,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 0. "DBEN0,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [n] Input Signal De-bounce Enable Control.DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." endif line.long 0x4 "P3_IMD,P3 Interrupt Mode Control" sif (cpuis("NUC029?AN")) bitfld.long 0x4 7. "IMD7,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x4 0.--7. 1. "IMD,Port 0-5 Pin [n] Edge or Level Detection Interrupt Mode Control.IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.." endif line.long 0x8 "P3_IEN,P3 Interrupt Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "IR_EN7,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 22. "IR_EN6,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 21. "IR_EN5,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 20. "IR_EN4,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 19. "IR_EN3,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 18. "IR_EN2,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 17. "IR_EN1,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 16. "IR_EN0,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 16.--23. 1. "IR_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Rising Edge or Input Level High.IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." bitfld.long 0x8 0. "IF_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Falling Edge or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "IF_EN7,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 6. "IF_EN6,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 5. "IF_EN5,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 4. "IF_EN4,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 3. "IF_EN3,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 2. "IF_EN2,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 1. "IF_EN1,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 0. "IF_EN0,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." endif line.long 0xC "P3_ISRC,P3 Interrupt Source Flag" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "ISRC7,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 6. "ISRC6,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 4. "ISRC4,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 2. "ISRC2,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 0. "ISRC0,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "ISRC,Port 0-5 Pin [n] Interrupt Source Flag.Write :.Note2:.P0_ISRC[3:2] are reserved..P1_ISRC[7:6] [1] are reserved..P2_ISRC[7] [1:0] are reserved..P3_ISRC[7] [3] are reserved..P4_ISRC[5:0] are reserved..P5_ISRC[7:6] are reserved." endif group.long 0x100++0xF line.long 0x0 "P4_PMD,P4 I/O Mode Control" bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "P4_OFFD,P4 Digital Input Path Disable Control" hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [n] Digital Input Path Disable Control" line.long 0x8 "P4_DOUT,P4 Data Output Value" sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "DOUT7,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 6. "DOUT6,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 5. "DOUT5,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 4. "DOUT4,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 3. "DOUT3,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 2. "DOUT2,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline bitfld.long 0x8 1. "DOUT1,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." bitfld.long 0x8 0. "DOUT0,Px Pin[n] Output Value.Each of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode." "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the corresponding.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 0.--7. 1. "DOUT,Port 0-5 Pin [n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode..Note2:.P0_DOUT[3:2] are reserved..P1_DOUT[7:6] [1] are.." endif line.long 0xC "P4_DMASK,P4 Data Output Write Mask" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "DMASK7,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 6. "DMASK6,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 5. "DMASK5,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 4. "DMASK4,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 3. "DMASK3,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 2. "DMASK2,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline bitfld.long 0xC 1. "DMASK1,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" bitfld.long 0xC 0. "DMASK0,Px Data Output Write Mask (write-protected).These bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1 the corresponding Px_DOUT[n] bit is protected. The write signal is masked write data to the.." "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "DMASK,Port 0-5 Pin [n] Data Output Write Mask.These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.." endif rgroup.long 0x110++0x3 line.long 0x0 "P4_PIN,P4 Pin Value" sif (cpuis("NUC029?AN")) rbitfld.long 0x0 7. "PIN7,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 6. "PIN6,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 5. "PIN5,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 4. "PIN4,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 3. "PIN3,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 2. "PIN2,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline rbitfld.long 0x0 1. "PIN1,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" rbitfld.long 0x0 0. "PIN0,Px Pin Values.The value read from each of these bit reflects the actual status of the respective Px pin" "0,1" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note2:.P0_PIN[3:2] are.." endif group.long 0x114++0xF line.long 0x0 "P4_DBEN,P4 De-bounce Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x0 7. "DBEN7,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 6. "DBEN6,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 5. "DBEN5,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 4. "DBEN4,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 3. "DBEN3,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 2. "DBEN2,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline bitfld.long 0x0 1. "DBEN1,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" bitfld.long 0x0 0. "DBEN0,Px Input Signal De-bounce Enable.DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal.." "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [n] Input Signal De-bounce Enable Control.DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." endif line.long 0x4 "P4_IMD,P4 Interrupt Mode Control" sif (cpuis("NUC029?AN")) bitfld.long 0x4 7. "IMD7,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port 0-4 Interrupt Mode Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is by level trigger the input.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x4 0.--7. 1. "IMD,Port 0-5 Pin [n] Edge or Level Detection Interrupt Mode Control.IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.." endif line.long 0x8 "P4_IEN,P4 Interrupt Enable Control" sif (cpuis("NUC029?AN")) bitfld.long 0x8 23. "IR_EN7,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 22. "IR_EN6,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 21. "IR_EN5,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 20. "IR_EN4,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 19. "IR_EN3,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 18. "IR_EN2,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline bitfld.long 0x8 17. "IR_EN1,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." bitfld.long 0x8 16. "IR_EN0,Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function .When set the IR_EN[n] bit '1':.If the.." "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0x8 16.--23. 1. "IR_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Rising Edge or Input Level High.IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." bitfld.long 0x8 0. "IF_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Falling Edge or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 7. "IF_EN7,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 6. "IF_EN6,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 5. "IF_EN5,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 4. "IF_EN4,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 3. "IF_EN3,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 2. "IF_EN2,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." newline bitfld.long 0x8 1. "IF_EN1,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." bitfld.long 0x8 0. "IF_EN0,Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low.IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit '1' also enable the pin wakeup function.When set the IF_EB[n] bit '1':.If the interrupt.." "0: Disable the Px[n] state low-level or high-to-low..,1: Enable the Px[n] state low-level or high-to-low.." endif line.long 0xC "P4_ISRC,P4 Interrupt Source Flag" sif (cpuis("NUC029?AN")) bitfld.long 0xC 7. "ISRC7,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 6. "ISRC6,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 4. "ISRC4,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 2. "ISRC2,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." bitfld.long 0xC 0. "ISRC0,Port 0-4 Interrupt Source Flag .Read :" "0: No interrupt at Px[n].No action,1: Indicates Px[n] generate an interrupt.Clear the.." newline endif sif (cpuis("NUC029?AE")) hexmask.long.byte 0xC 0.--7. 1. "ISRC,Port 0-5 Pin [n] Interrupt Source Flag.Write :.Note2:.P0_ISRC[3:2] are reserved..P1_ISRC[7:6] [1] are reserved..P2_ISRC[7] [1:0] are reserved..P3_ISRC[7] [3] are reserved..P4_ISRC[5:0] are reserved..P5_ISRC[7:6] are reserved." endif group.long 0x200++0x7 line.long 0x0 "P00_PDIO,GPIO P0.0 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P01_PDIO,GPIO P0.1 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif group.long 0x210++0x13 line.long 0x0 "P04_PDIO,GPIO P0.4 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P05_PDIO,GPIO P0.5 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x8 "P06_PDIO,GPIO P0.6 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x8 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0xC "P07_PDIO,GPIO P0.7 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0xC 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x10 "P10_PDIO,GPIO P1.0 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x10 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif group.long 0x228++0xF line.long 0x0 "P12_PDIO,GPIO P1.2 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P13_PDIO,GPIO P1.3 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x8 "P14_PDIO,GPIO P1.4 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x8 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0xC "P15_PDIO,GPIO P1.5 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0xC 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif group.long 0x248++0x13 line.long 0x0 "P22_PDIO,GPIO P2.2 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P23_PDIO,GPIO P2.3 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x8 "P24_PDIO,GPIO P2.4 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x8 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0xC "P25_PDIO,GPIO P2.5 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0xC 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x10 "P26_PDIO,GPIO P2.6 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x10 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif group.long 0x260++0xB line.long 0x0 "P30_PDIO,GPIO P3.0 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P31_PDIO,GPIO P3.1 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x8 "P32_PDIO,GPIO P3.2 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x8 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif group.long 0x270++0xB line.long 0x0 "P34_PDIO,GPIO P3.4 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P35_PDIO,GPIO P3.5 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x8 "P36_PDIO,GPIO P3.6 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x8 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif group.long 0x298++0x7 line.long 0x0 "P46_PDIO,GPIO P4.6 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif line.long 0x4 "P47_PDIO,GPIO P4.7 Pin Data Input/Output" sif (cpuis("NUC029?AE")) bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?AN")) bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif endif sif (cpuis("NUC029?DE")) group.long 0x0++0xF line.long 0x0 "GPIOA_PMD,GPIO Port A Pin I/O Mode Control" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOA_OFFD,GPIO Port A Pin Digital Input Path Disable Control" bitfld.long 0x4 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." line.long 0x8 "GPIOA_DOUT,GPIO Port A Data Output Value" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." line.long 0xC "GPIOA_DMASK,GPIO Port A Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_PIN,GPIO Port A Pin Value" bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" group.long 0x14++0xF line.long 0x0 "GPIOA_DBEN,GPIO Port A De-bounce Enable" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOA_IMD,GPIO Port A Interrupt Mode Control" bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOA_IEN,GPIO Port A Interrupt Enable" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOA_ISRC,GPIO Port A Interrupt Source Flag" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x40++0xF line.long 0x0 "GPIOB_PMD,GPIO Port B Pin I/O Mode Control" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOB_OFFD,GPIO Port B Pin Digital Input Path Disable Control" bitfld.long 0x4 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." line.long 0x8 "GPIOB_DOUT,GPIO Port B Data Output Value" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." line.long 0xC "GPIOB_DMASK,GPIO Port B Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x50++0x3 line.long 0x0 "GPIOB_PIN,GPIO Port B Pin Value" bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" group.long 0x54++0xF line.long 0x0 "GPIOB_DBEN,GPIO Port B De-bounce Enable" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOB_IMD,GPIO Port B Interrupt Mode Control" bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOB_IEN,GPIO Port B Interrupt Enable" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOB_ISRC,GPIO Port B Interrupt Source Flag" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x80++0xF line.long 0x0 "GPIOC_PMD,GPIO Port C Pin I/O Mode Control" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOC_OFFD,GPIO Port C Pin Digital Input Path Disable Control" bitfld.long 0x4 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." line.long 0x8 "GPIOC_DOUT,GPIO Port C Data Output Value" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." line.long 0xC "GPIOC_DMASK,GPIO Port C Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x90++0x3 line.long 0x0 "GPIOC_PIN,GPIO Port C Pin Value" bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" group.long 0x94++0xF line.long 0x0 "GPIOC_DBEN,GPIO Port C De-bounce Enable" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOC_IMD,GPIO Port C Interrupt Mode Control" bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOC_IEN,GPIO Port C Interrupt Enable" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOC_ISRC,GPIO Port C Interrupt Source Flag" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0xC0++0xF line.long 0x0 "GPIOD_PMD,GPIO Port D Pin I/O Mode Control" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOD_OFFD,GPIO Port D Pin Digital Input Path Disable Control" bitfld.long 0x4 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." line.long 0x8 "GPIOD_DOUT,GPIO Port D Data Output Value" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." line.long 0xC "GPIOD_DMASK,GPIO Port D Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0xD0++0x3 line.long 0x0 "GPIOD_PIN,GPIO Port D Pin Value" bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" group.long 0xD4++0xF line.long 0x0 "GPIOD_DBEN,GPIO Port D De-bounce Enable" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOD_IMD,GPIO Port D Interrupt Mode Control" bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOD_IEN,GPIO Port D Interrupt Enable" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOD_ISRC,GPIO Port D Interrupt Source Flag" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x100++0xF line.long 0x0 "GPIOE_PMD,GPIO Port E Pin I/O Mode Control" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOE_OFFD,GPIO Port E Pin Digital Input Path Disable Control" bitfld.long 0x4 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." line.long 0x8 "GPIOE_DOUT,GPIO Port E Data Output Value" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." line.long 0xC "GPIOE_DMASK,GPIO Port E Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x110++0x3 line.long 0x0 "GPIOE_PIN,GPIO Port E Pin Value" bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" group.long 0x114++0xF line.long 0x0 "GPIOE_DBEN,GPIO Port E De-bounce Enable" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOE_IMD,GPIO Port E Interrupt Mode Control" bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOE_IEN,GPIO Port E Interrupt Enable" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOE_ISRC,GPIO Port E Interrupt Source Flag" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x140++0xF line.long 0x0 "GPIOF_PMD,GPIO Port F Pin I/O Mode Control" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note2:.The initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOF_OFFD,GPIO Port F Pin Digital Input Path Disable Control" bitfld.long 0x4 31. "OFFD15,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 30. "OFFD14,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "OFFD13,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 28. "OFFD12,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "OFFD11,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 26. "OFFD10,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "OFFD9,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 24. "OFFD8,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "OFFD7,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 22. "OFFD6,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "OFFD5,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 20. "OFFD4,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "OFFD3,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 18. "OFFD2,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "OFFD1,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." bitfld.long 0x4 16. "OFFD0,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current leakage.." "0: I/O digital input path Enabled,1: I/O digital input path Disabled (digital input.." line.long 0x8 "GPIOF_DOUT,GPIO Port F Data Output Value" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.." "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.." line.long 0xC "GPIOF_DMASK,GPIO Port F Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x150++0x3 line.long 0x0 "GPIOF_PIN,GPIO Port F Pin Value" bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low..Note:." "0,1" group.long 0x154++0xF line.long 0x0 "GPIOF_DBEN,GPIO Port F De-bounce Enable" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOF_IMD,GPIO Port F Interrupt Mode Control" bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOF_IEN,GPIO Port F Interrupt Enable" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function..When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOF_ISRC,GPIO Port F Interrupt Source Flag" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag.Read :." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x200++0x8F line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x14 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x18 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x1C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x20 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x24 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x28 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x2C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x30 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x34 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x38 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x3C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x40 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x44 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x48 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x4C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x50 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x54 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x58 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x5C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x60 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x64 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x68 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x6C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x70 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x74 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x78 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x7C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x80 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x84 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x88 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x8C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" endif sif (cpuis("NUC029?AE")) group.long 0x140++0xF line.long 0x0 "P5_PMD,P5 I/O Mode Control" bitfld.long 0x0 14.--15. "PMD7,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,Port 0-5 I/O Pin [n] Mode Control.Determine each I/O mode of Px.n pin..Note2:.P0_PMD[7:4] are reserved..P1_PMD[15:12] [3:2] are reserved..P2_PMD[15:14] [3:0] are reserved..P3_PMD[15:14] [7:6] are reserved..P4_PMD[11:0] are.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "P5_OFFD,P5 Digital Input Path Disable Control" hexmask.long.byte 0x4 16.--23. 1. "OFFD,Port 0-5 Pin [n] Digital Input Path Disable Control" line.long 0x8 "P5_DOUT,P5 Data Output Value" hexmask.long.byte 0x8 0.--7. 1. "DOUT,Port 0-5 Pin [n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output and Quasi-bidirectional mode..Note2:.P0_DOUT[3:2] are reserved..P1_DOUT[7:6] [1] are.." line.long 0xC "P5_DMASK,P5 Data Output Write Mask" hexmask.long.byte 0xC 0.--7. 1. "DMASK,Port 0-5 Pin [n] Data Output Write Mask.These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding Px_DOUT[n] bit is protected. If the write signal is masked writing data to the protect.." rgroup.long 0x150++0x3 line.long 0x0 "P5_PIN,P5 Pin Value" hexmask.long.byte 0x0 0.--7. 1. "PIN,Port 0-5 Pin [n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note2:.P0_PIN[3:2] are.." group.long 0x154++0xF line.long 0x0 "P5_DBEN,P5 De-bounce Enable Control" hexmask.long.byte 0x0 0.--7. 1. "DBEN,Port 0-5 Pin [n] Input Signal De-bounce Enable Control.DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." line.long 0x4 "P5_IMD,P5 Interrupt Mode Control" hexmask.long.byte 0x4 0.--7. 1. "IMD,Port 0-5 Pin [n] Edge or Level Detection Interrupt Mode Control.IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If.." line.long 0x8 "P5_IEN,P5 Interrupt Enable Control" hexmask.long.byte 0x8 16.--23. 1. "IR_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Rising Edge or Input Level High.IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IR_EN[n].." bitfld.long 0x8 0. "IF_EN,Port 0-5 Pin [n] Interrupt Enabled by Input Falling Edge or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting the IF_EB[n] bit to.." "0: Px.n low level or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "P5_ISRC,P5 Interrupt Source Flag" hexmask.long.byte 0xC 0.--7. 1. "ISRC,Port 0-5 Pin [n] Interrupt Source Flag.Write :.Note2:.P0_ISRC[3:2] are reserved..P1_ISRC[7:6] [1] are reserved..P2_ISRC[7] [1:0] are reserved..P3_ISRC[7] [3] are reserved..P4_ISRC[5:0] are reserved..P5_ISRC[7:6] are reserved." group.long 0x2A0++0x17 line.long 0x0 "P50_PDIO,GPIO P5.0 Pin Data Input/Output" bitfld.long 0x0 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." line.long 0x4 "P51_PDIO,GPIO P5.1 Pin Data Input/Output" bitfld.long 0x4 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." line.long 0x8 "P52_PDIO,GPIO P5.2 Pin Data Input/Output" bitfld.long 0x8 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." line.long 0xC "P53_PDIO,GPIO P5.3 Pin Data Input/Output" bitfld.long 0xC 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." line.long 0x10 "P54_PDIO,GPIO P5.4 Pin Data Input/Output" bitfld.long 0x10 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." line.long 0x14 "P55_PDIO,GPIO P5.5 Pin Data Input/Output" bitfld.long 0x14 0. "P_PDIO,GPIO Px.n Pin Data Iutput/Output.Writing this bit can control one GPIO pin output value..Note2: The writing operation will not be affected by register Px_DMASK[n]." "0: Corresponding GPIO pin set to..,1: Corresponding GPIO pin set to.." endif sif (cpuis("NUC029?EE")) group.long 0x0++0xF line.long 0x0 "GPIOA_PMD,GPIO Port A Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOA_OFFD,GPIO Port A Pin Digital Input Path Disable Register" hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current.." line.long 0x8 "GPIOA_DOUT,GPIO Port A Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." line.long 0xC "GPIOA_DMASK,GPIO Port A Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_PIN,GPIO Port A Pin Value Register" bitfld.long 0x0 15. "PIN15,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" group.long 0x14++0xF line.long 0x0 "GPIOA_DBEN,GPIO Port A De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOA_IMD,GPIO Port A Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOA_IEN,GPIO Port A Interrupt Enable Register" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOA_ISRC,GPIO Port A Interrupt Source Flag Register" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x40++0xF line.long 0x0 "GPIOB_PMD,GPIO Port B Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOB_OFFD,GPIO Port B Pin Digital Input Path Disable Register" hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current.." line.long 0x8 "GPIOB_DOUT,GPIO Port B Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." line.long 0xC "GPIOB_DMASK,GPIO Port B Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x50++0x3 line.long 0x0 "GPIOB_PIN,GPIO Port B Pin Value Register" bitfld.long 0x0 15. "PIN15,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" group.long 0x54++0xF line.long 0x0 "GPIOB_DBEN,GPIO Port B De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOB_IMD,GPIO Port B Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOB_IEN,GPIO Port B Interrupt Enable Register" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOB_ISRC,GPIO Port B Interrupt Source Flag Register" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x80++0xF line.long 0x0 "GPIOC_PMD,GPIO Port C Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOC_OFFD,GPIO Port C Pin Digital Input Path Disable Register" hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current.." line.long 0x8 "GPIOC_DOUT,GPIO Port C Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." line.long 0xC "GPIOC_DMASK,GPIO Port C Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x90++0x3 line.long 0x0 "GPIOC_PIN,GPIO Port C Pin Value Register" bitfld.long 0x0 15. "PIN15,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" group.long 0x94++0xF line.long 0x0 "GPIOC_DBEN,GPIO Port C De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOC_IMD,GPIO Port C Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOC_IEN,GPIO Port C Interrupt Enable Register" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOC_ISRC,GPIO Port C Interrupt Source Flag Register" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0xC0++0xF line.long 0x0 "GPIOD_PMD,GPIO Port D Pin I/O Mode Control Register" line.long 0x4 "GPIOD_OFFD,GPIO Port D Pin Digital Input Path Disable Register" line.long 0x8 "GPIOD_DOUT,GPIO Port D Data Output Value Register" line.long 0xC "GPIOD_DMASK,GPIO Port D Data Output Write Mask Register" group.long 0x100++0xF line.long 0x0 "GPIOE_PMD,GPIO Port E Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOE_OFFD,GPIO Port E Pin Digital Input Path Disable Register" hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current.." line.long 0x8 "GPIOE_DOUT,GPIO Port E Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." line.long 0xC "GPIOE_DMASK,GPIO Port E Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x110++0x3 line.long 0x0 "GPIOE_PIN,GPIO Port E Pin Value Register" bitfld.long 0x0 15. "PIN15,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" group.long 0x114++0xF line.long 0x0 "GPIOE_DBEN,GPIO Port E De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOE_IMD,GPIO Port E Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOE_IEN,GPIO Port E Interrupt Enable Register" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOE_ISRC,GPIO Port E Interrupt Source Flag Register" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x140++0xF line.long 0x0 "GPIOF_PMD,GPIO Port F Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control.Determine each I/O mode of GPIOx pins..Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?" line.long 0x4 "GPIOF_OFFD,GPIO Port F Pin Digital Input Path Disable Register" hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit.Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid current.." line.long 0x8 "GPIOF_DOUT,GPIO Port F Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." newline bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode..Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High if.." line.long 0xC "GPIOF_DMASK,GPIO Port F Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" newline bitfld.long 0xC 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" bitfld.long 0xC 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask.These bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected" rgroup.long 0x150++0x3 line.long 0x0 "GPIOF_PIN,GPIO Port F Pin Value Register" bitfld.long 0x0 15. "PIN15,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 14. "PIN14,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 13. "PIN13,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 12. "PIN12,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 11. "PIN11,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 10. "PIN10,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 9. "PIN9,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 8. "PIN8,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 7. "PIN7,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 6. "PIN6,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 5. "PIN5,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 4. "PIN4,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 3. "PIN3,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 2. "PIN2,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" newline bitfld.long 0x0 1. "PIN1,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" bitfld.long 0x0 0. "PIN0,Port [A/B/C/E/F] Pin Values.Each bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 .." "0,1" group.long 0x154++0xF line.long 0x0 "GPIOF_DBEN,GPIO Port F De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit.DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled" line.long 0x4 "GPIOF_IMD,GPIO Port F Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control.IMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOF_IEN,GPIO Port F Interrupt Enable Register" bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High.IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function .When setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low.IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.When setting the IF_EN[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: .If the interrupt is level trigger" line.long 0xC "GPIOF_ISRC,GPIO Port F Interrupt Source Flag Register" bitfld.long 0xC 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." newline bitfld.long 0xC 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." bitfld.long 0xC 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag.Read :.Note2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: No interrupt at GPIOx[n]..No action,1: GPIOx[n] generates an interrupt..Clear the.." group.long 0x200++0xBF line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x14 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x18 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x1C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x20 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x24 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x28 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x2C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x30 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x34 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x38 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x3C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x40 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x44 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x48 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x4C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x50 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x54 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x58 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x5C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x60 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x64 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x68 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x6C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x70 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x74 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x78 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x7C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x80 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x84 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x88 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x8C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x90 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x94 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x98 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x9C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xA0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xA4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xA8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xAC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xB0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xB4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xB8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xBC "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0xBC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x300++0x4F line.long 0x0 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x14 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x18 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x1C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x20 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x20 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x24 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x24 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x28 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x28 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x2C "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x2C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x30 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x30 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x34 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x34 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x38 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x38 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x3C "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register" bitfld.long 0x3C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x40 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register" bitfld.long 0x40 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x44 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register" bitfld.long 0x44 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x48 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register" bitfld.long 0x48 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4C "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register" bitfld.long 0x4C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value.Note3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" endif sif (cpuis("NUC029?GE")) group.long 0x0++0xF line.long 0x0 "PA_MODE,PA I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PA_DOUT,PA Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PA_DATMSK,PA Data Output Write Mask" bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x10++0x3 line.long 0x0 "PA_PIN,PA Pin Value" bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" group.long 0x14++0x17 line.long 0x0 "PA_DBEN,PA De-bounce Enable Control" bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PA_INTEN,PA Interrupt Enable Control" bitfld.long 0x8 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "PA_INTSRC,PA Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable" bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" line.long 0x14 "PA_SLEWCTL,PA High Slew Rate Control" bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" group.long 0x40++0xF line.long 0x0 "PB_MODE,PB I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PB_DOUT,PB Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PB_DATMSK,PB Data Output Write Mask" bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x50++0x3 line.long 0x0 "PB_PIN,PB Pin Value" bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" group.long 0x54++0x17 line.long 0x0 "PB_DBEN,PB De-bounce Enable Control" bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PB_INTEN,PB Interrupt Enable Control" bitfld.long 0x8 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "PB_INTSRC,PB Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable" bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control" bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" group.long 0x80++0xF line.long 0x0 "PC_MODE,PC I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PC_DOUT,PC Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PC_DATMSK,PC Data Output Write Mask" bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x90++0x3 line.long 0x0 "PC_PIN,PC Pin Value" bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" group.long 0x94++0x17 line.long 0x0 "PC_DBEN,PC De-bounce Enable Control" bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PC_INTEN,PC Interrupt Enable Control" bitfld.long 0x8 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "PC_INTSRC,PC Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable" bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control" bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" group.long 0xC0++0xF line.long 0x0 "PD_MODE,PD I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PD_DOUT,PD Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PD_DATMSK,PD Data Output Write Mask" bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0xD0++0x3 line.long 0x0 "PD_PIN,PD Pin Value" bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" group.long 0xD4++0x17 line.long 0x0 "PD_DBEN,PD De-bounce Enable Control" bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PD_INTEN,PD Interrupt Enable Control" bitfld.long 0x8 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "PD_INTSRC,PD Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable" bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" line.long 0x14 "PD_SLEWCTL,PD High Slew Rate Control" bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" group.long 0x100++0xF line.long 0x0 "PE_MODE,PE I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PE_DINOFF,PE Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PE_DOUT,PE Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PE_DATMSK,PE Data Output Write Mask" bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x110++0x3 line.long 0x0 "PE_PIN,PE Pin Value" bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" group.long 0x114++0x1B line.long 0x0 "PE_DBEN,PE De-bounce Enable Control" bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PE_INTTYPE,PE Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PE_INTEN,PE Interrupt Enable Control" bitfld.long 0x8 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "PE_INTSRC,PE Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." line.long 0x10 "PE_SMTEN,PE Input Schmitt Trigger Enable" bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" line.long 0x14 "PE_SLEWCTL,PE High Slew Rate Control" bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" line.long 0x18 "PE_DRVCTL,PE High Drive Strength Control" bitfld.long 0x18 13. "HDRVEN13,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength" bitfld.long 0x18 12. "HDRVEN12,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength" newline bitfld.long 0x18 11. "HDRVEN11,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength" bitfld.long 0x18 10. "HDRVEN10,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength" newline bitfld.long 0x18 9. "HDRVEN9,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength" bitfld.long 0x18 8. "HDRVEN8,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength" group.long 0x140++0xF line.long 0x0 "PF_MODE,PF I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control.Determine each I/O mode of Px.n pins..Note3: The PE.14/PE.15 pin is ignored." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control.Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PF_DOUT,PF Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value.Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode..Note2: The PE.14/PE.15 pin is ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PF_DATMSK,PF Data Output Write Mask" bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask.These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x150++0x3 line.long 0x0 "PF_PIN,PF Pin Value" bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value.Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low..Note1: .Note2: The PE.14/PE.15 pin is ignored." "0,1" group.long 0x154++0x17 line.long 0x0 "PF_DBEN,PF De-bounce Enable Control" bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit.The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control.TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PF_INTEN,PF Interrupt Enable Control" bitfld.long 0x8 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit.The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. .When.." "0: Px.n level high or low to high interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" newline bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit.The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function..When setting.." "0: Px.n level low or high to low interrupt Disabled,1: .If the interrupt is level trigger" line.long 0xC "PF_INTSRC,PF Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag.Write Operation:.Note2: The PE.14/PE.15 pin is ignored." "0: No action..No interrupt at Px.n,1: Clear the corresponding pending interrupt..Px.n.." line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable" bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit.Note2: The PE.14/PE.15 pin is ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control" bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" newline bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control.Note2: The PE.14/PE.15 pin is ignored.." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate" group.long 0x180++0x3 line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control" bitfld.long 0x0 5. "ICLKON,Interrupt Clock on Mode.Note: It is recommended to disable this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.." bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the internal.." newline hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection" group.long 0x200++0x137 line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output" bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output" bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x80 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x84 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x88 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x8C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x90 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x94 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x98 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x9C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xA0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xA4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xA8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xAC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xB0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xB4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xB8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xBC "PC15_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xBC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xC0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xC4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xC8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xCC "PD3_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xCC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xD0 "PD4_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xD0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xD4 "PD5_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xD4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xD8 "PD6_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xD8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xDC "PD7_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xDC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xE0 "PD8_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xE0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xE4 "PD9_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xE4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xE8 "PD10_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xE8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xEC "PD11_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xEC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xF0 "PD12_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xF0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xF4 "PD13_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xF4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xF8 "PD14_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xF8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xFC "PD15_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0xFC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x100 "PE0_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x100 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x104 "PE1_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x104 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x108 "PE2_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x108 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10C "PE3_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x10C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x110 "PE4_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x110 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x114 "PE5_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x114 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x118 "PE6_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x118 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x11C "PE7_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x11C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x120 "PE8_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x120 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x124 "PE9_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x124 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x128 "PE10_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x128 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x12C "PE11_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x12C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x130 "PE12_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x130 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x134 "PE13_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x134 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x340++0x1F line.long 0x0 "PF0_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PF1_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PF2_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PF3_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PF4_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PF5_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PF6_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PF7_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output.Writing this bit can control one GPIO pin output value..Note3: The PE.14/PE.15 pin is ignored." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) group.long 0x180++0x3 line.long 0x0 "DBNCECON,Interrupt De-bounce Control" bitfld.long 0x0 5. "ICLK_ON,Interrupt Clock On Mode.Note: It is recommended to turn off this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.." bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.." newline hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection" endif sif (cpuis("NUC029?AN")) group.long 0x208++0x7 line.long 0x0 "P02_PDIO,GPIO P0.2 Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x4 "P03_PDIO,GPIO P0.3 Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" group.long 0x224++0x3 line.long 0x0 "P11_PDIO,GPIO P1.1 Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" group.long 0x238++0xF line.long 0x0 "P16_PDIO,GPIO P1.6 Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x4 "P17_PDIO,GPIO P1.7 Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x8 "P20_PDIO,GPIO P2.0 Pin Data Input/Output" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0xC "P21_PDIO,GPIO P2.1 Pin Data Input/Output" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" group.long 0x25C++0x3 line.long 0x0 "P27_PDIO,GPIO P2.7 Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" group.long 0x26C++0x3 line.long 0x0 "P33_PDIO,GPIO P3.3 Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" group.long 0x27C++0x1B line.long 0x0 "P37_PDIO,GPIO P3.7 Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x4 "P40_PDIO,GPIO P4.0 Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x8 "P41_PDIO,GPIO P4.1 Pin Data Input/Output" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0xC "P42_PDIO,GPIO P4.2 Pin Data Input/Output" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x10 "P43_PDIO,GPIO P4.3 Pin Data Input/Output" bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x14 "P44_PDIO,GPIO P4.4 Pin Data Input/Output" bitfld.long 0x14 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" line.long 0x18 "P45_PDIO,GPIO P4.5 Pin Data Input/Output" bitfld.long 0x18 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output.Write this bit can control one GPIO pin output value" "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high" endif sif (cpuis("NUC029?DE")) group.long 0x298++0x17 line.long 0x0 "PC6_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PC7_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PC8_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PC9_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PC10_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PC11_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x14 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x2B8++0x7 line.long 0x0 "PC14_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PC15_PDIO,GPIO PC.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x2D8++0x7 line.long 0x0 "PD6_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PD7_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x2F8++0x7 line.long 0x0 "PD14_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PD15_PDIO,GPIO PD.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x314++0x3 line.long 0x0 "PE5_PDIO,GPIO PE.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x340++0x7 line.long 0x0 "PF0_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PF1_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x350++0x13 line.long 0x0 "PF4_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PF5_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PF6_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PF7_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PF8_PDIO,GPIO PF.n Pin Data Input/Output" bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output.Write this bit can control one GPIO pin output value..Read this register to get GPIO pin status..For example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" endif tree.end sif (cpuis("NUC029?GE")) tree "HDIV (Hardware Divider)" base ad:0x50014000 group.long 0x0++0xF line.long 0x0 "HDIV_DIVIDEND,Dividend Source Register" hexmask.long 0x0 0.--31. 1. "DIVIDEND,Dividend Source.This register is given the dividend of divider before calculation starting." line.long 0x4 "HDIV_DIVISOR,Divisor Source Resister" hexmask.long.word 0x4 0.--15. 1. "DIVISOR,Divisor Source.This register is given the divisor of divider before calculation starts..Note: When this register is written hardware divider will start calculate." line.long 0x8 "HDIV_DIVQUO,Quotient Result Resister" hexmask.long 0x8 0.--31. 1. "QUOTIENT,Quotient Result.This register holds the quotient result of divider after calculation complete." line.long 0xC "HDIV_DIVREM,Remainder Result Register" hexmask.long 0xC 0.--31. 1. "REMAINDER,Remainder Result.The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) which holds the remainder result of divider after calculation complete. The remainder of hardware divider with sign extension (REMAINDER[31:16]) to.." rgroup.long 0x10++0x3 line.long 0x0 "HDIV_DIVSTS,Divider Status Register" bitfld.long 0x0 1. "DIV0,Divisor Zero Warning.Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written. This register is read only." "0: The divisor is not 0,1: The divisor is 0" bitfld.long 0x0 0. "FINISH,Division Finish Flag.The flag will become low when the divider is in calculation. The flag will go back to high once the calculation finished." "0: Under Calculation,1: Calculation finished" tree.end endif sif (cpuis("NUC029?AE")) base ad:0x40020000 elif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) base ad:0x0 endif tree "I2C (Inter-Integrated Circuit)" sif (cpuis("NUC029?AE")) group.long 0x0++0x7 line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Interrupt Enable Control" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Control" "0: I2C Controller Disabled,1: I2C Controller Enabled" newline bitfld.long 0x0 5. "STA,I2C START Control Bit.Setting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control Bit.In Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets.." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON[7]) is set the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit" "0,1" line.long 0x4 "I2CADRR0,I2C Slave Address Register 0" group.long 0x4++0x7 line.long 0x0 "I2CADDR0,I2C Slave Address Register 0" hexmask.long.byte 0x0 1.--7. 1. "I2CADDR,I2C Address Bits.The content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x0 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x4 "I2CDAT,I2C DATA Register" hexmask.long.byte 0x4 0.--7. 1. "I2CDAT,I2C Data Bits.Bit [7:0] is located with the 8-bit transferred data of the I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Bits" group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Bits.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Time-Out Counter Register" bitfld.long 0x4 2. "ENTI,Time-out Counter Enable Control.Note: When the 14-bit time-out counter is enabled it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x4 1. "DIV4,Time-out Counter Input Clock Divided by 4.Note: When enabled the time-out period is extended 4 times." "0: Time-out counter input clock divided by 4 Disabled,1: Time-out counter input clock divided by 4 Enabled" newline bitfld.long 0x4 0. "TIF,Time-out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1..Note: Software can write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register 1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Bits.The content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2CADDR2,I2C Slave Address Register 2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Bits.The content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CADDR3,I2C Slave Address Register 3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Bits.The content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register 0" hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Bits" line.long 0x18 "I2CADM1,I2C Slave Address Mask Register 1" hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Bits" line.long 0x1C "I2CADM2,I2C Slave Address Mask Register 2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Bits" line.long 0x20 "I2CADM3,I2C Slave Address Mask Register 3" hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Bits" group.long 0x3C++0x7 line.long 0x0 "I2CCON2,I2C Control Register 2" bitfld.long 0x0 4. "UNDER_INTEN,I2C UNDER RUN Interrupt Control Bit.Setting UNDER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO." "0: Disabled,1: Enabled" bitfld.long 0x0 3. "OVER_INTEN,I2C OVER RUN Interrupt Control Bit.Setting OVER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "NOSTRETCH,NO STRETCH the I2C BUS" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.." bitfld.long 0x0 1. "TWOFF_EN,TWO LEVEL FIFO Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "WAKEUPEN,Wake-Up Enable Control.The system can be wake up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register." "0: I2C wake up function Disabled,1: I2C wake up function Enabled" line.long 0x4 "I2CSTATUS2,I2C Status Register 2" bitfld.long 0x4 4. "UNDERUN,I2C UNDER RUN Status Bit" "0,1" bitfld.long 0x4 3. "OVERUN,I2C OVER RUN Status Bit" "0,1" newline bitfld.long 0x4 2. "EMPTY,I2C TWO LEVEL FIFO EMPTY" "0,1" bitfld.long 0x4 1. "FULL,I2C TWO LEVEL FIFO FULL" "0,1" newline bitfld.long 0x4 0. "WAKEUPIF,I2C Wake-up Interrupt Flag.When chip is woken up from Power-Down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1" endif sif (cpuis("NUC029?AN")) tree "I2C0" base ad:0x40020000 group.long 0x0++0xB line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Enable Interrupt" "0: Disable I2C interrupt,1: Enable I2C interrupt" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Bit" "0: Disable,1: Enable" bitfld.long 0x0 5. "STA,I2C START Control Bit.Setting STA to logic 1 to enter master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control Bit.In master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode setting STO.." "0,1" bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit" "0,1" line.long 0x4 "I2CADDR0,I2C Slave Address Register 0" hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x4 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0x8 "I2CDAT,I2C DATA Register" hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register.Bit [7:0] is located with the 8-bit transferred data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register.The status register of I2C:" group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C clock divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C clock divided Register.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Timeout Control Register" bitfld.long 0x4 2. "ENTI,Time-out counter is enabled/disable.When Enable the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared." "0: Disable,1: Enable" bitfld.long 0x4 1. "DIV4,Time-Out counter input clock is divided by 4 .When Enable The time-Out period is extend 4 times." "0: Disable,1: Enable" bitfld.long 0x4 0. "TIF,Time-Out Flag.This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1..S/W can write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register 1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x8 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0xC "I2CADDR2,I2C Slave Address Register 2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0x10 "I2CADDR3,I2C Slave Address Register 3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register 0" hexmask.long.byte 0x14 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x18 "I2CADM1,I2C Slave Address Mask Register 1" hexmask.long.byte 0x18 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x1C "I2CADM2,I2C Slave Address Mask Register 2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x20 "I2CADM3,I2C Slave Address Mask Register 3" hexmask.long.byte 0x20 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." group.long 0x3C++0x7 line.long 0x0 "I2CWKUPCON,I2C Wake Up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wakeup Function Enable" "0: Disable I2C wake up function,1: Enable I2C wake up function" line.long 0x4 "I2CWKUPSTS,I2C Wake Up Status Register" bitfld.long 0x4 0. "WKUPIF,I2C Wake Up Interrupt Flag.When chip is waked up from power down mode by I2C this bit is set to 1. Software can write 1 to clear this bit" "0,1" tree.end tree "I2C1" base ad:0x40120000 group.long 0x0++0xB line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Enable Interrupt" "0: Disable I2C interrupt,1: Enable I2C interrupt" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Bit" "0: Disable,1: Enable" bitfld.long 0x0 5. "STA,I2C START Control Bit.Setting STA to logic 1 to enter master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control Bit.In master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode setting STO.." "0,1" bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit" "0,1" line.long 0x4 "I2CADDR0,I2C Slave Address Register 0" hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x4 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0x8 "I2CDAT,I2C DATA Register" hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register.Bit [7:0] is located with the 8-bit transferred data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register.The status register of I2C:" group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C clock divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C clock divided Register.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Timeout Control Register" bitfld.long 0x4 2. "ENTI,Time-out counter is enabled/disable.When Enable the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared." "0: Disable,1: Enable" bitfld.long 0x4 1. "DIV4,Time-Out counter input clock is divided by 4 .When Enable The time-Out period is extend 4 times." "0: Disable,1: Enable" bitfld.long 0x4 0. "TIF,Time-Out Flag.This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1..S/W can write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register 1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x8 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0xC "I2CADDR2,I2C Slave Address Register 2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0x10 "I2CADDR3,I2C Slave Address Register 3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call Function" "0: Disable General Call Function,1: Enable General Call Function" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register 0" hexmask.long.byte 0x14 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x18 "I2CADM1,I2C Slave Address Mask Register 1" hexmask.long.byte 0x18 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x1C "I2CADM2,I2C Slave Address Mask Register 2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x20 "I2CADM3,I2C Slave Address Mask Register 3" hexmask.long.byte 0x20 1.--7. 1. "I2CADMx,I2C Address Mask register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." group.long 0x3C++0x7 line.long 0x0 "I2CWKUPCON,I2C Wake Up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wakeup Function Enable" "0: Disable I2C wake up function,1: Enable I2C wake up function" line.long 0x4 "I2CWKUPSTS,I2C Wake Up Status Register" bitfld.long 0x4 0. "WKUPIF,I2C Wake Up Interrupt Flag.When chip is waked up from power down mode by I2C this bit is set to 1. Software can write 1 to clear this bit" "0,1" tree.end endif sif (cpuis("NUC029?DE")) tree "I2C0" base ad:0x40020000 group.long 0x0++0xB line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Interrupt Enable Coontrol." "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Coontrol." "0: Disabled,1: Enabled" bitfld.long 0x0 5. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control.In Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode setting STO resets.." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control." "0,1" line.long 0x4 "I2CADDR0,I2C Slave Address Register0" hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x4 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x8 "I2CDAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register.This field is located with the 8-bit transferred data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register.There are 26 possible status codes. .When I2CSTATUS contains 0xF8 no serial interrupt is requested. .In addition states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an.." group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Time-out Counter Register" bitfld.long 0x4 2. "ENTI,Time-Out Counter Enable Coontrol .When Enabled the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared." "0: Disabled,1: Enabled" bitfld.long 0x4 1. "DIV4,Time-Out Counter Input Clock Divided By 4.When Enabled The time-out period is extend 4 times." "0: Disabled,1: Enabled" bitfld.long 0x4 0. "TIF,Time-Out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI (I2CON[7]) is set to 1..Note: Write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x8 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2CADDR2,I2C Slave Address Register2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CADDR3,I2C Slave Address Register3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register0" hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x18 "I2CADM1,I2C Slave Address Mask Register1" hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x1C "I2CADM2,I2C Slave Address Mask Register2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x20 "I2CADM3,I2C Slave Address Mask Register3" hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." group.long 0x3C++0x7 line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wake-Up Enable Coontrol." "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2CWKUPSTS,I2C Wake-up Status Register" bitfld.long 0x4 0. "WKUPIF,I2C Wake-Up Flag.Note: Software can write 1 to clear this bit." "0: Chip is not woken-up from Power-down mode by I2C,1: Chip is woken-up from Power-down mode by I2C" tree.end tree "I2C1" base ad:0x40120000 group.long 0x0++0xB line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Interrupt Enable Coontrol." "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Coontrol." "0: Disabled,1: Enabled" bitfld.long 0x0 5. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control.In Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode setting STO resets.." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control." "0,1" line.long 0x4 "I2CADDR0,I2C Slave Address Register0" hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x4 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x8 "I2CDAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register.This field is located with the 8-bit transferred data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register.There are 26 possible status codes. .When I2CSTATUS contains 0xF8 no serial interrupt is requested. .In addition states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an.." group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Time-out Counter Register" bitfld.long 0x4 2. "ENTI,Time-Out Counter Enable Coontrol .When Enabled the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared." "0: Disabled,1: Enabled" bitfld.long 0x4 1. "DIV4,Time-Out Counter Input Clock Divided By 4.When Enabled The time-out period is extend 4 times." "0: Disabled,1: Enabled" bitfld.long 0x4 0. "TIF,Time-Out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI (I2CON[7]) is set to 1..Note: Write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x8 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2CADDR2,I2C Slave Address Register2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CADDR3,I2C Slave Address Register3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call Function." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register0" hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x18 "I2CADM1,I2C Slave Address Mask Register1" hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x1C "I2CADM2,I2C Slave Address Mask Register2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x20 "I2CADM3,I2C Slave Address Mask Register3" hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." group.long 0x3C++0x7 line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wake-Up Enable Coontrol." "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2CWKUPSTS,I2C Wake-up Status Register" bitfld.long 0x4 0. "WKUPIF,I2C Wake-Up Flag.Note: Software can write 1 to clear this bit." "0: Chip is not woken-up from Power-down mode by I2C,1: Chip is woken-up from Power-down mode by I2C" tree.end endif sif (cpuis("NUC029?EE")) tree "I2C0" base ad:0x40020000 group.long 0x0++0xB line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Interrupt Enable Bit" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control.In Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode setting STO resets.." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1" line.long 0x4 "I2CADDR0,I2C Slave Address Register0" hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x8 "I2CDAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register.This field is located with the 8-bit transferred data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register.There are 26 possible status codes. .When I2CSTATUS contains 0xF8 no serial interrupt is requested. . In addition states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an.." group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Time-out Counter Register" bitfld.long 0x4 2. "ENTI,Time-Out Counter Enable Bit .When Enabled the 14-bit time-out counter will start counting when SI(I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared." "0: Disabled,1: Enabled" bitfld.long 0x4 1. "DIV4,Time-Out Counter Input Clock Divided By 4.When Enabled The time-out period is extend 4 times." "0: Disabled,1: Enabled" bitfld.long 0x4 0. "TIF,Time-Out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI(I2CON[7]) is set to 1..Note: Write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2CADDR2,I2C Slave Address Register2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CADDR3,I2C Slave Address Register3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register0" hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x18 "I2CADM1,I2C Slave Address Mask Register1" hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x1C "I2CADM2,I2C Slave Address Mask Register2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x20 "I2CADM3,I2C Slave Address Mask Register3" hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." group.long 0x3C++0x7 line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wake-Up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2CWKUPSTS,I2C Wake-up Status Register" bitfld.long 0x4 0. "WKUPIF,I2C Wake-Up Flag.Note: Software can write 1 to clear this bit." "0: Chip is not woken-up from Power-down mode by I2C,1: Chip is woken-up from Power-down mode by I2C" tree.end endif sif (cpuis("NUC029?EE")) tree "I2C1" base ad:0x40012000 group.long 0x0++0xB line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "EI,Interrupt Enable Bit" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "ENS1,I2C Controller Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control.In Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode setting STO resets.." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1" line.long 0x4 "I2CADDR0,I2C Slave Address Register0" hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x8 "I2CDAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register.This field is located with the 8-bit transferred data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register.There are 26 possible status codes. .When I2CSTATUS contains 0xF8 no serial interrupt is requested. . In addition states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an.." group.long 0x10++0x23 line.long 0x0 "I2CLK,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register.Note: The minimum value of I2CLK is 4." line.long 0x4 "I2CTOC,I2C Time-out Counter Register" bitfld.long 0x4 2. "ENTI,Time-Out Counter Enable Bit .When Enabled the 14-bit time-out counter will start counting when SI(I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared." "0: Disabled,1: Enabled" bitfld.long 0x4 1. "DIV4,Time-Out Counter Input Clock Divided By 4.When Enabled The time-out period is extend 4 times." "0: Disabled,1: Enabled" bitfld.long 0x4 0. "TIF,Time-Out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI(I2CON[7]) is set to 1..Note: Write 1 to clear this bit." "0,1" line.long 0x8 "I2CADDR1,I2C Slave Address Register1" hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2CADDR2,I2C Slave Address Register2" hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CADDR3,I2C Slave Address Register3" hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register.The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2CADM0,I2C Slave Address Mask Register0" hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x18 "I2CADM1,I2C Slave Address Mask Register1" hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x1C "I2CADM2,I2C Slave Address Mask Register2" hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." line.long 0x20 "I2CADM3,I2C Slave Address Mask Register3" hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Register.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit.." group.long 0x3C++0x7 line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wake-Up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2CWKUPSTS,I2C Wake-up Status Register" bitfld.long 0x4 0. "WKUPIF,I2C Wake-Up Flag.Note: Software can write 1 to clear this bit." "0: Chip is not woken-up from Power-down mode by I2C,1: Chip is woken-up from Power-down mode by I2C" tree.end endif sif (cpuis("NUC029?GE")) tree "I2C0" base ad:0x40020000 group.long 0x0++0xB line.long 0x0 "I2C_CTL,I2C Control Register 0" bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C serial function Disabled,1: I2C serial function Enabled" newline bitfld.long 0x0 5. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control.In Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1" line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0" hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x8 "I2C_DAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data .Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2C_STATUS,I2C Status Register 0" hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status" group.long 0x10++0x23 line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided .Note: The minimum value of I2C_CLKDIV is 4." line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register" bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit.When Enabled the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4.When Enabled The time-out period is extend 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled" newline bitfld.long 0x4 0. "TOIF,Time-out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1..Note: Software can write 1 to clear this bit." "0,1" line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1" hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2C_ADDR2,I2C Slave Address Register2" hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3" hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0" hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1" hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2" hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3" hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." group.long 0x3C++0xB line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register" bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit.Note: I2C controller could response when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C don't hold bus after wake-up disable,1: I2C don't hold bus after wake-up enable" bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register" bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame.Note: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.." bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done.Note: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.." newline bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag.When chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "I2C_CTL1,I2C Control Register 1" bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C sends STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.." bitfld.long 0x8 7. "NSTRETCH,No Stretch on the I2C Bus" "0: I2C SCL bus is stretched by hardware if the SI..,1: I2C SCL bus is not stretched by hardware if the.." newline bitfld.long 0x8 6. "TWOBUFRST,Two-level Buffer Reset" "0: No effect,1: Reset the related counters two-level buffer.." bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit" "0: Two-level buffer Disabled,1: Two-level buffer Enabled" newline bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit.Setting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1" bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit.Setting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1" newline bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic. This bit will be.." bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" rgroup.long 0x48++0x3 line.long 0x0 "I2C_STATUS1,I2C Status Register 1" bitfld.long 0x0 8. "ONBUSY,on Bus Busy.Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy" bitfld.long 0x0 7. "UDR,I2C Under Run Status Bit" "0,1" newline bitfld.long 0x0 6. "OVR,I2C over Run Status Bit" "0,1" bitfld.long 0x0 5. "EMPTY,Two-level Buffer Empty.This bit is set when POINTER is equal to 0." "0,1" newline bitfld.long 0x0 4. "FULL,Two-level Buffer Full.This bit is set when POINTER is equal to 2" "0,1" group.long 0x4C++0x3 line.long 0x0 "I2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.byte 0x0 6.--11. 1. "HTCTL,Hold Time Configure Control Register.This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode." hexmask.long.byte 0x0 0.--5. 1. "STCTL,Setup Time Configure Control Register .This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode..Note: Setup time setting should not make SCL output less than three PCLKs." tree.end tree "I2C1" base ad:0x40120000 group.long 0x0++0xB line.long 0x0 "I2C_CTL,I2C Control Register 0" bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C serial function Disabled,1: I2C serial function Enabled" newline bitfld.long 0x0 5. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 4. "STO,I2C STOP Control.In Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1" newline bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1" bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1" line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0" hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x8 "I2C_DAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data .Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port." rgroup.long 0xC++0x3 line.long 0x0 "I2C_STATUS,I2C Status Register 0" hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status" group.long 0x10++0x23 line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided .Note: The minimum value of I2C_CLKDIV is 4." line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register" bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit.When Enabled the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4.When Enabled The time-out period is extend 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled" newline bitfld.long 0x4 0. "TOIF,Time-out Flag.This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1..Note: Software can write 1 to clear this bit." "0,1" line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1" hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0xC "I2C_ADDR2,I2C Slave Address Register2" hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3" hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address .The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched." bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0" hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1" hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2" hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3" hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask.I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.." group.long 0x3C++0xB line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register" bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit.Note: I2C controller could response when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C don't hold bus after wake-up disable,1: I2C don't hold bus after wake-up enable" bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register" bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame.Note: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.." bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done.Note: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.." newline bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag.When chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "I2C_CTL1,I2C Control Register 1" bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C sends STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.." bitfld.long 0x8 7. "NSTRETCH,No Stretch on the I2C Bus" "0: I2C SCL bus is stretched by hardware if the SI..,1: I2C SCL bus is not stretched by hardware if the.." newline bitfld.long 0x8 6. "TWOBUFRST,Two-level Buffer Reset" "0: No effect,1: Reset the related counters two-level buffer.." bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit" "0: Two-level buffer Disabled,1: Two-level buffer Enabled" newline bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit.Setting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1" bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit.Setting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1" newline bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic. This bit will be.." bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" rgroup.long 0x48++0x3 line.long 0x0 "I2C_STATUS1,I2C Status Register 1" bitfld.long 0x0 8. "ONBUSY,on Bus Busy.Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy" bitfld.long 0x0 7. "UDR,I2C Under Run Status Bit" "0,1" newline bitfld.long 0x0 6. "OVR,I2C over Run Status Bit" "0,1" bitfld.long 0x0 5. "EMPTY,Two-level Buffer Empty.This bit is set when POINTER is equal to 0." "0,1" newline bitfld.long 0x0 4. "FULL,Two-level Buffer Full.This bit is set when POINTER is equal to 2" "0,1" group.long 0x4C++0x3 line.long 0x0 "I2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.byte 0x0 6.--11. 1. "HTCTL,Hold Time Configure Control Register.This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode." hexmask.long.byte 0x0 0.--5. 1. "STCTL,Setup Time Configure Control Register .This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode..Note: Setup time setting should not make SCL output less than three PCLKs." tree.end endif tree.end tree "INT (Interrupt Source Control)" base ad:0x50000300 rgroup.long 0x0++0x7F line.long 0x0 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x0 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x0 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x0 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x4 "IRQ1_SRC,IRQ1 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x4 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x4 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x4 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x8 "IRQ2_SRC,IRQ2 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x8 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x8 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x8 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0xC "IRQ3_SRC,IRQ3 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0xC 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0xC 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0xC 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x10 "IRQ4_SRC,IRQ4 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x10 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x10 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x10 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x14 "IRQ5_SRC,IRQ5 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x14 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x14 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x14 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x18 "IRQ6_SRC,IRQ6 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")) bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Bit3: PWM3_INT.Bit2: PWM2_INT.Bit1: PWM1_INT.Bit0: PWM0_INT" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x1C "IRQ7_SRC,IRQ7 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")) bitfld.long 0x1C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Bit3: PWM7_INT.Bit2: PWM6_INT.Bit1: PWM5_INT.Bit0: PWM4_INT" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x20 "IRQ8_SRC,IRQ8 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x20 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x20 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x20 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x24 "IRQ9_SRC,IRQ9 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x24 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x24 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x24 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x28 "IRQ10_SRC,IRQ10 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x28 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x28 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x28 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x28 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x2C "IRQ11_SRC,IRQ11 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x2C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x2C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x2C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x2C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x30 "IRQ12_SRC,IRQ12 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x30 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x30 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x30 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x30 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x34 "IRQ13_SRC,IRQ13 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x34 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x34 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x34 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x34 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x38 "IRQ14_SRC,IRQ14 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x38 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x38 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x38 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x38 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x3C "IRQ15_SRC,IRQ15 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x3C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x3C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x3C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x3C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x40 "IRQ16_SRC,IRQ16 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x40 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x40 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x40 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x40 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x44 "IRQ17_SRC,IRQ17 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x44 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x44 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x44 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x44 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x48 "IRQ18_SRC,IRQ18 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x48 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x48 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x48 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x48 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x4C "IRQ19_SRC,IRQ19 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x4C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x4C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x4C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x4C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x50 "IRQ20_SRC,IRQ20 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x50 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x50 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x50 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x50 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x54 "IRQ21_SRC,IRQ21 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x54 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x54 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x54 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x54 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x58 "IRQ22_SRC,IRQ22 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x58 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x58 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x58 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x58 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x5C "IRQ23_SRC,IRQ23 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x5C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x5C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x5C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x5C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x60 "IRQ24_SRC,IRQ24 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x60 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x60 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x60 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x60 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x64 "IRQ25_SRC,IRQ25 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x64 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x64 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x64 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x64 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x68 "IRQ26_SRC,IRQ26 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x68 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x68 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x68 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x68 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x6C "IRQ27_SRC,IRQ27 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x6C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x6C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x6C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x6C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x70 "IRQ28_SRC,IRQ28 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x70 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x70 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x70 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x70 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x74 "IRQ29_SRC,IRQ29 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x74 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x74 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x74 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x74 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x78 "IRQ30_SRC,IRQ30 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x78 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x78 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x78 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x78 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif line.long 0x7C "IRQ31_SRC,IRQ31 (BOD) Interrupt Source Identity" sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")) bitfld.long 0x7C 0.--2. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." "0,1,2,3,4,5,6,7" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x7C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x7C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x7C 0.--3. 1. "INT_SRC,Interrupt Source.Define the interrupt sources for interrupt event." endif sif (cpuis("NUC029?AE")) group.long 0x80++0x3 line.long 0x0 "NMI_CON,NMI Source Interrupt Select Control Register" bitfld.long 0x0 8. "NMI_SEL_EN,NMI Interrupt Enable Control (Write Protect).Note: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: NMI interrupt Disabled,1: NMI interrupt Enabled" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection.The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL." endif sif (cpuis("NUC029?AN")) group.long 0x80++0x3 line.long 0x0 "NMI_SEL,NMI source interrupt select control register" bitfld.long 0x0 8. "NMI_EN,NMI interrupt enable (write-protection bit).This bit is the protected bit. It means programming this needs to write '59h' '16h' '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100" "0: Disable NMI interrupt,1: Enable NMI interrupt" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI interrupt source selection.The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0].The NMI_SEL bit[4:0] used to select the NMI interrupt source" endif sif (cpuis("NUC029?DE")) group.long 0x80++0x3 line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register" bitfld.long 0x0 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100." "0: NMI interrupt Disabled,1: NMI interrupt Enabled" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection.The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL." endif sif (cpuis("NUC029?EE")) group.long 0x80++0x3 line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register" bitfld.long 0x0 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect).Note: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100." "0: NMI interrupt Disabled,1: NMI interrupt Enabled" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection.The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL." endif sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) group.long 0x84++0x3 line.long 0x0 "MCU_IRQ,MCU IRQ Number Identity Register" hexmask.long 0x0 0.--31. 1. "MCU_IRQ,MCU IRQ Source.The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode..The MCU_IRQ collects.." endif sif (cpuis("NUC029?DE")) group.long 0x88++0x3 line.long 0x0 "MCU_IRQCR,MCU Interrupt Request Control Register" bitfld.long 0x0 0. "FAST_IRQ,Fast IRQ Latency Enable Bit." "0: MCU IRQ latency is fixed at 13 clock cycles of..,1: MCU IRQ latency will not fixed MCU will enter.." endif sif (cpuis("NUC029?EE")) group.long 0x88++0x3 line.long 0x0 "MCU_IRQCR,MCU Interrupt Request Control Register" bitfld.long 0x0 0. "FAST_IRQ,Fast IRQ Latency Enable Bit" "0: MCU IRQ latency is fixed at 13 clock cycles of..,1: MCU IRQ latency will not fixed MCU will enter.." endif sif (cpuis("NUC029?GE")) group.long 0x80++0x3 line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register" bitfld.long 0x0 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: NMI interrupt Disabled,1: NMI interrupt Enabled" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection.The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL." endif tree.end sif (cpuis("NUC029?EE")) base ad:0x0 elif (cpuis("NUC029?GE")) base ad:0x50008000 endif sif (cpuis("NUC029?EE")||cpuis("NUC029?GE")) tree "PDMA (Peripheral Direct Memory Access)" sif (cpuis("NUC029?EE")) tree "CRC" base ad:0x50008E00 group.long 0x0++0x7 line.long 0x0 "CRC_CTL,CRC Control Register" bitfld.long 0x0 30.--31. "CRC_MODE,CRC Polynomial Mode.This field indicates the CRC operation polynomial mode." "0: CRC-CCITT Polynomial Mode,1: CRC-8 Polynomial Mode,?,?" bitfld.long 0x0 28.--29. "CPU_WDLEN,CPU Write Data Length.This field indicates the CPU write data length only when operating in CPU PIO mode..Note1: This field is only valid when operating in CPU PIO mode..Note2: When the write data length is 8-bit mode the valid data in.." "0: The write data length is 8-bit mode,1: The write data length is 16-bit mode,?,?" newline bitfld.long 0x0 27. "CHECKSUM_COM,Checksum 1's Complement.This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register." "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled" bitfld.long 0x0 26. "WDATA_COM,Write Data 1's Complement.This bit is used to enable the 1's complement function for write data value in CRC_WDATA register." "0: 1's complement for CRC write data in Disabled,1: 1's complement for CRC write data in Enabled" newline bitfld.long 0x0 25. "CHECKSUM_RVS,Checksum Reverse.This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register..Note: If the checksum result is 0XDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled" bitfld.long 0x0 24. "WDATA_RVS,Write Data Order Reverse.This bit is used to enable the bit order reverse function for write data value in CRC_WDATA register..Note: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reverse for CRC write data in Disabled,1: Bit order reverse for CRC write data in Enabled.." newline bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.This bit is used to trigger the CRC DMA transfer..Note1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode do not fill in any data in CRC_WDATA register..Note2: When CRC DMA transfer completed .." "0: No effect,1: CRC DMA data read or write transfer Enabled" bitfld.long 0x0 1. "CRC_RST,CRC Engine Reset.Note: When operated in CPU PIO mode setting this bit will reload the initial seed value (CRC_SEED register)." "0: No effect,1: Reset the internal CRC state machine and.." newline bitfld.long 0x0 0. "CRCCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled" line.long 0x4 "CRC_DMASAR,CRC DMA Source Address Register" hexmask.long 0x4 0.--31. 1. "CRC_DMASAR,CRC DMA Transfer Source Address Register.This field indicates a 32-bit source address of CRC DMA..Note: The source address must be word alignment" group.long 0xC++0x3 line.long 0x0 "CRC_DMABCR,CRC DMA Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "CRC_DMABCR,CRC DMA Transfer Byte Count Register.This field indicates a 16-bit total transfer byte count number of CRC DMA" rgroup.long 0x14++0x3 line.long 0x0 "CRC_DMACSAR,CRC DMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CRC_DMACSAR,CRC DMA Current Source Address Register (Read Only).This field indicates the current source address where the CRC DMA transfer just occurs." rgroup.long 0x1C++0x3 line.long 0x0 "CRC_DMACBCR,CRC DMA Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "CRC_DMACBCR,CRC DMA Current Remained Byte Count Register (Read Only).This field indicates the current remained byte count of CRC DMA..Note: Setting CRC_RST (CRC_CTL[1]) bit to 1 will clear this register value." group.long 0x20++0x7 line.long 0x0 "CRC_DMAIER,CRC DMA Interrupt Enable Register" bitfld.long 0x0 1. "CRC_BLKD_IE,CRC DMA Block Transfer Done Interrupt Enable Bit.Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF (CRC_DMAISR[1]) bit is set to 1." "0: Interrupt generator Disabled when CRC DMA..,1: Interrupt generator Enabled when CRC DMA.." bitfld.long 0x0 0. "CRC_TABORT_IE,CRC DMA Read/Write Target Abort Interrupt Enable Bit.Enable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF (CRC_DMAISR[0]) bit is set to 1." "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "CRC_DMAISR,CRC DMA Interrupt Status Register" bitfld.long 0x4 1. "CRC_BLKD_IF,CRC DMA Block Transfer Done Interrupt Flag.This bit indicates that CRC DMA transfer has finished or not..It is cleared by writing 1 to it through software...(When CRC DMA transfer done TRIG_EN (CRC_CTL[23]) bit will be cleared.." "0: Not finished if TRIG_EN (CRC_CTL[23]) bit has..,1: CRC transfer done if TRIG_EN (CRC_CTL[23]) bit.." bitfld.long 0x4 0. "CRC_TABORT_IF,CRC DMA Read/Write Target Abort Interrupt Flag.This bit indicates that CRC bus has error or not during CRC DMA transfer..It is cleared by writing 1 to it through software..Note: The bit filed indicate bus master received error response.." "0: No bus error response received during CRC DMA..,1: Bus error response received during CRC DMA.." group.long 0x80++0x7 line.long 0x0 "CRC_WDATA,CRC Write Data Register" hexmask.long 0x0 0.--31. 1. "CRC_WDATA,CRC Write Data Register.When operating in CPU PIO mode software can write data to this field to perform CRC operation..When operating in DMA mode this field indicates the DMA read data from memory and cannot be written..Note: When the.." line.long 0x4 "CRC_SEED,CRC Seed Register" hexmask.long 0x4 0.--31. 1. "CRC_SEED,CRC Seed Register.This field indicates the CRC seed value." rgroup.long 0x88++0x3 line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register" hexmask.long 0x0 0.--31. 1. "CRC_CHECKSUM,CRC Checksum Register.This fields indicates the CRC checksum result" tree.end tree "PDMA_CH0" base ad:0x50008000 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH1" base ad:0x50008100 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH2" base ad:0x50008200 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH3" base ad:0x50008300 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH4" base ad:0x50008400 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH5" base ad:0x50008500 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH6" base ad:0x50008600 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH7" base ad:0x50008700 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_CH8" base ad:0x50008800 group.long 0x0++0x3 line.long 0x0 "PDMA_CSR0,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR1,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR2,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR3,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR4,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR5,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR6,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x3 line.long 0x0 "PDMA_CSR7,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" group.long 0x0++0x7 line.long 0x0 "PDMA_CSR8,PDMA Channel x Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Bit.Note: When PDMA transfer completed this bit will be cleared automatically..If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection.Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved.,?,?" bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing successively,1: Reserved.,?,?" newline bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Bit.Setting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAR0,PDMA Channel x Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR1,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR2,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR3,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR4,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR5,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR6,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x3 line.long 0x0 "PDMA_SAR7,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." group.long 0x4++0x7 line.long 0x0 "PDMA_SAR8,PDMA Channel x Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA..Note: The source address must be word alignment." line.long 0x4 "PDMA_DAR0,PDMA Channel x Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR1,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR2,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR3,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR4,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR5,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR6,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x3 line.long 0x0 "PDMA_DAR7,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" group.long 0x8++0x7 line.long 0x0 "PDMA_DAR8,PDMA Channel x Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA..Note: The destination address must be word alignment" line.long 0x4 "PDMA_BCR0,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR1,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR2,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR3,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR4,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR5,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR6,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR7,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." group.long 0xC++0x3 line.long 0x0 "PDMA_BCR8,PDMA Channel x Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT1,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT2,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT3,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT4,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT5,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT6,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x3 line.long 0x0 "PDMA_POINT7,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." rgroup.long 0x10++0x7 line.long 0x0 "PDMA_POINT8,PDMA Channel x Internal Buffer Pointer Register" hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only).This field indicates the internal buffer pointer." line.long 0x4 "PDMA_CSAR0,PDMA Channel x Current Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR1,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR2,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR3,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR4,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR5,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR6,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x3 line.long 0x0 "PDMA_CSAR7,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." rgroup.long 0x14++0x7 line.long 0x0 "PDMA_CSAR8,PDMA Channel x Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only).This field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR1,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR2,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR3,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR4,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR5,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR6,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x3 line.long 0x0 "PDMA_CDAR7,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." rgroup.long 0x18++0x7 line.long 0x0 "PDMA_CDAR8,PDMA Channel x Current Destination Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only).This field indicates the destination address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x4 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR1,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR2,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR3,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR4,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR5,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR6,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR7,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." rgroup.long 0x1C++0x3 line.long 0x0 "PDMA_CBCR8,PDMA Channel x Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of PDMA..Note: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'." group.long 0x20++0x3 line.long 0x0 "PDMA_IER0,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER1,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER2,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER3,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER4,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER5,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER6,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x3 line.long 0x0 "PDMA_IER7,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." group.long 0x20++0x7 line.long 0x0 "PDMA_IER8,PDMA Channel x Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR0,PDMA Channel x Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR1,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR2,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR3,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR4,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR5,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR6,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR7,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x24++0x3 line.long 0x0 "PDMA_ISR8,PDMA Channel x Interrupt Status Register" bitfld.long 0x0 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag.This bit indicates that PDMA has finished all transfers..Write 1 to clear this bit to 0." "0: Not finished,1: Done" bitfld.long 0x0 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag.Write 1 to clear this bit to 0..Note: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received" rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C1,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C2,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C3,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C4,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C5,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C6,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C7,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_SBUF0_C8,PDMA Channel x Shared Buffer FIFO 0 Register" hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only).Each channel has its own 1 word internal buffer." tree.end tree "PDMA_GCR" base ad:0x50008F00 group.long 0x0++0xB line.long 0x0 "PDMA_GCRCSR,PDMA Global Control Register" bitfld.long 0x0 24. "CRC_CLK_EN,CRC Controller Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "CLK8_EN,PDMA Controller Channel 8 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 15. "CLK7_EN,PDMA Controller Channel 7 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 14. "CLK6_EN,PDMA Controller Channel 6 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 13. "CLK5_EN,PDMA Controller Channel 5 Clock Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "CLK4_EN,PDMA Controller Channel 4 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "CLK3_EN,PDMA Controller Channel 3 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "CLK2_EN,PDMA Controller Channel 2 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 9. "CLK1_EN,PDMA Controller Channel 1 Clock Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "CLK0_EN,PDMA Controller Channel 0 Clock Enable Bit" "0: Disabled,1: Enabled" line.long 0x4 "PDMA_PDSSR0,PDMA Service Selection Control Register 0" hexmask.long.byte 0x4 28.--31. 1. "SPI3_TXSEL,PDMA SPI3 TX Selection.This field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." hexmask.long.byte 0x4 24.--27. 1. "SPI3_RXSEL,PDMA SPI3 RX Selection .This field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." hexmask.long.byte 0x4 20.--23. 1. "SPI2_TXSEL,PDMA SPI2 TX Selection.This field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." hexmask.long.byte 0x4 16.--19. 1. "SPI2_RXSEL,PDMA SPI2 RX Selection.This field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." hexmask.long.byte 0x4 12.--15. 1. "SPI1_TXSEL,PDMA SPI1 TX Selection.This field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." newline hexmask.long.byte 0x4 8.--11. 1. "SPI1_RXSEL,PDMA SPI1 RX Selection.This field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." hexmask.long.byte 0x4 4.--7. 1. "SPI0_TXSEL,PDMA SPI0 TX Selection.This field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]).." hexmask.long.byte 0x4 0.--3. 1. "SPI0_RXSEL,PDMA SPI0 RX Selection.0000: CH0.0001: CH1.0010: CH2.0011: CH3 .0100: CH4 .0101: CH5.0110: CH6.0111: CH7.1000: CH8.Others : Reserved" line.long 0x8 "PDMA_PDSSR1,PDMA Service Selection Control Register 1" hexmask.long.byte 0x8 24.--27. 1. "ADC_RXSEL,PDMA ADC RX Selection.This field defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]).." hexmask.long.byte 0x8 12.--15. 1. "UART1_TXSEL,PDMA UART1 TX Selection.This field defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as UART0_RXSEL.." hexmask.long.byte 0x8 8.--11. 1. "UART1_RXSEL,PDMA UART1 RX Selection.This field defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as UART0_RXSEL.." hexmask.long.byte 0x8 4.--7. 1. "UART0_TXSEL,PDMA UART0 TX Selection.This field defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as UART0_RXSEL.." hexmask.long.byte 0x8 0.--3. 1. "UART0_RXSEL,PDMA UART0 RX Selection.0000: CH0.0001: CH1.0010: CH2.0011: CH3 .0100: CH4 .0101: CH5.0110: CH6.0111: CH7.1000: CH8.Others : Reserved" rgroup.long 0xC++0x3 line.long 0x0 "PDMA_GCRISR,PDMA Global Interrupt Status Register" bitfld.long 0x0 31. "INTR,Interrupt Status.This bit is the interrupt status of PDMA controller..Note: This bit is read only." "0,1" bitfld.long 0x0 16. "INTRCRC,Interrupt Status Of CRC Controller.This bit is the interrupt status of CRC controller.Note: This bit is read only" "0,1" bitfld.long 0x0 8. "INTR8,Interrupt Status Of Channel 8 .This bit is the interrupt status of PDMA channel8..Note: This bit is read only." "0,1" bitfld.long 0x0 7. "INTR7,Interrupt Status Of Channel 7 .This bit is the interrupt status of PDMA channel7..Note: This bit is read only." "0,1" bitfld.long 0x0 6. "INTR6,Interrupt Status Of Channel 6 .This bit is the interrupt status of PDMA channel6..Note: This bit is read only." "0,1" newline bitfld.long 0x0 5. "INTR5,Interrupt Status Of Channel 5 .This bit is the interrupt status of PDMA channel5..Note: This bit is read only." "0,1" bitfld.long 0x0 4. "INTR4,Interrupt Status Of Channel 4.This bit is the interrupt status of PDMA channel4..Note: This bit is read only." "0,1" bitfld.long 0x0 3. "INTR3,Interrupt Status Of Channel 3.This bit is the interrupt status of PDMA channel3..Note: This bit is read only." "0,1" bitfld.long 0x0 2. "INTR2,Interrupt Status Of Channel 2.This bit is the interrupt status of PDMA channel2..Note: This bit is read only." "0,1" bitfld.long 0x0 1. "INTR1,Interrupt Status Of Channel 1.This bit is the interrupt status of PDMA channel1..Note: This bit is read only." "0,1" newline bitfld.long 0x0 0. "INTR0,Interrupt Status Of Channel 0.This bit is the interrupt status of PDMA channel0..Note: This bit is read only." "0,1" tree.end endif sif (cpuis("NUC029?GE")) group.long 0x0++0x4F line.long 0x0 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel 0" hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count.The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field..Note: When.." bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection.This field is used for transfer width..Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?" newline bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment.This field is used to set the destination address increment size." "?,?,?,?" bitfld.long 0x0 8.--9. "SAINC,Source Address Increment.This Field Is Used To Set The Source Address Increment Size." "?,?,?,?" newline bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit.This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt..Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x0 4.--6. "BURSIZE,Burst Size.This field is used for peripheral to determine the burst size or used for determine the re-arbitration size..Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?" newline bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection.Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?" line.long 0x4 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel 0" hexmask.long 0x4 0.--31. 1. "SA,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA controller." line.long 0x8 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel 0" hexmask.long 0x8 0.--31. 1. "DA,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA controller." line.long 0xC "PDMA_DSCT0_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 0" hexmask.long.word 0xC 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset.This field indicates the offset of next descriptor table address in system memory. .Note: write operation is useless in this field." hexmask.long.word 0xC 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset.This field indicates the offset of the first descriptor table address in system memory. .Write Operation:.If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is start.." line.long 0x10 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel 1" hexmask.long.word 0x10 16.--29. 1. "TXCNT,Transfer Count.The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field..Note: When.." bitfld.long 0x10 12.--13. "TXWIDTH,Transfer Width Selection.This field is used for transfer width..Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?" newline bitfld.long 0x10 10.--11. "DAINC,Destination Address Increment.This field is used to set the destination address increment size." "?,?,?,?" bitfld.long 0x10 8.--9. "SAINC,Source Address Increment.This Field Is Used To Set The Source Address Increment Size." "?,?,?,?" newline bitfld.long 0x10 7. "TBINTDIS,Table Interrupt Disable Bit.This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt..Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x10 4.--6. "BURSIZE,Burst Size.This field is used for peripheral to determine the burst size or used for determine the re-arbitration size..Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?" newline bitfld.long 0x10 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x10 0.--1. "OPMODE,PDMA Operation Mode Selection.Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?" line.long 0x14 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel 1" hexmask.long 0x14 0.--31. 1. "SA,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA controller." line.long 0x18 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel 1" hexmask.long 0x18 0.--31. 1. "DA,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA controller." line.long 0x1C "PDMA_DSCT1_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 1" hexmask.long.word 0x1C 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset.This field indicates the offset of next descriptor table address in system memory. .Note: write operation is useless in this field." hexmask.long.word 0x1C 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset.This field indicates the offset of the first descriptor table address in system memory. .Write Operation:.If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is start.." line.long 0x20 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel 2" hexmask.long.word 0x20 16.--29. 1. "TXCNT,Transfer Count.The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field..Note: When.." bitfld.long 0x20 12.--13. "TXWIDTH,Transfer Width Selection.This field is used for transfer width..Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?" newline bitfld.long 0x20 10.--11. "DAINC,Destination Address Increment.This field is used to set the destination address increment size." "?,?,?,?" bitfld.long 0x20 8.--9. "SAINC,Source Address Increment.This Field Is Used To Set The Source Address Increment Size." "?,?,?,?" newline bitfld.long 0x20 7. "TBINTDIS,Table Interrupt Disable Bit.This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt..Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x20 4.--6. "BURSIZE,Burst Size.This field is used for peripheral to determine the burst size or used for determine the re-arbitration size..Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?" newline bitfld.long 0x20 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x20 0.--1. "OPMODE,PDMA Operation Mode Selection.Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?" line.long 0x24 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel 2" hexmask.long 0x24 0.--31. 1. "SA,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA controller." line.long 0x28 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel 2" hexmask.long 0x28 0.--31. 1. "DA,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA controller." line.long 0x2C "PDMA_DSCT2_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 2" hexmask.long.word 0x2C 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset.This field indicates the offset of next descriptor table address in system memory. .Note: write operation is useless in this field." hexmask.long.word 0x2C 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset.This field indicates the offset of the first descriptor table address in system memory. .Write Operation:.If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is start.." line.long 0x30 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel 3" hexmask.long.word 0x30 16.--29. 1. "TXCNT,Transfer Count.The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field..Note: When.." bitfld.long 0x30 12.--13. "TXWIDTH,Transfer Width Selection.This field is used for transfer width..Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?" newline bitfld.long 0x30 10.--11. "DAINC,Destination Address Increment.This field is used to set the destination address increment size." "?,?,?,?" bitfld.long 0x30 8.--9. "SAINC,Source Address Increment.This Field Is Used To Set The Source Address Increment Size." "?,?,?,?" newline bitfld.long 0x30 7. "TBINTDIS,Table Interrupt Disable Bit.This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt..Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x30 4.--6. "BURSIZE,Burst Size.This field is used for peripheral to determine the burst size or used for determine the re-arbitration size..Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?" newline bitfld.long 0x30 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x30 0.--1. "OPMODE,PDMA Operation Mode Selection.Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?" line.long 0x34 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel 3" hexmask.long 0x34 0.--31. 1. "SA,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA controller." line.long 0x38 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel 3" hexmask.long 0x38 0.--31. 1. "DA,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA controller." line.long 0x3C "PDMA_DSCT3_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 3" hexmask.long.word 0x3C 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset.This field indicates the offset of next descriptor table address in system memory. .Note: write operation is useless in this field." hexmask.long.word 0x3C 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset.This field indicates the offset of the first descriptor table address in system memory. .Write Operation:.If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is start.." line.long 0x40 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel 4" hexmask.long.word 0x40 16.--29. 1. "TXCNT,Transfer Count.The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field..Note: When.." bitfld.long 0x40 12.--13. "TXWIDTH,Transfer Width Selection.This field is used for transfer width..Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?" newline bitfld.long 0x40 10.--11. "DAINC,Destination Address Increment.This field is used to set the destination address increment size." "?,?,?,?" bitfld.long 0x40 8.--9. "SAINC,Source Address Increment.This Field Is Used To Set The Source Address Increment Size." "?,?,?,?" newline bitfld.long 0x40 7. "TBINTDIS,Table Interrupt Disable Bit.This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt..Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x40 4.--6. "BURSIZE,Burst Size.This field is used for peripheral to determine the burst size or used for determine the re-arbitration size..Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?" newline bitfld.long 0x40 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x40 0.--1. "OPMODE,PDMA Operation Mode Selection.Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?" line.long 0x44 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel 4" hexmask.long 0x44 0.--31. 1. "SA,PDMA Transfer Source Address Register.This field indicates a 32-bit source address of PDMA controller." line.long 0x48 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel 4" hexmask.long 0x48 0.--31. 1. "DA,PDMA Transfer Destination Address Register.This field indicates a 32-bit destination address of PDMA controller." line.long 0x4C "PDMA_DSCT4_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 4" hexmask.long.word 0x4C 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset.This field indicates the offset of next descriptor table address in system memory. .Note: write operation is useless in this field." hexmask.long.word 0x4C 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset.This field indicates the offset of the first descriptor table address in system memory. .Write Operation:.If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is start.." rgroup.long 0x50++0x13 line.long 0x0 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel 0" hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only).This field indicates a 32-bit current external description address of PDMA controller..Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.." line.long 0x4 "PDMA_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel 1" hexmask.long 0x4 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only).This field indicates a 32-bit current external description address of PDMA controller..Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.." line.long 0x8 "PDMA_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel 2" hexmask.long 0x8 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only).This field indicates a 32-bit current external description address of PDMA controller..Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.." line.long 0xC "PDMA_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel 3" hexmask.long 0xC 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only).This field indicates a 32-bit current external description address of PDMA controller..Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.." line.long 0x10 "PDMA_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel 4" hexmask.long 0x10 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only).This field indicates a 32-bit current external description address of PDMA controller..Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.." group.long 0x400++0x3 line.long 0x0 "PDMA_CHCTL,PDMA Channel Control Register" bitfld.long 0x0 4. "CHEN4,PDMA Channel n Enable Bit.Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled..Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x0 3. "CHEN3,PDMA Channel n Enable Bit.Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled..Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x0 2. "CHEN2,PDMA Channel n Enable Bit.Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled..Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x0 1. "CHEN1,PDMA Channel n Enable Bit.Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled..Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x0 0. "CHEN0,PDMA Channel n Enable Bit.Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled..Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" wgroup.long 0x404++0x7 line.long 0x0 "PDMA_PAUSE,PDMA Transfer Pause Control Register" bitfld.long 0x0 4. "PAUSE4,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x0 3. "PAUSE3,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x0 2. "PAUSE2,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x0 1. "PAUSE1,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x0 0. "PAUSE0,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" line.long 0x4 "PDMA_SWREQ,PDMA Software Request Register" bitfld.long 0x4 4. "SWREQ4,PDMA Channel n Software Request Register (Write Only).Set this bit to 1 to generate a software request to PDMA [n]..Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or.." "0: No effect,1: Generate a software request" bitfld.long 0x4 3. "SWREQ3,PDMA Channel n Software Request Register (Write Only).Set this bit to 1 to generate a software request to PDMA [n]..Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or.." "0: No effect,1: Generate a software request" newline bitfld.long 0x4 2. "SWREQ2,PDMA Channel n Software Request Register (Write Only).Set this bit to 1 to generate a software request to PDMA [n]..Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or.." "0: No effect,1: Generate a software request" bitfld.long 0x4 1. "SWREQ1,PDMA Channel n Software Request Register (Write Only).Set this bit to 1 to generate a software request to PDMA [n]..Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or.." "0: No effect,1: Generate a software request" newline bitfld.long 0x4 0. "SWREQ0,PDMA Channel n Software Request Register (Write Only).Set this bit to 1 to generate a software request to PDMA [n]..Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or.." "0: No effect,1: Generate a software request" rgroup.long 0x40C++0x3 line.long 0x0 "PDMA_TRGSTS,PDMA Channel Request Status Register" bitfld.long 0x0 4. "REQSTS4,PDMA Channel n Request Status (Read Only).This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically." "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x0 3. "REQSTS3,PDMA Channel n Request Status (Read Only).This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically." "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x0 2. "REQSTS2,PDMA Channel n Request Status (Read Only).This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically." "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x0 1. "REQSTS1,PDMA Channel n Request Status (Read Only).This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically." "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x0 0. "REQSTS0,PDMA Channel n Request Status (Read Only).This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically." "0: PDMA Channel n has no request,1: PDMA Channel n has a request" group.long 0x410++0x3 line.long 0x0 "PDMA_PRISET,PDMA Fixed Priority Setting Register" bitfld.long 0x0 4. "FPRISET4,PDMA Channel n Fixed Priority Setting Register.Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect..Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x0 3. "FPRISET3,PDMA Channel n Fixed Priority Setting Register.Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect..Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x0 2. "FPRISET2,PDMA Channel n Fixed Priority Setting Register.Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect..Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x0 1. "FPRISET1,PDMA Channel n Fixed Priority Setting Register.Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect..Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x0 0. "FPRISET0,PDMA Channel n Fixed Priority Setting Register.Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect..Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." wgroup.long 0x414++0x3 line.long 0x0 "PDMA_PRICLR,PDMA Fixed Priority Clear Register" bitfld.long 0x0 4. "FPRICLR4,PDMA Channel n Fixed Priority Clear Register (Write Only).Set this bit to 1 to clear fixed priority level..Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x0 3. "FPRICLR3,PDMA Channel n Fixed Priority Clear Register (Write Only).Set this bit to 1 to clear fixed priority level..Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x0 2. "FPRICLR2,PDMA Channel n Fixed Priority Clear Register (Write Only).Set this bit to 1 to clear fixed priority level..Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x0 1. "FPRICLR1,PDMA Channel n Fixed Priority Clear Register (Write Only).Set this bit to 1 to clear fixed priority level..Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x0 0. "FPRICLR0,PDMA Channel n Fixed Priority Clear Register (Write Only).Set this bit to 1 to clear fixed priority level..Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting" group.long 0x418++0x13 line.long 0x0 "PDMA_INTEN,PDMA Interrupt Enable Register" bitfld.long 0x0 4. "INTEN4,PDMA Channel n Interrupt Enable Register.This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x0 3. "INTEN3,PDMA Channel n Interrupt Enable Register.This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x0 2. "INTEN2,PDMA Channel n Interrupt Enable Register.This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x0 1. "INTEN1,PDMA Channel n Interrupt Enable Register.This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x0 0. "INTEN0,PDMA Channel n Interrupt Enable Register.This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" line.long 0x4 "PDMA_INTSTS,PDMA Interrupt Status Register" bitfld.long 0x4 9. "REQTOF1,PDMA Channel n Request Time-out Flag.This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits." "0: No request time-out,1: Peripheral request time-out" bitfld.long 0x4 8. "REQTOF0,PDMA Channel n Request Time-out Flag.This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits." "0: No request time-out,1: Peripheral request time-out" newline rbitfld.long 0x4 2. "TEIF,Table Empty Interrupt Flag (Read Only).This bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty" rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only).This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission" newline rbitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only).This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received" line.long 0x8 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register" bitfld.long 0x8 4. "ABTIF4,PDMA Channel n Read/Write Target Abort Interrupt Status Flag.This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.." bitfld.long 0x8 3. "ABTIF3,PDMA Channel n Read/Write Target Abort Interrupt Status Flag.This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.." newline bitfld.long 0x8 2. "ABTIF2,PDMA Channel n Read/Write Target Abort Interrupt Status Flag.This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.." bitfld.long 0x8 1. "ABTIF1,PDMA Channel n Read/Write Target Abort Interrupt Status Flag.This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.." newline bitfld.long 0x8 0. "ABTIF0,PDMA Channel n Read/Write Target Abort Interrupt Status Flag.This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.." line.long 0xC "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register" bitfld.long 0xC 4. "TDIF4,PDMA Channel n Transfer Done Flag Register.This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0xC 3. "TDIF3,PDMA Channel n Transfer Done Flag Register.This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0xC 2. "TDIF2,PDMA Channel n Transfer Done Flag Register.This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0xC 1. "TDIF1,PDMA Channel n Transfer Done Flag Register.This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0xC 0. "TDIF0,PDMA Channel n Transfer Done Flag Register.This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" line.long 0x10 "PDMA_SCATSTS,PDMA Scatter-gather Table Empty Status Register" bitfld.long 0x10 4. "TEMPTYF4,Table Empty Flag Register.T This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.." bitfld.long 0x10 3. "TEMPTYF3,Table Empty Flag Register.T This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.." newline bitfld.long 0x10 2. "TEMPTYF2,Table Empty Flag Register.T This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.." bitfld.long 0x10 1. "TEMPTYF1,Table Empty Flag Register.T This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.." newline bitfld.long 0x10 0. "TEMPTYF0,Table Empty Flag Register.T This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.." rgroup.long 0x42C++0x3 line.long 0x0 "PDMA_TACTSTS,PDMA Transfer Active Flag Register" bitfld.long 0x0 4. "TXACTF4,PDMA Channel n Transfer on Active Flag Register (Read Only).This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active" bitfld.long 0x0 3. "TXACTF3,PDMA Channel n Transfer on Active Flag Register (Read Only).This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active" newline bitfld.long 0x0 2. "TXACTF2,PDMA Channel n Transfer on Active Flag Register (Read Only).This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active" bitfld.long 0x0 1. "TXACTF1,PDMA Channel n Transfer on Active Flag Register (Read Only).This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active" newline bitfld.long 0x0 0. "TXACTF0,PDMA Channel n Transfer on Active Flag Register (Read Only).This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active" group.long 0x430++0x13 line.long 0x0 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register" bitfld.long 0x0 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,?,?,?,?,?,?" bitfld.long 0x0 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,?,?,?,?,?,?" line.long 0x4 "PDMA_TOUTEN,PDMA Time-out Enable Register" bitfld.long 0x4 1. "TOUTEN1,PDMA Channel n Time-out Enable Bit" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled" bitfld.long 0x4 0. "TOUTEN0,PDMA Channel n Time-out Enable Bit" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled" line.long 0x8 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register" bitfld.long 0x8 1. "TOUTIEN1,PDMA Channel n Time-out Interrupt Enable Bit" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled" bitfld.long 0x8 0. "TOUTIEN0,PDMA Channel n Time-out Interrupt Enable Bit" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled" line.long 0xC "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register" hexmask.long.word 0xC 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address Register.In Scatter-Gather mode this is the base address for calculating the next link - list address. The next link address equation is .Note: Only useful in Scatter-Gather mode." line.long 0x10 "PDMA_TOC0_1,PDMA Channel 0 and Channel 1 Time-out Counter Register" hexmask.long.word 0x10 16.--31. 1. "TOC1,Time-out Counter for Channel 1.This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description." hexmask.long.word 0x10 0.--15. 1. "TOC0,Time-out Counter for Channel 0.This controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock." group.long 0x460++0x3 line.long 0x0 "PDMA_RESET,PDMA Channel Reset Control Register" bitfld.long 0x0 4. "RESET4,PDMA Channel n Reset Control Register .Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n" bitfld.long 0x0 3. "RESET3,PDMA Channel n Reset Control Register .Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n" newline bitfld.long 0x0 2. "RESET2,PDMA Channel n Reset Control Register .Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n" bitfld.long 0x0 1. "RESET1,PDMA Channel n Reset Control Register .Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n" newline bitfld.long 0x0 0. "RESET0,PDMA Channel n Reset Control Register .Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n" group.long 0x480++0x7 line.long 0x0 "PDMA_REQSEL0_3,PDMA Channel 0 to Channel 3 Request Source Select Register" hexmask.long.byte 0x0 24.--29. 1. "REQSRC3,Channel 3 Request Source Selection.This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. .Note: The channel configuration is the same as REQSRC0 field. Please refer to the.." hexmask.long.byte 0x0 16.--21. 1. "REQSRC2,Channel 2 Request Source Selection.This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. .Note: The channel configuration is the same as REQSRC0 field. Please refer to the.." newline hexmask.long.byte 0x0 8.--13. 1. "REQSRC1,Channel 1 Request Source Selection.This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. .Note: The channel configuration is the same as REQSRC0 field. Please refer to the.." hexmask.long.byte 0x0 0.--5. 1. "REQSRC0,Channel 0 Request Source Selection.This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0..Note1: A request source can't assign to two channels at the same time..Note2: This.." line.long 0x4 "PDMA_REQSEL4,PDMA Channel 4 Request Source Select Register" hexmask.long.byte 0x4 0.--5. 1. "REQSRC4,Channel 4 Request Source Selection.This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. .Note: The channel configuration is the same as REQSRC0 field. Please refer to the.." endif tree.end endif sif (cpuis("NUC029?AE")) base ad:0x40040000 elif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) base ad:0x0 endif tree "PWM (Pulse Width Modulation)" sif (cpuis("NUC029?AE")) group.long 0x0++0x3B line.long 0x0 "PPR,PWM Pre-scale Register" hexmask.long.byte 0x0 16.--23. 1. "CP45,Clock Prescaler 4 for PWM Counter 4 and 5.Clock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter." hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 for PWM Counter 2 and 3.Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter." newline hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 for PWM Counter 0 and 1.Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter." line.long 0x4 "CSR,PWM Clock Select Register" bitfld.long 0x4 20.--22. "CSR5,Timer 5 Clock Source Selection.Select clock input for PWM timer." "0: Input Clock Divided by 2,1: Input Clock Divided by 4,?,?,?,?,?,?" bitfld.long 0x4 16.--18. "CSR4,Timer 4 Clock Source Selection.Select clock input for PWM timer..(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "CSR3,Timer 3 Clock Source Selection.Select clock input for PWM timer..(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "CSR2,Timer 2 Clock Source Selection.Select clock input for PWM timer..(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CSR1,Timer 1 Clock Source Selection.Select clock input for PWM timer..(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CSR0,Timer 0 Clock Source Selection.Select clock input for PWM timer..(Table is the same as CSR5.)" "0,1,2,3,4,5,6,7" line.long 0x8 "PCR,PWM Control Register" bitfld.long 0x8 31. "PWMTYPE,PWM Aligned Type Selection Bit" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x8 30. "GRP,Group Bit" "0: The signals timing of all PWM channels are..,1: Unify the signals timing of PWM0 PWM2 and PWM4.." newline bitfld.long 0x8 28.--29. "PWMMOD,PWM Operating Mode Selection" "0: Independent mode,1: Complementary mode,?,?" bitfld.long 0x8 27. "CLRPWM,Clear PWM Counter Control Bit.Note: It is automatically cleared by hardware." "0: Do not clear PWM counter,1: All 16-bit PWM counters cleared to 0x0000" newline bitfld.long 0x8 26. "DZEN45,Dead-zone 4 Generator Enable Control (PWM4 and PWM5 pair for PWM group).Note: When the dead-zone generator is enabled the pair of PWM4 and PWM5 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled" bitfld.long 0x8 25. "DZEN23,Dead-zone 2 Generator Enable Control (PWM2 and PWM3 pair for PWM group).Note: When the dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled" newline bitfld.long 0x8 24. "DZEN01,Dead-zone 0 Generator Enable Control (PWM0 and PWM1 pair for PWM group).Note: When the dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group." "0: Disabled,1: Enabled" bitfld.long 0x8 23. "CH5MOD,PWM-Timer 5 Auto-reload/One-Shot Mode.Note: If there is a rising transition at this bit it will cause CNR5 and CMR5 cleared." "0: One-shot mode,1: Auto-reload mode" newline bitfld.long 0x8 22. "CH5INV,PWM-Timer 5 Output Inverter Enable Control" "0: Inverter Disabled,1: Inverter Enabled" bitfld.long 0x8 20. "CH5EN,PWM-Timer 5 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled" newline bitfld.long 0x8 19. "CH4MOD,PWM-Timer 4 Auto-reload/One-Shot Mode.Note: If there is a rising transition at this bit it will cause CNR4 and CMR4 cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 18. "CH4INV,PWM-Timer 4 Output Inverter Enable Control" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 16. "CH4EN,PWM-Timer 4 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled" bitfld.long 0x8 15. "CH3MOD,PWM-Timer 3 Auto-reload/One-Shot Mode.Note: If there is a rising transition at this bit it will cause CNR3 and CMR3 cleared." "0: One-shot mode,1: Auto-reload mode" newline bitfld.long 0x8 14. "CH3INV,PWM-Timer 3 Output Inverter Enable Control" "0: Inverter Disabled,1: Inverter Enabled" bitfld.long 0x8 12. "CH3EN,PWM-Timer 3 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled" newline bitfld.long 0x8 11. "CH2MOD,PWM-Timer 2 Auto-reload/One-Shot Mode.Note: If there is a rising transition at this bit it will cause CNR2 and CMR2 cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 10. "CH2INV,PWM-Timer 2 Output Inverter Enable Control" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 8. "CH2EN,PWM-Timer 2 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled" bitfld.long 0x8 7. "CH1MOD,PWM-Timer 1 Auto-reload/One-Shot Mode.Note: If there is a rising transition at this bit it will cause CNR1 and CMR1 cleared." "0: One-shot mode,1: Auto-reload mode" newline bitfld.long 0x8 6. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 4. "CH1EN,PWM-Timer 1 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled" newline bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Auto-reload/One-Shot Mode.Note: If there is a rising transition at this bit it will cause CNR0 and CMR0 cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter Enable Control" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 1. "DB_MODE,PWM Debug Mode Configuration Bit (Available in DEBUG mode only)" "0: Safe mode: The timer is frozen and PWM outputs..,1: Normal mode: The timer continues to operate.." bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled" line.long 0xC "CNR0,PWM Counter Register 0" hexmask.long.word 0xC 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value.Note: Any write to CNRn will take effect in next PWM cycle." line.long 0x10 "CNR1,PWM Counter Register 1" hexmask.long.word 0x10 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value.Note: Any write to CNRn will take effect in next PWM cycle." line.long 0x14 "CNR2,PWM Counter Register 2" hexmask.long.word 0x14 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value.Note: Any write to CNRn will take effect in next PWM cycle." line.long 0x18 "CNR3,PWM Counter Register 3" hexmask.long.word 0x18 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value.Note: Any write to CNRn will take effect in next PWM cycle." line.long 0x1C "CNR4,PWM Counter Register 4" hexmask.long.word 0x1C 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value.Note: Any write to CNRn will take effect in next PWM cycle." line.long 0x20 "CNR5,PWM Counter Register 5" hexmask.long.word 0x20 0.--15. 1. "CNRn,PWM Counter/Timer Loaded Value.Note: Any write to CNRn will take effect in next PWM cycle." line.long 0x24 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x24 0.--15. 1. "CMRn,PWM Comparator Bits.Note: Any write to CMRn will take effect in next PWM cycle." line.long 0x28 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x28 0.--15. 1. "CMRn,PWM Comparator Bits.Note: Any write to CMRn will take effect in next PWM cycle." line.long 0x2C "CMR2,PWM Comparator Register 2" hexmask.long.word 0x2C 0.--15. 1. "CMRn,PWM Comparator Bits.Note: Any write to CMRn will take effect in next PWM cycle." line.long 0x30 "CMR3,PWM Comparator Register 3" hexmask.long.word 0x30 0.--15. 1. "CMRn,PWM Comparator Bits.Note: Any write to CMRn will take effect in next PWM cycle." line.long 0x34 "CMR4,PWM Comparator Register 4" hexmask.long.word 0x34 0.--15. 1. "CMRn,PWM Comparator Bits.Note: Any write to CMRn will take effect in next PWM cycle." line.long 0x38 "CMR5,PWM Comparator Register 5" hexmask.long.word 0x38 0.--15. 1. "CMRn,PWM Comparator Bits.Note: Any write to CMRn will take effect in next PWM cycle." group.long 0x54++0x33 line.long 0x0 "PIER,PWM Interrupt Enable Control Register" bitfld.long 0x0 17. "INT_TYPE,PWM Interrupt Type Selection Bit.Note: This bit is effective when PWM in central align mode only." "0: PWMPIFn will be set if PWM counter underflows,1: PWMPIFn will be set if PWM counter matches CNRn.." bitfld.long 0x0 16. "BRKIE,Fault Brake0 and 1 Interrupt Enable Control" "0: Disabling flags BKF0 and BKF1 to trigger PWM..,1: Enabling flags BKF0 and BKF1 can trigger PWM.." newline bitfld.long 0x0 13. "PWMDIE5,PWM Channel 5 Duty Interrupt Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 12. "PWMDIE4,PWM Channel 4 Duty Interrupt Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "PWMPIE5,PWM Channel 5 Period Interrupt Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "PWMPIE4,PWM Channel 4 Period Interrupt Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "PWMPIE3,PWM Channel 3 Period Interrupt Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 2. "PWMPIE2,PWM Channel 2 Period Interrupt Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "PWMPIE1,PWM Channel 1 Period Interrupt Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 0. "PWMPIE0,PWM Channel 0 Period Interrupt Enable Control" "0: Disabled,1: Enabled" line.long 0x4 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x4 17. "BKF1,PWM Brake1 Flag.Note: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.." bitfld.long 0x4 16. "BKF0,PWM Brake0 Flag.Note: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.." newline bitfld.long 0x4 13. "PWMDIF5,PWM channel 5 Duty Interrupt Flag.Flag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction. .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x4 12. "PWMDIF4,PWM channel 4 Duty Interrupt Flag.Flag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction. .Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x4 11. "PWMDIF3,PWM channel 3 Duty Interrupt Flag.Flag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction. .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x4 10. "PWMDIF2,PWM channel 2 Duty Interrupt Flag.Flag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction. .Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x4 9. "PWMDIF1,PWM channel 1 Duty Interrupt Flag.Flag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction. .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x4 8. "PWMDIF0,PWM channel 0 Duty Interrupt Flag.Flag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction. .Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x4 5. "PWMPIF5,PWM channel 5 Period Interrupt Flag.Flag is set by hardware when PWM5 down counter reaches zero. .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x4 4. "PWMPIF4,PWM channel 4 Period Interrupt Flag.Flag is set by hardware when PWM4 down counter reaches zero. .Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x4 3. "PWMPIF3,PWM channel 3 Period Interrupt Flag.Flag is set by hardware when PWM3 down counter reaches zero. .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x4 2. "PWMPIF2,PWM channel 2 Period Interrupt Flag.Flag is set by hardware when PWM2 down counter reaches zero. .Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x4 1. "PWMPIF1,PWM channel 1 Period Interrupt Flag.Flag is set by hardware when PWM1 down counter reaches zero. .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x4 0. "PWMPIF0,PWM channel 0 Period Interrupt Flag.Flag is set by hardware when PWM0 down counter reaches zero. .Note: Software can write 1 to clear this bit." "0,1" line.long 0x8 "PWMPOE,PWM Output Enable for Channel 0~5" bitfld.long 0x8 5. "PWM5,PWM Channel 5 Output Enable Control.Note: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 5 output to pin Disabled,1: PWM channel 5 output to pin Enabled" bitfld.long 0x8 4. "PWM4,PWM Channel 4 Output Enable Control.Note: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 4 output to pin Disabled,1: PWM channel 4 output to pin Enabled" newline bitfld.long 0x8 3. "PWM3,PWM Channel 3 Output Enable Control.Note: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled" bitfld.long 0x8 2. "PWM2,PWM Channel 2 Output Enable Control.Note: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled" newline bitfld.long 0x8 1. "PWM1,PWM Channel 1 Output Enable Control.Note: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled" bitfld.long 0x8 0. "PWM0,PWM Channel 0 Output Enable Control.Note: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled" line.long 0xC "PFBCON,PWM Fault Brake Control Register" bitfld.long 0xC 31. "D7BKO7,D7 Brake Output Select Bit" "0: D7 output low when fault brake conditions asserted,1: D7 output high when fault brake conditions.." bitfld.long 0xC 30. "D6BKO6,D6 Brake Output Select Bit" "0: D6 output low when fault brake conditions asserted,1: D6 output high when fault brake conditions.." newline bitfld.long 0xC 29. "PWMBKO5,PWM Channel 5 Brake Output Select Bit" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.." bitfld.long 0xC 28. "PWMBKO4,PWM Channel 4 Brake Output Select Bit" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.." newline bitfld.long 0xC 27. "PWMBKO3,PWM Channel 3 Brake Output Select Bit" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.." bitfld.long 0xC 26. "PWMBKO2,PWM Channel 2 Brake Output Select Bit" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.." newline bitfld.long 0xC 25. "PWMBKO1,PWM Channel 1 Brake Output Select Bit" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.." bitfld.long 0xC 24. "PWMBKO0,PWM Channel 0 Brake Output Select Bit" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.." newline bitfld.long 0xC 7. "BKF,PWM Fault Brake Event Flag (write 1 clear).Software can write 1 to clear this bit and must clear this bit before restart PWM counter." "0: PWM output initial state when fault brake..,1: PWM output fault brake state when fault brake.." bitfld.long 0xC 3. "CPO1BKEN,BKP0 Fault Brake Function Source Selection" "0: EINT0 as one brake source in BKP0,1: CPO1 as one brake source in BKP0" newline bitfld.long 0xC 2. "CPO0BKEN,BKP1 Fault Brake Function Source Selection" "0: EINT1 as one brake source in BKP1,1: CPO0 as one brake source in BKP1" bitfld.long 0xC 1. "BKEN1,Enable BKP1 Pin Trigger Fault Brake Function 1" "0: Disabling BKP1 pin can trigger brake function 1..,1: Enabling a falling at BKP1 pin can trigger brake.." newline bitfld.long 0xC 0. "BKEN0,Enable BKP0 Pin Trigger Fault Brake Function 0" "0: Disabling BKP0 pin can trigger brake function 0..,1: Enabling a falling at BKP0 pin can trigger brake.." line.long 0x10 "PDZIR,PWM Dead-zone Interval Register" hexmask.long.byte 0x10 16.--23. 1. "DZI45,Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 pair)..These 8 bits determine dead-zone length..The unit time of dead-zone length is received from corresponding CSR bits." hexmask.long.byte 0x10 8.--15. 1. "DZI23,Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair)..These 8 bits determine dead-zone length..The unit time of dead-zone length is received from corresponding CSR bits." newline hexmask.long.byte 0x10 0.--7. 1. "DZI01,Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 pair)..These 8 bits determine dead-zone length..The unit time of dead-zone length is received from corresponding CSR bits." line.long 0x14 "TRGCON0,PWM Trigger Control Register 0" bitfld.long 0x14 27. "P3TRGEN,Enable PWM trigger ADC function while Channel3's counter matching 0.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" bitfld.long 0x14 26. "CM3TRGFEN,Enable PWM trigger ADC function while Channel3's counter matching CMR3 in down-count direction.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" newline bitfld.long 0x14 25. "CNT3TRGEN,Enable PWM trigger ADC function while Channel3's counter matching CNR3.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled" bitfld.long 0x14 24. "CM3TRGREN,Enable PWM trigger ADC function while Channel3's counter matching CMR3 in up-count direction.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled" newline bitfld.long 0x14 19. "P2TRGEN,Enable PWM trigger ADC function while Channel2's counter matching 0.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" bitfld.long 0x14 18. "CM2TRGFEN,Enable PWM trigger ADC function while Channel2's counter matching CMR2 in down-count direction.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" newline bitfld.long 0x14 17. "CNT2TRGEN,Enable PWM trigger ADC function while Channel2's counter matching CNR2.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled" bitfld.long 0x14 16. "CM2TRGREN,Enable PWM trigger ADC function while Channel2's counter matching CMR2 in up-count direction.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled" newline bitfld.long 0x14 11. "P1TRGEN,Enable PWM trigger ADC function while Channel1's counter matching 0 .Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" bitfld.long 0x14 10. "CM1TRGFEN,Enable PWM trigger ADC function while Channel1's counter matching CMR1 in down-count direction.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" newline bitfld.long 0x14 9. "CNT1TRGEN,Enable PWM trigger ADC function while Channel1's counter matching CNR1.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled" bitfld.long 0x14 8. "CM1TRGREN,Enable PWM trigger ADC function while Channel1's counter matching CMR1 in up-count direction.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled" newline bitfld.long 0x14 3. "P0TRGEN,Enable PWM trigger ADC function while Channel0's counter matching 0.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" bitfld.long 0x14 2. "CM0TRGFEN,Enable PWM trigger ADC function while Channel0's counter matching CMR0 in down-count direction.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" newline bitfld.long 0x14 1. "CNT0TRGEN,Enable PWM trigger ADC function while Channel0's counter matching CNR0.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled" bitfld.long 0x14 0. "CM0TRGREN,Enable PWM trigger ADC function while Channel0's counter matching CMR0 in up-count direction.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled" line.long 0x18 "TRGCON1,PWM Trigger Control Register 1" bitfld.long 0x18 11. "P5TRGEN,Enable PWM trigger ADC function while Channel5's counter matching 0.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" bitfld.long 0x18 10. "CM5TRGFEN,Enable PWM trigger ADC function while Channel5's counter matching CMR5 in down-count direction.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" newline bitfld.long 0x18 9. "CNT5TRGEN,Enable PWM trigger ADC function while Channel5's counter matching CNR5.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled" bitfld.long 0x18 8. "CM5TRGREN,Enable PWM trigger ADC function while Channel5's counter matching CMR5 in up-count direction.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled" newline bitfld.long 0x18 3. "P4TRGEN,Enable PWM trigger ADC function while Channel4's counter matching 0.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" bitfld.long 0x18 2. "CM4TRGFEN,Enable PWM trigger ADC function while Channel4's counter matching CMR4 in down-count direction.Note: This bit is valid for both center aligned mode and edged aligned mode." "0: Disabled,1: Enabled" newline bitfld.long 0x18 1. "CNT4TRGEN,Enable PWM trigger ADC function while Channel4's counter matching CNR4.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any effect." "0: Disabled,1: Enabled" bitfld.long 0x18 0. "CM4TRGREN,Enable PWM trigger ADC function while Channel4's counter matching CMR4 in up-count direction.Note: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode setting this bit is meaningless and will not take any.." "0: Disabled,1: Enabled" line.long 0x1C "TRGSTS0,PWM Trigger Status Register 0" bitfld.long 0x1C 27. "PERID3FLAG,When counter counting to period this bit will be set for trigger ADC .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 26. "CMR3FLAG_F,When counter counting down to CMR this bit will be set for trigger ADC.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 25. "CNT3FLAG,When counter counting to CNR this bit will be set for trigger ADC.Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 24. "CMR3FLAG_R,When counter counting up to CMR this bit will be set for trigger ADC.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 19. "PERID2FLAG,ADC trigger flag by period .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 18. "CMR2FLAG_F,ADC trigger flag by counting down to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 17. "CNT2FLAG,ADC trigger flag by counting to CNR.Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 16. "CMR2FLAG_R,ADC trigger flag by counting up to CMR .Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 11. "PERID1FLAG,ADC trigger flag by period .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 10. "CMR1FLAG_F,ADC trigger flag by counting down to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 9. "CNT1FLAG,ADC trigger flag by counting to CNR.Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 8. "CMR1FLAG_R,ADC trigger flag by counting up to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 3. "PERID0FLAG,ADC trigger flag by period .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 2. "CMR0FLAG_F,ADC trigger flag by counting down to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x1C 1. "CNT0FLAG,ADC trigger flag by counting to CNR.Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x1C 0. "CMR0FLAG_R,ADC trigger flag by counting up to CMR.Note: Software can write 1 to clear this bit." "0,1" line.long 0x20 "TRGSTS1,PWM Trigger Status Register 1" bitfld.long 0x20 11. "PERID5FLAG,ADC trigger flag by period .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x20 10. "CMR5FLAG_F,ADC trigger flag by counting down to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x20 9. "CNT5FLAG,ADC trigger flag by counting to CNR.Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x20 8. "CMR5FLAG_R,ADC trigger flag by counting up to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x20 3. "PERID4FLAG,ADC trigger flag by period .Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x20 2. "CMR4FLAG_F,ADC trigger flag by counting down to CMR.Note: Software can write 1 to clear this bit." "0,1" newline bitfld.long 0x20 1. "CNT4FLAG,ADC trigger flag by counting to CNR.Note: Software can write 1 to clear this bit." "0,1" bitfld.long 0x20 0. "CMR4FLAG_R,ADC trigger flag by counting up to CMR.Note: Software can write 1 to clear this bit." "0,1" line.long 0x24 "PHCHG,Phase Changed Register" bitfld.long 0x24 31. "CE0,ACMP0 Trigger Function Enable Control.Note: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set." "0: Disabled,1: Enabled" bitfld.long 0x24 30. "T0,Timer0 trigger PWM function Enable Control.When this bit is set timer0 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled" newline bitfld.long 0x24 28.--29. "CMP0SEL,CMP0SEL.Select the positive input source of ACMP0." "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?" bitfld.long 0x24 27. "CH31TOFF0,Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x24 26. "CH21TOFF0,Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x24 25. "CH11TOFF0,Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x24 24. "CH01TOFF0,Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x24 23. "CE1,ACMP1 Trigger Function Enable Control.Note: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set." "0: Disabled,1: Enabled" newline bitfld.long 0x24 22. "T1,Timer1 Trigger PWM Function Enable Control.When this bit is set timer1 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled" bitfld.long 0x24 20.--21. "CMP1SEL,CMP1SEL.Select the positive input source of ACMP1." "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?" newline bitfld.long 0x24 19. "CH31TOFF1,Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x24 18. "CH21TOFF1,Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x24 17. "CH11TOFF1,Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x24 16. "CH01TOFF1,Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x24 15. "ACCNT1,Hardware auto clear CE1 when ACMP1 trigger it." "0: Enabled,1: Disabled" bitfld.long 0x24 14. "ACCNT0,Hardware auto clear CE0 when ACMP0 trigger it." "0: Enabled,1: Disabled" newline bitfld.long 0x24 13. "PWM5,PWM channel 5 output enable control." "0: Output the original channel 5 waveform,1: Output D5 specified in bit 5 of PHCHG register" bitfld.long 0x24 12. "PWM4,PWM channel 4 output enable control." "0: Output the original channel 4 waveform,1: Output D4 specified in bit 4 of PHCHG register" newline bitfld.long 0x24 11. "PWM3,PWM channel 3 output enable control." "0: Output the original channel 3 waveform,1: Output D3 specified in bit 3 of PHCHG register" bitfld.long 0x24 10. "PWM2,PWM channel 2 output enable control." "0: Output the original channel 2 waveform,1: Output D2 specified in bit 2 of PHCHG register" newline bitfld.long 0x24 9. "PWM1,PWM channel 1 output enable control." "0: Output the original channel 1 waveform,1: Output D1 specified in bit 1 of PHCHG register" bitfld.long 0x24 8. "PWM0,PWM Channel 0 Output Enable Control" "0: Output the original channel 0 waveform,1: Output D0 specified in bit 0 of PHCHG register" newline bitfld.long 0x24 7. "D7,D7: when MASK1 is 1 channel 7's output waveform is D7." "0: Output low,1: Output high" bitfld.long 0x24 6. "D6,D6: when MASK6 is 1 channel 6's output waveform is D6." "0: Output low,1: Output high" newline bitfld.long 0x24 5. "D5,D5: when PWM5 is zero channel 5's output waveform is D5." "0: Output low,1: Output high" bitfld.long 0x24 4. "D4,D4: when PWM4 is zero channel 4's output waveform is D4." "0: Output low,1: Output high" newline bitfld.long 0x24 3. "D3,D3: when PWM3 is zero channel 3's output waveform is D3." "0: Output low,1: Output high" bitfld.long 0x24 2. "D2,D2: when PWM2 is zero channel 2's output waveform is D2." "0: Output low,1: Output high" newline bitfld.long 0x24 1. "D1,D1: when PWM1 is zero channel 1's output waveform is D1." "0: Output low,1: Output high" bitfld.long 0x24 0. "D0,D0: when PWM0 is zero channel 0's output waveform is D0." "0: Output low,1: Output high" line.long 0x28 "PHCHGNXT,Next Phase Change Register" bitfld.long 0x28 31. "CE0,ACMP0 Trigger Function Enable Control.Note: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set." "0: Disabled,1: Enabled" bitfld.long 0x28 30. "T0,Timer0 trigger PWM Function Enable Control.When this bit is set timer0 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled" newline bitfld.long 0x28 28.--29. "CMP0SEL,CMP0SEL.Select the positive input source of ACMP0." "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?" bitfld.long 0x28 27. "CH31TOFF0,Setting this bit will force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x28 26. "CH21TOFF0,Setting this bit will force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application.Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x28 25. "CH11TOFF0,Setting this bit will force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x28 24. "CH01TOFF0,Setting this bit will force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x28 23. "CE1,ACMP1 Trigger Function Enable Control.Note: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set." "0: Disabled,1: Enabled" newline bitfld.long 0x28 22. "T1,Timer1 Trigger PWM Function Enable Control.When this bit is set timer1 time-out event will update PHCHG with PHCHG_NXT register." "0: Disabled,1: Enabled" bitfld.long 0x28 20.--21. "CMP1SEL,CMP1SEL.Select the positive input source of ACMP1." "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?" newline bitfld.long 0x28 19. "CH31TOFF1,Setting this bit will force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x28 18. "CH21TOFF1,Setting this bit will force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x28 17. "CH11TOFF1,Setting this bit will force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: Only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" bitfld.long 0x28 16. "CH01TOFF1,Setting this bit will force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it; this feature is usually in step motor application..Note: only for PWM0 PWM1 PWM2 PWM3." "0: Disabled,1: Enabled" newline bitfld.long 0x28 15. "ACCNT1,Hardware auto clear CE1 when ACMP1 trigger it." "0: Enabled,1: Disabled" bitfld.long 0x28 14. "ACCNT0,Hardware auto clear CE0 when ACMP0 trigger it." "0: Enabled,1: Disabled" newline bitfld.long 0x28 13. "PWM5,PWM Channel 5 Output Enable Control" "0: Output the original channel 5 waveform,1: Output D5 specified in bit 5 of PHCHG register" bitfld.long 0x28 12. "PWM4,PWM Channel 4 Output Enable Control" "0: Output the original channel 4 waveform,1: Output D4 specified in bit 4 of PHCHG register" newline bitfld.long 0x28 11. "PWM3,PWM Channel 3 Output Enable Control" "0: Output the original channel 3 waveform,1: Output D3 specified in bit 3 of PHCHG register" bitfld.long 0x28 10. "PWM2,PWM Channel 2 Output Enable Control" "0: Output the original channel 2 waveform,1: Output D2 specified in bit 2 of PHCHG register" newline bitfld.long 0x28 9. "PWM1,PWM Channel 1 Output Enable Control" "0: Output the original channel 1 waveform,1: Output D1 specified in bit 1 of PHCHG register" bitfld.long 0x28 8. "PWM0,PWM Channel 0 Output Enable Control" "0: Output the original channel 0 waveform,1: Output D0 specified in bit 0 of PHCHG register" newline bitfld.long 0x28 7. "D7,D7: when MASK1 is 1 channel 7's output waveform is D7." "0: Output low,1: Output high" bitfld.long 0x28 6. "D6,D6: when MASK6 is 1 channel 6's output waveform is D6." "0: Output low,1: Output high" newline bitfld.long 0x28 5. "D5,D5: when PWM5 is zero channel 5's output waveform is D5." "0: Output low,1: Output high" bitfld.long 0x28 4. "D4,D4: when PWM4 is zero channel 4's output waveform is D4." "0: Output low,1: Output high" newline bitfld.long 0x28 3. "D3,D3: when PWM3 is zero channel 3's output waveform is D3." "0: Output low,1: Output high" bitfld.long 0x28 2. "D2,D2: when PWM2 is zero channel 2's output waveform is D2." "0: Output low,1: Output high" newline bitfld.long 0x28 1. "D1,D1: when PWM1 is zero channel 1's output waveform is D1." "0: Output low,1: Output high" bitfld.long 0x28 0. "D0,D0: when PWM0 is zero channel 0's output waveform is D0." "0: Output low,1: Output high" line.long 0x2C "PHCHGMASK,Phase Change MASK Register" bitfld.long 0x2C 9. "CMPMASK1,MASK for ACMP1.Note: Register CMP1CR is describe in Comparator Controller chapter" "0: The input of ACMP is controlled by CMP1CR,1: The input of ACMP is controlled by CMP1SEL of.." bitfld.long 0x2C 8. "CMPMASK0,MASK for ACMP0 .Note: Register CMP0CR is describe in Comparator Controller chapter" "0: The input of ACMP is controlled by CMP0CR,1: The input of ACMP is controlled by CMP0SEL of.." newline bitfld.long 0x2C 7. "MASK7,MASK for D7" "0: Original GPIO P0.0,1: D7" bitfld.long 0x2C 6. "MASK6,MASK for D6" "0: Original GPIO P0.1,1: D6" line.long 0x30 "INTACCUCTL,Period Interrupt Accumulation Control Register" hexmask.long.byte 0x30 4.--7. 1. "PERIODCNT,Interrupt Accumulation Bits.When INTACCUEN0 is set PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero the PWM0 interrupt will occurred and PERIODCNT will reload itself." bitfld.long 0x30 0. "INTACCUEN0,Interrupt Accumulation Function Enable Control" "0: Disabled,1: Enabled" endif sif (cpuis("NUC029?AN")) tree "PWMA" base ad:0x40040000 group.long 0x0++0x13 line.long 0x0 "PPR,PWM Pre-scale Register" hexmask.long.byte 0x0 24.--31. 1. "DZI23,Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).These 8 bits determine dead zone length." hexmask.long.byte 0x0 16.--23. 1. "DZI01,Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).These 8 bits determine dead zone length." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock prescaler 2 (PWM counter 2 3 for group A and PWM counter 6 7 for group B).Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock prescaler 0 (PWM counter 0 1 for group A and PWM counter 4 5 for group B).Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter" line.long 0x4 "CSR,PWM Clock Select Register" bitfld.long 0x4 12.--14. "CSR3,Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "CSR2,Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B).Select clock input for PWM timer..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CSR1,Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B).Select clock input for PWM timer..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CSR0,Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B).Select clock input for PWM timer..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PCR,PWM Control Register" bitfld.long 0x8 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B)" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x8 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B)" "0: Edge-aligned type,1: Center-aligned type" newline bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B).Note: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable (PWM timer 3 for group A and PWM timer 7 for group B)" "0: PWM3 output polar inverse Disabled,1: PWM3 output polar inverse Enabled" bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B).Note: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter Enable(PWM timer 2 for group A and PWM timer 6 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable (PWM timer 2 for group A and PWM timer 6 for group B)" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B).Note: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter Enable(PWM timer 1 for group A and PWM timer 5 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable (PWM timer 1 for group A and PWM timer 5 for group B)" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled" bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable (PWM timer 1 for group A and PWM timer 5 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).Note: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6.." "0: Disabled,1: Enabled" bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).Note: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B).Note: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter Enable(PWM timer 0 for group A and PWM timer 4 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable (PWM timer 0 for group A and PWM timer 4 for group B)" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" line.long 0xC "CNR0,PWM Counter Register 0" hexmask.long.word 0xC 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x10 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x10 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x14++0x3 line.long 0x0 "PDR0,PWM Data Register 0" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x18++0x7 line.long 0x0 "CNR1,PWM Counter Register 1" hexmask.long.word 0x0 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x4 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PDR1,PWM Data Register 1" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x24++0x7 line.long 0x0 "CNR2,PWM Counter Register 2" hexmask.long.word 0x0 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x4 "CMR2,PWM Comparator Register 2" hexmask.long.word 0x4 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PDR2,PWM Data Register 2" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x30++0x7 line.long 0x0 "CNR3,PWM Counter Register 3" hexmask.long.word 0x0 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x4 "CMR3,PWM Comparator Register 3" hexmask.long.word 0x4 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PDR3,PWM Data Register 3" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x40++0x7 line.long 0x0 "PIER,PWM Interrupt Enable Register" bitfld.long 0x0 25. "INT23DTYPE,PWM23 Duty Interrupt Type Selection Bit (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).Note: Set INT23DTYPE to 1 only work when PWM operating in center aligned type." "0: PWMDIFn will be set if PWM counter down count..,1: PWMDIFn will be set when PWM counter up count.." bitfld.long 0x0 24. "INT01DTYPE,PWM01 Duty Interrupt Type Selection Bit (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).Note: Set INT01DTYPE to 1 only work when PWM operating in center aligned type." "0: PWMDIFn will be set if PWM counter down count..,1: PWMDIFn will be set when PWM counter up count.." newline bitfld.long 0x0 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).Note: Set INT23TYPE to 1 only work when PWM operating in center aligned type." "0: PWMIFn will be set if PWM counter underflow. PWM..,1: PWMIFn will be set if PWM counter matches CNRn.." bitfld.long 0x0 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).Note: Set INT01TYPE to 1 only work when PWM operating in center aligned type." "0: PWMIFn will be set if PWM counter underflow. PWM..,1: PWMIFn will be set if PWM counter matches CNRn.." newline bitfld.long 0x0 11. "PWMDIE3,PWM channel 3 Duty Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "PWMDIE2,PWM channel 2 Duty Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "PWMDIE1,PWM channel 1 Duty Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "PWMDIE0,PWM channel 0 Duty Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "PWMIE3,PWM channel 3 Period Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 2. "PWMIE2,PWM channel 2 Period Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "PWMIE1,PWM channel 1 Period Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 0. "PWMIE0,PWM channel 0 Period Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x4 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x4 11. "PWMDIF3,PWM channel 3 Duty Interrupt Flag.Flag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" bitfld.long 0x4 10. "PWMDIF2,PWM channel 2 Duty Interrupt Flag.Flag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" newline bitfld.long 0x4 9. "PWMDIF1,PWM channel 1 Duty Interrupt Flag.Flag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" bitfld.long 0x4 8. "PWMDIF0,PWM channel 0 Duty Interrupt Flag.Flag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" newline bitfld.long 0x4 3. "PWMIF3,PWM channel 3 Period Interrupt Status.This bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" bitfld.long 0x4 2. "PWMIF2,PWM channel 2 Period Interrupt Status.This bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" newline bitfld.long 0x4 1. "PWMIF1,PWM channel 1 Period Interrupt Status.This bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" bitfld.long 0x4 0. "PWMIF0,PWM channel 0 Period Interrupt Status.This bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" group.long 0x50++0x7 line.long 0x0 "CCR0,PWM Capture Control Register 0" bitfld.long 0x0 23. "CFLRI1,CFLR1 Latched Indicator Bit.When PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 22. "CRLRI1,CRLR1 Latched Indicator Bit.When PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 20. "CAPIF1,Capture1 Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 19. "CAPCH1EN,Channel 1 Capture Function Enable.When Enable Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt." "0: Capture function on PWM group channel 1 Disabled,1: Capture function on PWM group channel 1 Enabled" newline bitfld.long 0x0 18. "CFL_IE1,PWM Group Channel 1 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 1 has falling transition Capture will issues an Interrupt." "0: Disable falling latch interrupt,1: Enable falling latch interrupt" bitfld.long 0x0 17. "CRL_IE1,PWM Group Channel 1 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 1 has rising transition Capture will issues an Interrupt." "0: Disable rising latch interrupt,1: Enable rising latch interrupt" newline bitfld.long 0x0 16. "INV1,PWM Group Channel 1 Inverter Enable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x0 7. "CFLRI0,CFLR0 Latched Indicator Bit.When PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 6. "CRLRI0,CRLR0 Latched Indicator Bit.When PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. .Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 4. "CAPIF0,Capture0 Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 3. "CAPCH0EN,Channel 0 Capture Function Enable.When Enable Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt." "0: Capture function on PWM group channel 0 Disabled,1: Capture function on PWM group channel 0 Enabled" bitfld.long 0x0 2. "CFL_IE0,PWM Group Channel 0 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 0 has falling transition Capture will issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x0 1. "CRL_IE0,PWM Group Channel 0 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 0 has rising transition Capture will issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x0 0. "INV0,PWM Group Channel 0 Inverter Enable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." line.long 0x4 "CCR2,PWM Capture Control Register 2" bitfld.long 0x4 23. "CFLRI3,CFLR3 Latched Indicator Bit.When PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0" "0,1" bitfld.long 0x4 22. "CRLRI3,CRLR3 Latched Indicator Bit.When PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 20. "CAPIF3,Capture3 Interrupt Indication Flag.Write 1 to clear this bit to zero." "0,1" bitfld.long 0x4 19. "CAPCH3EN,Channel 3 Capture Function Enable.When Enable Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 3 Interrupt." "0: Capture function on PWM group channel 3 Disabled,1: Capture function on PWM group channel 3 Enabled" newline bitfld.long 0x4 18. "CFL_IE3,PWM Group Channel 3 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 3 has falling transition Capture will issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 17. "CRL_IE3,PWM Group Channel 3 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 3 has rising transition Capture will issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 16. "INV3,PWM Group Channel 3 Inverter EnableEnable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x4 7. "CFLRI2,CFLR2 Latched Indicator Bit.When PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware..Note: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 6. "CRLRI2,CRLR2 Latched Indicator Bit.When PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware..Note: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x4 4. "CAPIF2,Capture2 Interrupt Indication Flag.Note: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 3. "CAPCH2EN,Channel 2 Capture Function Enable.When Enable Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 2 Interrupt." "0: Disable capture function on PWM group channel 2,1: Enable capture function on PWM group channel 2" bitfld.long 0x4 2. "CFL_IE2,PWM Group Channel 2 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 2 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x4 1. "CRL_IE2,PWM Group Channel 2 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 2 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x4 0. "INV2,PWM Group Channel 2 Inverter EnableEnable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." rgroup.long 0x58++0x1F line.long 0x0 "CRLR0,PWM Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "CFLR0,PWM Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x8 "CRLR1,PWM Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "CFLR1,PWM Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x10 "CRLR2,PWM Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "CFLR2,PWM Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x18 "CRLR3,PWM Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "CFLR3,PWM Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." group.long 0x78++0xF line.long 0x0 "CAPENR,PWM Capture Input 0~3 Enable Register" hexmask.long.byte 0x0 0.--3. 1. "CAPENR,Capture Input Enable Register.There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. .CAPENR.Bit 3210 for PWM group A.Bit xxx1 ( Capture channel 0 is from P2.0 or P4.0 (only one port can be.." line.long 0x4 "POE,PWM Output Enable Register for Channel 0~3" bitfld.long 0x4 3. "PWM3,PWM Channel 3 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 3 output to pin,1: Enable PWM channel 3 output to pin" bitfld.long 0x4 2. "PWM2,PWM Channel 2 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 2 output to pin,1: Enable PWM channel 2 output to pin" newline bitfld.long 0x4 1. "PWM1,PWM Channel 1 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 1 output to pin,1: Enable PWM channel 1 output to pin" bitfld.long 0x4 0. "PWM0,PWM Channel 0 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 0 output to pin,1: Enable PWM channel 0 output to pin" line.long 0x8 "TCON,PWM Trigger Control Register for Channel 0~3" bitfld.long 0x8 11. "PWM3DTEN,Channel 3 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 3 trigger ADC function,1: Enable PWM channel 3 trigger ADC function" bitfld.long 0x8 10. "PWM2DTEN,Channel 2 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 2 trigger ADC function,1: Enable PWM channel 2 trigger ADC function" newline bitfld.long 0x8 9. "PWM1DTEN,Channel 1 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 1 trigger ADC function,1: Enable PWM channel 1 trigger ADC function" bitfld.long 0x8 8. "PWM0DTEN,Channel 0 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 0 trigger ADC function,1: Enable PWM channel 0 trigger ADC function" newline bitfld.long 0x8 3. "PWM3TEN,Channel 3 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 3 trigger ADC function,1: Enable PWM channel 3 trigger ADC function" bitfld.long 0x8 2. "PWM2TEN,Channel 2 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 2 trigger ADC function,1: Enable PWM channel 2 trigger ADC function" newline bitfld.long 0x8 1. "PWM1TEN,Channel 1 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 1 trigger ADC function,1: Enable PWM channel 1 trigger ADC function" bitfld.long 0x8 0. "PWM0TEN,Channel 0 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 0 trigger ADC function,1: Enable PWM channel 0 trigger ADC function" line.long 0xC "TSTATUS,PWM Trigger Status Register" bitfld.long 0xC 3. "PWM3TF,PWM Channel 3 Trigger ADC Flag.This bit is set to 1 by hardware when PWM3 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" bitfld.long 0xC 2. "PWM2TF,PWM Channel 2 Trigger ADC Flag.This bit is set to 1 by hardware when PWM2 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" newline bitfld.long 0xC 1. "PWM1TF,PWM Channel 1 Trigger ADC Flag.This bit is set to 1 by hardware when PWM1 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" bitfld.long 0xC 0. "PWM0TF,PWM Channel 0 Trigger ADC Flag.This bit is set to 1 by hardware when PWM0 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" group.long 0x98++0x3 line.long 0x0 "PSCR,PWM Synchronous Control Register" bitfld.long 0x0 24. "PSSEN3,PWM3 Synchronous Start Enable.If this bit is set to 1 PWM group-Timer3 will synchronous start with PWM group A-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM3 synchronous start disable,1: PWM3 synchronous start enable" bitfld.long 0x0 16. "PSSEN2,PWM2 Synchronous Start Enable.If this bit is set to 1 PWM-Timer2 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM2 synchronous start disable,1: PWM2 synchronous start enable" newline bitfld.long 0x0 8. "PSSEN1,PWM1 Synchronous Start Enable.If this bit is set to 1 PWM-Timer1 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM1 synchronous start disable,1: PWM1 synchronous start enable" bitfld.long 0x0 0. "PSSEN0,PWM0 Synchronous Start Enable.If this bit is set to 1 PWM-Timer0 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM0 synchronous start disable,1: PWM0 synchronous start enable" tree.end tree "PWMB" base ad:0x40140000 group.long 0x0++0x13 line.long 0x0 "PPR,PWM Pre-scale Register" hexmask.long.byte 0x0 24.--31. 1. "DZI23,Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).These 8 bits determine dead zone length." hexmask.long.byte 0x0 16.--23. 1. "DZI01,Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).These 8 bits determine dead zone length." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock prescaler 2 (PWM counter 2 3 for group A and PWM counter 6 7 for group B).Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock prescaler 0 (PWM counter 0 1 for group A and PWM counter 4 5 for group B).Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter" line.long 0x4 "CSR,PWM Clock Select Register" bitfld.long 0x4 12.--14. "CSR3,Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "CSR2,Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B).Select clock input for PWM timer..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CSR1,Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B).Select clock input for PWM timer..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CSR0,Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B).Select clock input for PWM timer..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PCR,PWM Control Register" bitfld.long 0x8 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B)" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x8 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B)" "0: Edge-aligned type,1: Center-aligned type" newline bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B).Note: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable (PWM timer 3 for group A and PWM timer 7 for group B)" "0: PWM3 output polar inverse Disabled,1: PWM3 output polar inverse Enabled" bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B).Note: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter Enable(PWM timer 2 for group A and PWM timer 6 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable (PWM timer 2 for group A and PWM timer 6 for group B)" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B).Note: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter Enable(PWM timer 1 for group A and PWM timer 5 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable (PWM timer 1 for group A and PWM timer 5 for group B)" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled" bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable (PWM timer 1 for group A and PWM timer 5 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).Note: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6.." "0: Disabled,1: Enabled" bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).Note: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B).Note: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared." "0: One-shot Mode,1: Auto-reload Mode" bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter Enable(PWM timer 0 for group A and PWM timer 4 for group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable (PWM timer 0 for group A and PWM timer 4 for group B)" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" line.long 0xC "CNR0,PWM Counter Register 0" hexmask.long.word 0xC 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x10 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x10 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x14++0x3 line.long 0x0 "PDR0,PWM Data Register 0" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x18++0x7 line.long 0x0 "CNR1,PWM Counter Register 1" hexmask.long.word 0x0 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x4 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PDR1,PWM Data Register 1" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x24++0x7 line.long 0x0 "CNR2,PWM Counter Register 2" hexmask.long.word 0x0 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x4 "CMR2,PWM Comparator Register 2" hexmask.long.word 0x4 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PDR2,PWM Data Register 2" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x30++0x7 line.long 0x0 "CNR3,PWM Counter Register 3" hexmask.long.word 0x0 0.--15. 1. "CNRn,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at center-aligned type CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF .." line.long 0x4 "CMR3,PWM Comparator Register 3" hexmask.long.word 0x4 0.--15. 1. "CMRn,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PDR3,PWM Data Register 3" hexmask.long.word 0x0 0.--15. 1. "PDRn,PWM Data Register.User can monitor PDR to know the current value in 16-bit down counter." group.long 0x40++0x7 line.long 0x0 "PIER,PWM Interrupt Enable Register" bitfld.long 0x0 25. "INT23DTYPE,PWM23 Duty Interrupt Type Selection Bit (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).Note: Set INT23DTYPE to 1 only work when PWM operating in center aligned type." "0: PWMDIFn will be set if PWM counter down count..,1: PWMDIFn will be set when PWM counter up count.." bitfld.long 0x0 24. "INT01DTYPE,PWM01 Duty Interrupt Type Selection Bit (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).Note: Set INT01DTYPE to 1 only work when PWM operating in center aligned type." "0: PWMDIFn will be set if PWM counter down count..,1: PWMDIFn will be set when PWM counter up count.." newline bitfld.long 0x0 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 pair for PWM group A PWM6 and PWM7 pair for PWM group B).Note: Set INT23TYPE to 1 only work when PWM operating in center aligned type." "0: PWMIFn will be set if PWM counter underflow. PWM..,1: PWMIFn will be set if PWM counter matches CNRn.." bitfld.long 0x0 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 pair for PWM group A PWM4 and PWM5 pair for PWM group B).Note: Set INT01TYPE to 1 only work when PWM operating in center aligned type." "0: PWMIFn will be set if PWM counter underflow. PWM..,1: PWMIFn will be set if PWM counter matches CNRn.." newline bitfld.long 0x0 11. "PWMDIE3,PWM channel 3 Duty Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "PWMDIE2,PWM channel 2 Duty Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "PWMDIE1,PWM channel 1 Duty Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "PWMDIE0,PWM channel 0 Duty Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "PWMIE3,PWM channel 3 Period Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 2. "PWMIE2,PWM channel 2 Period Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "PWMIE1,PWM channel 1 Period Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 0. "PWMIE0,PWM channel 0 Period Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x4 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x4 11. "PWMDIF3,PWM channel 3 Duty Interrupt Flag.Flag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" bitfld.long 0x4 10. "PWMDIF2,PWM channel 2 Duty Interrupt Flag.Flag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" newline bitfld.long 0x4 9. "PWMDIF1,PWM channel 1 Duty Interrupt Flag.Flag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" bitfld.long 0x4 8. "PWMDIF0,PWM channel 0 Duty Interrupt Flag.Flag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in edge-aligned type.." "0,1" newline bitfld.long 0x4 3. "PWMIF3,PWM channel 3 Period Interrupt Status.This bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" bitfld.long 0x4 2. "PWMIF2,PWM channel 2 Period Interrupt Status.This bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" newline bitfld.long 0x4 1. "PWMIF1,PWM channel 1 Period Interrupt Status.This bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" bitfld.long 0x4 0. "PWMIF0,PWM channel 0 Period Interrupt Status.This bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to zero" "0,1" group.long 0x50++0x7 line.long 0x0 "CCR0,PWM Capture Control Register 0" bitfld.long 0x0 23. "CFLRI1,CFLR1 Latched Indicator Bit.When PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 22. "CRLRI1,CRLR1 Latched Indicator Bit.When PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 20. "CAPIF1,Capture1 Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 19. "CAPCH1EN,Channel 1 Capture Function Enable.When Enable Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt." "0: Capture function on PWM group channel 1 Disabled,1: Capture function on PWM group channel 1 Enabled" newline bitfld.long 0x0 18. "CFL_IE1,PWM Group Channel 1 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 1 has falling transition Capture will issues an Interrupt." "0: Disable falling latch interrupt,1: Enable falling latch interrupt" bitfld.long 0x0 17. "CRL_IE1,PWM Group Channel 1 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 1 has rising transition Capture will issues an Interrupt." "0: Disable rising latch interrupt,1: Enable rising latch interrupt" newline bitfld.long 0x0 16. "INV1,PWM Group Channel 1 Inverter Enable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x0 7. "CFLRI0,CFLR0 Latched Indicator Bit.When PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 6. "CRLRI0,CRLR0 Latched Indicator Bit.When PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. .Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 4. "CAPIF0,Capture0 Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 3. "CAPCH0EN,Channel 0 Capture Function Enable.When Enable Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt." "0: Capture function on PWM group channel 0 Disabled,1: Capture function on PWM group channel 0 Enabled" bitfld.long 0x0 2. "CFL_IE0,PWM Group Channel 0 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 0 has falling transition Capture will issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x0 1. "CRL_IE0,PWM Group Channel 0 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 0 has rising transition Capture will issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x0 0. "INV0,PWM Group Channel 0 Inverter Enable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." line.long 0x4 "CCR2,PWM Capture Control Register 2" bitfld.long 0x4 23. "CFLRI3,CFLR3 Latched Indicator Bit.When PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0" "0,1" bitfld.long 0x4 22. "CRLRI3,CRLR3 Latched Indicator Bit.When PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware..Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 20. "CAPIF3,Capture3 Interrupt Indication Flag.Write 1 to clear this bit to zero." "0,1" bitfld.long 0x4 19. "CAPCH3EN,Channel 3 Capture Function Enable.When Enable Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 3 Interrupt." "0: Capture function on PWM group channel 3 Disabled,1: Capture function on PWM group channel 3 Enabled" newline bitfld.long 0x4 18. "CFL_IE3,PWM Group Channel 3 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 3 has falling transition Capture will issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 17. "CRL_IE3,PWM Group Channel 3 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 3 has rising transition Capture will issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 16. "INV3,PWM Group Channel 3 Inverter EnableEnable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x4 7. "CFLRI2,CFLR2 Latched Indicator Bit.When PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware..Note: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 6. "CRLRI2,CRLR2 Latched Indicator Bit.When PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware..Note: Write 1 to clear this bit to 0" "0,1" bitfld.long 0x4 4. "CAPIF2,Capture2 Interrupt Indication Flag.Note: Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 3. "CAPCH2EN,Channel 2 Capture Function Enable.When Enable Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disable Capture does not update CRLR and CFLR and disable PWM group channel 2 Interrupt." "0: Disable capture function on PWM group channel 2,1: Enable capture function on PWM group channel 2" bitfld.long 0x4 2. "CFL_IE2,PWM Group Channel 2 Falling Latch Interrupt Enable.When Enable if Capture detects PWM group channel 2 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x4 1. "CRL_IE2,PWM Group Channel 2 Rising Latch Interrupt Enable.When Enable if Capture detects PWM group channel 2 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x4 0. "INV2,PWM Group Channel 2 Inverter EnableEnable" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." rgroup.long 0x58++0x1F line.long 0x0 "CRLR0,PWM Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "CFLR0,PWM Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x8 "CRLR1,PWM Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "CFLR1,PWM Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x10 "CRLR2,PWM Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "CFLR2,PWM Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x18 "CRLR3,PWM Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 0.--15. 1. "CRLRn,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "CFLR3,PWM Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 0.--15. 1. "CFLRn,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." group.long 0x78++0xF line.long 0x0 "CAPENR,PWM Capture Input 0~3 Enable Register" hexmask.long.byte 0x0 0.--3. 1. "CAPENR,Capture Input Enable Register.There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. .CAPENR.Bit 3210 for PWM group A.Bit xxx1 ( Capture channel 0 is from P2.0 or P4.0 (only one port can be.." line.long 0x4 "POE,PWM Output Enable Register for Channel 0~3" bitfld.long 0x4 3. "PWM3,PWM Channel 3 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 3 output to pin,1: Enable PWM channel 3 output to pin" bitfld.long 0x4 2. "PWM2,PWM Channel 2 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 2 output to pin,1: Enable PWM channel 2 output to pin" newline bitfld.long 0x4 1. "PWM1,PWM Channel 1 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 1 output to pin,1: Enable PWM channel 1 output to pin" bitfld.long 0x4 0. "PWM0,PWM Channel 0 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 0 output to pin,1: Enable PWM channel 0 output to pin" line.long 0x8 "TCON,PWM Trigger Control Register for Channel 0~3" bitfld.long 0x8 11. "PWM3DTEN,Channel 3 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 3 trigger ADC function,1: Enable PWM channel 3 trigger ADC function" bitfld.long 0x8 10. "PWM2DTEN,Channel 2 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 2 trigger ADC function,1: Enable PWM channel 2 trigger ADC function" newline bitfld.long 0x8 9. "PWM1DTEN,Channel 1 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 1 trigger ADC function,1: Enable PWM channel 1 trigger ADC function" bitfld.long 0x8 8. "PWM0DTEN,Channel 0 PWM Duty Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 0 trigger ADC function,1: Enable PWM channel 0 trigger ADC function" newline bitfld.long 0x8 3. "PWM3TEN,Channel 3 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 3 trigger ADC function,1: Enable PWM channel 3 trigger ADC function" bitfld.long 0x8 2. "PWM2TEN,Channel 2 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 2 trigger ADC function,1: Enable PWM channel 2 trigger ADC function" newline bitfld.long 0x8 1. "PWM1TEN,Channel 1 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 1 trigger ADC function,1: Enable PWM channel 1 trigger ADC function" bitfld.long 0x8 0. "PWM0TEN,Channel 0 PWM Period Trigger ADC Enable Register.As PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow..As PWM operating at center-aligned type enable this.." "0: Disable PWM channel 0 trigger ADC function,1: Enable PWM channel 0 trigger ADC function" line.long 0xC "TSTATUS,PWM Trigger Status Register" bitfld.long 0xC 3. "PWM3TF,PWM Channel 3 Trigger ADC Flag.This bit is set to 1 by hardware when PWM3 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" bitfld.long 0xC 2. "PWM2TF,PWM Channel 2 Trigger ADC Flag.This bit is set to 1 by hardware when PWM2 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" newline bitfld.long 0xC 1. "PWM1TF,PWM Channel 1 Trigger ADC Flag.This bit is set to 1 by hardware when PWM1 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" bitfld.long 0xC 0. "PWM0TF,PWM Channel 0 Trigger ADC Flag.This bit is set to 1 by hardware when PWM0 trigger ADC condition matched. As this bit is set to 1 ADC will start conversion if ADC triggered source is selected by PWM..Software can write 1 to clear this bit." "0,1" group.long 0x98++0x3 line.long 0x0 "PSCR,PWM Synchronous Control Register" bitfld.long 0x0 24. "PSSEN3,PWM3 Synchronous Start Enable.If this bit is set to 1 PWM group-Timer3 will synchronous start with PWM group A-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM3 synchronous start disable,1: PWM3 synchronous start enable" bitfld.long 0x0 16. "PSSEN2,PWM2 Synchronous Start Enable.If this bit is set to 1 PWM-Timer2 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM2 synchronous start disable,1: PWM2 synchronous start enable" newline bitfld.long 0x0 8. "PSSEN1,PWM1 Synchronous Start Enable.If this bit is set to 1 PWM-Timer1 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM1 synchronous start disable,1: PWM1 synchronous start enable" bitfld.long 0x0 0. "PSSEN0,PWM0 Synchronous Start Enable.If this bit is set to 1 PWM-Timer0 will synchronous start with group A PWM-Timer0 when SW writes 1 to PCR.CH0EN in PWM group A." "0: PWM0 synchronous start disable,1: PWM0 synchronous start enable" tree.end endif sif (cpuis("NUC029?DE")) tree "PWM0" base ad:0x40040000 group.long 0x0++0x7 line.long 0x0 "PWM_CTL0,PWM Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect).PWM pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to REGWRPROT register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to REGWRPROT register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Control.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-Load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." line.long 0x4 "PWM_CTL1,PWM Control Register 1" bitfld.long 0x4 24.--26. "PWMMODEn,PWM Mode.Each bit n controls the corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?" bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4.Each bit n controls corresponding PWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2.Each bit n controls corresponding PWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0.Each bit n controls corresponding PWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" group.long 0x10++0x17 line.long 0x0 "PWM_CLKSRC,PWM Clock Source Register" bitfld.long 0x0 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select." "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select." "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select." "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" line.long 0x4 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0_1" hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x8 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2_3" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0xC "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4_5" hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x10 "PWM_CNTEN,PWM Counter Enable Register" bitfld.long 0x10 4. "CNTEN4,PWM Counter Enable 4." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x10 2. "CNTEN2,PWM Counter Enable 2." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x10 0. "CNTEN0,PWM Counter Enable 0." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" line.long 0x14 "PWM_CNTCLR,PWM Clear Counter Register" bitfld.long 0x14 4. "CNTCLR4,Clear PWM Counter Control Bit 4.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit PWM counter to 0000H" bitfld.long 0x14 2. "CNTCLR2,Clear PWM Counter Control Bit 2.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit PWM counter to 0000H" newline bitfld.long 0x14 0. "CNTCLR0,Clear PWM Counter Control Bit 0.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit PWM counter to 0000H" group.long 0x30++0x3 line.long 0x0 "PWM_PERIOD0,PWM Period Register 0" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x38++0x3 line.long 0x0 "PWM_PERIOD2,PWM Period Register 2" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x40++0x3 line.long 0x0 "PWM_PERIOD4,PWM Period Register 4" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x50++0x17 line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." group.long 0x70++0xB line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0_1" bitfld.long 0x0 24. "DTCKSEL,Dead-Time Clock Select (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x0 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to REGWRPROT register." line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2_3" bitfld.long 0x4 24. "DTCKSEL,Dead-Time Clock Select (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x4 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to REGWRPROT register." line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4_5" bitfld.long 0x8 24. "DTCKSEL,Dead-Time Clock Select (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x8 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to REGWRPROT register." rgroup.long 0x90++0x3 line.long 0x0 "PWM_CNT0,PWM Counter Register 0" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." rgroup.long 0x98++0x3 line.long 0x0 "PWM_CNT2,PWM Counter Register 2" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." rgroup.long 0xA0++0x3 line.long 0x0 "PWM_CNT4,PWM Counter Register 4" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." group.long 0xB0++0x2B line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0" hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,PWM Period (Center) Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter count to (PERIODn+1)..Note: This bit is center point control when PWM counter operating in up-down counter.." hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,PWM Zero Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter count to zero." line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1" hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,PWM Compare Down Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter down count to CMPDAT..Note: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4." hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,PWM Compare Up Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter up count to CMPDAT..Note: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4." line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register" hexmask.long.byte 0x8 0.--5. 1. "MSKENn,PWM Mask Enable Control.Each bit n controls the corresponding PWM channel n..The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. ." line.long 0xC "PWM_MSK,PWM Mask Data Register" hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,PWM Mask Data Bit.This data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.." line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register" bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select.For PWM0 setting:." "0: Brake 1 pin source come from PWM0_BRAKE1..Brake..,1: Brake 1 pin source come from PWM1_BRAKE1..Brake.." bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select.For PWM0 setting:." "0: Brake 0 pin source come from PWM0_BRAKE0..Brake..,1: Brake 0 pin source come from PWM1_BRAKE0..Brake.." newline bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse." "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.." bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count.The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "BRK1FCS,Brake 1 Edge Detector Filter Clock Selection." "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 8. "BRK1FEN,PWM Brake 1 Noise Filter Enable Control." "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled" newline bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse." "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.." bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count.The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1.--3. "BRK0FCS,Brake 0 Edge Detector Filter Clock Selection." "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 0. "BRK0FEN,PWM Brake 0 Noise Filter Enable Control." "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled" line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register" bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Control." "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.." bitfld.long 0x14 1. "BODBRKEN,Brown-Out Detection Trigger PWM Brake Function 0 Enable." "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled" newline bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Control." "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled" line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0_1" bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?" bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?" newline bitfld.long 0x18 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x18 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2_3" bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?" bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?" newline bitfld.long 0x1C 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x1C 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4_5" bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?" bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?" newline bitfld.long 0x20 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x20 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register" hexmask.long.byte 0x24 0.--5. 1. "PINVn,PWM PIN Polar Inverse Control.The register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.." line.long 0x28 "PWM_POEN,PWM Output Enable Register" hexmask.long.byte 0x28 0.--5. 1. "POENn,PWM Pin Output Enable Control.Each bit n controls the corresponding PWM channel n.." wgroup.long 0xDC++0x3 line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register" bitfld.long 0x0 8.--10. "BRKLTRGn,PWM Level Brake Software Trigger (Write Only) (Write Protect).Each bit n controls the corresponding PWM pair n..Write 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. .Note: This register is write.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "BRKETRGn,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Each bit n controls the corresponding PWM pair n..Write 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. .Note: This register is write protected." "0,1,2,3,4,5,6,7" group.long 0xE0++0xF line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0" hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,PWM Compare Down Count Interrupt Enable Control.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4." hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,PWM Compare Up Count Interrupt Enable Control.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4." newline bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable 4.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable 2.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable 0.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable 4.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable 2.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable 0.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1" bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-Detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.." bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-Detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.." newline bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-Detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.." bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-Detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled" newline bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-Detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled" bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-Detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled" line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0" hexmask.long.byte 0x8 24.--29. 1. "CMPDIFn,PWM Compare Down Count Interrupt Flag.Each bit n controls the corresponding PWM channel n..Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it..Note1: If CMPDAT equal to.." hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMPDAT equal to.." newline bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag 4.This bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag 2.This bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2 software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag 0.This bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag 4.This bit is set by hardware when PWM_CH4 counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag 2.This bit is set by hardware when PWM_CH2 counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag 0.This bit is set by hardware when PWM_CH0 counter reaches zero software can write 1 to clear this bit to zero." "0,1" line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1" rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel5 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel5 level-detect brake state is released,1: When PWM channel5 level-detect brake detects a.." rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel4 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel4 level-detect brake state is released,1: When PWM channel4 level-detect brake detects a.." newline rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel3 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel3 level-detect brake state is released,1: When PWM channel3 level-detect brake detects a.." rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel2 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel2 level-detect brake state is released,1: When PWM channel2 level-detect brake detects a.." newline rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel1 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel1 level-detect brake state is released,1: When PWM channel1 level-detect brake detects a.." rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel0 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel0 level-detect brake state is released,1: When PWM channel0 level-detect brake detects a.." newline bitfld.long 0xC 21. "BRKESTS5,PWM Channel5 Edge-Detect Brake Status." "0: PWM channel5 edge-detect brake state is released,1: When PWM channel5 edge-detect brake detects a.." bitfld.long 0xC 20. "BRKESTS4,PWM Channel4 Edge-Detect Brake Status." "0: PWM channel4 edge-detect brake state is released,1: When PWM channel4 edge-detect brake detects a.." newline bitfld.long 0xC 19. "BRKESTS3,PWM Channel3 Edge-Detect Brake Status." "0: PWM channel3 edge-detect brake state is released,1: When PWM channel3 edge-detect brake detects a.." bitfld.long 0xC 18. "BRKESTS2,PWM Channel2 Edge-Detect Brake Status." "0: PWM channel2 edge-detect brake state is released,1: When PWM channel2 edge-detect brake detects a.." newline bitfld.long 0xC 17. "BRKESTS1,PWM Channel1 Edge-Detect Brake Status." "0: PWM channel1 edge-detect brake state is released,1: When PWM channel1 edge-detect brake detects a.." bitfld.long 0xC 16. "BRKESTS0,PWM Channel0 Edge-Detect Brake Status." "0: PWM channel0 edge-detect brake state is released,1: When PWM channel0 edge-detect brake detects a.." newline bitfld.long 0xC 13. "BRKLIF5,PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel5 level-detect brake event do not..,1: When PWM channel5 level-detect brake event.." bitfld.long 0xC 12. "BRKLIF4,PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel4 level-detect brake event do not..,1: When PWM channel4 level-detect brake event.." newline bitfld.long 0xC 11. "BRKLIF3,PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel3 level-detect brake event do not..,1: When PWM channel3 level-detect brake event.." bitfld.long 0xC 10. "BRKLIF2,PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel2 level-detect brake event do not..,1: When PWM channel2 level-detect brake event.." newline bitfld.long 0xC 9. "BRKLIF1,PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel1 level-detect brake event do not..,1: When PWM channel1 level-detect brake event.." bitfld.long 0xC 8. "BRKLIF0,PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel0 level-detect brake event do not..,1: When PWM channel0 level-detect brake event.." newline bitfld.long 0xC 5. "BRKEIF5,PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel5 edge-detect brake event do not..,1: When PWM channel5 edge-detect brake event.." bitfld.long 0xC 4. "BRKEIF4,PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel4 edge-detect brake event do not..,1: When PWM channel4 edge-detect brake event.." newline bitfld.long 0xC 3. "BRKEIF3,PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel3 edge-detect brake event do not..,1: When PWM channel3 edge-detect brake event.." bitfld.long 0xC 2. "BRKEIF2,PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel2 edge-detect brake event do not..,1: When PWM channel2 edge-detect brake event.." newline bitfld.long 0xC 1. "BRKEIF1,PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel1 edge-detect brake event do not..,1: When PWM channel1 edge-detect brake event.." bitfld.long 0xC 0. "BRKEIF0,PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel0 edge-detect brake event do not..,1: When PWM channel0 edge-detect brake event.." group.long 0xF8++0x7 line.long 0x0 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger ADC Source Select." newline bitfld.long 0x0 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger ADC Source Select." newline bitfld.long 0x0 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger ADC Source Select." newline bitfld.long 0x0 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger ADC Source Select." line.long 0x4 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger ADC Source Select." newline bitfld.long 0x4 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger ADC Source Select." group.long 0x110++0x3 line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register" bitfld.long 0x0 8.--9. "SSRC,PWM Synchronous Start Source Select." "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,?,?" bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable 4.When synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). ." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable 2.When synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). ." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable 0.When synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). ." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" wgroup.long 0x114++0x3 line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register" bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only).PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time..Writing this bit to 1 will also set the counter.." "0,1" group.long 0x120++0x3 line.long 0x0 "PWM_STATUS,PWM Status Register" hexmask.long.byte 0x0 16.--21. 1. "ADCTRGn,ADC Start Of Conversion Status.Each bit n controls the corresponding PWM channel n.." bitfld.long 0x0 4. "CNTMAX4,Time-Base Counter 4 Equal To 0xFFFF Latched Status." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." newline bitfld.long 0x0 2. "CNTMAX2,Time-Base Counter 2 Equal To 0xFFFF Latched Status." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." bitfld.long 0x0 0. "CNTMAX0,Time-Base Counter 0 Equal To 0xFFFF Latched Status." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." group.long 0x200++0x7 line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register" hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Control.Each bit n controls the corresponding PWM channel n.." line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register" hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload Enable Control.Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Control.Each bit n controls the corresponding PWM channel n.." newline hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Control.Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Control.Each bit n controls the corresponding PWM channel n.." rgroup.long 0x208++0x33 line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register" hexmask.long.byte 0x0 8.--13. 1. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be cleared automatically.." hexmask.long.byte 0x0 0.--5. 1. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be cleared automatically.." line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." group.long 0x250++0x7 line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register" hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,PWM Capture Falling Latch Interrupt Enable Control.Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,PWM Capture Rising Latch Interrupt Enable Control.Each bit n controls the corresponding PWM channel n.." line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register" hexmask.long.byte 0x4 8.--13. 1. "CFLIFn,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CRLIFn,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.." rgroup.long 0x304++0x3 line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x30C++0x3 line.long 0x0 "PWM_PBUF2,PWM PERIOD2 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x314++0x3 line.long 0x0 "PWM_PBUF4,PWM PERIOD4 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x31C++0x17 line.long 0x0 "PWM_CMPBUF0,PWM CMPDAT0 Buffer" hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x4 "PWM_CMPBUF1,PWM CMPDAT1 Buffer" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x8 "PWM_CMPBUF2,PWM CMPDAT2 Buffer" hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0xC "PWM_CMPBUF3,PWM CMPDAT3 Buffer" hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x10 "PWM_CMPBUF4,PWM CMPDAT4 Buffer" hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x14 "PWM_CMPBUF5,PWM CMPDAT5 Buffer" hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." tree.end tree "PWM1" base ad:0x40140000 group.long 0x0++0x7 line.long 0x0 "PWM_CTL0,PWM Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect).PWM pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to REGWRPROT register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to REGWRPROT register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Control.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-Load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." line.long 0x4 "PWM_CTL1,PWM Control Register 1" bitfld.long 0x4 24.--26. "PWMMODEn,PWM Mode.Each bit n controls the corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?" bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4.Each bit n controls corresponding PWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2.Each bit n controls corresponding PWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0.Each bit n controls corresponding PWM channel n.." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" group.long 0x10++0x17 line.long 0x0 "PWM_CLKSRC,PWM Clock Source Register" bitfld.long 0x0 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select." "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select." "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select." "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" line.long 0x4 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0_1" hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x8 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2_3" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0xC "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4_5" hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-Scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x10 "PWM_CNTEN,PWM Counter Enable Register" bitfld.long 0x10 4. "CNTEN4,PWM Counter Enable 4." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x10 2. "CNTEN2,PWM Counter Enable 2." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x10 0. "CNTEN0,PWM Counter Enable 0." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" line.long 0x14 "PWM_CNTCLR,PWM Clear Counter Register" bitfld.long 0x14 4. "CNTCLR4,Clear PWM Counter Control Bit 4.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit PWM counter to 0000H" bitfld.long 0x14 2. "CNTCLR2,Clear PWM Counter Control Bit 2.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit PWM counter to 0000H" newline bitfld.long 0x14 0. "CNTCLR0,Clear PWM Counter Control Bit 0.It is automatically cleared by hardware.." "0: No effect,1: Clear 16-bit PWM counter to 0000H" group.long 0x30++0x3 line.long 0x0 "PWM_PERIOD0,PWM Period Register 0" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x38++0x3 line.long 0x0 "PWM_PERIOD2,PWM Period Register 2" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x40++0x3 line.long 0x0 "PWM_PERIOD4,PWM Period Register 4" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0..Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD.." group.long 0x50++0x17 line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.CMP use to compare with CNT to generate PWM waveform interrupt and trigger ADC..In independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point..In complementary mode PWM_CMPDAT0 2 4 denote as first.." group.long 0x70++0xB line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0_1" bitfld.long 0x0 24. "DTCKSEL,Dead-Time Clock Select (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x0 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to REGWRPROT register." line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2_3" bitfld.long 0x4 24. "DTCKSEL,Dead-Time Clock Select (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x4 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to REGWRPROT register." line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4_5" bitfld.long 0x8 24. "DTCKSEL,Dead-Time Clock Select (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x8 16. "DTEN,Enable Dead-Time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-Time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to REGWRPROT register." rgroup.long 0x90++0x3 line.long 0x0 "PWM_CNT0,PWM Counter Register 0" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." rgroup.long 0x98++0x3 line.long 0x0 "PWM_CNT2,PWM Counter Register 2" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." rgroup.long 0xA0++0x3 line.long 0x0 "PWM_CNT4,PWM Counter Register 4" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)." "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only).User can monitor CNT to know the current value in 16-bit period counter." group.long 0xB0++0x2B line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0" hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,PWM Period (Center) Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter count to (PERIODn+1)..Note: This bit is center point control when PWM counter operating in up-down counter.." hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,PWM Zero Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter count to zero." line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1" hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,PWM Compare Down Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter down count to CMPDAT..Note: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4." hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,PWM Compare Up Point Control.Each bit n controls the corresponding PWM channel n..PWM can control output level when PWM counter up count to CMPDAT..Note: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4." line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register" hexmask.long.byte 0x8 0.--5. 1. "MSKENn,PWM Mask Enable Control.Each bit n controls the corresponding PWM channel n..The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. ." line.long 0xC "PWM_MSK,PWM Mask Data Register" hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,PWM Mask Data Bit.This data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.." line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register" bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select.For PWM0 setting:." "0: Brake 1 pin source come from PWM0_BRAKE1..Brake..,1: Brake 1 pin source come from PWM1_BRAKE1..Brake.." bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select.For PWM0 setting:." "0: Brake 0 pin source come from PWM0_BRAKE0..Brake..,1: Brake 0 pin source come from PWM1_BRAKE0..Brake.." newline bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse." "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.." bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count.The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "BRK1FCS,Brake 1 Edge Detector Filter Clock Selection." "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 8. "BRK1FEN,PWM Brake 1 Noise Filter Enable Control." "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled" newline bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse." "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.." bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count.The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1.--3. "BRK0FCS,Brake 0 Edge Detector Filter Clock Selection." "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 0. "BRK0FEN,PWM Brake 0 Noise Filter Enable Control." "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled" line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register" bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Control." "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.." bitfld.long 0x14 1. "BODBRKEN,Brown-Out Detection Trigger PWM Brake Function 0 Enable." "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled" newline bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Control." "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled" line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0_1" bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?" bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?" newline bitfld.long 0x18 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x18 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2_3" bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?" bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?" newline bitfld.long 0x1C 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x1C 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4_5" bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select For Odd Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?" bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select For Even Channel (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?" newline bitfld.long 0x20 15. "SYSLEN,Enable System Fail As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x20 7. "SYSEEN,Enable System Fail As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register" hexmask.long.byte 0x24 0.--5. 1. "PINVn,PWM PIN Polar Inverse Control.The register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.." line.long 0x28 "PWM_POEN,PWM Output Enable Register" hexmask.long.byte 0x28 0.--5. 1. "POENn,PWM Pin Output Enable Control.Each bit n controls the corresponding PWM channel n.." wgroup.long 0xDC++0x3 line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register" bitfld.long 0x0 8.--10. "BRKLTRGn,PWM Level Brake Software Trigger (Write Only) (Write Protect).Each bit n controls the corresponding PWM pair n..Write 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. .Note: This register is write.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "BRKETRGn,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Each bit n controls the corresponding PWM pair n..Write 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. .Note: This register is write protected." "0,1,2,3,4,5,6,7" group.long 0xE0++0xF line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0" hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,PWM Compare Down Count Interrupt Enable Control.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4." hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,PWM Compare Up Count Interrupt Enable Control.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4." newline bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable 4.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable 2.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable 0.Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable 4.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable 2.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable 0.Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1" bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-Detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.." bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-Detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.." newline bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-Detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.." bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-Detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled" newline bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-Detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled" bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-Detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled" line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0" hexmask.long.byte 0x8 24.--29. 1. "CMPDIFn,PWM Compare Down Count Interrupt Flag.Each bit n controls the corresponding PWM channel n..Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it..Note1: If CMPDAT equal to.." hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMPDAT equal to.." newline bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag 4.This bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag 2.This bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2 software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag 0.This bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag 4.This bit is set by hardware when PWM_CH4 counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag 2.This bit is set by hardware when PWM_CH2 counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag 0.This bit is set by hardware when PWM_CH0 counter reaches zero software can write 1 to clear this bit to zero." "0,1" line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1" rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel5 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel5 level-detect brake state is released,1: When PWM channel5 level-detect brake detects a.." rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel4 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel4 level-detect brake state is released,1: When PWM channel4 level-detect brake detects a.." newline rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel3 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel3 level-detect brake state is released,1: When PWM channel3 level-detect brake detects a.." rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel2 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel2 level-detect brake state is released,1: When PWM channel2 level-detect brake detects a.." newline rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel1 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel1 level-detect brake state is released,1: When PWM channel1 level-detect brake detects a.." rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel0 Level-Detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel0 level-detect brake state is released,1: When PWM channel0 level-detect brake detects a.." newline bitfld.long 0xC 21. "BRKESTS5,PWM Channel5 Edge-Detect Brake Status." "0: PWM channel5 edge-detect brake state is released,1: When PWM channel5 edge-detect brake detects a.." bitfld.long 0xC 20. "BRKESTS4,PWM Channel4 Edge-Detect Brake Status." "0: PWM channel4 edge-detect brake state is released,1: When PWM channel4 edge-detect brake detects a.." newline bitfld.long 0xC 19. "BRKESTS3,PWM Channel3 Edge-Detect Brake Status." "0: PWM channel3 edge-detect brake state is released,1: When PWM channel3 edge-detect brake detects a.." bitfld.long 0xC 18. "BRKESTS2,PWM Channel2 Edge-Detect Brake Status." "0: PWM channel2 edge-detect brake state is released,1: When PWM channel2 edge-detect brake detects a.." newline bitfld.long 0xC 17. "BRKESTS1,PWM Channel1 Edge-Detect Brake Status." "0: PWM channel1 edge-detect brake state is released,1: When PWM channel1 edge-detect brake detects a.." bitfld.long 0xC 16. "BRKESTS0,PWM Channel0 Edge-Detect Brake Status." "0: PWM channel0 edge-detect brake state is released,1: When PWM channel0 edge-detect brake detects a.." newline bitfld.long 0xC 13. "BRKLIF5,PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel5 level-detect brake event do not..,1: When PWM channel5 level-detect brake event.." bitfld.long 0xC 12. "BRKLIF4,PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel4 level-detect brake event do not..,1: When PWM channel4 level-detect brake event.." newline bitfld.long 0xC 11. "BRKLIF3,PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel3 level-detect brake event do not..,1: When PWM channel3 level-detect brake event.." bitfld.long 0xC 10. "BRKLIF2,PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel2 level-detect brake event do not..,1: When PWM channel2 level-detect brake event.." newline bitfld.long 0xC 9. "BRKLIF1,PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel1 level-detect brake event do not..,1: When PWM channel1 level-detect brake event.." bitfld.long 0xC 8. "BRKLIF0,PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel0 level-detect brake event do not..,1: When PWM channel0 level-detect brake event.." newline bitfld.long 0xC 5. "BRKEIF5,PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel5 edge-detect brake event do not..,1: When PWM channel5 edge-detect brake event.." bitfld.long 0xC 4. "BRKEIF4,PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel4 edge-detect brake event do not..,1: When PWM channel4 edge-detect brake event.." newline bitfld.long 0xC 3. "BRKEIF3,PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel3 edge-detect brake event do not..,1: When PWM channel3 edge-detect brake event.." bitfld.long 0xC 2. "BRKEIF2,PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel2 edge-detect brake event do not..,1: When PWM channel2 edge-detect brake event.." newline bitfld.long 0xC 1. "BRKEIF1,PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel1 edge-detect brake event do not..,1: When PWM channel1 edge-detect brake event.." bitfld.long 0xC 0. "BRKEIF0,PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect).Note: This register is write protected. Refer to REGWRPROT register." "0: PWM channel0 edge-detect brake event do not..,1: When PWM channel0 edge-detect brake event.." group.long 0xF8++0x7 line.long 0x0 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger ADC Source Select." newline bitfld.long 0x0 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger ADC Source Select." newline bitfld.long 0x0 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger ADC Source Select." newline bitfld.long 0x0 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger ADC Source Select." line.long 0x4 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger ADC Source Select." newline bitfld.long 0x4 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger ADC Source Select." group.long 0x110++0x3 line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register" bitfld.long 0x0 8.--9. "SSRC,PWM Synchronous Start Source Select." "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,?,?" bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable 4.When synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). ." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable 2.When synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). ." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable 0.When synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). ." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" wgroup.long 0x114++0x3 line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register" bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only).PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time..Writing this bit to 1 will also set the counter.." "0,1" group.long 0x120++0x3 line.long 0x0 "PWM_STATUS,PWM Status Register" hexmask.long.byte 0x0 16.--21. 1. "ADCTRGn,ADC Start Of Conversion Status.Each bit n controls the corresponding PWM channel n.." bitfld.long 0x0 4. "CNTMAX4,Time-Base Counter 4 Equal To 0xFFFF Latched Status." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." newline bitfld.long 0x0 2. "CNTMAX2,Time-Base Counter 2 Equal To 0xFFFF Latched Status." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." bitfld.long 0x0 0. "CNTMAX0,Time-Base Counter 0 Equal To 0xFFFF Latched Status." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." group.long 0x200++0x7 line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register" hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Control.Each bit n controls the corresponding PWM channel n.." line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register" hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload Enable Control.Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Control.Each bit n controls the corresponding PWM channel n.." newline hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Control.Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Control.Each bit n controls the corresponding PWM channel n.." rgroup.long 0x208++0x33 line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register" hexmask.long.byte 0x0 8.--13. 1. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be cleared automatically.." hexmask.long.byte 0x0 0.--5. 1. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be cleared automatically.." line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." group.long 0x250++0x7 line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register" hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,PWM Capture Falling Latch Interrupt Enable Control.Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,PWM Capture Rising Latch Interrupt Enable Control.Each bit n controls the corresponding PWM channel n.." line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register" hexmask.long.byte 0x4 8.--13. 1. "CFLIFn,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.." hexmask.long.byte 0x4 0.--5. 1. "CRLIFn,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.." rgroup.long 0x304++0x3 line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x30C++0x3 line.long 0x0 "PWM_PBUF2,PWM PERIOD2 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x314++0x3 line.long 0x0 "PWM_PBUF4,PWM PERIOD4 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." rgroup.long 0x31C++0x17 line.long 0x0 "PWM_CMPBUF0,PWM CMPDAT0 Buffer" hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x4 "PWM_CMPBUF1,PWM CMPDAT1 Buffer" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x8 "PWM_CMPBUF2,PWM CMPDAT2 Buffer" hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0xC "PWM_CMPBUF3,PWM CMPDAT3 Buffer" hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x10 "PWM_CMPBUF4,PWM CMPDAT4 Buffer" hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." line.long 0x14 "PWM_CMPBUF5,PWM CMPDAT5 Buffer" hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMP active register." tree.end endif sif (cpuis("NUC029?EE")) tree "PWMA" base ad:0x40040000 group.long 0x0++0x13 line.long 0x0 "PPR,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZI23,Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A).These 8-bit determine the Dead-zone length." hexmask.long.byte 0x0 16.--23. 1. "DZI01,Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B).These 8-bit determine the Dead-zone length." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-Timer2 / 3 For Group A).Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B).Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer" line.long 0x4 "CSR,PWM Clock Source Divider Select Register" bitfld.long 0x4 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A).Select clock source divider for PWM timer 3." "0: 2,1: 4,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A).Select clock source divider for PWM timer 2..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B).Select clock source divider for PWM timer 1..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B).Select clock source divider for PWM timer 0..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PCR,PWM Control Register" bitfld.long 0x8 31. "PWM23TYPE,PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A)" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x8 30. "PWM01TYPE,PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)" "0: Edge-aligned type,1: Center-aligned type" newline bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A).Note: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A)" "0: PWM3 output polar inverse Disable,1: PWM3 output polar inverse Enable" bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable (PWM Timer 3 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A).Note: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A)" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable (PWM Timer 2 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B).Note: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Inverter Disable,1: Inverter Enable" newline bitfld.long 0x8 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled" bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A).Note: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A." "0: Disabled,1: Enabled" bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B).Note: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B).Note: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running" line.long 0xC "CNR0,PWM Counter Register 0" hexmask.long.word 0xC 0.--15. 1. "CNRx,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.." line.long 0x10 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x10 0.--15. 1. "CMRx,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x14++0x3 line.long 0x0 "PDR0,PWM Data Register 0" hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register.User can monitor PDR to know the current value in 16-bit counter." group.long 0x18++0x7 line.long 0x0 "CNR1,PWM Counter Register 1" hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.." line.long 0x4 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PDR1,PWM Data Register 1" hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register.User can monitor PDR to know the current value in 16-bit counter." group.long 0x24++0x7 line.long 0x0 "CNR2,PWM Counter Register 2" hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.." line.long 0x4 "CMR2,PWM Comparator Register 2" hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PDR2,PWM Data Register 2" hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register.User can monitor PDR to know the current value in 16-bit counter." group.long 0x30++0x7 line.long 0x0 "CNR3,PWM Counter Register 3" hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.." line.long 0x4 "CMR3,PWM Comparator Register 3" hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PDR3,PWM Data Register 3" hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register.User can monitor PDR to know the current value in 16-bit counter." group.long 0x3C++0xB line.long 0x0 "PBCR,PWM Backward Compatible Register" bitfld.long 0x0 0. "BCn,PWM Backward Compatible Register.Refer to the CCR0/CCR2 register bit 6 7 22 23 description.Note: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2." "0: Configure write 0 to clear CFLRI0~3 and CRLRI0~3,1: Configure write 1 to clear CFLRI0~3 and CRLRI0~3" line.long 0x4 "PIER,PWM Interrupt Enable Register" bitfld.long 0x4 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A).Note: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.." bitfld.long 0x4 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B).Note: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.." newline bitfld.long 0x4 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x4 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" line.long 0x8 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x8 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag.Flag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" bitfld.long 0x8 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag.Flag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" newline bitfld.long 0x8 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag.Flag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" bitfld.long 0x8 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag.Flag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" newline bitfld.long 0x8 3. "PWMIF3,PWM Channel 3 Period Interrupt Status.This bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" bitfld.long 0x8 2. "PWMIF2,PWM Channel 2 Period Interrupt Status.This bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x8 1. "PWMIF1,PWM Channel 1 Period Interrupt Status.This bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" bitfld.long 0x8 0. "PWMIF0,PWM Channel 0 Period Interrupt Status.This bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" group.long 0x50++0x7 line.long 0x0 "CCR0,PWM Capture Control Register 0" bitfld.long 0x0 23. "CFLRI1,CFLR1 Latched Indicator Bit.When PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1" bitfld.long 0x0 22. "CRLRI1,CRLR1 Latched Indicator Bit.When PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1" newline bitfld.long 0x0 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 19. "CAPCH1EN,Channel 1 Capture Function Enable Bit.When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disabled Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt." "0: Capture function on PWM group channel 1 Disabled,1: Capture function on PWM group channel 1 Enabled" newline bitfld.long 0x0 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x0 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x0 16. "INV1,Channel 1 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x0 7. "CFLRI0,CFLR0 Latched Indicator.When PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" newline bitfld.long 0x0 6. "CRLRI0,CRLR0 Latched Indicator.When PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" bitfld.long 0x0 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 3. "CAPCH0EN,Channel 0 Capture Function Enable.When Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disabled Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt." "0: Capture function on PWM group channel 0 Disabled,1: Capture function on PWM group channel 0 Enabled" bitfld.long 0x0 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 0 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x0 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x0 0. "INV0,Channel 0 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." line.long 0x4 "CCR2,PWM Capture Control Register 2" bitfld.long 0x4 23. "CFLRI3,CFLR3 Latched Indicator.When PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" bitfld.long 0x4 22. "CRLRI3,CRLR3 Latched Indicator.When PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" newline bitfld.long 0x4 20. "CAPIF3,Channel 3 Capture Interrupt Indication Flag.Write 1 to clear this bit to 0" "0,1" bitfld.long 0x4 19. "CAPCH3EN,Channel 3 Capture Function Enable Bit.When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disabled Capture does not update CRLR and CFLR and disable PWM group channel 3 Interrupt." "0: Capture function on PWM group channel 3 Disabled,1: Capture function on PWM group channel 3 Enabled" newline bitfld.long 0x4 18. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 3 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 17. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 3 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 16. "INV3,Channel 3 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x4 7. "CFLRI2,CFLR2 Latched Indicator.When PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if BCn bit is 0 and can write 1.." "0,1" newline bitfld.long 0x4 6. "CRLRI2,CRLR2 Latched Indicator.When PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" bitfld.long 0x4 4. "CAPIF2,Channel 2 Capture Interrupt Indication Flag.Write 1 to clear this bit to 0" "0,1" newline bitfld.long 0x4 3. "CAPCH2EN,Channel 2 Capture Function Enable Bit.When Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disabled Capture does not update CRLR and CFLR and disable PWM group channel 2 Interrupt." "0: Capture function on PWM group channel 2 Disabled,1: Capture function on PWM group channel 2 Enabled" bitfld.long 0x4 2. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 2 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x4 1. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 2 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x4 0. "INV2,Channel 2 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." rgroup.long 0x58++0x1F line.long 0x0 "CRLR0,PWM Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 0.--15. 1. "CRLRx,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "CFLR0,PWM Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 0.--15. 1. "CFLRx,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x8 "CRLR1,PWM Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 0.--15. 1. "CRLRx,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "CFLR1,PWM Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 0.--15. 1. "CFLRx,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x10 "CRLR2,PWM Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 0.--15. 1. "CRLRx,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "CFLR2,PWM Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 0.--15. 1. "CFLRx,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x18 "CRLR3,PWM Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 0.--15. 1. "CRLRx,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "CFLR3,PWM Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 0.--15. 1. "CFLRx,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." group.long 0x78++0xF line.long 0x0 "CAPENR,PWM Capture Input 0~3 Enable Register" bitfld.long 0x0 3. "CINEN3,Channel 3 Capture Input Enable Bit" "0: PWM Channel 3 capture input path Disabled. The..,1: PWM Channel 3 capture input path Enabled. The.." bitfld.long 0x0 2. "CINEN2,Channel 2 Capture Input Enable Bit" "0: PWM Channel 2 capture input path Disabled. The..,1: PWM Channel 2 capture input path Enabled. The.." newline bitfld.long 0x0 1. "CINEN1,Channel 1 Capture Input Enable Bit" "0: PWM Channel 1 capture input path Disabled. The..,1: PWM Channel 1 capture input path Enabled. The.." bitfld.long 0x0 0. "CINEN0,Channel 0 Capture Input Enable Bit" "0: PWM Channel 0 capture input path Disabled. The..,1: PWM Channel 0 capture input path Enabled. The.." line.long 0x4 "POE,PWM Output Enable for Channel 0~3" bitfld.long 0x4 3. "POE3,Channel 3 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled" bitfld.long 0x4 2. "POE2,Channel 2 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled" newline bitfld.long 0x4 1. "POE1,Channel 1 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled" bitfld.long 0x4 0. "POE0,Channel 0 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled" line.long 0x8 "TCON,PWM Trigger Control for Channel 0~3" bitfld.long 0x8 3. "PWM3TEN,Channel 3 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 3 trigger ADC function Disabled,1: PWM channel 3 trigger ADC function Enabled" bitfld.long 0x8 2. "PWM2TEN,Channel 2 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 2 trigger ADC function Disabled,1: PWM channel 2 trigger ADC function Enabled" newline bitfld.long 0x8 1. "PWM1TEN,Channel 1 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 1 trigger ADC function Disabled,1: PWM channel 1 trigger ADC function Enabled" bitfld.long 0x8 0. "PWM0TEN,Channel 0 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 0 trigger ADC function Disabled,1: PWM channel 0 trigger ADC function Enabled" line.long 0xC "TSTATUS,PWM Trigger Status Register" bitfld.long 0xC 3. "PWM3TF,Channel 3 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" bitfld.long 0xC 2. "PWM2TF,Channel 2 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" newline bitfld.long 0xC 1. "PWM1TF,Channel 1 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" bitfld.long 0xC 0. "PWM0TF,Channel 0 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" rgroup.long 0x88++0xF line.long 0x0 "SYNCBUSY0,PWM0 Synchronous Busy Status Register" bitfld.long 0x0 0. "S_BUSY,PWM Synchronous Busy.When software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1" line.long 0x4 "SYNCBUSY1,PWM1 Synchronous Busy Status Register" bitfld.long 0x4 0. "S_BUSY,PWM Synchronous Busy.When Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1" line.long 0x8 "SYNCBUSY2,PWM2 Synchronous Busy Status Register" bitfld.long 0x8 0. "S_BUSY,PWM Synchronous Busy.When Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this.." "0,1" line.long 0xC "SYNCBUSY3,PWM3 Synchronous Busy Status Register" bitfld.long 0xC 0. "S_BUSY,PWM Synchronous Busy.When Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check this.." "0,1" tree.end tree "PWMB" base ad:0x40140000 group.long 0x0++0x13 line.long 0x0 "PPR,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZI23,Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A).These 8-bit determine the Dead-zone length." hexmask.long.byte 0x0 16.--23. 1. "DZI01,Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B).These 8-bit determine the Dead-zone length." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-Timer2 / 3 For Group A).Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B).Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer" line.long 0x4 "CSR,PWM Clock Source Divider Select Register" bitfld.long 0x4 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A).Select clock source divider for PWM timer 3." "0: 2,1: 4,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A).Select clock source divider for PWM timer 2..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B).Select clock source divider for PWM timer 1..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B).Select clock source divider for PWM timer 0..(Table is the same as CSR3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PCR,PWM Control Register" bitfld.long 0x8 31. "PWM23TYPE,PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A)" "0: Edge-aligned type,1: Center-aligned type" bitfld.long 0x8 30. "PWM01TYPE,PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)" "0: Edge-aligned type,1: Center-aligned type" newline bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A).Note: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A)" "0: PWM3 output polar inverse Disable,1: PWM3 output polar inverse Enable" bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable (PWM Timer 3 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A).Note: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A)" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable (PWM Timer 2 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B).Note: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Inverter Disable,1: Inverter Enable" newline bitfld.long 0x8 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled" bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running" newline bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A).Note: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A." "0: Disabled,1: Enabled" bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B).Note: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5.." "0: Disabled,1: Enabled" newline bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B).Note: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared." "0: One-shot mode,1: Auto-reload mode" bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: Inverter Disabled,1: Inverter Enabled" newline bitfld.long 0x8 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running" line.long 0xC "CNR0,PWM Counter Register 0" hexmask.long.word 0xC 0.--15. 1. "CNRx,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.." line.long 0x10 "CMR0,PWM Comparator Register 0" hexmask.long.word 0x10 0.--15. 1. "CMRx,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x14++0x3 line.long 0x0 "PDR0,PWM Data Register 0" hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register.User can monitor PDR to know the current value in 16-bit counter." group.long 0x18++0x7 line.long 0x0 "CNR1,PWM Counter Register 1" hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value.CNR determines the PWM period..Note: Any write to CNR will take effect in next PWM cycle..Note: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.." line.long 0x4 "CMR1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register.CMR determines the PWM duty..Note: Any write to CNR will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PDR1,PWM Data Register 1" hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register.User can monitor PDR to know the current value in 16-bit counter." group.long 0x3C++0xB line.long 0x0 "PBCR,PWM Backward Compatible Register" bitfld.long 0x0 0. "BCn,PWM Backward Compatible Register.Refer to the CCR0/CCR2 register bit 6 7 22 23 description.Note: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2." "0: Configure write 0 to clear CFLRI0~3 and CRLRI0~3,1: Configure write 1 to clear CFLRI0~3 and CRLRI0~3" line.long 0x4 "PIER,PWM Interrupt Enable Register" bitfld.long 0x4 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A).Note: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.." bitfld.long 0x4 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B).Note: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.." newline bitfld.long 0x4 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x4 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" bitfld.long 0x4 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable Bit" "0: Disabled,1: Enabled" line.long 0x8 "PIIR,PWM Interrupt Indication Register" bitfld.long 0x8 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag.Flag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" bitfld.long 0x8 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag.Flag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" newline bitfld.long 0x8 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag.Flag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" bitfld.long 0x8 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag.Flag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it..Note: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1" newline bitfld.long 0x8 3. "PWMIF3,PWM Channel 3 Period Interrupt Status.This bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" bitfld.long 0x8 2. "PWMIF2,PWM Channel 2 Period Interrupt Status.This bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x8 1. "PWMIF1,PWM Channel 1 Period Interrupt Status.This bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" bitfld.long 0x8 0. "PWMIF0,PWM Channel 0 Period Interrupt Status.This bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1" group.long 0x50++0x3 line.long 0x0 "CCR0,PWM Capture Control Register 0" bitfld.long 0x0 23. "CFLRI1,CFLR1 Latched Indicator Bit.When PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1" bitfld.long 0x0 22. "CRLRI1,CRLR1 Latched Indicator Bit.When PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1" newline bitfld.long 0x0 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" bitfld.long 0x0 19. "CAPCH1EN,Channel 1 Capture Function Enable Bit.When Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disabled Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt." "0: Capture function on PWM group channel 1 Disabled,1: Capture function on PWM group channel 1 Enabled" newline bitfld.long 0x0 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x0 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x0 16. "INV1,Channel 1 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." bitfld.long 0x0 7. "CFLRI0,CFLR0 Latched Indicator.When PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" newline bitfld.long 0x0 6. "CRLRI0,CRLR0 Latched Indicator.When PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware..Software can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1" bitfld.long 0x0 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag.Write 1 to clear this bit to 0." "0,1" newline bitfld.long 0x0 3. "CAPCH0EN,Channel 0 Capture Function Enable.When Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch)..When Disabled Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt." "0: Capture function on PWM group channel 0 Disabled,1: Capture function on PWM group channel 0 Enabled" bitfld.long 0x0 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 0 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" newline bitfld.long 0x0 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Bit.When Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" bitfld.long 0x0 0. "INV0,Channel 0 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.." rgroup.long 0x58++0xF line.long 0x0 "CRLR0,PWM Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 0.--15. 1. "CRLRx,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "CFLR0,PWM Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 0.--15. 1. "CFLRx,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." line.long 0x8 "CRLR1,PWM Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 0.--15. 1. "CRLRx,Capture Rising Latch Register.Latch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "CFLR1,PWM Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 0.--15. 1. "CFLRx,Capture Falling Latch Register.Latch the PWM counter when Channel 0/1/2/3 has Falling transition." group.long 0x78++0xF line.long 0x0 "CAPENR,PWM Capture Input 0~3 Enable Register" bitfld.long 0x0 3. "CINEN3,Channel 3 Capture Input Enable Bit" "0: PWM Channel 3 capture input path Disabled. The..,1: PWM Channel 3 capture input path Enabled. The.." bitfld.long 0x0 2. "CINEN2,Channel 2 Capture Input Enable Bit" "0: PWM Channel 2 capture input path Disabled. The..,1: PWM Channel 2 capture input path Enabled. The.." newline bitfld.long 0x0 1. "CINEN1,Channel 1 Capture Input Enable Bit" "0: PWM Channel 1 capture input path Disabled. The..,1: PWM Channel 1 capture input path Enabled. The.." bitfld.long 0x0 0. "CINEN0,Channel 0 Capture Input Enable Bit" "0: PWM Channel 0 capture input path Disabled. The..,1: PWM Channel 0 capture input path Enabled. The.." line.long 0x4 "POE,PWM Output Enable for Channel 0~3" bitfld.long 0x4 3. "POE3,Channel 3 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled" bitfld.long 0x4 2. "POE2,Channel 2 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled" newline bitfld.long 0x4 1. "POE1,Channel 1 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled" bitfld.long 0x4 0. "POE0,Channel 0 Output Enable Bit.Note: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled" line.long 0x8 "TCON,PWM Trigger Control for Channel 0~3" bitfld.long 0x8 3. "PWM3TEN,Channel 3 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 3 trigger ADC function Disabled,1: PWM channel 3 trigger ADC function Enabled" bitfld.long 0x8 2. "PWM2TEN,Channel 2 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 2 trigger ADC function Disabled,1: PWM channel 2 trigger ADC function Enabled" newline bitfld.long 0x8 1. "PWM1TEN,Channel 1 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 1 trigger ADC function Disabled,1: PWM channel 1 trigger ADC function Enabled" bitfld.long 0x8 0. "PWM0TEN,Channel 0 Center-Aligned Trigger Enable Bit.PWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1..Note: This function is only supported when PWM operating at Center-aligned type." "0: PWM channel 0 trigger ADC function Disabled,1: PWM channel 0 trigger ADC function Enabled" line.long 0xC "TSTATUS,PWM Trigger Status Register" bitfld.long 0xC 3. "PWM3TF,Channel 3 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" bitfld.long 0xC 2. "PWM2TF,Channel 2 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" newline bitfld.long 0xC 1. "PWM1TF,Channel 1 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" bitfld.long 0xC 0. "PWM0TF,Channel 0 Center-Aligned Trigger Flag.For Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1" rgroup.long 0x88++0x7 line.long 0x0 "SYNCBUSY0,PWM0 Synchronous Busy Status Register" bitfld.long 0x0 0. "S_BUSY,PWM Synchronous Busy.When software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1" line.long 0x4 "SYNCBUSY1,PWM1 Synchronous Busy Status Register" bitfld.long 0x4 0. "S_BUSY,PWM Synchronous Busy.When Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1" tree.end endif sif (cpuis("NUC029?GE")) tree "PWM0" base ad:0x40040000 group.long 0x0++0x2B line.long 0x0 "PWM_CTL0,PWM Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect).PWM pin will keep output no matter ICE debug mode acknowledged or not..Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. .Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each PWM channel are..,1: Unify the PWMx_CH2 and PWMx_CH4 to output the.." bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." newline bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." newline bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." newline bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." bitfld.long 0x0 13. "WINLDEN5,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." newline bitfld.long 0x0 12. "WINLDEN4,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." bitfld.long 0x0 11. "WINLDEN3,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." newline bitfld.long 0x0 10. "WINLDEN2,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." bitfld.long 0x0 9. "WINLDEN1,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." newline bitfld.long 0x0 8. "WINLDEN0,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." bitfld.long 0x0 5. "CTRLD5,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" newline bitfld.long 0x0 4. "CTRLD4,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" bitfld.long 0x0 3. "CTRLD3,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" newline bitfld.long 0x0 2. "CTRLD2,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" bitfld.long 0x0 1. "CTRLD1,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" newline bitfld.long 0x0 0. "CTRLD0,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" line.long 0x4 "PWM_CTL1,PWM Control Register 1" bitfld.long 0x4 26. "OUTMODE4,PWM Output Mode.Each bit n controls the output mode of corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x4 25. "OUTMODE2,PWM Output Mode.Each bit n controls the output mode of corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode" newline bitfld.long 0x4 24. "OUTMODE0,PWM Output Mode.Each bit n controls the output mode of corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x4 21. "CNTMODE5,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x4 20. "CNTMODE4,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" bitfld.long 0x4 19. "CNTMODE3,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x4 18. "CNTMODE2,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" bitfld.long 0x4 17. "CNTMODE1,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x4 16. "CNTMODE0,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" bitfld.long 0x4 10.--11. "CNTTYPE5,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 6.--7. "CNTTYPE3,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 2.--3. "CNTTYPE1,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" line.long 0x8 "PWM_SYNC,PWM Synchronization Register" bitfld.long 0x8 26. "PHSDIR4,PWM Phase Direction Control.Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.." bitfld.long 0x8 25. "PHSDIR2,PWM Phase Direction Control.Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.." newline bitfld.long 0x8 24. "PHSDIR0,PWM Phase Direction Control.Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.." bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of PWM0_SYNC_IN pin is passed to the..,1: The inversed state of PWM0_SYNC_IN pin is passed.." newline bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count.The register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" newline bitfld.long 0x8 16. "SNFLTEN,PWM0_SYNC_IN Noise Filter Enable Bit" "0: Noise filter of input PWM0_SYNC_IN pin Disabled,1: Noise filter of input PWM0_SYNC_IN pin Enabled" bitfld.long 0x8 12.--13. "SINSRC4,PWM0_SYNC_IN Source Selection.Each bit n controls corresponding PWM channel n." "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?" newline bitfld.long 0x8 10.--11. "SINSRC2,PWM0_SYNC_IN Source Selection.Each bit n controls corresponding PWM channel n." "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?" bitfld.long 0x8 8.--9. "SINSRC0,PWM0_SYNC_IN Source Selection.Each bit n controls corresponding PWM channel n." "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?" newline bitfld.long 0x8 2. "PHSEN4,SYNC Phase Enable Bits.n denotes PWM channel 0 2 4 and m denotes channel 1 3 5." "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.." bitfld.long 0x8 1. "PHSEN2,SYNC Phase Enable Bits.n denotes PWM channel 0 2 4 and m denotes channel 1 3 5." "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.." newline bitfld.long 0x8 0. "PHSEN0,SYNC Phase Enable Bits.n denotes PWM channel 0 2 4 and m denotes channel 1 3 5." "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.." line.long 0xC "PWM_SWSYNC,PWM Software Control Synchronization Register" bitfld.long 0xC 2. "SWSYNC4,Software SYNC Function.Each bit n controls corresponding PWM channel n..When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1" bitfld.long 0xC 1. "SWSYNC2,Software SYNC Function.Each bit n controls corresponding PWM channel n..When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1" newline bitfld.long 0xC 0. "SWSYNC0,Software SYNC Function.Each bit n controls corresponding PWM channel n..When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1" line.long 0x10 "PWM_CLKSRC,PWM Clock Source Register" bitfld.long 0x10 16.--18. "ECLKSRC4,PWMx_CH4/5 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,?,?,?,?,?,?" bitfld.long 0x10 8.--10. "ECLKSRC2,PWMx_CH2/3 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,?,?,?,?,?,?" newline bitfld.long 0x10 0.--2. "ECLKSRC0,PWMx_CH0/1 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,?,?,?,?,?,?" line.long 0x14 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0/1" hexmask.long.word 0x14 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x18 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2/3" hexmask.long.word 0x18 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x1C "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4/5" hexmask.long.word 0x1C 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x20 "PWM_CNTEN,PWM Counter Enable Register" bitfld.long 0x20 5. "CNTEN5,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x20 4. "CNTEN4,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x20 3. "CNTEN3,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x20 2. "CNTEN2,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x20 1. "CNTEN1,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x20 0. "CNTEN0,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" line.long 0x24 "PWM_CNTCLR,PWM Clear Counter Register" bitfld.long 0x24 5. "CNTCLR5,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." bitfld.long 0x24 4. "CNTCLR4,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." newline bitfld.long 0x24 3. "CNTCLR3,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." bitfld.long 0x24 2. "CNTCLR2,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." newline bitfld.long 0x24 1. "CNTCLR1,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." bitfld.long 0x24 0. "CNTCLR0,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." line.long 0x28 "PWM_LOAD,PWM Load Register" bitfld.long 0x28 5. "LOAD5,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." bitfld.long 0x28 4. "LOAD4,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." newline bitfld.long 0x28 3. "LOAD3,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." bitfld.long 0x28 2. "LOAD2,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." newline bitfld.long 0x28 1. "LOAD1,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." bitfld.long 0x28 0. "LOAD0,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." group.long 0x30++0x17 line.long 0x0 "PWM_PERIOD0,PWM Period Register 0" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x4 "PWM_PERIOD1,PWM Period Register 1" hexmask.long.word 0x4 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x8 "PWM_PERIOD2,PWM Period Register 2" hexmask.long.word 0x8 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0xC "PWM_PERIOD3,PWM Period Register 3" hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x10 "PWM_PERIOD4,PWM Period Register 4" hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x14 "PWM_PERIOD5,PWM Period Register 5" hexmask.long.word 0x14 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." group.long 0x50++0x17 line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." group.long 0x70++0xB line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1" bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.." bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to SYS_REGLCTL register." line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3" bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.." bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to SYS_REGLCTL register." line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5" bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.." bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to SYS_REGLCTL register." group.long 0x80++0xB line.long 0x0 "PWM_PHS0_1,PWM Counter Phase Register 0/1" hexmask.long.word 0x0 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits.PHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function." line.long 0x4 "PWM_PHS2_3,PWM Counter Phase Register 2/3" hexmask.long.word 0x4 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits.PHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function." line.long 0x8 "PWM_PHS4_5,PWM Counter Phase Register 4/5" hexmask.long.word 0x8 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits.PHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function." rgroup.long 0x90++0x17 line.long 0x0 "PWM_CNT0,PWM Counter Register 0" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x4 "PWM_CNT1,PWM Counter Register 1" bitfld.long 0x4 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x4 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x8 "PWM_CNT2,PWM Counter Register 2" bitfld.long 0x8 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x8 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0xC "PWM_CNT3,PWM Counter Register 3" bitfld.long 0xC 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0xC 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x10 "PWM_CNT4,PWM Counter Register 4" bitfld.long 0x10 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x10 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x14 "PWM_CNT5,PWM Counter Register 5" bitfld.long 0x14 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x14 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." group.long 0xB0++0x2B line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0" bitfld.long 0x0 26.--27. "PRDPCTL5,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" bitfld.long 0x0 24.--25. "PRDPCTL4,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" newline bitfld.long 0x0 22.--23. "PRDPCTL3,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" bitfld.long 0x0 20.--21. "PRDPCTL2,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" newline bitfld.long 0x0 18.--19. "PRDPCTL1,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" bitfld.long 0x0 16.--17. "PRDPCTL0,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" newline bitfld.long 0x0 10.--11. "ZPCTL5,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" bitfld.long 0x0 8.--9. "ZPCTL4,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" newline bitfld.long 0x0 6.--7. "ZPCTL3,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" bitfld.long 0x0 4.--5. "ZPCTL2,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" newline bitfld.long 0x0 2.--3. "ZPCTL1,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" bitfld.long 0x0 0.--1. "ZPCTL0,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1" bitfld.long 0x4 26.--27. "CMPDCTL5,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" bitfld.long 0x4 24.--25. "CMPDCTL4,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" newline bitfld.long 0x4 22.--23. "CMPDCTL3,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" bitfld.long 0x4 20.--21. "CMPDCTL2,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" newline bitfld.long 0x4 18.--19. "CMPDCTL1,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" bitfld.long 0x4 16.--17. "CMPDCTL0,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" newline bitfld.long 0x4 10.--11. "CMPUCTL5,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" bitfld.long 0x4 8.--9. "CMPUCTL4,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" newline bitfld.long 0x4 6.--7. "CMPUCTL3,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" bitfld.long 0x4 4.--5. "CMPUCTL2,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" newline bitfld.long 0x4 2.--3. "CMPUCTL1,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" bitfld.long 0x4 0.--1. "CMPUCTL0,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register" bitfld.long 0x8 5. "MSKEN5,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." bitfld.long 0x8 4. "MSKEN4,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." newline bitfld.long 0x8 3. "MSKEN3,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." bitfld.long 0x8 2. "MSKEN2,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." newline bitfld.long 0x8 1. "MSKEN1,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." bitfld.long 0x8 0. "MSKEN0,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." line.long 0xC "PWM_MSK,PWM Mask Data Register" bitfld.long 0xC 5. "MSKDAT5,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" bitfld.long 0xC 4. "MSKDAT4,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" newline bitfld.long 0xC 3. "MSKDAT3,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" bitfld.long 0xC 2. "MSKDAT2,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" newline bitfld.long 0xC 1. "MSKDAT1,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" bitfld.long 0xC 0. "MSKDAT0,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register" bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select.For PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1..Brake..,1: Brake 1 pin source come from PWM1_BRAKE1..Brake.." bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select.For PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0..Brake..,1: Brake 0 pin source come from PWM1_BRAKE0..Brake.." newline bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: Brake pin event will be detected if PWM1_BRAKEx..,1: Brake pin event will be detected if PWM1_BRAKEx.." bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count.The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled" newline bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: Brake pin event will be detected if PWM0_BRAKEx..,1: Brake pin event will be detected if PWM0_BRAKEx.." bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count.The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled" line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register" bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup event..,1: Brake Function triggered by Core lockup event.." bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled" newline bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.." line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1" bitfld.long 0x18 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled" bitfld.long 0x18 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled" newline bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx brake..,?,?" bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect even channels..,1: PWM even channel output tri-state when PWMx..,?,?" newline bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.." bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.." newline bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3" bitfld.long 0x1C 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled" bitfld.long 0x1C 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled" newline bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx brake..,?,?" bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect even channels..,1: PWM even channel output tri-state when PWMx..,?,?" newline bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.." bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.." newline bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5" bitfld.long 0x20 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled" bitfld.long 0x20 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled" newline bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx brake..,?,?" bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect even channels..,1: PWM even channel output tri-state when PWMx..,?,?" newline bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.." bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.." newline bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register" bitfld.long 0x24 5. "PINV5,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" bitfld.long 0x24 4. "PINV4,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" newline bitfld.long 0x24 3. "PINV3,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" bitfld.long 0x24 2. "PINV2,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" newline bitfld.long 0x24 1. "PINV1,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" bitfld.long 0x24 0. "PINV0,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" line.long 0x28 "PWM_POEN,PWM Output Enable Register" bitfld.long 0x28 5. "POEN5,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" bitfld.long 0x28 4. "POEN4,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" newline bitfld.long 0x28 3. "POEN3,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" bitfld.long 0x28 2. "POEN2,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" newline bitfld.long 0x28 1. "POEN1,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" bitfld.long 0x28 0. "POEN0,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" wgroup.long 0xDC++0x3 line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register" bitfld.long 0x0 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" bitfld.long 0x0 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" newline bitfld.long 0x0 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" bitfld.long 0x0 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" newline bitfld.long 0x0 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" bitfld.long 0x0 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" group.long 0xE0++0x13 line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0" bitfld.long 0x0 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x0 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x0 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x0 23. "IFAIEN4_5,PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled" bitfld.long 0x0 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x0 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x0 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x0 15. "IFAIEN2_3,PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled" newline bitfld.long 0x0 13. "PIEN5,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 11. "PIEN3,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 9. "PIEN1,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 7. "IFAIEN0_1,PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled" bitfld.long 0x0 5. "ZIEN5,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x0 3. "ZIEN3,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x0 1. "ZIEN1,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1" bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.." bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.." newline bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.." bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled" newline bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled" bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled" line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0" bitfld.long 0x8 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" bitfld.long 0x8 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" newline bitfld.long 0x8 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" bitfld.long 0x8 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" newline bitfld.long 0x8 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" bitfld.long 0x8 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" newline bitfld.long 0x8 23. "IFAIF4_5,PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Flag.Flag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 21. "CMPUIF5,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" newline bitfld.long 0x8 20. "CMPUIF4,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" bitfld.long 0x8 19. "CMPUIF3,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" newline bitfld.long 0x8 18. "CMPUIF2,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" bitfld.long 0x8 17. "CMPUIF1,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" newline bitfld.long 0x8 16. "CMPUIF0,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" bitfld.long 0x8 15. "IFAIF2_3,PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Flag.Flag is set by hardware when condition match IFSEL2_3 bits in PWM_IFA register software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 13. "PIF5,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" newline bitfld.long 0x8 11. "PIF3,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" newline bitfld.long 0x8 9. "PIF1,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" newline bitfld.long 0x8 7. "IFAIF0_1,PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Flag.Flag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 5. "ZIF5,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 3. "ZIF3,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 1. "ZIF1,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1" rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." newline rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." newline rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." newline bitfld.long 0xC 21. "BRKESTS5,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." bitfld.long 0xC 20. "BRKESTS4,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." newline bitfld.long 0xC 19. "BRKESTS3,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." bitfld.long 0xC 18. "BRKESTS2,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." newline bitfld.long 0xC 17. "BRKESTS1,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." bitfld.long 0xC 16. "BRKESTS0,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." newline bitfld.long 0xC 8. "BRKLIFn,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." bitfld.long 0xC 5. "BRKEIF5,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0xC 4. "BRKEIF4,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0xC 3. "BRKEIF3,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0xC 2. "BRKEIF2,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0xC 1. "BRKEIF1,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0xC 0. "BRKEIF0,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." line.long 0x10 "PWM_IFA,PWM Interrupt Flag Accumulator Register" bitfld.long 0x10 23. "IFAEN4_5,PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 4/5 interrupt flag accumulator..,1: PWM Channel 4/5 interrupt flag accumulator Enabled" bitfld.long 0x10 20.--22. "IFSEL4_5,PWM Channel 4/5 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 4,1: CNT equal to PERIOD in channel 4,?,?,?,?,?,?" newline hexmask.long.byte 0x10 16.--19. 1. "IFCNT4_5,PWM Channel 4/5 Interrupt Flag Counter.The register sets the count number which defines how many times of PWM Channel 4/5 period occurs to set IFAIF4_5 bit to request the PWM period interrupt. .PWM flag will be set in every IFCNT4_5[3:0] times.." bitfld.long 0x10 15. "IFAEN2_3,PWM Channel 2/3 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 2/3 interrupt flag accumulator..,1: PWM Channel 2/3 interrupt flag accumulator Enabled" newline bitfld.long 0x10 12.--14. "IFSEL2_3,PWM Channel 2/3 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 2,1: CNT equal to PERIOD in channel 2,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--11. 1. "IFCNT2_3,PWM Channel 2/3 Interrupt Flag Counter.The register sets the count number which defines how many times of PWM Channel 2/3 period occurs to set IFAIF2_3 bit to request the PWM period interrupt. .PWM flag will be set in every IFCNT2_3[3:0] times.." newline bitfld.long 0x10 7. "IFAEN0_1,PWM Channel 0/1 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 0/1 interrupt flag accumulator..,1: PWM Channel 0/1 interrupt flag accumulator Enabled" bitfld.long 0x10 4.--6. "IFSEL0_1,PWM Channel 0/1 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 0,1: CNT equal to PERIOD in channel 0,?,?,?,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "IFCNT0_1,PWM Channel 0/1 Interrupt Flag Counter.The register sets the count number which defines how many times of PWM Channel 0/1 period occurs to set IFAIF0_1 bit to request the PWM period interrupt. .PWM flag will be set in every IFCNT0_1 [3:0].." group.long 0xF8++0x13 line.long 0x0 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,PWM_CH3 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger ADC Source Select" newline bitfld.long 0x0 23. "TRGEN2,PWM_CH2 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger ADC Source Select" newline bitfld.long 0x0 15. "TRGEN1,PWM_CH1 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger ADC Source Select" newline bitfld.long 0x0 7. "TRGEN0,PWM_CH0 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger ADC Source Select" line.long 0x4 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,PWM_CH5 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger ADC Source Select" newline bitfld.long 0x4 7. "TRGEN4,PWM_CH4 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger ADC Source Select" line.long 0x8 "PWM_FTCMPDAT0_1,PWM Free Trigger Compare Register 0/1" hexmask.long.word 0x8 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register" line.long 0xC "PWM_FTCMPDAT2_3,PWM Free Trigger Compare Register 2/3" hexmask.long.word 0xC 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register" line.long 0x10 "PWM_FTCMPDAT4_5,PWM Free Trigger Compare Register 4/5" hexmask.long.word 0x10 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register" group.long 0x110++0x3 line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register" bitfld.long 0x0 8. "SSRC,PWM Synchronous Start Source Select Bit" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1" bitfld.long 0x0 5. "SSEN5,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x0 3. "SSEN3,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x0 1. "SSEN1,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" wgroup.long 0x114++0x3 line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register" bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only).PMW counter synchronous enable function is used to make selected PWM channels (PWMx_CHn) start counting at the same time..Writing this bit to 1 will also set the counter enable bit (CNTENn n.." "0,1" group.long 0x118++0xB line.long 0x0 "PWM_LEBCTL,PWM Leading Edge Blanking Control Register" bitfld.long 0x0 16.--17. "TRGTYPE,PWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source rising..,1: When detect leading edge blanking source falling..,?,?" bitfld.long 0x0 10. "SRCEN4,PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit" "0: PWM Leading Edge Blanking Source from PWMx_CH4..,1: PWM Leading Edge Blanking Source from PWMx_CH4.." newline bitfld.long 0x0 9. "SRCEN2,PWM Leading Edge Blanking Source From PWMx_CH2 Enable Bit" "0: PWM Leading Edge Blanking Source from PWMx_CH2..,1: PWM Leading Edge Blanking Source from PWMx_CH2.." bitfld.long 0x0 8. "SRCEN0,PWM Leading Edge Blanking Source From PWMx_CH0 Enable Bit" "0: PWM Leading Edge Blanking Source from PWMx_CH0..,1: PWM Leading Edge Blanking Source from PWMx_CH0.." newline bitfld.long 0x0 0. "LEBEN,PWM Leading Edge Blanking Enable Bit" "0: PWM Leading Edge Blanking Disabled,1: PWM Leading Edge Blanking Enabled" line.long 0x4 "PWM_LEBCNT,PWM Leading Edge Blanking Counter Register" hexmask.long.word 0x4 0.--8. 1. "LEBCNT,PWM Leading Edge Blanking Counter.This counter value decides leading edge blanking window size." line.long 0x8 "PWM_STATUS,PWM Status Register" bitfld.long 0x8 21. "ADCTRGF5,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." bitfld.long 0x8 20. "ADCTRGF4,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." newline bitfld.long 0x8 19. "ADCTRGF3,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." bitfld.long 0x8 18. "ADCTRGF2,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." newline bitfld.long 0x8 17. "ADCTRGF1,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." bitfld.long 0x8 16. "ADCTRGF0,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." newline bitfld.long 0x8 10. "SYNCINF4,Input Synchronization Latched Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software.." bitfld.long 0x8 9. "SYNCINF2,Input Synchronization Latched Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software.." newline bitfld.long 0x8 8. "SYNCINF0,Input Synchronization Latched Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software.." bitfld.long 0x8 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." newline bitfld.long 0x8 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." bitfld.long 0x8 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." newline bitfld.long 0x8 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." bitfld.long 0x8 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." newline bitfld.long 0x8 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." group.long 0x200++0x7 line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register" bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." newline bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." newline bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register" bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." newline bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." newline bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." newline bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." newline bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." newline bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." rgroup.long 0x208++0x33 line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register" bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." group.long 0x23C++0x3 line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register" bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5" bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order .Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3." "0: PWM_FCAPDAT4/5 register is the first captured..,1: PWM_RCAPDAT4/5 register is the first captured.." newline bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT4/5 register,?,?" bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.." newline bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3" bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order .Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to 0x3." "0: PWM_FCAPDAT2/3 register is the first captured..,1: PWM_RCAPDAT2/3 register is the first captured.." newline bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT2/3 register,?,?" bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.." newline bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1" bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order .Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3." "0: PWM_FCAPDAT0/1 register is the first captured..,1: PWM_RCAPDAT0/1 register is the first captured.." newline bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT0/1 register,?,?" bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.." rgroup.long 0x240++0xB line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 0/1 PDMA Register" hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only).This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA." line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 2/3 PDMA Register" hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only).This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA." line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 4/5 PDMA Register" hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only).This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA." group.long 0x250++0x7 line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register" bitfld.long 0x0 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x0 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x0 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x0 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x0 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x0 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x0 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x0 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" newline bitfld.long 0x0 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x0 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" newline bitfld.long 0x0 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x0 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register" bitfld.long 0x4 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x4 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x4 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x4 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x4 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x4 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x4 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x4 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x4 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x4 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x4 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x4 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." rgroup.long 0x304++0x47 line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x4 "PWM_PBUF1,PWM PERIOD1 Buffer" hexmask.long.word 0x4 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x8 "PWM_PBUF2,PWM PERIOD2 Buffer" hexmask.long.word 0x8 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0xC "PWM_PBUF3,PWM PERIOD3 Buffer" hexmask.long.word 0xC 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x10 "PWM_PBUF4,PWM PERIOD4 Buffer" hexmask.long.word 0x10 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x14 "PWM_PBUF5,PWM PERIOD5 Buffer" hexmask.long.word 0x14 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x18 "PWM_CMPBUF0,PWM CMPDAT0 Buffer" hexmask.long.word 0x18 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x1C "PWM_CMPBUF1,PWM CMPDAT1 Buffer" hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x20 "PWM_CMPBUF2,PWM CMPDAT2 Buffer" hexmask.long.word 0x20 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x24 "PWM_CMPBUF3,PWM CMPDAT3 Buffer" hexmask.long.word 0x24 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x28 "PWM_CMPBUF4,PWM CMPDAT4 Buffer" hexmask.long.word 0x28 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x2C "PWM_CMPBUF5,PWM CMPDAT5 Buffer" hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x30 "PWM_CPSCBUF0_1,PWM CLKPSC0_1 Buffer" hexmask.long.word 0x30 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer.Used as PWM counter clock pre-scare active register." line.long 0x34 "PWM_CPSCBUF2_3,PWM CLKPSC2_3 Buffer" hexmask.long.word 0x34 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer.Used as PWM counter clock pre-scare active register." line.long 0x38 "PWM_CPSCBUF4_5,PWM CLKPSC4_5 Buffer" hexmask.long.word 0x38 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer.Used as PWM counter clock pre-scare active register." line.long 0x3C "PWM_FTCBUF0_1,PWM FTCMPDAT0_1 Buffer" hexmask.long.word 0x3C 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only).Used as FTCMPDAT active register." line.long 0x40 "PWM_FTCBUF2_3,PWM FTCMPDAT2_3 Buffer" hexmask.long.word 0x40 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only).Used as FTCMPDAT active register." line.long 0x44 "PWM_FTCBUF4_5,PWM FTCMPDAT4_5 Buffer" hexmask.long.word 0x44 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only).Used as FTCMPDAT active register." group.long 0x34C++0x3 line.long 0x0 "PWM_FTCI,PWM FTCMPDAT Indicator Register" bitfld.long 0x0 10. "FTCMD4,PWM FTCMPDAT Down Indicator.Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" bitfld.long 0x0 9. "FTCMD2,PWM FTCMPDAT Down Indicator.Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" newline bitfld.long 0x0 8. "FTCMD0,PWM FTCMPDAT Down Indicator.Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" bitfld.long 0x0 2. "FTCMU4,PWM FTCMPDAT Up Indicator.Indicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" newline bitfld.long 0x0 1. "FTCMU2,PWM FTCMPDAT Up Indicator.Indicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" bitfld.long 0x0 0. "FTCMU0,PWM FTCMPDAT Up Indicator.Indicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" tree.end tree "PWM1" base ad:0x40140000 group.long 0x0++0x2B line.long 0x0 "PWM_CTL0,PWM Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect).PWM pin will keep output no matter ICE debug mode acknowledged or not..Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. .Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each PWM channel are..,1: Unify the PWMx_CH2 and PWMx_CH4 to output the.." bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." newline bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." newline bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." newline bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits.Each bit n controls the corresponding PWM channel n..Note: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid." "0: PERIODn register will load to PBUFn register at..,1: PERIODn/CMPDATn registers will load to PBUFn and.." bitfld.long 0x0 13. "WINLDEN5,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." newline bitfld.long 0x0 12. "WINLDEN4,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." bitfld.long 0x0 11. "WINLDEN3,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." newline bitfld.long 0x0 10. "WINLDEN2,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." bitfld.long 0x0 9. "WINLDEN1,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." newline bitfld.long 0x0 8. "WINLDEN0,Window Load Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PERIODn register will load to PBUFn register at..,1: PERIODn register will load to PBUFn and CMPDATn.." bitfld.long 0x0 5. "CTRLD5,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" newline bitfld.long 0x0 4. "CTRLD4,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" bitfld.long 0x0 3. "CTRLD3,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" newline bitfld.long 0x0 2. "CTRLD2,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" bitfld.long 0x0 1. "CTRLD1,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" newline bitfld.long 0x0 0. "CTRLD0,Center Re-load.Each bit n controls the corresponding PWM channel n..In up-down counter type PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a.." "0,1" line.long 0x4 "PWM_CTL1,PWM Control Register 1" bitfld.long 0x4 26. "OUTMODE4,PWM Output Mode.Each bit n controls the output mode of corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x4 25. "OUTMODE2,PWM Output Mode.Each bit n controls the output mode of corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode" newline bitfld.long 0x4 24. "OUTMODE0,PWM Output Mode.Each bit n controls the output mode of corresponding PWM channel n..Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x4 21. "CNTMODE5,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x4 20. "CNTMODE4,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" bitfld.long 0x4 19. "CNTMODE3,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x4 18. "CNTMODE2,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" bitfld.long 0x4 17. "CNTMODE1,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x4 16. "CNTMODE0,PWM Counter Mode.Each bit n controls the corresponding PWM channel n." "0: Auto-reload mode,1: One-shot mode" bitfld.long 0x4 10.--11. "CNTTYPE5,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 6.--7. "CNTTYPE3,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 2.--3. "CNTTYPE1,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type.Each bit n controls corresponding PWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" line.long 0x8 "PWM_SYNC,PWM Synchronization Register" bitfld.long 0x8 26. "PHSDIR4,PWM Phase Direction Control.Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.." bitfld.long 0x8 25. "PHSDIR2,PWM Phase Direction Control.Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.." newline bitfld.long 0x8 24. "PHSDIR0,PWM Phase Direction Control.Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.." bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of PWM0_SYNC_IN pin is passed to the..,1: The inversed state of PWM0_SYNC_IN pin is passed.." newline bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count.The register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" newline bitfld.long 0x8 16. "SNFLTEN,PWM0_SYNC_IN Noise Filter Enable Bit" "0: Noise filter of input PWM0_SYNC_IN pin Disabled,1: Noise filter of input PWM0_SYNC_IN pin Enabled" bitfld.long 0x8 12.--13. "SINSRC4,PWM0_SYNC_IN Source Selection.Each bit n controls corresponding PWM channel n." "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?" newline bitfld.long 0x8 10.--11. "SINSRC2,PWM0_SYNC_IN Source Selection.Each bit n controls corresponding PWM channel n." "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?" bitfld.long 0x8 8.--9. "SINSRC0,PWM0_SYNC_IN Source Selection.Each bit n controls corresponding PWM channel n." "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?" newline bitfld.long 0x8 2. "PHSEN4,SYNC Phase Enable Bits.n denotes PWM channel 0 2 4 and m denotes channel 1 3 5." "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.." bitfld.long 0x8 1. "PHSEN2,SYNC Phase Enable Bits.n denotes PWM channel 0 2 4 and m denotes channel 1 3 5." "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.." newline bitfld.long 0x8 0. "PHSEN0,SYNC Phase Enable Bits.n denotes PWM channel 0 2 4 and m denotes channel 1 3 5." "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.." line.long 0xC "PWM_SWSYNC,PWM Software Control Synchronization Register" bitfld.long 0xC 2. "SWSYNC4,Software SYNC Function.Each bit n controls corresponding PWM channel n..When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1" bitfld.long 0xC 1. "SWSYNC2,Software SYNC Function.Each bit n controls corresponding PWM channel n..When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1" newline bitfld.long 0xC 0. "SWSYNC0,Software SYNC Function.Each bit n controls corresponding PWM channel n..When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1" line.long 0x10 "PWM_CLKSRC,PWM Clock Source Register" bitfld.long 0x10 16.--18. "ECLKSRC4,PWMx_CH4/5 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,?,?,?,?,?,?" bitfld.long 0x10 8.--10. "ECLKSRC2,PWMx_CH2/3 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,?,?,?,?,?,?" newline bitfld.long 0x10 0.--2. "ECLKSRC0,PWMx_CH0/1 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,?,?,?,?,?,?" line.long 0x14 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0/1" hexmask.long.word 0x14 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x18 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2/3" hexmask.long.word 0x18 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x1C "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4/5" hexmask.long.word 0x1C 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)." line.long 0x20 "PWM_CNTEN,PWM Counter Enable Register" bitfld.long 0x20 5. "CNTEN5,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x20 4. "CNTEN4,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x20 3. "CNTEN3,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x20 2. "CNTEN2,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x20 1. "CNTEN1,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x20 0. "CNTEN0,PWM Counter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" line.long 0x24 "PWM_CNTCLR,PWM Clear Counter Register" bitfld.long 0x24 5. "CNTCLR5,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." bitfld.long 0x24 4. "CNTCLR4,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." newline bitfld.long 0x24 3. "CNTCLR3,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." bitfld.long 0x24 2. "CNTCLR2,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." newline bitfld.long 0x24 1. "CNTCLR1,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." bitfld.long 0x24 0. "CNTCLR0,Clear PWM Counter Control Bit.It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n." "0: No effect,1: Clear 16-bit PWM counter to.." line.long 0x28 "PWM_LOAD,PWM Load Register" bitfld.long 0x28 5. "LOAD5,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." bitfld.long 0x28 4. "LOAD4,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." newline bitfld.long 0x28 3. "LOAD3,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." bitfld.long 0x28 2. "LOAD2,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." newline bitfld.long 0x28 1. "LOAD1,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." bitfld.long 0x28 0. "LOAD0,Re-load PWM Comparator Register (CMPDAT) Control Bit.This bit is software write and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n..Write Operation:" "0: No effect..No load window is set,1: Set load window of window loading mode..Load.." group.long 0x30++0x17 line.long 0x0 "PWM_PERIOD0,PWM Period Register 0" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x4 "PWM_PERIOD1,PWM Period Register 1" hexmask.long.word 0x4 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x8 "PWM_PERIOD2,PWM Period Register 2" hexmask.long.word 0x8 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0xC "PWM_PERIOD3,PWM Period Register 3" hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x10 "PWM_PERIOD4,PWM Period Register 4" hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." line.long 0x14 "PWM_PERIOD5,PWM Period Register 5" hexmask.long.word 0x14 0.--15. 1. "PERIOD,PWM Period Register.Up-Count mode: .In this mode PWM counter counts from 0 to PERIOD and restarts from 0." group.long 0x50++0x17 line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.CMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC..In independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point..In complementary mode .." group.long 0x70++0xB line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1" bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.." bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to SYS_REGLCTL register." line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3" bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.." bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to SYS_REGLCTL register." line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5" bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.." bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect).Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following formula: .Note: This register is write protected. Refer to SYS_REGLCTL register." group.long 0x80++0xB line.long 0x0 "PWM_PHS0_1,PWM Counter Phase Register 0/1" hexmask.long.word 0x0 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits.PHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function." line.long 0x4 "PWM_PHS2_3,PWM Counter Phase Register 2/3" hexmask.long.word 0x4 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits.PHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function." line.long 0x8 "PWM_PHS4_5,PWM Counter Phase Register 4/5" hexmask.long.word 0x8 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits.PHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function." rgroup.long 0x90++0x17 line.long 0x0 "PWM_CNT0,PWM Counter Register 0" bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x4 "PWM_CNT1,PWM Counter Register 1" bitfld.long 0x4 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x4 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x8 "PWM_CNT2,PWM Counter Register 2" bitfld.long 0x8 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x8 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0xC "PWM_CNT3,PWM Counter Register 3" bitfld.long 0xC 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0xC 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x10 "PWM_CNT4,PWM Counter Register 4" bitfld.long 0x10 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x10 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." line.long 0x14 "PWM_CNT5,PWM Counter Register 5" bitfld.long 0x14 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x14 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only).User can monitor CNT to know the current value in 16-bit period counter." group.long 0xB0++0x2B line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0" bitfld.long 0x0 26.--27. "PRDPCTL5,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" bitfld.long 0x0 24.--25. "PRDPCTL4,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" newline bitfld.long 0x0 22.--23. "PRDPCTL3,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" bitfld.long 0x0 20.--21. "PRDPCTL2,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" newline bitfld.long 0x0 18.--19. "PRDPCTL1,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" bitfld.long 0x0 16.--17. "PRDPCTL0,PWM Period (Center) Point Control.PWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n..Note: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?" newline bitfld.long 0x0 10.--11. "ZPCTL5,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" bitfld.long 0x0 8.--9. "ZPCTL4,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" newline bitfld.long 0x0 6.--7. "ZPCTL3,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" bitfld.long 0x0 4.--5. "ZPCTL2,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" newline bitfld.long 0x0 2.--3. "ZPCTL1,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" bitfld.long 0x0 0.--1. "ZPCTL0,PWM Zero Point Control.PWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n." "0: Do nothing,1: PWM zero point output Low,?,?" line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1" bitfld.long 0x4 26.--27. "CMPDCTL5,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" bitfld.long 0x4 24.--25. "CMPDCTL4,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" newline bitfld.long 0x4 22.--23. "CMPDCTL3,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" bitfld.long 0x4 20.--21. "CMPDCTL2,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" newline bitfld.long 0x4 18.--19. "CMPDCTL1,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" bitfld.long 0x4 16.--17. "CMPDCTL0,PWM Compare Down Point Control.PWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?" newline bitfld.long 0x4 10.--11. "CMPUCTL5,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" bitfld.long 0x4 8.--9. "CMPUCTL4,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" newline bitfld.long 0x4 6.--7. "CMPUCTL3,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" bitfld.long 0x4 4.--5. "CMPUCTL2,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" newline bitfld.long 0x4 2.--3. "CMPUCTL1,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" bitfld.long 0x4 0.--1. "CMPUCTL0,PWM Compare Up Point Control.PWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?" line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register" bitfld.long 0x8 5. "MSKEN5,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." bitfld.long 0x8 4. "MSKEN4,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." newline bitfld.long 0x8 3. "MSKEN3,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." bitfld.long 0x8 2. "MSKEN2,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." newline bitfld.long 0x8 1. "MSKEN1,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." bitfld.long 0x8 0. "MSKEN0,PWM Mask Enable Bits.The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.." line.long 0xC "PWM_MSK,PWM Mask Data Register" bitfld.long 0xC 5. "MSKDAT5,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" bitfld.long 0xC 4. "MSKDAT4,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" newline bitfld.long 0xC 3. "MSKDAT3,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" bitfld.long 0xC 2. "MSKDAT2,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" newline bitfld.long 0xC 1. "MSKDAT1,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" bitfld.long 0xC 0. "MSKDAT0,PWM Mask Data Bit.This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn" line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register" bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select.For PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1..Brake..,1: Brake 1 pin source come from PWM1_BRAKE1..Brake.." bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select.For PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0..Brake..,1: Brake 0 pin source come from PWM1_BRAKE0..Brake.." newline bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: Brake pin event will be detected if PWM1_BRAKEx..,1: Brake pin event will be detected if PWM1_BRAKEx.." bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count.The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled" newline bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: Brake pin event will be detected if PWM0_BRAKEx..,1: Brake pin event will be detected if PWM0_BRAKEx.." bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count.The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled" line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register" bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup event..,1: Brake Function triggered by Core lockup event.." bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled" newline bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.." line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1" bitfld.long 0x18 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled" bitfld.long 0x18 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled" newline bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx brake..,?,?" bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect even channels..,1: PWM even channel output tri-state when PWMx..,?,?" newline bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.." bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.." newline bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3" bitfld.long 0x1C 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled" bitfld.long 0x1C 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled" newline bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx brake..,?,?" bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect even channels..,1: PWM even channel output tri-state when PWMx..,?,?" newline bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.." bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.." newline bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5" bitfld.long 0x20 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled" bitfld.long 0x20 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled" newline bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx brake..,?,?" bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx brake event will not affect even channels..,1: PWM even channel output tri-state when PWMx..,?,?" newline bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.." bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.." newline bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register" bitfld.long 0x24 5. "PINV5,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" bitfld.long 0x24 4. "PINV4,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" newline bitfld.long 0x24 3. "PINV3,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" bitfld.long 0x24 2. "PINV2,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" newline bitfld.long 0x24 1. "PINV1,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" bitfld.long 0x24 0. "PINV0,PWM PIN Polar Inverse Control.The register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled" line.long 0x28 "PWM_POEN,PWM Output Enable Register" bitfld.long 0x28 5. "POEN5,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" bitfld.long 0x28 4. "POEN4,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" newline bitfld.long 0x28 3. "POEN3,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" bitfld.long 0x28 2. "POEN2,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" newline bitfld.long 0x28 1. "POEN1,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" bitfld.long 0x28 0. "POEN0,PWMx_CHn Pin Output Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode" wgroup.long 0xDC++0x3 line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register" bitfld.long 0x0 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" bitfld.long 0x0 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" newline bitfld.long 0x0 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" bitfld.long 0x0 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" newline bitfld.long 0x0 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" bitfld.long 0x0 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect).Write 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n..Note: This register is write.." "0,1" group.long 0xE0++0x13 line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0" bitfld.long 0x0 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x0 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x0 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x0 23. "IFAIEN4_5,PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled" bitfld.long 0x0 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x0 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x0 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x0 15. "IFAIEN2_3,PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled" newline bitfld.long 0x0 13. "PIEN5,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 11. "PIEN3,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 9. "PIEN1,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note1: When up-down counter type period point means center point..Note2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x0 7. "IFAIEN0_1,PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled" bitfld.long 0x0 5. "ZIEN5,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x0 3. "ZIEN3,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x0 1. "ZIEN1,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1" bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.." bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.." newline bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.." bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled" newline bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled" bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled" line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0" bitfld.long 0x8 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" bitfld.long 0x8 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" newline bitfld.long 0x8 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" bitfld.long 0x8 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" newline bitfld.long 0x8 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" bitfld.long 0x8 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag.Flag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP.." "0,1" newline bitfld.long 0x8 23. "IFAIF4_5,PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Flag.Flag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 21. "CMPUIF5,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" newline bitfld.long 0x8 20. "CMPUIF4,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" bitfld.long 0x8 19. "CMPUIF3,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" newline bitfld.long 0x8 18. "CMPUIF2,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" bitfld.long 0x8 17. "CMPUIF1,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" newline bitfld.long 0x8 16. "CMPUIF0,PWM Compare Up Count Interrupt Flag.Flag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n..Note1: If CMP equal.." "0,1" bitfld.long 0x8 15. "IFAIF2_3,PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Flag.Flag is set by hardware when condition match IFSEL2_3 bits in PWM_IFA register software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 13. "PIF5,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" newline bitfld.long 0x8 11. "PIF3,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" newline bitfld.long 0x8 9. "PIF1,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag.This bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n." "0,1" newline bitfld.long 0x8 7. "IFAIF0_1,PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Flag.Flag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 5. "ZIF5,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 3. "ZIF3,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 1. "ZIF1,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag.Each bit n controls the corresponding PWM channel n..This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero." "0,1" line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1" rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." newline rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." newline rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel n Level-detect Brake Status (Read Only).Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.." newline bitfld.long 0xC 21. "BRKESTS5,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." bitfld.long 0xC 20. "BRKESTS4,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." newline bitfld.long 0xC 19. "BRKESTS3,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." bitfld.long 0xC 18. "BRKESTS2,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." newline bitfld.long 0xC 17. "BRKESTS1,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." bitfld.long 0xC 16. "BRKESTS0,PWM Channel n Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.." newline bitfld.long 0xC 8. "BRKLIFn,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." bitfld.long 0xC 5. "BRKEIF5,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0xC 4. "BRKEIF4,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0xC 3. "BRKEIF3,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0xC 2. "BRKEIF2,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0xC 1. "BRKEIF1,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0xC 0. "BRKEIF0,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." line.long 0x10 "PWM_IFA,PWM Interrupt Flag Accumulator Register" bitfld.long 0x10 23. "IFAEN4_5,PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 4/5 interrupt flag accumulator..,1: PWM Channel 4/5 interrupt flag accumulator Enabled" bitfld.long 0x10 20.--22. "IFSEL4_5,PWM Channel 4/5 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 4,1: CNT equal to PERIOD in channel 4,?,?,?,?,?,?" newline hexmask.long.byte 0x10 16.--19. 1. "IFCNT4_5,PWM Channel 4/5 Interrupt Flag Counter.The register sets the count number which defines how many times of PWM Channel 4/5 period occurs to set IFAIF4_5 bit to request the PWM period interrupt. .PWM flag will be set in every IFCNT4_5[3:0] times.." bitfld.long 0x10 15. "IFAEN2_3,PWM Channel 2/3 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 2/3 interrupt flag accumulator..,1: PWM Channel 2/3 interrupt flag accumulator Enabled" newline bitfld.long 0x10 12.--14. "IFSEL2_3,PWM Channel 2/3 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 2,1: CNT equal to PERIOD in channel 2,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--11. 1. "IFCNT2_3,PWM Channel 2/3 Interrupt Flag Counter.The register sets the count number which defines how many times of PWM Channel 2/3 period occurs to set IFAIF2_3 bit to request the PWM period interrupt. .PWM flag will be set in every IFCNT2_3[3:0] times.." newline bitfld.long 0x10 7. "IFAEN0_1,PWM Channel 0/1 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 0/1 interrupt flag accumulator..,1: PWM Channel 0/1 interrupt flag accumulator Enabled" bitfld.long 0x10 4.--6. "IFSEL0_1,PWM Channel 0/1 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 0,1: CNT equal to PERIOD in channel 0,?,?,?,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "IFCNT0_1,PWM Channel 0/1 Interrupt Flag Counter.The register sets the count number which defines how many times of PWM Channel 0/1 period occurs to set IFAIF0_1 bit to request the PWM period interrupt. .PWM flag will be set in every IFCNT0_1 [3:0].." group.long 0xF8++0x13 line.long 0x0 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,PWM_CH3 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger ADC Source Select" newline bitfld.long 0x0 23. "TRGEN2,PWM_CH2 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger ADC Source Select" newline bitfld.long 0x0 15. "TRGEN1,PWM_CH1 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger ADC Source Select" newline bitfld.long 0x0 7. "TRGEN0,PWM_CH0 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger ADC Source Select" line.long 0x4 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,PWM_CH5 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger ADC Source Select" newline bitfld.long 0x4 7. "TRGEN4,PWM_CH4 Trigger ADC enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger ADC Source Select" line.long 0x8 "PWM_FTCMPDAT0_1,PWM Free Trigger Compare Register 0/1" hexmask.long.word 0x8 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register" line.long 0xC "PWM_FTCMPDAT2_3,PWM Free Trigger Compare Register 2/3" hexmask.long.word 0xC 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register" line.long 0x10 "PWM_FTCMPDAT4_5,PWM Free Trigger Compare Register 4/5" hexmask.long.word 0x10 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register" group.long 0x110++0x3 line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register" bitfld.long 0x0 8. "SSRC,PWM Synchronous Start Source Select Bit" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1" bitfld.long 0x0 5. "SSEN5,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x0 3. "SSEN3,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x0 1. "SSEN1,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable Bits.When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" wgroup.long 0x114++0x3 line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register" bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only).PMW counter synchronous enable function is used to make selected PWM channels (PWMx_CHn) start counting at the same time..Writing this bit to 1 will also set the counter enable bit (CNTENn n.." "0,1" group.long 0x118++0xB line.long 0x0 "PWM_LEBCTL,PWM Leading Edge Blanking Control Register" bitfld.long 0x0 16.--17. "TRGTYPE,PWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source rising..,1: When detect leading edge blanking source falling..,?,?" bitfld.long 0x0 10. "SRCEN4,PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit" "0: PWM Leading Edge Blanking Source from PWMx_CH4..,1: PWM Leading Edge Blanking Source from PWMx_CH4.." newline bitfld.long 0x0 9. "SRCEN2,PWM Leading Edge Blanking Source From PWMx_CH2 Enable Bit" "0: PWM Leading Edge Blanking Source from PWMx_CH2..,1: PWM Leading Edge Blanking Source from PWMx_CH2.." bitfld.long 0x0 8. "SRCEN0,PWM Leading Edge Blanking Source From PWMx_CH0 Enable Bit" "0: PWM Leading Edge Blanking Source from PWMx_CH0..,1: PWM Leading Edge Blanking Source from PWMx_CH0.." newline bitfld.long 0x0 0. "LEBEN,PWM Leading Edge Blanking Enable Bit" "0: PWM Leading Edge Blanking Disabled,1: PWM Leading Edge Blanking Enabled" line.long 0x4 "PWM_LEBCNT,PWM Leading Edge Blanking Counter Register" hexmask.long.word 0x4 0.--8. 1. "LEBCNT,PWM Leading Edge Blanking Counter.This counter value decides leading edge blanking window size." line.long 0x8 "PWM_STATUS,PWM Status Register" bitfld.long 0x8 21. "ADCTRGF5,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." bitfld.long 0x8 20. "ADCTRGF4,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." newline bitfld.long 0x8 19. "ADCTRGF3,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." bitfld.long 0x8 18. "ADCTRGF2,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." newline bitfld.long 0x8 17. "ADCTRGF1,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." bitfld.long 0x8 16. "ADCTRGF0,ADC Start of Conversion Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.." newline bitfld.long 0x8 10. "SYNCINF4,Input Synchronization Latched Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software.." bitfld.long 0x8 9. "SYNCINF2,Input Synchronization Latched Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software.." newline bitfld.long 0x8 8. "SYNCINF0,Input Synchronization Latched Flag.Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software.." bitfld.long 0x8 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." newline bitfld.long 0x8 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." bitfld.long 0x8 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." newline bitfld.long 0x8 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." bitfld.long 0x8 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." newline bitfld.long 0x8 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag.Each bit n controls the corresponding PWM channel n." "0: indicates the time-base counter(PWM_CNTn[15:0])..,1: indicates the time-base counter(PWM_CNTn[15:0]).." group.long 0x200++0x7 line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register" bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." newline bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." newline bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits.Each bit n controls the corresponding PWM channel n." "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.." line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register" bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." newline bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." newline bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.." newline bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." newline bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." newline bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits.Each bit n controls the corresponding PWM channel n." "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.." rgroup.long 0x208++0x33 line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register" bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" newline bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only).This flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n..Note: This bit will be.." "0,1" line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only).When rising capture condition happened the PWM counter value will be saved in this register." line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only).When falling capture condition happened the PWM counter value will be saved in this register." group.long 0x23C++0x3 line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register" bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5" bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order .Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3." "0: PWM_FCAPDAT4/5 register is the first captured..,1: PWM_RCAPDAT4/5 register is the first captured.." newline bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT4/5 register,?,?" bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.." newline bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3" bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order .Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to 0x3." "0: PWM_FCAPDAT2/3 register is the first captured..,1: PWM_RCAPDAT2/3 register is the first captured.." newline bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT2/3 register,?,?" bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.." newline bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1" bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order .Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3." "0: PWM_FCAPDAT0/1 register is the first captured..,1: PWM_RCAPDAT0/1 register is the first captured.." newline bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT0/1 register,?,?" bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.." rgroup.long 0x240++0xB line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 0/1 PDMA Register" hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only).This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA." line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 2/3 PDMA Register" hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only).This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA." line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 4/5 PDMA Register" hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only).This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA." group.long 0x250++0x7 line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register" bitfld.long 0x0 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x0 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x0 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x0 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x0 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x0 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled." "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x0 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x0 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" newline bitfld.long 0x0 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x0 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" newline bitfld.long 0x0 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x0 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits.Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled." "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register" bitfld.long 0x4 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x4 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x4 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x4 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x4 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x4 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x4 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x4 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x4 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x4 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x4 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x4 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag.This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n..Note: When Capture with PDMA operating corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer.." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." rgroup.long 0x304++0x47 line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x4 "PWM_PBUF1,PWM PERIOD1 Buffer" hexmask.long.word 0x4 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x8 "PWM_PBUF2,PWM PERIOD2 Buffer" hexmask.long.word 0x8 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0xC "PWM_PBUF3,PWM PERIOD3 Buffer" hexmask.long.word 0xC 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x10 "PWM_PBUF4,PWM PERIOD4 Buffer" hexmask.long.word 0x10 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x14 "PWM_PBUF5,PWM PERIOD5 Buffer" hexmask.long.word 0x14 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only).Used as PERIOD active register." line.long 0x18 "PWM_CMPBUF0,PWM CMPDAT0 Buffer" hexmask.long.word 0x18 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x1C "PWM_CMPBUF1,PWM CMPDAT1 Buffer" hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x20 "PWM_CMPBUF2,PWM CMPDAT2 Buffer" hexmask.long.word 0x20 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x24 "PWM_CMPBUF3,PWM CMPDAT3 Buffer" hexmask.long.word 0x24 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x28 "PWM_CMPBUF4,PWM CMPDAT4 Buffer" hexmask.long.word 0x28 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x2C "PWM_CMPBUF5,PWM CMPDAT5 Buffer" hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only).Used as CMPDAT active register." line.long 0x30 "PWM_CPSCBUF0_1,PWM CLKPSC0_1 Buffer" hexmask.long.word 0x30 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer.Used as PWM counter clock pre-scare active register." line.long 0x34 "PWM_CPSCBUF2_3,PWM CLKPSC2_3 Buffer" hexmask.long.word 0x34 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer.Used as PWM counter clock pre-scare active register." line.long 0x38 "PWM_CPSCBUF4_5,PWM CLKPSC4_5 Buffer" hexmask.long.word 0x38 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer.Used as PWM counter clock pre-scare active register." line.long 0x3C "PWM_FTCBUF0_1,PWM FTCMPDAT0_1 Buffer" hexmask.long.word 0x3C 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only).Used as FTCMPDAT active register." line.long 0x40 "PWM_FTCBUF2_3,PWM FTCMPDAT2_3 Buffer" hexmask.long.word 0x40 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only).Used as FTCMPDAT active register." line.long 0x44 "PWM_FTCBUF4_5,PWM FTCMPDAT4_5 Buffer" hexmask.long.word 0x44 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only).Used as FTCMPDAT active register." group.long 0x34C++0x3 line.long 0x0 "PWM_FTCI,PWM FTCMPDAT Indicator Register" bitfld.long 0x0 10. "FTCMD4,PWM FTCMPDAT Down Indicator.Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" bitfld.long 0x0 9. "FTCMD2,PWM FTCMPDAT Down Indicator.Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" newline bitfld.long 0x0 8. "FTCMD0,PWM FTCMPDAT Down Indicator.Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" bitfld.long 0x0 2. "FTCMU4,PWM FTCMPDAT Up Indicator.Indicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" newline bitfld.long 0x0 1. "FTCMU2,PWM FTCMPDAT Up Indicator.Indicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" bitfld.long 0x0 0. "FTCMU0,PWM FTCMPDAT Up Indicator.Indicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit. Each bit n controls the corresponding.." "0,1" tree.end endif tree.end sif (cpuis("NUC029?EE")||cpuis("NUC029?GE")) tree "RTC (Real-Time Clock)" base ad:0x40008000 sif (cpuis("NUC029?EE")) group.long 0x0++0x23 line.long 0x0 "INIR,RTC Initiation Register" hexmask.long 0x0 1.--31. 1. "INIR,RTC Initiation.When RTC block is powered on RTC is at reset state. User has to write a number (0xa5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357 the RTC will be in un-reset state permanently..The INIR is.." rbitfld.long 0x0 0. "INIR_Active,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state" line.long 0x4 "AER,RTC Access Enable Register" rbitfld.long 0x4 16. "ENF,RTC Register Access Enable Flag (Read Only).Note: This bit will be set after AER[15:0] is load a 0xA965 and will be cleared automatically after 1024 RTC clocks." "0: RTC register read/write access Disabled,1: RTC register read/write access Enabled" hexmask.long.word 0x4 0.--15. 1. "AER,RTC Register Access Enable Password (Write Only).Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clocks." line.long 0x8 "FCR,RTC Frequency Compensation Register" hexmask.long.byte 0x8 8.--11. 1. "INTEGER,Integer Part.Please refer to 6.12.5.4." hexmask.long.byte 0x8 0.--5. 1. "FRACTION,Fraction Part.Note: Digit in FCR must be expressed as hexadecimal number.." line.long 0xC "TLR,Time Loading Register" bitfld.long 0xC 20.--21. "_10HR,10-Hour Time Digit (0~2)" "0,1,2,3" hexmask.long.byte 0xC 16.--19. 1. "_1HR,1-Hour Time Digit (0~9)" newline bitfld.long 0xC 12.--14. "_10MIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "_1MIN,1-Min Time Digit (0~9)" newline bitfld.long 0xC 4.--6. "_10SEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "_1SEC,1-Sec Time Digit (0~9)" line.long 0x10 "CLR,Calendar Loading Register" hexmask.long.byte 0x10 20.--23. 1. "_10YEAR,10-Year Calendar Digit (0~9)" hexmask.long.byte 0x10 16.--19. 1. "_1YEAR,1-Year Calendar Digit (0~9)" newline bitfld.long 0x10 12. "_10MON,10-Month Calendar Digit (0~1)" "0,1" hexmask.long.byte 0x10 8.--11. 1. "_1MON,1-Month Calendar Digit (0~9)" newline bitfld.long 0x10 4.--5. "_10DAY,10-Day Calendar Digit (0~3)" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "_1DAY,1-Day Calendar Digit (0~9)" line.long 0x14 "TSSR,Time Scale Selection Register" bitfld.long 0x14 0. "_24H_12H,24-Hour / 12-Hour Time Scale Selection.It indicates that RTC TLR and TAR counter are in 24-hour time scale or 12-hour time scale. Please refer to 6.12.5.6." "0: 24-hour time scale selected,1: 24-hour time scale selected" line.long 0x18 "DWR,Day of the Week Register" bitfld.long 0x18 0.--2. "DWR,Day Of The Week Register" "0: Sunday,1: Monday,?,?,?,?,?,?" line.long 0x1C "TAR,Time Alarm Register" bitfld.long 0x1C 20.--21. "_10HR,10-Hour Time Digit of Alarm Setting (0~2)" "0,1,2,3" hexmask.long.byte 0x1C 16.--19. 1. "_1HR,1-Hour Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 12.--14. "_10MIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "_1MIN,1-Min Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 4.--6. "_10SEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--3. 1. "_1SEC,1-Sec Time Digit of Alarm Setting (0~9)" line.long 0x20 "CAR,Calendar Alarm Register" hexmask.long.byte 0x20 20.--23. 1. "_10YEAR,10-Year Calendar Digit of Alarm Setting (0~9)" hexmask.long.byte 0x20 16.--19. 1. "_1YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 12. "_10MON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1" hexmask.long.byte 0x20 8.--11. 1. "_1MON,1-Month Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 4.--5. "_10DAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "_1DAY,1-Day Calendar Digit of Alarm Setting (0~9)" rgroup.long 0x24++0x3 line.long 0x0 "LIR,Leap Year Indicator Register" bitfld.long 0x0 0. "LIR,Leap Year Indication Register (Read Only)" "0: This year is not a leap year,1: This year is a leap year" group.long 0x28++0xB line.long 0x0 "RIER,RTC Interrupt Enable Register" bitfld.long 0x0 1. "TIER,Time Tick Interrupt Enable Bit.This bit is used to enable/disable RTC Time Tick Interrupt and generate an interrupt signal if TIF (RIIR[1] RTC Time Tick Interrupt Flag) is set to 1..Note: This bit will also trigger a wake-up event while system.." "0: RTC Time Tick Interrupt Disabled,1: RTC Time Tick Interrupt Enabled" bitfld.long 0x0 0. "AIER,Alarm Interrupt Enable Bit.This bit is used to enable/disable RTC Alarm Interrupt and generate an interrupt signal if AIF (RIIR[0] RTC Alarm Interrupt Flag) is set to 1..Note: This bit will also trigger a wake-up event while system runs in.." "0: RTC Alarm Interrupt Disabled,1: RTC Alarm Interrupt Enabled" line.long 0x4 "RIIR,RTC Interrupt Indicator Register" bitfld.long 0x4 1. "TIF,RTC Time Tick Interrupt Flag.When RTC time tick happened this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TIER (RIER[1]) is set to 1. Chip will also be wake-up if RTC Tick Interrupt is enabled and this bit.." "0: Tick condition does not occur,1: Tick condition occur" bitfld.long 0x4 0. "AIF,RTC Alarm Interrupt Flag.When RTC time counters TLR and CLR match the alarm setting time registers TAR and CAR this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled AIER (RIER[0]) is set to 1. Chip will be.." "0: Alarm condition is not matched,1: Alarm condition is matched" line.long 0x8 "TTR,RTC Time Tick Register" bitfld.long 0x8 0.--2. "TTR,Time Tick Register.These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. .Note: This register can be read back after the RTC register access enable bit ENF (AER[16]) is active." "0: Time tick is 1 second,1: Time tick is 1/2 second,?,?,?,?,?,?" group.long 0x3C++0x53 line.long 0x0 "SPRCTL,RTC Spare Functional Control Register" bitfld.long 0x0 7. "SPRRDY,SPR Register Ready.This bit indicates if the registers SPRCTL SPR0 ~ SPR19 are ready to be accessed..After user writing registers SPRCTL SPR0 ~ SPR19 read this bit to check if these registers are updated done is necessary..Note: This bit is.." "0: SPRCTL SPR0 ~ SPR19 updating is in progress,1: SPRCTL SPR0 ~ SPR19 are updated done and ready.." bitfld.long 0x0 2. "SPREN,SPR Register Enable Bit.Note: When spare register is disabled RTC SPR0 ~ SPR19 cannot be accessed." "0: Spare register is Disabled,1: Spare register is Enabled" line.long 0x4 "SPR0,RTC Spare Register 0" line.long 0x8 "SPR1,RTC Spare Register 1" line.long 0xC "SPR2,RTC Spare Register 2" line.long 0x10 "SPR3,RTC Spare Register 3" line.long 0x14 "SPR4,RTC Spare Register 4" line.long 0x18 "SPR5,RTC Spare Register 5" line.long 0x1C "SPR6,RTC Spare Register 6" line.long 0x20 "SPR7,RTC Spare Register 7" line.long 0x24 "SPR8,RTC Spare Register 8" line.long 0x28 "SPR9,RTC Spare Register 9" line.long 0x2C "SPR10,RTC Spare Register 10" line.long 0x30 "SPR11,RTC Spare Register 11" line.long 0x34 "SPR12,RTC Spare Register 12" line.long 0x38 "SPR13,RTC Spare Register 13" line.long 0x3C "SPR14,RTC Spare Register 14" line.long 0x40 "SPR15,RTC Spare Register 15" line.long 0x44 "SPR16,RTC Spare Register 16" line.long 0x48 "SPR17,RTC Spare Register 17" line.long 0x4C "SPR18,RTC Spare Register 18" line.long 0x50 "SPR19,RTC Spare Register 19" endif sif (cpuis("NUC029?GE")) group.long 0x0++0x23 line.long 0x0 "RTC_INIT,RTC Initiation Register" hexmask.long 0x0 1.--31. 1. "INIT,RTC Initiation.When RTC block is first powered on RTC is at reset state. User has to write a special number 0xA5EB1357 to INIT to make RTC leaving reset state. Once the INIT is written as 0xA5EB1357 the RTC will be at normal active state.." rbitfld.long 0x0 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state" line.long 0x4 "RTC_RWEN,RTC Access Enable Register" bitfld.long 0x4 24. "RTCBUSY,RTC Write Busy Flag.This bit indicates RTC registers are writable or not..Note: RTCBUSY falg will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.Reserved." "0: RTC register write Disabled,1: RTC register write Enabled" rbitfld.long 0x4 16. "RWENF,RTC Register Access Enable Bit (Read Only).Note1: This bit will be set after RWEN is load a 0xA965 and be cleared automatically after 1024 RTC clocks expired..Note2: RWENF will be mask to 0 during RTCBUSY is 1 and first turn on RTCCKEN.." "0: RTC register read/write Disabled,1: RTC register read/write Enabled" newline hexmask.long.word 0x4 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only).Writing 0xA965 to this field will enable RTC register access period and keep 1024 RTC clocks..Note: Writing others vaule will clear RWENF and disable RTC register access function immediately." line.long 0x8 "RTC_FREQADJ,RTC Frequency Compensation Register" hexmask.long.tbyte 0x8 0.--21. 1. "FREQADJ,Frequency Compensation Value.User has to get actual clock frequency of LXT LXT frequency..Note: This formula is suitable only when RTCSEL (CLK_CLKSEL2[18]) is 0 RTC clock source is from LXT.Reserved." line.long 0xC "RTC_TIME,RTC Time Loading Register" bitfld.long 0xC 20.--21. "TENHR,10-hour Time Digit (0~2).Note: When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication RTC_TIME[21] is 0 means AM hour and RTC_TIME[21] is 1 means PM hour." "0,1,2,3" hexmask.long.byte 0xC 16.--19. 1. "HR,1-Hour Time Digit (0~9)" newline bitfld.long 0xC 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "MIN,1-Min Time Digit (0~9)" newline bitfld.long 0xC 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "SEC,1-Sec Time Digit (0~9)" line.long 0x10 "RTC_CAL,RTC Calendar Loading Register" hexmask.long.byte 0x10 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)" hexmask.long.byte 0x10 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)" newline bitfld.long 0x10 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1" hexmask.long.byte 0x10 8.--11. 1. "MON,1-Month Calendar Digit (0~9)" newline bitfld.long 0x10 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)" line.long 0x14 "RTC_CLKFMT,RTC Time Scale Selection Register" bitfld.long 0x14 0. "_24HEN,24-hour / 12-hour Time Scale Selection.Indicates that RTC_TIME and RTC_TALM register are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected" line.long 0x18 "RTC_WEEKDAY,RTC Day of the Week Register" bitfld.long 0x18 0.--2. "WEEKDAY,Day of the Week Register .Note: RTC will not check WEEKDAY setting with RTC_CAL is reasonable or not." "0: Sunday,1: Monday,?,?,?,?,?,?" line.long 0x1C "RTC_TALM,RTC Time Alarm Register" bitfld.long 0x1C 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3" hexmask.long.byte 0x1C 16.--19. 1. "HR,1-Hour Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "MIN,1-Min Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--3. 1. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" line.long 0x20 "RTC_CALM,RTC Calendar Alarm Register" hexmask.long.byte 0x20 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" hexmask.long.byte 0x20 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1" hexmask.long.byte 0x20 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" rgroup.long 0x24++0x3 line.long 0x0 "RTC_LEAPYEAR,RTC Leap Year Indicaton Register" bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication Register (Read Only)" "0: This year is not a leap year,1: This year is leap year" group.long 0x28++0x13 line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register" bitfld.long 0x0 1. "TICKIEN,Time Tick Interrupt Enable Bit" "0: RTC time tick interrupt Disabled,1: RTC time tick interrupt Enabled" bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable Bit" "0: RTC alarm interrupt Disabled,1: RTC alarm interrupt Enabled" line.long 0x4 "RTC_INTSTS,RTC Interrupt Status Register" bitfld.long 0x4 1. "TICKIF,RTC Time Tick Interrupt Flag.When RTC time tick event happened TICKIF will be set to 1 and a time tick interrupt signal will be generated if TICKIEN (RTC_INTEN[1]) is enabled. Chip will also be waken up when time tick interrupt signal occurred.." "0: Tick condition did not occur,1: Tick condition occurred" bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag.When current RTC counter in RTC_TIME and RTC_CAL are matched RTC alarm settings in RTC_TALM and RTC_CALM ALMIF will be set to 1 and an alarm interrupt signal will be generated if ALMIEN (RTC_INTEN[0]) is enabled. Chip.." "0: Alarm condition is not matched,1: Alarm condition is matched" line.long 0x8 "RTC_TICK,RTC Time Tick Register" bitfld.long 0x8 0.--2. "TICK,Time Tick Register.These bits are used to select RTC time tick period for periodic time tick interrupt request." "0: Time tick is 1 second,1: Time tick is 1/2 second,?,?,?,?,?,?" line.long 0xC "RTC_TAMSK,RTC Time Alarm Mask Register" bitfld.long 0xC 5. "MTENHR,Mask 10-hour Time Digit of Alarm Setting (0~2).Note: MTENHR function is only for 24-hour time scale mode." "0,1" bitfld.long 0xC 4. "MHR,Mask 1-hour Time Digit of Alarm Setting (0~9).Note: MHR function is only for 24-hour time scale mode." "0,1" newline bitfld.long 0xC 3. "MTENMIN,Mask 10-Min Time Digit of alarm setting (0~5)" "0,1" bitfld.long 0xC 2. "MMIN,Mask 1-Min Time Digit of alarm setting (0~9)" "0,1" newline bitfld.long 0xC 1. "MTENSEC,Mask 10-Sec Time Digit of alarm setting (0~5)" "0,1" bitfld.long 0xC 0. "MSEC,Mask 1-Sec Time Digit of alarm setting (0~9)" "0,1" line.long 0x10 "RTC_CAMSK,RTC Calendar Alarm Mask Register" bitfld.long 0x10 5. "MTENYEAR,Mask 10-Year Calendar Digit of alarm setting (0~9)" "0,1" bitfld.long 0x10 4. "MYEAR,Mask 1-Year Calendar Digit of alarm setting (0~9)" "0,1" newline bitfld.long 0x10 3. "MTENMON,Mask 10-Month Calendar Digit of alarm setting (0~1)" "0,1" bitfld.long 0x10 2. "MMON,Mask 1-Month Calendar Digit of alarm setting (0~9)" "0,1" newline bitfld.long 0x10 1. "MTENDAY,Mask 10-Day Calendar Digit of alarm setting (0~3)" "0,1" bitfld.long 0x10 0. "MDAY,Mask 1-Day Calendar Digit of alarm setting (0~9)" "0,1" group.long 0x100++0x13 line.long 0x0 "RTC_LXTCTL,RTC 32 KHz Oscillator Control Register" bitfld.long 0x0 1.--3. "GAIN,Oscillator Gain Option.User can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption." "0: L0 mode,1: L1 mode,?,?,?,?,?,?" line.long 0x4 "RTC_LXTOCTL,RTC X32KO Pin Control Register" bitfld.long 0x4 3. "CTLSEL,I/O Pin State Backup Selection.When low speed 32 kHz oscillator (LXT) is disabled X32KO pin can be used as GPIO PF.0 function. User can program CTLSEL to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT.." "0: X32KO (PF.0) pin I/O function is controlled by..,1: X32KO (PF.0) pin I/O function is controlled by.." bitfld.long 0x4 2. "DOUT,I/O Pin Output Data" "0: X32KO (PF.0) will drive low in output mode,1: X32KO (PF.0) will drive high in output mode" newline bitfld.long 0x4 0.--1. "OPMODE,I/O Pin Operation Mode" "0: X32KO (PF.0) is in Input mode without pull-up..,1: X32KO (PF.0) is in Push-pull output mode,?,?" line.long 0x8 "RTC_LXTICTL,RTC X32KI Pin Control Register" bitfld.long 0x8 3. "CTLSEL,I/O Pin State Backup Selection.When low speed 32 kHz oscillator (LXT) is disabled X32KO pin can be used as GPIO PF.1 function. User can program CTLSEL to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT.." "0: X32KI (PF.1) pin I/O function is controlled by..,1: X32KI (PF.1) pin I/O function is controlled by.." bitfld.long 0x8 2. "DOUT,IO Pin Output Data" "0: X32KI (PF.1) will drive low in output mode,1: X32KI (PF.1) will drive high in output mode" newline bitfld.long 0x8 0.--1. "OPMODE,I/O Pin Operation Mode" "0: X32KI (PF.1) is in Input mode without pull-up..,1: X32KI (PF.1) is in Push-pull output mode,?,?" line.long 0xC "RTC_PF2CTL,RTC PF.2 Pin Control Register" bitfld.long 0xC 3. "CTLSEL,I/O Pin State Backup Selection.User can program CTLSEL to decide GPIO PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register..Note: CTLSEL will be set to 1 automatically by hardware when.." "0: GPIO PF.2 pin I/O function is controlled by GPIO..,1: GPIO PF.2 pin I/O function is controlled by.." bitfld.long 0xC 2. "DOUT,I/O Pin Output Data" "0: GPIO PF.2 will drive low in output mode,1: GPIO PF.2 will drive high in output mode" newline bitfld.long 0xC 0.--1. "OPMODE,I/O Pin Operation Mode" "0: PF.2 is in Input mode without pull-up resistor,1: PF.2 is in Push-pull output mode,?,?" line.long 0x10 "RTC_DSTCTL,RTC Daylight Saving Time Control Register" bitfld.long 0x10 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Time function is not performed,1: Daylight Saving Time function is performed" bitfld.long 0x10 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted one.." newline bitfld.long 0x10 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one hour.." endif tree.end endif tree "SCS (System Controller Space)" base ad:0xE000E000 group.long 0x10++0xB line.long 0x0 "SYST_CSR,SysTick Control and Status Register" bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag.Returns 1 if timer counted to 0 since last time this register was read..COUNTFLAG is set by a count transition from 1 to 0..COUNTFLAG is cleared on read or by a write to the Current Value register." "0,1" bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is optional refer to STCLK_S,1: Core clock used for SysTick timer" newline bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.." bitfld.long 0x0 0. "ENABLE,System Tick Counter Enable Control" "0: Counter Disabled,1: Counter Enabled and will operate in a multi-shot.." line.long 0x4 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value.Value to load into the Current Value register when the counter reaches 0." line.long 0x8 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value.Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.." group.long 0x100++0x3 line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-Enable Control Register" sif (cpuis("NUC029?AE")) hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Control.Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write:.Read value indicates the current enable status." endif sif (cpuis("NUC029?DE")) hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Register.Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write Operation:.Read value indicates the current enable status." newline endif sif (cpuis("NUC029?EE")) hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Register.Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write Operation:.Read value indicates the current enable status." endif sif (cpuis("NUC029?GE")) hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Register.Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write Operation:.Note: Read value indicates the current enable status." endif group.long 0x180++0x3 line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-Enable Control Register" sif (cpuis("NUC029?AE")) hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Control.Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write:.Read value indicates the current enable status." endif sif (cpuis("NUC029?DE")) hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Bits.Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write Operation:.Read value indicates the current enable status." newline endif sif (cpuis("NUC029?EE")) hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Bits.Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write Operation:.Read value indicates the current enable status." endif sif (cpuis("NUC029?GE")) hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Bits.Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Write Operation:.Note: Read value indicates the current enable status." endif group.long 0x200++0x3 line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-Pending Control Register" sif (cpuis("NUC029?AE")) hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Bits.Write:.Read value indicates the current pending status." endif sif (cpuis("NUC029?DE")) hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Register.Write Operation:.Read value indicates the current pending status." newline endif sif (cpuis("NUC029?EE")) hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Register.Write Operation:.Read value indicates the current pending status." endif sif (cpuis("NUC029?GE")) hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Bits.Write Operation:.Note: Read value indicates the current pending status." endif group.long 0x280++0x3 line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-Pending Control Register" sif (cpuis("NUC029?AE")) hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Bits.Write:.Read value indicates the current pending status." endif sif (cpuis("NUC029?DE")) hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register.Write Operation:.Read value indicates the current pending status." newline endif sif (cpuis("NUC029?EE")) hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register.Write Operation:.Read value indicates the current pending status." endif sif (cpuis("NUC029?GE")) hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Bits.Write Operation:.Note: Read value indicates the current pending status." endif group.long 0x400++0x1F line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register" bitfld.long 0x0 30.--31. "PRI_3,Priority of IRQ3.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x0 22.--23. "PRI_2,Priority of IRQ2.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x0 14.--15. "PRI_1,Priority of IRQ1.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x0 6.--7. "PRI_0,Priority of IRQ0.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register" bitfld.long 0x4 30.--31. "PRI_7,Priority of IRQ7.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_6,Priority of IRQ6.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x4 14.--15. "PRI_5,Priority of IRQ5.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 6.--7. "PRI_4,Priority of IRQ4.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register" bitfld.long 0x8 30.--31. "PRI_11,Priority of IRQ11.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x8 22.--23. "PRI_10,Priority of IRQ10.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x8 14.--15. "PRI_9,Priority of IRQ9.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x8 6.--7. "PRI_8,Priority of IRQ8.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register" bitfld.long 0xC 30.--31. "PRI_15,Priority of IRQ15.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0xC 22.--23. "PRI_14,Priority of IRQ14.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0xC 14.--15. "PRI_13,Priority of IRQ13.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0xC 6.--7. "PRI_12,Priority of IRQ12.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register" bitfld.long 0x10 30.--31. "PRI_19,Priority of IRQ19.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x10 22.--23. "PRI_18,Priority of IRQ18.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x10 14.--15. "PRI_17,Priority of IRQ17.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x10 6.--7. "PRI_16,Priority of IRQ16.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register" bitfld.long 0x14 30.--31. "PRI_23,Priority of IRQ23.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x14 22.--23. "PRI_22,Priority of IRQ22.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x14 14.--15. "PRI_21,Priority of IRQ21.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x14 6.--7. "PRI_20,Priority of IRQ20.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register" bitfld.long 0x18 30.--31. "PRI_27,Priority of IRQ27.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x18 22.--23. "PRI_26,Priority of IRQ26.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x18 14.--15. "PRI_25,Priority of IRQ25.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x18 6.--7. "PRI_24,Priority of IRQ24.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register" bitfld.long 0x1C 30.--31. "PRI_31,Priority of IRQ31.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x1C 22.--23. "PRI_30,Priority of IRQ30.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x1C 14.--15. "PRI_29,Priority of IRQ29.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x1C 6.--7. "PRI_28,Priority of IRQ28.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" rgroup.long 0xD00++0x3 line.long 0x0 "CPUID,CPUID Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer Code" hexmask.long.byte 0x0 16.--19. 1. "PART,Architecture of the Processor.Read as 0xC for ARMv6-M parts." newline hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number of the Processor.Read as 0xC20." hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision Number.Read as 0x0." group.long 0xD04++0x3 line.long 0x0 "ICSR,Interrupt Control State Register" bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit.Write:.Note: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This.." "0: No effect..NMI exception not pending,1: Changes NMI exception state to pending..NMI.." bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit.Write:.Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect..PendSV exception is not pending,1: Changes PendSV exception state to.." newline bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit.Write:.Note: This bit is write-only. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.." bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit.Write:" "0: No effect..SysTick exception is not pending,1: Changes SysTick exception state to.." newline bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit.Write:.Note: This bit is write-only. When you want to clear PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.." bitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preemption Bit.If set a pending exception will be serviced on exit from the debug halt state..This bit is read only." "0,1" newline bitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag excluding NMI and Faults.This bit is read only." "0: Interrupt not pending,1: Interrupt pending" sif (cpuis("NUC029?AE")) hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Exception Number of the Highest Priority Pending Enabled Exception.This bit is read only." newline hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Contains the Active Exception Number.This bit is read only." endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Indicates the exception number of the highest priority pending enabled exception:" newline endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Indicates The Exception Number Of The Highest Priority Pending Enabled Exception:." endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Indicates The Exception Number Of The Highest Priority Pending Enabled Exception:" newline endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Indicates the Exception Number of the Highest Priority Pending Enabled Exception:" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Contains The Active Exception Number." newline endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Contains The Active Exception Number" endif sif (cpuis("NUC029?GE")) hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Contains the Active Exception Number" newline endif sif (cpuis("NUC029?AN")) hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Contains the active exception number" endif group.long 0xD0C++0x7 line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key.Write:.When writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting.." bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request.Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested..The bit is a write only bit and self-clears as part of the reset sequence." "0,1" newline bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit.Reserved for debug use. When writing to the register user must write 0 to this bit otherwise behavior is unpredictable." "0,1" line.long 0x4 "SCR,System Control Register" bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending Bit.When an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects next WFE..The processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.." bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection.Controls whether the processor uses sleep or deep sleep as its low power mode:" "0: Sleep mode,1: Deep Sleep mode" newline bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit Enable.This bit indicates sleep-on-exit when returning from Handler mode to Thread mode:.Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep on return from ISR to.." group.long 0xD1C++0x7 line.long 0x0 "SHPR2,System Handler Priority Register 2" bitfld.long 0x0 30.--31. "PRI_11,Priority of System Handler 11 - SVCall.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" line.long 0x4 "SHPR3,System Handler Priority Register 3" bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV.0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3" tree.end sif (cpuis("NUC029?AE")) base ad:0x40030000 elif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) base ad:0x0 endif tree "SPI (Serial Peripheral Interface)" sif (cpuis("NUC029?AE")) group.long 0x0++0xB line.long 0x0 "SPI_CNTRL,SPI Control and Status Register" rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).Note: It's a mutual mirror bit of SPI_STATUS[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full" rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).Note: It's a mutual mirror bit of SPI_STAUTS[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty" newline rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only).Note: It's a mutual mirror bit of SPI_STATUS[25]" "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full" rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).Note: It's a mutual mirror bit of SPI_CNTRL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty" newline bitfld.long 0x0 21. "FIFO,FIFO Mode Enable Control.Note 1: Before enabling FIFO mode the other related settings should be set in advance..Note 2: In Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data into the.." "0: FIFO Mode Disabled,1: Before enabling FIFO mode" bitfld.long 0x0 19. "REORDER,Byte Reorder Function.Note: This setting is only available if TX_BIT_LEN is defined as 16 24 and 32 bits." "0: Byte reorder function Disabled,1: Byte reorder function Enabled" newline bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "IE,Unit-Transfer Interrupt Enable Control" "0: SPI unit-transfer interrupt Disabled,1: SPI unit-transfer interrupt Enabled" newline bitfld.long 0x0 16. "IF,Unit-Transfer Interrupt Flag.Note 1: This bit will be cleared by writing 1 to itself..Note 2: It's a mutual mirror bit of SPI_STATUS[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself" hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.." newline bitfld.long 0x0 11. "CLKP,Clock Polarity" "0: SPICLK idle low,1: SPICLK idle high" bitfld.long 0x0 10. "LSB,LSB First" "0: The MSB is transmitted/received first,1: The LSB is transmitted/received first" newline hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length.This field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits." bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge" "0: The transmitted data output signal is driven on..,1: The transmitted data output signal is driven on.." newline bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge" "0: The received data input signal latched on the..,1: The received data input signal latched on the.." bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status.If FIFO mode is enabled this bit will be controlled by hardware and is Read only..If FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit.." "0: Writing 0 to this bit to stop data transfer if..,1: When FIFO mode is disabled" line.long 0x4 "SPI_DIVIDER,SPI Clock Divider Register" hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Bits (Master Only).The value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the.." line.long 0x8 "SPI_SSR,SPI Slave Select Register" rbitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Flag (Read Only Slave Only).When the SS_LTRIG bit is set in Slave mode this bit can be read to indicate the received bit number is met the requirement or not." "0: The transaction number or the transferred bit..,1: The transaction number and the transferred bit.." bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)" "0: The input slave select signal is edge-trigger,1: The input slave select signal is level-trigger" newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: SPISS pin signal will be asserted/de-asserted by..,1: SPISS pin signal will be generated automatically.." bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level (Slave Only).It defines the active status of slave select signal (SPISS)..If SS_LTRIG bit is 1:" "0: The slave select signal SPISS is active at..,1: The slave select signal SPISS is active at.." newline bitfld.long 0x8 0. "SSR,Slave Select Control Bit (Master Only).If AUTOSS bit is 0 " "0: Set the SPISS line to inactive state..Keep the..,1: Set the proper SPISS line to active.." rgroup.long 0x10++0x3 line.long 0x0 "SPI_RX,SPI Data Receive Register" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Bits (Read Only).The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register..For example if TX_BIT_LEN is set to 0x08 bit RX.." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TX,SPI Data Transmit Register" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Bits (Write Only).The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register..For example if TX_BIT_LEN is set to 0x08 the bit TX [7:0].." group.long 0x3C++0xB line.long 0x0 "SPI_CNTRL2,SPI Control and Status Register 2" bitfld.long 0x0 31. "BCn,Clock Configuration Backward Compatible Option.Note: Refer to the description of SPI_DIVIDER register for details." "0: The clock configuration is backward compatible,1: The clock configuration is not backward compatible" bitfld.long 0x0 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option (Slave Only).Note: This setting is only available if the SPI controller is configured as level trigger in slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x0 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status (Slave Only).This bit dedicates if a transaction has started in slave 3-wire mode. .Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit..Note 2: It.." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared automatically when a.." bitfld.long 0x0 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable Control (Slave Only).It is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled" newline bitfld.long 0x0 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control Bit (Slave Only).In normal operation there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN..If the number of received bits is less than the requirement.." "0: No force the transfer done when the NOSLVSEL bit..,1: Force the transfer done when the NOSLVSEL bit is.." bitfld.long 0x0 8. "NOSLVSEL,Slave 3-Wire Mode Enable Control (Slave Only).The SPI controller work with 3-wire interface including SPICLK SPI_MISO and SPI_MOSI .Note: In Slave 3-wire mode the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1." "0: The controller is 4-wire bi-direction interface,1: The controller is 3-wire bi-direction interface.." line.long 0x4 "SPI_FIFO_CTL,SPI FIFO Control Register" bitfld.long 0x4 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3" bitfld.long 0x4 24.--25. "RX_THRESHOLD,Received FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3" newline bitfld.long 0x4 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable Control" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" bitfld.long 0x4 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Control" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" newline bitfld.long 0x4 3. "TX_INTEN,Transmit Threshold Interrupt Enable Control" "0: Transmit threshold interrupt Disabled,1: Transmit threshold interrupt Enabled" bitfld.long 0x4 2. "RX_INTEN,Receive Threshold Interrupt Enable Control" "0: Receive threshold interrupt Disabled,1: Receive threshold interrupt Enabled" newline bitfld.long 0x4 1. "TX_CLR,Clear Transmit FIFO Buffer.Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared." "0: No effect,1: Clear transmit FIFO buffer" bitfld.long 0x4 0. "RX_CLR,Clear Receive FIFO Buffer.Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared." "0: No effect,1: Clear receive FIFO buffer" line.long 0x8 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x8 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only).Indicates the valid data count of transmit FIFO buffer." rbitfld.long 0x8 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).Note: It's a mutual mirror bit of SPI_CNTRL[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full" newline rbitfld.long 0x8 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only) .Note: It's a mutual mirror bit of SPI_CNTRL[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty" rbitfld.long 0x8 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only) .Note: It's a mutual mirror bit of SPI_CNTRL[25]." "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full" newline rbitfld.long 0x8 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).Note: It's a mutual mirror bit of SPI_CNTRL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty" bitfld.long 0x8 20. "TIMEOUT,Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: The receive FIFO buffer is not empty and it does.." newline bitfld.long 0x8 16. "IF,SPI Unit-Transfer Interrupt Flag.Note 1: This bit will be cleared by writing 1 to itself..Note 2: It's a mutual mirror bit of SPI_CNTRL[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself" hexmask.long.byte 0x8 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only).Indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x8 11. "SLV_START_INTSTS,Slave Start Interrupt Status (Slave Only).It is used to dedicate that the transfer has started in slave 3-wire mode. .Note 1: It will be cleared as transfer done or by writing one to this bit..Note 2: It's a mutual mirror bit of.." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared as transfer done or by.." rbitfld.long 0x8 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." newline bitfld.long 0x8 2. "RX_OVERRUN,Receive FIFO Overrun Status.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0: No overrun in receive FIFO,1: Overrun in receive FIFO" rbitfld.long 0x8 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.." endif sif (cpuis("NUC029?AN")) tree "SPI0" base ad:0x40030000 group.long 0x0++0xB line.long 0x0 "SPI_CNTRL,Control and Status Register" rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only).It's a mutual mirror bit of SPI_STATUS[27]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is full" rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only).It's a mutual mirror bit of SPI_STAUTS[26]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is empty" newline rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only).It's a mutual mirror bit of SPI_STATUS[25]." "0: Indicates that the receive FIOF buffer is not full,1: Indicates that the receive FIFO buffer is full" rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only).It's a mutual mirror bit of SPI_CNTRL[24]." "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty" newline bitfld.long 0x0 21. "FIFO,FIFO Mode.Note:.Before enabling FIFO mode the other related settings should be set in advance.. In master mode if the FIFO mode is enabled the GO_BUSY bit will be set to '1' automatically after writing data into the 8-depth FIFO. It means all.." "0: Disable FIFO Mode,1: Enable FIFO Mode" bitfld.long 0x0 19. "REORDER,Byte Reorder Function.Note:.Byte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits." "0: Disable the byte reorder function,1: Enable byte reorder function" newline bitfld.long 0x0 18. "SLAVE,Slave Mode Enable Bit" "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "IE,SPI Unit Transfer Interrupt Enable Bit" "0: Disable SPI unit transfer interrupt,1: Enable SPI unit transfer interrupt" newline bitfld.long 0x0 16. "IF,SPI Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: It indicates that the transfer does not finish yet,1: It indicates that the SPI controller has.." hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only).These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." newline bitfld.long 0x0 11. "CLKP,Clock Polarity" "0: SPICLK idle low,1: SPICLK idle high" bitfld.long 0x0 10. "LSB,LSB First" "0: The MSB which bit of SPI_TX0/SPI_RX0 register..,1: The LSB bit 0 of the SPI_TX0 register is sent.." newline hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length.This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits." bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge" "0: The transmitted data output signal is changed on..,1: The transmitted data output signal is changed on.." newline bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge" "0: The received data input signal is latched on the..,1: The received data input signal is latched on the.." bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status.If the FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically..In FIFO mode this bit will be controlled by.." "0: Writing 0 to this bit to stop data transfer if..,1: In master mode writing 1 to this bit to start.." line.long 0x4 "SPI_DIVIDER,Clock Divider Register" hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register (master only).The value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:.If the bit of BCn SPI_CNTRL2[31] is.." line.long 0x8 "SPI_SSR,Slave Select Register" bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag.In slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done..Note: This bit is READ only" "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave only)" "0: The slave select signal is edge-trigger. This is..,1: The slave select signal will be level-trigger." newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master only)" "0: If this bit is cleared slave select signal will..,1: If this bit is set SPISSx signal will be.." bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level.It defines the active status of slave select signal (SPISSx)." "0: The slave select signal SPISSx is active on..,1: The slave select signal SPISSx is active on.." newline bitfld.long 0x8 0. "SSR,Slave Select Control Bits (Master only).If AUTOSS bit is cleared writing 1 to this field sets the SPISSx line to active state and writing 0 sets the line back to inactive state..If AUTOSS bit is set writing 0 to this field will keep the SPISSx.." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.The data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit .." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register..For example if TX_BIT_LEN is set to.." group.long 0x3C++0xB line.long 0x0 "SPI_CNTRL2,Control and Status Register 2" bitfld.long 0x0 31. "BCn,SPI Engine Clock Backward Compatible Option.Refer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: The clock configuration is not backward compatible" bitfld.long 0x0 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option .This setting is only available if the SPI controller is configured as level trigger slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x0 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status.It is used to dedicate that the transfer has started in slave 3-wire mode." "0: It indicates that the SPI transfer is not active,1: It indicates that the transfer has started in.." bitfld.long 0x0 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable.It is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the.." "0: Disable the transfer start interrupt,1: Enable the transaction start interrupt. It will.." newline bitfld.long 0x0 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control Bit.In normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN..If the received bits are less than the requirement and there is no more serial.." "0,1" bitfld.long 0x0 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit.This is used to ignore the slave select signal in slave mode. The SPI controller can work with 3-wire interface including SPICLK SPI_MISO and SPI_MOSI..Note: In 3-wire mode the SS_LTRIG SPI_SSR[4] shall be set.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" line.long 0x4 "SPI_FIFO_CTL,SPI FIFO Control Register" bitfld.long 0x4 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3" bitfld.long 0x4 24.--25. "RX_THRESHOLD,Received FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3" newline bitfld.long 0x4 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable" "0: Disable time-out interrupt,1: Enable time-out interrupt" bitfld.long 0x4 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable" "0: Disable Receive FIFO overrun interrupt,1: Enable Receive FIFO overrun interrupt" newline bitfld.long 0x4 3. "TX_INTEN,Transmit Threshold Interrupt Enable" "0: Disable transmit threshold interrupt,1: Enable transmit threshold interrupt" bitfld.long 0x4 2. "RX_INTEN,Receive Threshold Interrupt Enable" "0: Disable receive threshold interrupt,1: Enable receive threshold interrupt" newline bitfld.long 0x4 1. "TX_CLR,Clear Transmit FIFO Buffer" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.." bitfld.long 0x4 0. "RX_CLR,Clear Receive FIFO Buffer" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.." line.long 0x8 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x8 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (read only).Indicates the valid data count of transmit FIFO buffer." rbitfld.long 0x8 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only).It's a mutual mirror bit of SPI_CNTRL[27]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is full" newline rbitfld.long 0x8 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only) .It's a mutual mirror bit of SPI_CNTRL[26]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is empty" rbitfld.long 0x8 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only) .It's a mutual mirror bit of SPI_CNTRL[25]." "0: Indicates that the receive FIFO buffer is not full,1: Indicates that the receive FIFO buffer is full" newline rbitfld.long 0x8 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only).It's a mutual mirror bit of SPI_CNTRL[24]." "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty" bitfld.long 0x8 20. "TIMEOUT,Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: It indicates that the receive FIFO buffer is not.." newline bitfld.long 0x8 16. "IF,SPI Unit Transfer Interrupt Flag.It's a mutual mirror bit of SPI_CNTRL[16]..Note: This bit will be cleared by writing 1 to itself." "0: It indicates that the transfer does not finish yet,1: It indicates that the SPI controller has.." hexmask.long.byte 0x8 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (read only).Indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x8 11. "SLV_START_INTSTS,Slave Start Interrupt Status.It is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11]." "0: It indicates that the transfer is not started,1: It indicates that the transfer has started in.." rbitfld.long 0x8 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (read only)" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.." newline bitfld.long 0x8 2. "RX_OVERRUN,Receive FIFO Overrun Status.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x8 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (read only)" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.." tree.end tree "SPI1" base ad:0x40034000 group.long 0x0++0xB line.long 0x0 "SPI_CNTRL,Control and Status Register" rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only).It's a mutual mirror bit of SPI_STATUS[27]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is full" rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only).It's a mutual mirror bit of SPI_STAUTS[26]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is empty" newline rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only).It's a mutual mirror bit of SPI_STATUS[25]." "0: Indicates that the receive FIOF buffer is not full,1: Indicates that the receive FIFO buffer is full" rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only).It's a mutual mirror bit of SPI_CNTRL[24]." "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty" newline bitfld.long 0x0 21. "FIFO,FIFO Mode.Note:.Before enabling FIFO mode the other related settings should be set in advance.. In master mode if the FIFO mode is enabled the GO_BUSY bit will be set to '1' automatically after writing data into the 8-depth FIFO. It means all.." "0: Disable FIFO Mode,1: Enable FIFO Mode" bitfld.long 0x0 19. "REORDER,Byte Reorder Function.Note:.Byte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits." "0: Disable the byte reorder function,1: Enable byte reorder function" newline bitfld.long 0x0 18. "SLAVE,Slave Mode Enable Bit" "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "IE,SPI Unit Transfer Interrupt Enable Bit" "0: Disable SPI unit transfer interrupt,1: Enable SPI unit transfer interrupt" newline bitfld.long 0x0 16. "IF,SPI Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: It indicates that the transfer does not finish yet,1: It indicates that the SPI controller has.." hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only).These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." newline bitfld.long 0x0 11. "CLKP,Clock Polarity" "0: SPICLK idle low,1: SPICLK idle high" bitfld.long 0x0 10. "LSB,LSB First" "0: The MSB which bit of SPI_TX0/SPI_RX0 register..,1: The LSB bit 0 of the SPI_TX0 register is sent.." newline hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length.This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits." bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge" "0: The transmitted data output signal is changed on..,1: The transmitted data output signal is changed on.." newline bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge" "0: The received data input signal is latched on the..,1: The received data input signal is latched on the.." bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status.If the FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically..In FIFO mode this bit will be controlled by.." "0: Writing 0 to this bit to stop data transfer if..,1: In master mode writing 1 to this bit to start.." line.long 0x4 "SPI_DIVIDER,Clock Divider Register" hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register (master only).The value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:.If the bit of BCn SPI_CNTRL2[31] is.." line.long 0x8 "SPI_SSR,Slave Select Register" bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag.In slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done..Note: This bit is READ only" "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave only)" "0: The slave select signal is edge-trigger. This is..,1: The slave select signal will be level-trigger." newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master only)" "0: If this bit is cleared slave select signal will..,1: If this bit is set SPISSx signal will be.." bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level.It defines the active status of slave select signal (SPISSx)." "0: The slave select signal SPISSx is active on..,1: The slave select signal SPISSx is active on.." newline bitfld.long 0x8 0. "SSR,Slave Select Control Bits (Master only).If AUTOSS bit is cleared writing 1 to this field sets the SPISSx line to active state and writing 0 sets the line back to inactive state..If AUTOSS bit is set writing 0 to this field will keep the SPISSx.." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.The data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit .." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register..For example if TX_BIT_LEN is set to.." group.long 0x3C++0xB line.long 0x0 "SPI_CNTRL2,Control and Status Register 2" bitfld.long 0x0 31. "BCn,SPI Engine Clock Backward Compatible Option.Refer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: The clock configuration is not backward compatible" bitfld.long 0x0 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option .This setting is only available if the SPI controller is configured as level trigger slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x0 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status.It is used to dedicate that the transfer has started in slave 3-wire mode." "0: It indicates that the SPI transfer is not active,1: It indicates that the transfer has started in.." bitfld.long 0x0 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable.It is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the.." "0: Disable the transfer start interrupt,1: Enable the transaction start interrupt. It will.." newline bitfld.long 0x0 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control Bit.In normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN..If the received bits are less than the requirement and there is no more serial.." "0,1" bitfld.long 0x0 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit.This is used to ignore the slave select signal in slave mode. The SPI controller can work with 3-wire interface including SPICLK SPI_MISO and SPI_MOSI..Note: In 3-wire mode the SS_LTRIG SPI_SSR[4] shall be set.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" line.long 0x4 "SPI_FIFO_CTL,SPI FIFO Control Register" bitfld.long 0x4 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3" bitfld.long 0x4 24.--25. "RX_THRESHOLD,Received FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3" newline bitfld.long 0x4 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable" "0: Disable time-out interrupt,1: Enable time-out interrupt" bitfld.long 0x4 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable" "0: Disable Receive FIFO overrun interrupt,1: Enable Receive FIFO overrun interrupt" newline bitfld.long 0x4 3. "TX_INTEN,Transmit Threshold Interrupt Enable" "0: Disable transmit threshold interrupt,1: Enable transmit threshold interrupt" bitfld.long 0x4 2. "RX_INTEN,Receive Threshold Interrupt Enable" "0: Disable receive threshold interrupt,1: Enable receive threshold interrupt" newline bitfld.long 0x4 1. "TX_CLR,Clear Transmit FIFO Buffer" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.." bitfld.long 0x4 0. "RX_CLR,Clear Receive FIFO Buffer" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.." line.long 0x8 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x8 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (read only).Indicates the valid data count of transmit FIFO buffer." rbitfld.long 0x8 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only).It's a mutual mirror bit of SPI_CNTRL[27]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is full" newline rbitfld.long 0x8 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only) .It's a mutual mirror bit of SPI_CNTRL[26]." "0: Indicates that the transmit FIFO buffer is not..,1: Indicates that the transmit FIFO buffer is empty" rbitfld.long 0x8 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only) .It's a mutual mirror bit of SPI_CNTRL[25]." "0: Indicates that the receive FIFO buffer is not full,1: Indicates that the receive FIFO buffer is full" newline rbitfld.long 0x8 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only).It's a mutual mirror bit of SPI_CNTRL[24]." "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty" bitfld.long 0x8 20. "TIMEOUT,Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: It indicates that the receive FIFO buffer is not.." newline bitfld.long 0x8 16. "IF,SPI Unit Transfer Interrupt Flag.It's a mutual mirror bit of SPI_CNTRL[16]..Note: This bit will be cleared by writing 1 to itself." "0: It indicates that the transfer does not finish yet,1: It indicates that the SPI controller has.." hexmask.long.byte 0x8 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (read only).Indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x8 11. "SLV_START_INTSTS,Slave Start Interrupt Status.It is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11]." "0: It indicates that the transfer is not started,1: It indicates that the transfer has started in.." rbitfld.long 0x8 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (read only)" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.." newline bitfld.long 0x8 2. "RX_OVERRUN,Receive FIFO Overrun Status.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x8 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (read only)" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.." tree.end endif sif (cpuis("NUC029?DE")) tree "SPI0" base ad:0x40030000 group.long 0x0++0xB line.long 0x0 "SPI_CNTRL,Control and Status Register" rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[27].." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[26].." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" newline rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[25].." "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[24].." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" newline bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable Coontrol (Master Only).Note: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.." bitfld.long 0x0 21. "FIFO,FIFO Mode Enable Bit.Note:.Before enabling FIFO mode the other related settings should be set in advance..In Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer;.." "0: FIFO mode Disabled,1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit.Note:.Byte Reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits..In Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.." bitfld.long 0x0 18. "SLAVE,Slave Mode Enable Bit." "0: Master mode,1: Slave mode" newline bitfld.long 0x0 17. "IE,Unit Transfer Interrupt Enable Bit." "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled" bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" newline hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x0 11. "CLKP,Clock Polarity." "0: SPI bus clock is idle low,1: SPI bus clock is idle high" newline bitfld.long 0x0 10. "LSB,Send LSB First." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0/1 register is sent.." hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length.This field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.." newline bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge." "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.." bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge." "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.." newline bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit And Busy Status.If FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.." line.long 0x4 "SPI_DIVIDER,Clock Divider Register" hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only).The value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: ..If the VARCLK_EN bit.." hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register .The value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. .If the bit of.." line.long 0x8 "SPI_SSR,Slave Select Register" bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag.In Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. .Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.." bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)." "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.." newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master Only)." "0: If this bit is cleared slave select signal will..,1: If this bit is set SPI0_SPISS0 signal will be.." bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level.This bit defines the active status of slave select signal (SPI0_SPISS0).." "0: The slave select signal SPI0_SPISS0 is active on..,1: The slave select signal SPI0_SPISS0 is active on.." newline bitfld.long 0x8 0. "SSR,Slave Select Control Bit (Master Only).If AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPI0_SPISS0 line to an active state and writing 0 sets the line back to inactive state..If the AUTOSS bit is set writing 0 to any.." "0,1" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.The data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.." line.long 0x4 "SPI_RX1,Data Receive Register 1" hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register.The data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register..For example if TX_BIT_LEN is set to.." line.long 0x4 "SPI_TX1,Data Transmit Register 1" hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register.The data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register..For example if TX_BIT_LEN is set to.." group.long 0x34++0x3 line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register" hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern.This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description." group.long 0x3C++0xB line.long 0x0 "SPI_CNTRL2,Control and Status Register 2" bitfld.long 0x0 31. "BCn,SPI Peripheral Clock Backward Compatible Option.Refer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible" bitfld.long 0x0 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option .This setting is only available if the SPI controller is configured as level trigger slave device.." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x0 13. "DUAL_IO_EN,Dual I/O Mode Enable Bit." "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled" bitfld.long 0x0 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control." "0: Dual Input mode,1: Dual Output mode" newline bitfld.long 0x0 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status.This bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].." "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode." bitfld.long 0x0 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable Bit.Used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.." newline bitfld.long 0x0 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control.In normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN..If the received bits are less than the requirement and there is no more SPI clock.." "0,1" bitfld.long 0x0 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit.This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI0_CLK SPI0_MISO0 and SPI0_MOSI0 pins..Note: In Slave 3-wire mode the SS_LTRIG .." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" line.long 0x4 "SPI_FIFO_CTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "RX_THRESHOLD,Receive FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 21. "TIMEOUT_INTEN,Receive FIFO Time-Out Interrupt Enable Bit." "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" bitfld.long 0x4 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Bit." "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" newline bitfld.long 0x4 3. "TX_INTEN,Transmit Threshold Interrupt Enable Bit." "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0x4 2. "RX_INTEN,Receive Threshold Interrupt Enable Bit." "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0x4 1. "TX_CLR,Clear Transmit FIFO Buffer." "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.." bitfld.long 0x4 0. "RX_CLR,Clear Receive FIFO Buffer." "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.." line.long 0x8 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x8 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." rbitfld.long 0x8 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[27].." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x8 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[26].." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x8 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[25].." "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" newline rbitfld.long 0x8 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24].." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" bitfld.long 0x8 20. "TIMEOUT,Time-Out Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." newline bitfld.long 0x8 16. "IF,SPI Unit Transfer Interrupt Flag.It is a mutual mirror bit of SPI_CNTRL[16]..Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" hexmask.long.byte 0x8 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x8 11. "SLV_START_INTSTS,Slave Start Interrupt Status.It is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].." "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode." rbitfld.long 0x8 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)." "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." newline bitfld.long 0x8 2. "RX_OVERRUN,Receive FIFO Overrun Status.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x8 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)." "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.." tree.end endif sif (cpuis("NUC029?EE")) tree "SPI0" base ad:0x40030000 group.long 0x0++0xB line.long 0x0 "SPI_CNTRL,Control and Status Register" rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[27]." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[26]." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" newline rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[25]." "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24]." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" newline bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable Bit (Master Only).Note: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.." bitfld.long 0x0 21. "FIFO,FIFO Mode EnableBit.Note1: Before enabling FIFO mode the other related settings should be set in advance..Note2: In Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO.." "0: FIFO mode Disabled,1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function EnableBit.Note1: Byte Reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits..Note2: In Slave mode with level-trigger configuration the slave select pin must be kept at active state during the.." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.." bitfld.long 0x0 18. "SLAVE,Slave Mode EnableBit" "0: Master mode,1: Slave mode" newline bitfld.long 0x0 17. "IE,Unit Transfer Interrupt EnableBit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled" bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" newline hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x0 11. "CLKP,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high" newline bitfld.long 0x0 10. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0 register is sent.." hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length.This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits." newline bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.." bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.." newline bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit And Busy Status.If FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.." line.long 0x4 "SPI_DIVIDER,Clock Divider Register" hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only).The value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: ..If the VARCLK_EN bit.." hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register .The value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. .If the bit of.." line.long 0x8 "SPI_SSR,Slave Select Register" bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag.In Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. .Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.." bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)" "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.." newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master Only)" "0: If this bit is cleared slave select signals will..,1: If this bit is set SPIn_SPISS0 signals will be.." bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level.This bit defines the active status of slave select signal (SPIn_SPISS0)." "0: The slave select signal SPIn_SPISS0 is active on..,1: The slave select signal SPIn_SPISS0 is active on.." newline bitfld.long 0x8 0. "SSR,Slave Select Control Bits (Master Only).If AUTOSS bit is cleared writing 1 to any bit of this field sets the SPIn_SPISS0 line to an active state and writing 0 sets the line back to inactive state..If the AUTOSS bit is set writing 0 to this field.." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.The data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register..For example if TX_BIT_LEN is set to.." group.long 0x34++0x13 line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register" hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern.This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description." line.long 0x4 "SPI_DMA,SPI DMA Control Register" bitfld.long 0x4 2. "PDMA_RST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.." bitfld.long 0x4 1. "RX_DMA_GO,Receive DMA Start.Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1" newline bitfld.long 0x4 0. "TX_DMA_GO,Transmit DMA Start.Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done..If the SPI transmit.." "0,1" line.long 0x8 "SPI_CNTRL2,Control and Status Register 2" bitfld.long 0x8 31. "BCn,SPI Peripheral Clock Backward Compatible Option.Refer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible" bitfld.long 0x8 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option .This setting is only available if the SPI controller is configured as level trigger slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x8 13. "DUAL_IO_EN,Dual I/O Mode EnableBit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled" bitfld.long 0x8 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control" "0: Dual Input mode,1: Dual Output mode" newline bitfld.long 0x8 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status.This bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11]." "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode." bitfld.long 0x8 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt EnableBit.Used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.." newline bitfld.long 0x8 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control.In normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN..If the received bits are less than the requirement and there is no more SPI clock.." "0,1" bitfld.long 0x8 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit.This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPIn_CLK SPIn_MISO and SPIn_MOSI..Note: In Slave 3-wire mode the SS_LTRIG SPI_SSR[4].." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" line.long 0xC "SPI_FIFO_CTL,SPI FIFO Control Register" bitfld.long 0xC 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "RX_THRESHOLD,Receive FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 21. "TIMEOUT_INTEN,Receive FIFO Time-Out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" bitfld.long 0xC 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" newline bitfld.long 0xC 3. "TX_INTEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0xC 2. "RX_INTEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0xC 1. "TX_CLR,Clear Transmit FIFO Buffer" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.." bitfld.long 0xC 0. "RX_CLR,Clear Receive FIFO Buffer" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.." line.long 0x10 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x10 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." rbitfld.long 0x10 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[27]." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x10 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[26]." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x10 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24]." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" newline rbitfld.long 0x10 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24]." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" bitfld.long 0x10 20. "TIMEOUT,Time-Out Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." newline bitfld.long 0x10 16. "IF,SPI Unit Transfer Interrupt Flag.It is a mutual mirror bit of SPI_CNTRL[16]..Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" hexmask.long.byte 0x10 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x10 11. "SLV_START_INTSTS,Slave Start Interrupt Status.It is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11]." "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode." rbitfld.long 0x10 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." newline bitfld.long 0x10 2. "RX_OVERRUN,Receive FIFO Overrun Status.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x10 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.." tree.end tree "SPI1" base ad:0x40034000 group.long 0x0++0xB line.long 0x0 "SPI_CNTRL,Control and Status Register" rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[27]." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[26]." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" newline rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_STATUS[25]." "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24]." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" newline bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable Bit (Master Only).Note: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.." bitfld.long 0x0 21. "FIFO,FIFO Mode EnableBit.Note1: Before enabling FIFO mode the other related settings should be set in advance..Note2: In Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO.." "0: FIFO mode Disabled,1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function EnableBit.Note1: Byte Reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits..Note2: In Slave mode with level-trigger configuration the slave select pin must be kept at active state during the.." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.." bitfld.long 0x0 18. "SLAVE,Slave Mode EnableBit" "0: Master mode,1: Slave mode" newline bitfld.long 0x0 17. "IE,Unit Transfer Interrupt EnableBit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled" bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" newline hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x0 11. "CLKP,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high" newline bitfld.long 0x0 10. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0 register is sent.." hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length.This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits." newline bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.." bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.." newline bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit And Busy Status.If FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.." line.long 0x4 "SPI_DIVIDER,Clock Divider Register" hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only).The value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: ..If the VARCLK_EN bit.." hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register .The value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. .If the bit of.." line.long 0x8 "SPI_SSR,Slave Select Register" bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag.In Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. .Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.." bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)" "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.." newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master Only)" "0: If this bit is cleared slave select signals will..,1: If this bit is set SPIn_SPISS0 signals will be.." bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level.This bit defines the active status of slave select signal (SPIn_SPISS0)." "0: The slave select signal SPIn_SPISS0 is active on..,1: The slave select signal SPIn_SPISS0 is active on.." newline bitfld.long 0x8 0. "SSR,Slave Select Control Bits (Master Only).If AUTOSS bit is cleared writing 1 to any bit of this field sets the SPIn_SPISS0 line to an active state and writing 0 sets the line back to inactive state..If the AUTOSS bit is set writing 0 to this field.." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.The data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.." wgroup.long 0x20++0x3 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register..For example if TX_BIT_LEN is set to.." group.long 0x34++0x13 line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register" hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern.This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description." line.long 0x4 "SPI_DMA,SPI DMA Control Register" bitfld.long 0x4 2. "PDMA_RST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.." bitfld.long 0x4 1. "RX_DMA_GO,Receive DMA Start.Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1" newline bitfld.long 0x4 0. "TX_DMA_GO,Transmit DMA Start.Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done..If the SPI transmit.." "0,1" line.long 0x8 "SPI_CNTRL2,Control and Status Register 2" bitfld.long 0x8 31. "BCn,SPI Peripheral Clock Backward Compatible Option.Refer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible" bitfld.long 0x8 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option .This setting is only available if the SPI controller is configured as level trigger slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.." newline bitfld.long 0x8 13. "DUAL_IO_EN,Dual I/O Mode EnableBit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled" bitfld.long 0x8 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control" "0: Dual Input mode,1: Dual Output mode" newline bitfld.long 0x8 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status.This bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11]." "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode." bitfld.long 0x8 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt EnableBit.Used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.." newline bitfld.long 0x8 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control.In normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN..If the received bits are less than the requirement and there is no more SPI clock.." "0,1" bitfld.long 0x8 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit.This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPIn_CLK SPIn_MISO and SPIn_MOSI..Note: In Slave 3-wire mode the SS_LTRIG SPI_SSR[4].." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" line.long 0xC "SPI_FIFO_CTL,SPI FIFO Control Register" bitfld.long 0xC 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "RX_THRESHOLD,Receive FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 21. "TIMEOUT_INTEN,Receive FIFO Time-Out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" bitfld.long 0xC 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" newline bitfld.long 0xC 3. "TX_INTEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0xC 2. "RX_INTEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0xC 1. "TX_CLR,Clear Transmit FIFO Buffer" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.." bitfld.long 0xC 0. "RX_CLR,Clear Receive FIFO Buffer" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.." line.long 0x10 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x10 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." rbitfld.long 0x10 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[27]." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x10 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[26]." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x10 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24]." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" newline rbitfld.long 0x10 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only).It is a mutual mirror bit of SPI_CNTRL[24]." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" bitfld.long 0x10 20. "TIMEOUT,Time-Out Interrupt Flag.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." newline bitfld.long 0x10 16. "IF,SPI Unit Transfer Interrupt Flag.It is a mutual mirror bit of SPI_CNTRL[16]..Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" hexmask.long.byte 0x10 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x10 11. "SLV_START_INTSTS,Slave Start Interrupt Status.It is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11]." "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode." rbitfld.long 0x10 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." newline bitfld.long 0x10 2. "RX_OVERRUN,Receive FIFO Overrun Status.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x10 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.." tree.end endif sif (cpuis("NUC029?GE")) tree "SPI0" base ad:0x40030000 group.long 0x0++0x17 line.long 0x0 "SPIx_CTL,SPI Control Register" bitfld.long 0x0 20. "DATDIR,Data Port Direction Control.This bit is used to select the data input/output direction in half-duplex transfer." "0: SPI data is input direction,1: SPI data is output direction" bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit.Note: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.." newline bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled" newline bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit (Master Only).This bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled" bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit.This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer" newline bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.." hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width.This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits." newline hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high" newline bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.." bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.." newline bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit.In Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1..Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled" line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider.The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation...where . is the peripheral.." line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register" bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled" bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled" newline bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled" bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled" newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled" bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity.This bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high" newline bitfld.long 0x8 0. "SS,Slave Selection Control (Master Only).If AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state..Keep..,1: set the SPIx_SS line to active state..SPIx_SS.." line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register" bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.." bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit.Note: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x10 28.--29. "TXTH,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3" bitfld.long 0x10 24.--25. "RXTH,Receive FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3" newline bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear.Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.." bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear.Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.." newline bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled" bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity.Note:.1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active..2. This bit should be set as 0 in I2S mode..3. When TX underflow event occurs SPIx_MISO pin state.." "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.." newline bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled" newline bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled" bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled" newline bitfld.long 0x10 1. "TXRST,Transmit Reset.Note: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.." bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit." line.long 0x14 "SPIx_STATUS,SPI Status Register" hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." newline rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only).Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST" bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag.When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL..Note1: This bit will be cleared by writing 1 to it..Note2: If reset slave's transmission.." "0: No effect,1: No data in Transmit FIFO and TX shift register.." newline rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only).Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled" newline bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun" newline rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.." rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" newline rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag.In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1..Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs" newline bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag.In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1..Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs" rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only).Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1" newline bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag.Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred" bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag.Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred" newline bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state" wgroup.long 0x20++0x3 line.long 0x0 "SPIx_TX,SPI Data Transmit Register" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.." rgroup.long 0x30++0x3 line.long 0x0 "SPIx_RX,SPI Data Receive Register" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.." group.long 0x60++0xB line.long 0x0 "SPIx_I2SCTL,I2S Control Register" bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?" bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit.Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled" newline bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit.Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode" newline bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit.If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled" bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit.If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled" newline bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit.If MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled" bitfld.long 0x0 8. "SLAVE,Slave Mode.I2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from the NUC029GE series to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and.." "0: Master mode,1: Slave mode" newline bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte" bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format" newline bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?" bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero" newline bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled" bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled" newline bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit.Note:.1. If this bit is enabled I2Sx_BCLK will start to output in Master mode..2. Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: I2S mode Enabled" line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register" hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider.The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:..where . is the frequency of I2S peripheral clock source which is defined in.." hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider.If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:.where. is the frequency of I2S peripheral clock.." line.long 0x8 "SPIx_I2SSTS,I2S Status Register" rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only).Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST" bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel" newline bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel" bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag.When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1..Note: This bit will be cleared by writing 1 to it." "0,1" newline rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only).Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled" newline bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to it." "0,1" newline rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.." rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" newline rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only).This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel" tree.end tree "SPI1" base ad:0x40034000 group.long 0x0++0x17 line.long 0x0 "SPIx_CTL,SPI Control Register" bitfld.long 0x0 20. "DATDIR,Data Port Direction Control.This bit is used to select the data input/output direction in half-duplex transfer." "0: SPI data is input direction,1: SPI data is output direction" bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit.Note: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.." newline bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled" newline bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit (Master Only).This bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled" bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit.This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer" newline bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.." hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width.This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits." newline hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high" newline bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.." bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.." newline bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit.In Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1..Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled" line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider.The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation...where . is the peripheral.." line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register" bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled" bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled" newline bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled" bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled" newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled" bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity.This bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high" newline bitfld.long 0x8 0. "SS,Slave Selection Control (Master Only).If AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state..Keep..,1: set the SPIx_SS line to active state..SPIx_SS.." line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register" bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.." bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit.Note: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x10 28.--29. "TXTH,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3" bitfld.long 0x10 24.--25. "RXTH,Receive FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3" newline bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear.Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.." bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear.Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.." newline bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled" bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity.Note:.1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active..2. This bit should be set as 0 in I2S mode..3. When TX underflow event occurs SPIx_MISO pin state.." "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.." newline bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled" bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled" newline bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled" bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled" newline bitfld.long 0x10 1. "TXRST,Transmit Reset.Note: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.." bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit." line.long 0x14 "SPIx_STATUS,SPI Status Register" hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." newline rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only).Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST" bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag.When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL..Note1: This bit will be cleared by writing 1 to it..Note2: If reset slave's transmission.." "0: No effect,1: No data in Transmit FIFO and TX shift register.." newline rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only).Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled" newline bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun" newline rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.." rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" newline rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag.In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1..Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs" newline bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag.In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1..Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs" rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only).Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1" newline bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag.Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred" bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag.Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred" newline bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag.Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state" wgroup.long 0x20++0x3 line.long 0x0 "SPIx_TX,SPI Data Transmit Register" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.." rgroup.long 0x30++0x3 line.long 0x0 "SPIx_RX,SPI Data Receive Register" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.." group.long 0x60++0xB line.long 0x0 "SPIx_I2SCTL,I2S Control Register" bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?" bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit.Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled" newline bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit.Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode" newline bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit.If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled" bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit.If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled" newline bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit.If MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled" bitfld.long 0x0 8. "SLAVE,Slave Mode.I2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from the NUC029GE series to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and.." "0: Master mode,1: Slave mode" newline bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte" bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format" newline bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?" bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero" newline bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled" bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled" newline bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit.Note:.1. If this bit is enabled I2Sx_BCLK will start to output in Master mode..2. Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: I2S mode Enabled" line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register" hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider.The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:..where . is the frequency of I2S peripheral clock source which is defined in.." hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider.If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:.where. is the frequency of I2S peripheral clock.." line.long 0x8 "SPIx_I2SSTS,I2S Status Register" rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only).Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST" bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel" newline bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel" bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag.When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1..Note: This bit will be cleared by writing 1 to it." "0,1" newline rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.." rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full" newline rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty" rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only).Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled" newline bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag.Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.." bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag.When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to it." "0,1" newline rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.." rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full" newline rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty" rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only).This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel" tree.end endif tree.end sif (cpuis("NUC029?GE")) tree "SYS (System Control Registers)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "SYS_PDID,Part Device Identification Number Register" hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only).This register reflects device part number code. Software can read this register to identify which device is used." group.long 0x4++0xF line.long 0x0 "SYS_RSTSTS,System Reset Status Register" bitfld.long 0x0 8. "CPULKRF,CPU Lockup Reset Flag.The CPU lockup reset flag is set by hardware If Cortex-M0 lockup happened..Note: This bit can be cleared by software writing '1'." "0: No reset from CPU lockup happened,1: The Cortex-M0 lockup happened and chip is reset" bitfld.long 0x0 7. "CPURF,CPU Reset Flag.The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC)..Note: This bit can be cleared by software writing '1'." "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by software.." newline bitfld.long 0x0 5. "MCURF,MCU Reset Flag.The MCU reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source..Note: This bit can be cleared by software writing '1'." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." bitfld.long 0x0 4. "BODRF,BOD Reset Flag.The BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source..Note: This bit can be cleared by software writing '1'." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.." newline bitfld.long 0x0 3. "LVRF,LVR Reset Flag.The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source..Note: This bit can be cleared by software writing '1'." "0: No reset from LVR,1: LVR controller had issued the reset signal to.." bitfld.long 0x0 2. "WDTRF,WDT Reset Flag.The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source..Note1: This bit can be cleared by software writing '1'..Note2: Watchdog Timer register.." "0: No reset from watchdog timer or window watchdog..,1: The watchdog timer or window watchdog timer had.." newline bitfld.long 0x0 1. "PINRF,nRESET Pin Reset Flag.The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source..Note: This bit can be cleared by software writing '1'." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.." bitfld.long 0x0 0. "PORF,POR Reset Flag.The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source..Note: This bit can be cleared by software writing '1'." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.." line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0" bitfld.long 0x4 7. "CRCRST,CRC Calculation Controller Reset (Write Protect).Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state..Note: This bit is write protected. Refer to the.." "0: CRC calculation controller normal operation,1: CRC calculation controller reset" bitfld.long 0x4 4. "HDIVRST,HDIV Controller Reset (Write Protect).Set this bit to 1 will generate a reset signal to the HDIV controller. User needs to set this bit to 0 to release from the reset state..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: HDIV controller normal operation,1: HDIV controller reset" newline bitfld.long 0x4 3. "EBIRST,EBI Controller Reset (Write Protect).Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: EBI controller normal operation,1: EBI controller reset" bitfld.long 0x4 2. "PDMARST,PDMA Controller Reset (Write Protect).Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA controller normal operation,1: PDMA controller reset" newline bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect).Setting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles..Note: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset" bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect).Setting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles..The CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset" line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1" bitfld.long 0x8 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset" bitfld.long 0x8 27. "USBDRST,USB Device Controller Reset" "0: USB device controller normal operation,1: USB device controller reset" newline bitfld.long 0x8 22. "ACMP01RST,ACMP01 Controller Reset" "0: ACMP01 controller normal operation,1: ACMP01 controller reset" bitfld.long 0x8 21. "PWM1RST,PWM1 Controller Reset" "0: PWM1 controller normal operation,1: PWM1 controller reset" newline bitfld.long 0x8 20. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset" bitfld.long 0x8 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset" newline bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset" bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset" newline bitfld.long 0x8 13. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset" bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset" newline bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset" bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset" newline bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset" bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset" newline bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset" bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset" newline bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset" line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2" bitfld.long 0xC 10. "USCI2RST,USCI2 Controller Reset" "0: USCI2 controller normal operation,1: USCI2 controller reset" bitfld.long 0xC 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset" newline bitfld.long 0xC 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset" bitfld.long 0xC 1. "SC1RST,SC1 Controller Reset" "0: SC1 controller normal operation,1: SC1 controller reset" newline bitfld.long 0xC 0. "SC0RST,SC0 Controller Reset" "0: SC0 controller normal operation,1: SC0 controller reset" group.long 0x18++0x7 line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register" bitfld.long 0x0 25.--27. "VDETDGSEL,Voltage Detector Output De-glitch Time Select (Write Protect).Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: VDET output is sampled by VDET clock,1: 16 system clock (HCLK),?,?,?,?,?,?" bitfld.long 0x0 24. "VDETOUT,Voltage Detector Output Status.It means the detected voltage is lower than Bandgap. If the VDETEN is 0 VDET function disabled this bit always responds 0." "0: VDET output status is 0,1: VDET output status is 1" newline bitfld.long 0x0 19. "VDETIF,Voltage Detector Interrupt Flag.Note: This bit can be cleared by software writing '1'." "0: VDET does not detect any voltage draft at..,1: When VDET detects the external pin is dropped.." bitfld.long 0x0 18. "VDETIEN,Voltage Detector Interrupt Enable Bit" "0: VDET interrupt Disabled,1: VDET interrupt Enabled" newline bitfld.long 0x0 17. "VDETPINSEL,Voltage Detector External Input Voltage Pin Selection.Note1: If VDET_P0 is selected multi-function pin must be selected correctly in PB0MFP (SYS_GPB_MFPL[3:0])..Note2: If VDET_P1 is selected multi-function pin must be selected correctly in.." "0: The input voltage is from VDET_P0 (PB.0),1: The input voltage is from VDET_P1 (PB.1)" bitfld.long 0x0 16. "VDETEN,Voltage Detector Enable Bit.Note1: This function is still active in whole chip power-down mode..Note2: This function need use LIRC or LXT as VDET clock source which is selected in VDETCKSEL (CLK_BODCLK[0])..Note2: The input pin for VDET detect.." "0: VDET detect external input voltage function..,1: VDET detect external input voltage function.." newline bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect).Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?" bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect).Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),?,?,?,?,?,?" newline bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect).The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default..Note1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled" bitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status.It means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function disabled this bit always responds 0." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1" newline bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect).Note1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response..Note2: This bit is write protected. Refer to the SYS_REGLCTL.." "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled" bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag.Note: This bit can be cleared by software writing '1'." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.." newline bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect).The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit..Note1: .While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled" bitfld.long 0x0 1.--2. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect).The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21])..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-Out Detector threshold voltage is 2.2V,1: Brown-Out Detector threshold voltage is 2.7V,?,?" newline bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect).The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [23])..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled" line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register" bitfld.long 0x4 1. "VBATUGEN,VBAT Unity Gain Buffer Enable Bit.This bit is used to enable/disable VBAT unity gain buffer function..Note: After this bit is set to 1 the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. Please refer.." "0: VBAT unity gain buffer function Disabled (default),1: VBAT unity gain buffer function Enabled" bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Bit.This bit is used to enable/disable temperature sensor function..Note: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled" group.long 0x24++0x7 line.long 0x0 "SYS_PORCTL,Power-on Reset Controller Register" hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect).When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.." line.long 0x4 "SYS_VREFCTL,VREF Control Register" hexmask.long.byte 0x4 0.--4. 1. "VREFCTL,Int_VREF Control Bits (Write Protect).Note: These bit are write protected. Refer to the SYS_REGLCTL register." group.long 0x30++0x2B line.long 0x0 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register" hexmask.long.byte 0x0 28.--31. 1. "PA7MFP,PA.7 Multi-function Pin Selection" hexmask.long.byte 0x0 24.--27. 1. "PA6MFP,PA.6 Multi-function Pin Selection" newline hexmask.long.byte 0x0 20.--23. 1. "PA5MFP,PA.5 Multi-function Pin Selection" hexmask.long.byte 0x0 16.--19. 1. "PA4MFP,PA.4 Multi-function Pin Selection" newline hexmask.long.byte 0x0 12.--15. 1. "PA3MFP,PA.3 Multi-function Pin Selection" hexmask.long.byte 0x0 8.--11. 1. "PA2MFP,PA.2 Multi-function Pin Selection" newline hexmask.long.byte 0x0 4.--7. 1. "PA1MFP,PA.1 Multi-function Pin Selection" hexmask.long.byte 0x0 0.--3. 1. "PA0MFP,PA.0 Multi-function Pin Selection" line.long 0x4 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register" hexmask.long.byte 0x4 28.--31. 1. "PA15MFP,PA.15 Multi-function Pin Selection" hexmask.long.byte 0x4 24.--27. 1. "PA14MFP,PA.14 Multi-function Pin Selection" newline hexmask.long.byte 0x4 20.--23. 1. "PA13MFP,PA.13 Multi-function Pin Selection" hexmask.long.byte 0x4 16.--19. 1. "PA12MFP,PA.12 Multi-function Pin Selection" newline hexmask.long.byte 0x4 12.--15. 1. "PA11MFP,PA.11 Multi-function Pin Selection" hexmask.long.byte 0x4 8.--11. 1. "PA10MFP,PA.10 Multi-function Pin Selection" newline hexmask.long.byte 0x4 4.--7. 1. "PA9MFP,PA.9 Multi-function Pin Selection" hexmask.long.byte 0x4 0.--3. 1. "PA8MFP,PA.8 Multi-function Pin Selection" line.long 0x8 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register" hexmask.long.byte 0x8 28.--31. 1. "PB7MFP,PB.7 Multi-function Pin Selection" hexmask.long.byte 0x8 24.--27. 1. "PB6MFP,PB.6 Multi-function Pin Selection" newline hexmask.long.byte 0x8 20.--23. 1. "PB5MFP,PB.5 Multi-function Pin Selection" hexmask.long.byte 0x8 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection" newline hexmask.long.byte 0x8 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection" hexmask.long.byte 0x8 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection" newline hexmask.long.byte 0x8 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection" hexmask.long.byte 0x8 0.--3. 1. "PB0MFP,PB.0 Multi-function Pin Selection" line.long 0xC "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register" hexmask.long.byte 0xC 28.--31. 1. "PB15MFP,PB.15 Multi-function Pin Selection" hexmask.long.byte 0xC 24.--27. 1. "PB14MFP,PB.14 Multi-function Pin Selection" newline hexmask.long.byte 0xC 20.--23. 1. "PB13MFP,PB.13 Multi-function Pin Selection" hexmask.long.byte 0xC 16.--19. 1. "PB12MFP,PB.12 Multi-function Pin Selection" newline hexmask.long.byte 0xC 12.--15. 1. "PB11MFP,PB.11 Multi-function Pin Selection" hexmask.long.byte 0xC 8.--11. 1. "PB10MFP,PB.10 Multi-function Pin Selection" newline hexmask.long.byte 0xC 4.--7. 1. "PB9MFP,PB.9 Multi-function Pin Selection" hexmask.long.byte 0xC 0.--3. 1. "PB8MFP,PB.8 Multi-function Pin Selection" line.long 0x10 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register" hexmask.long.byte 0x10 28.--31. 1. "PC7MFP,PC.7 Multi-function Pin Selection" hexmask.long.byte 0x10 24.--27. 1. "PC6MFP,PC.6 Multi-function Pin Selection" newline hexmask.long.byte 0x10 20.--23. 1. "PC5MFP,PC.5 Multi-function Pin Selection" hexmask.long.byte 0x10 16.--19. 1. "PC4MFP,PC.4 Multi-function Pin Selection" newline hexmask.long.byte 0x10 12.--15. 1. "PC3MFP,PC.3 Multi-function Pin Selection" hexmask.long.byte 0x10 8.--11. 1. "PC2MFP,PC.2 Multi-function Pin Selection" newline hexmask.long.byte 0x10 4.--7. 1. "PC1MFP,PC.1 Multi-function Pin Selection" hexmask.long.byte 0x10 0.--3. 1. "PC0MFP,PC.0 Multi-function Pin Selection" line.long 0x14 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register" hexmask.long.byte 0x14 28.--31. 1. "PC15MFP,PC15 Multi-function Pin Selection" hexmask.long.byte 0x14 24.--27. 1. "PC14MFP,PC14 Multi-function Pin Selection" newline hexmask.long.byte 0x14 20.--23. 1. "PC13MFP,PC13 Multi-function Pin Selection" hexmask.long.byte 0x14 16.--19. 1. "PC12MFP,PC12 Multi-function Pin Selection" newline hexmask.long.byte 0x14 12.--15. 1. "PC11MFP,PC11 Multi-function Pin Selection" hexmask.long.byte 0x14 8.--11. 1. "PC10MFP,PC10 Multi-function Pin Selection" newline hexmask.long.byte 0x14 4.--7. 1. "PC9MFP,PC9 Multi-function Pin Selection" hexmask.long.byte 0x14 0.--3. 1. "PC8MFP,PC8 Multi-function Pin Selection" line.long 0x18 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register" hexmask.long.byte 0x18 28.--31. 1. "PD7MFP,PD.7 Multi-function Pin Selection" hexmask.long.byte 0x18 24.--27. 1. "PD6MFP,PD.6 Multi-function Pin Selection" newline hexmask.long.byte 0x18 20.--23. 1. "PD5MFP,PD.5 Multi-function Pin Selection" hexmask.long.byte 0x18 16.--19. 1. "PD4MFP,PD.4 Multi-function Pin Selection" newline hexmask.long.byte 0x18 12.--15. 1. "PD3MFP,PD.3 Multi-function Pin Selection" hexmask.long.byte 0x18 8.--11. 1. "PD2MFP,PD.2 Multi-function Pin Selection" newline hexmask.long.byte 0x18 4.--7. 1. "PD1MFP,PD.1 Multi-function Pin Selection" hexmask.long.byte 0x18 0.--3. 1. "PD0MFP,PD.0 Multi-function Pin Selection" line.long 0x1C "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register" hexmask.long.byte 0x1C 28.--31. 1. "PD15MFP,PD.15 Multi-function Pin Selection" hexmask.long.byte 0x1C 24.--27. 1. "PD14MFP,PD.14 Multi-function Pin Selection" newline hexmask.long.byte 0x1C 20.--23. 1. "PD13MFP,PD.13 Multi-function Pin Selection" hexmask.long.byte 0x1C 16.--19. 1. "PD12MFP,PD.12 Multi-function Pin Selection" newline hexmask.long.byte 0x1C 12.--15. 1. "PD11MFP,PD.11 Multi-function Pin Selection" hexmask.long.byte 0x1C 8.--11. 1. "PD10MFP,PD.10 Multi-function Pin Selection" newline hexmask.long.byte 0x1C 4.--7. 1. "PD9MFP,PD.9 Multi-function Pin Selection" hexmask.long.byte 0x1C 0.--3. 1. "PD8MFP,PD.8 Multi-function Pin Selection" line.long 0x20 "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register" hexmask.long.byte 0x20 28.--31. 1. "PE7MFP,PE.7 Multi-function Pin Selection" hexmask.long.byte 0x20 24.--27. 1. "PE6MFP,PE.6 Multi-function Pin Selection" newline hexmask.long.byte 0x20 20.--23. 1. "PE5MFP,PE.5 Multi-function Pin Selection" hexmask.long.byte 0x20 16.--19. 1. "PE4MFP,PE.4 Multi-function Pin Selection" newline hexmask.long.byte 0x20 12.--15. 1. "PE3MFP,PE.3 Multi-function Pin Selection" hexmask.long.byte 0x20 8.--11. 1. "PE2MFP,PE.2 Multi-function Pin Selection" newline hexmask.long.byte 0x20 4.--7. 1. "PE1MFP,PE.1 Multi-function Pin Selection" hexmask.long.byte 0x20 0.--3. 1. "PE0MFP,PE.0 Multi-function Pin Selection" line.long 0x24 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register" hexmask.long.byte 0x24 20.--23. 1. "PE13MFP,PE.13 Multi-function Pin Selection" hexmask.long.byte 0x24 16.--19. 1. "PE12MFP,PE.12 Multi-function Pin Selection" newline hexmask.long.byte 0x24 12.--15. 1. "PE11MFP,PE.11 Multi-function Pin Selection" hexmask.long.byte 0x24 8.--11. 1. "PE10MFP,PE.10 Multi-function Pin Selection" newline hexmask.long.byte 0x24 4.--7. 1. "PE9MFP,PE.9 Multi-function Pin Selection" hexmask.long.byte 0x24 0.--3. 1. "PE8MFP,PE.8 Multi-function Pin Selection" line.long 0x28 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register" hexmask.long.byte 0x28 28.--31. 1. "PF7MFP,PF.7 Multi-function Pin Selection" hexmask.long.byte 0x28 24.--27. 1. "PF6MFP,PF.6 Multi-function Pin Selection" newline hexmask.long.byte 0x28 20.--23. 1. "PF5MFP,PF.5 Multi-function Pin Selection" hexmask.long.byte 0x28 16.--19. 1. "PF4MFP,PF.4 Multi-function Pin Selection.The default value is set by Flash controller user configuration register CFGXT1(CONFIG0[27]) bit." newline hexmask.long.byte 0x28 12.--15. 1. "PF3MFP,PF.3 Multi-function Pin Selection.The default value is set by Flash controller user configuration register CFGXT1(CONFIG0[27]) bit." hexmask.long.byte 0x28 8.--11. 1. "PF2MFP,PF.2 Multi-function Pin Selection" newline hexmask.long.byte 0x28 4.--7. 1. "PF1MFP,PF.1 Multi-function Pin Selection" hexmask.long.byte 0x28 0.--3. 1. "PF0MFP,PF.0 Multi-function Pin Selection" group.long 0x80++0xB line.long 0x0 "SYS_IRCTCTL0,HIRC0 Trim Control Register" bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from USB SOF.." bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." newline bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count.This field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked..Once the HIRC0 locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?" bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection.This field defines that trim value calculation is based on how many clocks of reference clock (32.768 kHz LXT)..Note: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" newline bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection.This field indicates the target frequency of internal high speed RC oscillator 0 (HIRC0) auto trim..During auto trim operation if clock error detected with CESTOPEN(SYS_IRCTCTL0[8]) is set to 1 or trim retry limitation.." "0: Disable HIRC0 auto trim function,1: Enable HIRC0 auto trim function and trim HIRC to..,?,?" line.long 0x4 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register" bitfld.long 0x4 10. "CLKEIEN1,HIRC1 Clock Error Interrupt Enable Bit.This bit controls if CPU would get an interrupt while HIRC1 clock is inaccuracy during auto trim operation..If this bit is set to1 and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation an.." "0: Disable CLKERRIF(SYS_IRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTSTS[2]) status to.." bitfld.long 0x4 9. "TFAILIEN1,HIRC1 Trim Failure Interrupt Enable Bit.This bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL1[1:0])..If.." "0: Disable TFAILIF(SYS_IRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger.." newline bitfld.long 0x4 2. "CLKEIEN,HIRC0 Clock Error Interrupt Enable Bit.This bit controls if CPU would get an interrupt while HIRC0 clock is inaccuracy during auto trim operation..If this bit is set to1 and CLKERRIF(SYS_IRCTSTS0[2]) is set during auto trim operation an.." "0: Disable CLKERRIF(SYS_IRCTSTS0[2]) status to..,1: Enable CLKERRIF(SYS_IRCTSTS0[2]) status to.." bitfld.long 0x4 1. "TFAILIEN,HIRC0 Trim Failure Interrupt Enable Bit.This bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL0[1:0])..If.." "0: Disable TFAILIF(SYS_IRCTSTS0[1]) status to..,1: Enable TFAILIF(SYS_IRCTSTS0[1]) status to.." line.long 0x8 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register" bitfld.long 0x8 10. "CLKERRIF1,HIRC1 Clock Error Interrupt Status.When the frequency of SOF or 48 MHz internal high speed RC oscillator 1 (HIRC1) is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is inaccuracy.Once this.." "0: HIRC1 Clock frequency is accuracy,1: HIRC1 Clock frequency is inaccuracy" bitfld.long 0x8 9. "TFAILIF1,HIRC1 Trim Failure Interrupt Status.This bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and.." "0: HIRC1 trim value update limitation count does..,1: HIRC1 trim value update limitation count reached.." newline bitfld.long 0x8 8. "FREQLOCK1,HIRC1 Frequency Lock Status.This bit indicates the HIRC1 frequency is locked..This is a status bit and doesn't trigger any interrupt." "0: The internal high-speed RC oscillator 1..,1: The internal high-speed RC oscillator 1.." bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status.When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator 0 (HIRC0) is shift larger to unreasonable value this bit will be set and to be an.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy" newline bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status.This bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_iRCTCTL0[1:0]).." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.." bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status.This bit indicates the HIRC0 frequency is locked..This is a status bit and doesn't trigger any interrupt." "0: The internal high-speed RC oscillator 0..,1: The internal high-speed RC oscillator 0.." group.long 0x90++0x3 line.long 0x0 "SYS_IRCTCTL1,HIRC1 Trim Control Register" bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from USB SOF.." bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." newline bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count.This field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked..Once the HIRC1 locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?" bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection.This field defines that trim value calculation is based on how many clocks of reference clock (1 kHz SOF)..Note: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" newline bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection.This field indicates the target frequency of internal high speed RC oscillator 1 (HIRC 1) auto trim..During auto trim operation if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry.." "0: Disable HIRC1 auto trim function,1: Reserved.,?,?" group.long 0xC0++0x3 line.long 0x0 "SYS_MODCTL,Modulation Control Register" bitfld.long 0x0 4.--6. "MODPWMSEL,PWM0 Channel Select for Modulation.Select the PWM0 channel to modulate with the UART1_TXD..Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1." "0: PWM0 channel 0 modulate with UART1_TXD,1: PWM0 channel 1 modulate with UART1_TXD,?,?,?,?,?,?" bitfld.long 0x0 1. "MODH,Modulation at Data High.Select modulation pulse(PWM) at UART1_TXD high or low" "0: Modulation pulse at UART1_TXD low,1: Modulation pulse at UART1_TXD high" newline bitfld.long 0x0 0. "MODEN,Modulation Function Enable Bit.This bit enables modulation funcion by modulating with PWM channel output and UART1_TXD." "0: Modulation Function Disabled,1: Modulation Function Enabled" group.long 0xD0++0x3 line.long 0x0 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register" bitfld.long 0x0 4. "USBBIST,USB BIST Enable Bit (Write Protect).This bit enables BIST test for USB RAM.Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System USB BIST Disabled,1: System USB BIST Enabled" bitfld.long 0x0 2. "CRBIST,CACHE BIST Enable Bit (Write Protect).This bit enables BIST test for CACHE RAM.Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System CACHE BIST Disabled,1: System CACHE BIST Enabled" newline bitfld.long 0x0 0. "SRBIST,SRAM BIST Enable Bit (Write Protect).This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_4FFF.Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: System SRAM BIST Disabled,1: System SRAM BIST Enabled" rgroup.long 0xD4++0x3 line.long 0x0 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register" bitfld.long 0x0 20. "USBBEND,USB SRAM BIST Test Finish" "0: USB SRAM BIST is active,1: USB SRAM BIST test finish" bitfld.long 0x0 18. "CRBEND,CACHE SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finish" newline bitfld.long 0x0 16. "SRBEND,SRAM BIST Test Finish" "0: System SRAM BIST active,1: System SRAM BIST finish" bitfld.long 0x0 4. "USBBEF,USB SRAM BIST Fail Flag" "0: USB SRAM BIST test pass,1: USB SRAM BIST test fail" newline bitfld.long 0x0 2. "CRBISTEF,CACHE SRAM BIST Fail Flag" "0: System CACHE RAM BIST test pass,1: System CACHE RAM BIST test fail" bitfld.long 0x0 0. "SRBISTEF,System SRAM BIST Fail Flag" "0: System SRAM BIST test pass,1: System SRAM BIST test fail" group.long 0x100++0x3 line.long 0x0 "SYS_REGLCTL,Register Lock Control Register" hexmask.long.byte 0x0 1.--7. 1. "REGLCTL,Register Lock Control Code (Write Only).Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.." rbitfld.long 0x0 0. "REGLCTL0,Register Lock Control Disable Index (Read Only).The Protected registers are:.SYS_IPRST0: address 0x5000_0008Reserved..SYS_BODCTL: address 0x5000_0018.SYS_PORCTL: address 0x5000_0024.SYS_VREFCTL: address 0x5000_0028.SYS_SRAM_BISTCTL:.." "0: Write-protection Enabled for writing protected..,1: Write-protection Disabled for writing protected.." rgroup.long 0x114++0x3 line.long 0x0 "SYS_TSOFFSET,Temperature Sensor Offset Register" hexmask.long.word 0x0 0.--11. 1. "VTEMP,Temperature Sensor Offset Value .This field reflects temperature sensor output voltage offset at 25oC from Flash.Reserved." tree.end endif sif (cpuis("NUC029?AE")) base ad:0x40010000 elif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) base ad:0x0 endif tree "TIMER" sif (cpuis("NUC029?AE")) group.long 0x0++0xB line.long 0x0 "TCSR0,Timer0 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Control (Write Protect).Timer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Control" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Control.If this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0,1,2,3" newline bitfld.long 0x0 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Control.This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description." "0: External event counter mode Disabled,1: External event counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake-Up Enable Control.When WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 19. "CAP_SRC,Capture Pin Source Selection" "0: Capture Function source is from TxEX pin,1: Capture Function source is from ACMPx output.." bitfld.long 0x0 18. "TOUT_PIN,Toggle Out Pin Selection.When Timer is set to toggle mode " "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin" newline bitfld.long 0x0 17. "PERIODIC_SEL,Periodic Mode Behavior Selection" "0: In One-shot or Periodic mode when write new TCMP..,1: In One-shot or Periodic mode when write new TCMP.." bitfld.long 0x0 16. "TDR_EN,Data Load Enable Control.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." newline hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter" line.long 0x4 "TCMPR0,Timer0 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown state." line.long 0x8 "TISR0,Timer0 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-up Flag.This bit indicates the interrupt wake-up flag status of Time..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0xC++0x7 line.long 0x0 "TDR0,Timer0 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSRx[16]) is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP0,Timer0 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x14++0x7 line.long 0x0 "TEXCON0,Timer0 External Control Register" bitfld.long 0x0 8. "CAP_MODE,Capture Mode Selection" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control" "0: Tx (x = 0~1) pin de-bounce Disabled,1: Tx (x = 0~1) pin de-bounce Enabled" newline bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control" "0: TxEX (x = 0~1) pin de-bounce Disabled,1: TxEX (x = 0~1) pin de-bounce Enabled" bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Control.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TxEX (x = 0~1) pin detection Interrupt Disabled,1: TxEX (x = 0~1) pin detection Interrupt Enabled" newline bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TxEX (x = 0~1) pin is using to..,1: Transition on TxEX (x = 0~1) pin is using to.." bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Control" "0: RSTCAPSEL function of TxEX (x = 0~1) pin will be..,1: RSTCAPSEL function of TxEX (x = 0~1) pin is active" newline bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detection" "0: A 1 to 0 transition on TxEX (x = 0~1) will be..,1: A 0 to 1 transition on TxEX (x = 0~1) will be..,?,?" bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection" "0: A falling edge of Tx (x = 0~1) pin will be counted,1: A rising edge of Tx (x = 0~1) pin will be counted" line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag.This bit indicates the external capture interrupt flag status.Note: This bit is cleared by writing 1 to it" "0: TxEX (x = 0 1) pin interrupt did not occur,1: TxEX (x = 0 1) pin interrupt occurred" group.long 0x20++0xB line.long 0x0 "TCSR1,Timer1 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Control (Write Protect).Timer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Control" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Control.If this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0,1,2,3" newline bitfld.long 0x0 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Control.This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description." "0: External event counter mode Disabled,1: External event counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake-Up Enable Control.When WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 19. "CAP_SRC,Capture Pin Source Selection" "0: Capture Function source is from TxEX pin,1: Capture Function source is from ACMPx output.." bitfld.long 0x0 18. "TOUT_PIN,Toggle Out Pin Selection.When Timer is set to toggle mode " "0: Time0/1 toggle output pin is T0/T1 pin,1: Time0/1 toggle output pin is T0EX/T1EX pin" newline bitfld.long 0x0 17. "PERIODIC_SEL,Periodic Mode Behavior Selection" "0: In One-shot or Periodic mode when write new TCMP..,1: In One-shot or Periodic mode when write new TCMP.." bitfld.long 0x0 16. "TDR_EN,Data Load Enable Control.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." newline hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter" line.long 0x4 "TCMPR1,Timer1 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown state." line.long 0x8 "TISR1,Timer1 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-up Flag.This bit indicates the interrupt wake-up flag status of Time..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x2C++0x7 line.long 0x0 "TDR1,Timer1 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSRx[16]) is set to 1 TDR register value will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP1,Timer1 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF flag is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x34++0x7 line.long 0x0 "TEXCON1,Timer1 External Control Register" bitfld.long 0x0 8. "CAP_MODE,Capture Mode Selection" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-bounce Enable Control" "0: Tx (x = 0~1) pin de-bounce Disabled,1: Tx (x = 0~1) pin de-bounce Enabled" newline bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-bounce Enable Control" "0: TxEX (x = 0~1) pin de-bounce Disabled,1: TxEX (x = 0~1) pin de-bounce Enabled" bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Control.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TxEX (x = 0~1) pin detection Interrupt Disabled,1: TxEX (x = 0~1) pin detection Interrupt Enabled" newline bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TxEX (x = 0~1) pin is using to..,1: Transition on TxEX (x = 0~1) pin is using to.." bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Control" "0: RSTCAPSEL function of TxEX (x = 0~1) pin will be..,1: RSTCAPSEL function of TxEX (x = 0~1) pin is active" newline bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detection" "0: A 1 to 0 transition on TxEX (x = 0~1) will be..,1: A 0 to 1 transition on TxEX (x = 0~1) will be..,?,?" bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection" "0: A falling edge of Tx (x = 0~1) pin will be counted,1: A rising edge of Tx (x = 0~1) pin will be counted" line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag.This bit indicates the external capture interrupt flag status.Note: This bit is cleared by writing 1 to it" "0: TxEX (x = 0 1) pin interrupt did not occur,1: TxEX (x = 0 1) pin interrupt occurred" endif sif (cpuis("NUC029?AN")) tree "TMR01" base ad:0x40010000 group.long 0x0++0xB line.long 0x0 "TCSR0,Timer0 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected).TIMER counter will keep going no matter ICE debug mode acknowledged or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR." "0: Disable timer Interrupt,1: Enable timer Interrupt" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0,1,2,3" newline bitfld.long 0x0 26. "CRST,Timer Reset Bit.Set this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0." "0: No effect,1: Reset Timer's pre-scaled counter internal 24-bit.." rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read only).This bit indicates the up-timer status." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is the counter mode enable bit. When Timer is used as an event counter this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of.." "0: Disable counter mode,1: Enable counter mode" bitfld.long 0x0 23. "WAKE_EN,Wake up Enable.When WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 22. "CAP_SRC,Capture Function Source" "0: Capture Function source is from TxEX (Timer..,1: Capture Function source is from ACMP(Analog.." bitfld.long 0x0 21. "TOGGLE_PIN,Toggle Mode Output PIN" "0: Toggle mode output to Tx (Timer Event Count Pin),1: Toggle mode output to TxEX (Timer External Pin)" newline bitfld.long 0x0 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable.When users update TCMP TDR will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is enabled" bitfld.long 0x0 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable.This bit controls if the inter-timer trigger mode is enabled..If inter-timer trigger mode is enabled the TIMER0/TIMER2 will be in counter mode and counting with external clock source or event. And .." "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update disable,1: Timer Data Register update enable" hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Pre-scale Counter" line.long 0x4 "TCMPR0,Timer0 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.Note1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state..Note2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP." line.long 0x8 "TISR0,Timer0 Interrupt Status Register" bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt status of Timer..TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit." "0,1" rgroup.long 0xC++0x7 line.long 0x0 "TDR0,Timer0 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1" line.long 0x4 "TCAP0,Timer0 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP. User can.." group.long 0x14++0x7 line.long 0x0 "TEXCON0,Timer0 External Control Register" bitfld.long 0x0 7. "TCDB,Timer Counter pin De-bounce enable bit.If this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" bitfld.long 0x0 6. "TEXDB,Timer External Capture pin De-bounce enable bit.If this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" newline bitfld.long 0x0 5. "TEXIEN,Timer External interrupt Enable Bit" "0: Disable timer External Interrupt,1: Enable timer External Interrupt" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable. .This bit enables the reset/capture function on the TEX pin." "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.." bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase .This bit indicates the external count pin phase." "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.." line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag.This bit indicates the external interrupt status of Timer..This bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred. It is.." "0,1" group.long 0x20++0xB line.long 0x0 "TCSR1,Timer1 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected).TIMER counter will keep going no matter ICE debug mode acknowledged or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR." "0: Disable timer Interrupt,1: Enable timer Interrupt" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0,1,2,3" newline bitfld.long 0x0 26. "CRST,Timer Reset Bit.Set this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0." "0: No effect,1: Reset Timer's pre-scaled counter internal 24-bit.." rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read only).This bit indicates the up-timer status." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is the counter mode enable bit. When Timer is used as an event counter this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of.." "0: Disable counter mode,1: Enable counter mode" bitfld.long 0x0 23. "WAKE_EN,Wake up Enable.When WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 22. "CAP_SRC,Capture Function Source" "0: Capture Function source is from TxEX (Timer..,1: Capture Function source is from ACMP(Analog.." bitfld.long 0x0 21. "TOGGLE_PIN,Toggle Mode Output PIN" "0: Toggle mode output to Tx (Timer Event Count Pin),1: Toggle mode output to TxEX (Timer External Pin)" newline bitfld.long 0x0 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable.When users update TCMP TDR will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is enabled" bitfld.long 0x0 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable.This bit controls if the inter-timer trigger mode is enabled..If inter-timer trigger mode is enabled the TIMER0/TIMER2 will be in counter mode and counting with external clock source or event. And .." "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update disable,1: Timer Data Register update enable" hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Pre-scale Counter" line.long 0x4 "TCMPR1,Timer1 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.Note1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state..Note2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP." line.long 0x8 "TISR1,Timer1 Interrupt Status Register" bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt status of Timer..TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit." "0,1" rgroup.long 0x2C++0x7 line.long 0x0 "TDR1,Timer1 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1" line.long 0x4 "TCAP1,Timer1 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP. User can.." group.long 0x34++0x7 line.long 0x0 "TEXCON1,Timer1 External Control Register" bitfld.long 0x0 7. "TCDB,Timer Counter pin De-bounce enable bit.If this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" bitfld.long 0x0 6. "TEXDB,Timer External Capture pin De-bounce enable bit.If this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" newline bitfld.long 0x0 5. "TEXIEN,Timer External interrupt Enable Bit" "0: Disable timer External Interrupt,1: Enable timer External Interrupt" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable. .This bit enables the reset/capture function on the TEX pin." "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.." bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase .This bit indicates the external count pin phase." "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.." line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag.This bit indicates the external interrupt status of Timer..This bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred. It is.." "0,1" tree.end tree "TMR23" base ad:0x40110000 group.long 0x0++0xB line.long 0x0 "TCSR2,Timer2 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected).TIMER counter will keep going no matter ICE debug mode acknowledged or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR." "0: Disable timer Interrupt,1: Enable timer Interrupt" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0,1,2,3" newline bitfld.long 0x0 26. "CRST,Timer Reset Bit.Set this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0." "0: No effect,1: Reset Timer's pre-scaled counter internal 24-bit.." rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read only).This bit indicates the up-timer status." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is the counter mode enable bit. When Timer is used as an event counter this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of.." "0: Disable counter mode,1: Enable counter mode" bitfld.long 0x0 23. "WAKE_EN,Wake up Enable.When WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 22. "CAP_SRC,Capture Function Source" "0: Capture Function source is from TxEX (Timer..,1: Capture Function source is from ACMP(Analog.." bitfld.long 0x0 21. "TOGGLE_PIN,Toggle Mode Output PIN" "0: Toggle mode output to Tx (Timer Event Count Pin),1: Toggle mode output to TxEX (Timer External Pin)" newline bitfld.long 0x0 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable.When users update TCMP TDR will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is enabled" bitfld.long 0x0 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable.This bit controls if the inter-timer trigger mode is enabled..If inter-timer trigger mode is enabled the TIMER0/TIMER2 will be in counter mode and counting with external clock source or event. And .." "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update disable,1: Timer Data Register update enable" hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Pre-scale Counter" line.long 0x4 "TCMPR2,Timer2 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.Note1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state..Note2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP." line.long 0x8 "TISR2,Timer2 Interrupt Status Register" bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt status of Timer..TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit." "0,1" rgroup.long 0xC++0x7 line.long 0x0 "TDR2,Timer2 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1" line.long 0x4 "TCAP2,Timer2 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP. User can.." group.long 0x14++0x7 line.long 0x0 "TEXCON2,Timer2 External Control Register" bitfld.long 0x0 7. "TCDB,Timer Counter pin De-bounce enable bit.If this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" bitfld.long 0x0 6. "TEXDB,Timer External Capture pin De-bounce enable bit.If this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" newline bitfld.long 0x0 5. "TEXIEN,Timer External interrupt Enable Bit" "0: Disable timer External Interrupt,1: Enable timer External Interrupt" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable. .This bit enables the reset/capture function on the TEX pin." "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.." bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase .This bit indicates the external count pin phase." "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.." line.long 0x4 "TEXISR2,Timer2 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag.This bit indicates the external interrupt status of Timer..This bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred. It is.." "0,1" group.long 0x20++0xB line.long 0x0 "TCSR3,Timer3 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected).TIMER counter will keep going no matter ICE debug mode acknowledged or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR." "0: Disable timer Interrupt,1: Enable timer Interrupt" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0,1,2,3" newline bitfld.long 0x0 26. "CRST,Timer Reset Bit.Set this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0." "0: No effect,1: Reset Timer's pre-scaled counter internal 24-bit.." rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read only).This bit indicates the up-timer status." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is the counter mode enable bit. When Timer is used as an event counter this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of.." "0: Disable counter mode,1: Enable counter mode" bitfld.long 0x0 23. "WAKE_EN,Wake up Enable.When WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU." "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 22. "CAP_SRC,Capture Function Source" "0: Capture Function source is from TxEX (Timer..,1: Capture Function source is from ACMP(Analog.." bitfld.long 0x0 21. "TOGGLE_PIN,Toggle Mode Output PIN" "0: Toggle mode output to Tx (Timer Event Count Pin),1: Toggle mode output to TxEX (Timer External Pin)" newline bitfld.long 0x0 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable.When users update TCMP TDR will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is enabled" bitfld.long 0x0 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable.This bit controls if the inter-timer trigger mode is enabled..If inter-timer trigger mode is enabled the TIMER0/TIMER2 will be in counter mode and counting with external clock source or event. And .." "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update disable,1: Timer Data Register update enable" hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Pre-scale Counter" line.long 0x4 "TCMPR3,Timer3 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.Note1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state..Note2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP." line.long 0x8 "TISR3,Timer3 Interrupt Status Register" bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt status of Timer..TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit." "0,1" rgroup.long 0x2C++0x7 line.long 0x0 "TDR3,Timer3 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1" line.long 0x4 "TCAP3,Timer3 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP. User can.." group.long 0x34++0x7 line.long 0x0 "TEXCON3,Timer3 External Control Register" bitfld.long 0x0 7. "TCDB,Timer Counter pin De-bounce enable bit.If this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" bitfld.long 0x0 6. "TEXDB,Timer External Capture pin De-bounce enable bit.If this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit." "0: Disable De-bounce,1: Enable De-bounce" newline bitfld.long 0x0 5. "TEXIEN,Timer External interrupt Enable Bit" "0: Disable timer External Interrupt,1: Enable timer External Interrupt" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable. .This bit enables the reset/capture function on the TEX pin." "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.." bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase .This bit indicates the external count pin phase." "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.." line.long 0x4 "TEXISR3,Timer3 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag.This bit indicates the external interrupt status of Timer..This bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred. It is.." "0,1" tree.end endif sif (cpuis("NUC029?DE")) tree "TMR01" base ad:0x40010000 group.long 0x0++0xB line.long 0x0 "TCSR0,Timer0 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit." "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode." "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset." "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status.." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.6.5.6 for detail description.." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 19. "TRG_PWM_EN,Trigger PWM Enable Bit.If this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.." "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out interrupt.." bitfld.long 0x0 18. "TRG_SRC_SEL,Trigger Source Select Bit.This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter." line.long 0x4 "TCMPR0,Timer0 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR0,Timer0 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0xC++0x7 line.long 0x0 "TDR0,Timer0 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP0,Timer0 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x14++0x7 line.long 0x0 "TEXCON0,Timer0 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection." "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin.." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection." "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin.." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" group.long 0x20++0xB line.long 0x0 "TCSR1,Timer1 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit." "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode." "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset." "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status.." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.6.5.6 for detail description.." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 19. "TRG_PWM_EN,Trigger PWM Enable Bit.If this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.." "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out interrupt.." bitfld.long 0x0 18. "TRG_SRC_SEL,Trigger Source Select Bit.This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter." line.long 0x4 "TCMPR1,Timer1 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR1,Timer1 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x2C++0x7 line.long 0x0 "TDR1,Timer1 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP1,Timer1 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x34++0x7 line.long 0x0 "TEXCON1,Timer1 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection." "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin.." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection." "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin.." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" tree.end tree "TMR23" base ad:0x40110000 group.long 0x0++0xB line.long 0x0 "TCSR2,Timer2 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit." "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode." "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset." "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status.." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.6.5.6 for detail description.." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 19. "TRG_PWM_EN,Trigger PWM Enable Bit.If this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.." "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out interrupt.." bitfld.long 0x0 18. "TRG_SRC_SEL,Trigger Source Select Bit.This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter." line.long 0x4 "TCMPR2,Timer2 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR2,Timer2 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0xC++0x7 line.long 0x0 "TDR2,Timer2 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP2,Timer2 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x14++0x7 line.long 0x0 "TEXCON2,Timer2 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection." "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin.." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection." "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin.." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR2,Timer2 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" group.long 0x20++0xB line.long 0x0 "TCSR3,Timer3 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit." "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode." "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset." "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status.." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.6.5.6 for detail description.." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 19. "TRG_PWM_EN,Trigger PWM Enable Bit.If this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered PWM.." "0: Timer interrupt trigger PWM Disabled,1: If TRG_SRC_SEL (TCSR[18]) = 0 time-out interrupt.." bitfld.long 0x0 18. "TRG_SRC_SEL,Trigger Source Select Bit.This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter." line.long 0x4 "TCMPR3,Timer3 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR3,Timer3 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x2C++0x7 line.long 0x0 "TDR3,Timer3 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP3,Timer3 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x34++0x7 line.long 0x0 "TEXCON3,Timer3 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection." "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin.." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection." "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin.." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR3,Timer3 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" tree.end endif sif (cpuis("NUC029?EE")) tree "TMR01" base ad:0x40010000 group.long 0x0++0xB line.long 0x0 "TCSR0,Timer0 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter" line.long 0x4 "TCMPR0,Timer0 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR0,Timer0 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0xC++0x7 line.long 0x0 "TDR0,Timer0 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP0,Timer0 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x14++0x7 line.long 0x0 "TEXCON0,Timer0 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" group.long 0x20++0xB line.long 0x0 "TCSR1,Timer1 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter" line.long 0x4 "TCMPR1,Timer1 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR1,Timer1 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x2C++0x7 line.long 0x0 "TDR1,Timer1 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP1,Timer1 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x34++0x7 line.long 0x0 "TEXCON1,Timer1 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" tree.end tree "TMR23" base ad:0x40110000 group.long 0x0++0xB line.long 0x0 "TCSR2,Timer2 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter" line.long 0x4 "TCMPR2,Timer2 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR2,Timer2 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0xC++0x7 line.long 0x0 "TDR2,Timer2 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP2,Timer2 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x14++0x7 line.long 0x0 "TEXCON2,Timer2 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR2,Timer2 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" group.long 0x20++0xB line.long 0x0 "TCSR3,Timer3 Control and Status Register" bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x0 29. "IE,Interrupt Enable Bit.If this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled" bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.." rbitfld.long 0x0 25. "CACT,Timer Active Status (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit .This bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description." "0: External counter mode Disabled,1: External counter mode Enabled" bitfld.long 0x0 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" newline bitfld.long 0x0 16. "TDR_EN,Data Load Enable Bit.When TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting." "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.." hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter" line.long 0x4 "TCMPR3,Timer3 Compare Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value.TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF flag will set to 1..Note1: Never write 0x0 or 0x1 in TCMP field or the core will run into unknown.." line.long 0x8 "TISR3,Timer3 Interrupt Status Register" bitfld.long 0x8 1. "TWF,Timer Wake-Up Flag.This bit indicates the interrupt wake-up flag status of Timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: TDR value matches the TCMP value" rgroup.long 0x2C++0x7 line.long 0x0 "TDR3,Timer3 Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register.If TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value." line.long 0x4 "TCAP3,Timer3 Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register.When TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately." group.long 0x34++0x7 line.long 0x0 "TEXCON3,Timer3 External Control Register" bitfld.long 0x0 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled" bitfld.long 0x0 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit.If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled" newline bitfld.long 0x0 5. "TEXIEN,Timer External Capture Interrupt Enable Bit.If TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1." "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled" bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.." newline bitfld.long 0x0 3. "TEXEN,Timer External Pin Function Enable Bit.This bit enables the RSTCAPSEL function on the TMx_EXT pin." "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active" bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?" newline bitfld.long 0x0 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection.This bit indicates the detection phase of TMx_EXT pin." "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted" line.long 0x4 "TEXISR3,Timer3 External Interrupt Status Register" bitfld.long 0x4 0. "TEXIF,Timer External Capture Interrupt Flag.This bit indicates the external capture interrupt flag status..When TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred" tree.end endif sif (cpuis("NUC029?GE")) tree "TMR01" base ad:0x40010000 group.long 0x0++0xF line.long 0x0 "TIMER0_CTL,Timer0 Control Register" bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit.Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit.Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit .This bit is for external counting pin function enabled. .Note: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" newline bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit.If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit.If the updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode Disabled,1: The behavior selection in periodic mode Enabled" newline bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit.Setting this bit will enable the inter-timer trigger capture function..The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter.Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value." line.long 0x4 "TIMER0_CMP,Timer0 Comparator Register" hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value.CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1..Note1: Never write 0x0 or 0x1 in CMPDAT field .." line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register" bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag.This bit indicates the interrupt wake-up flag status of timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value" line.long 0xC "TIMER0_CNT,Timer0 Data Register" rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only).This bit indicates if the counter reset operation active..When user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register.Read operation:.Read this register to get CNT value. For example:.If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24-bit counter value..If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT.." rgroup.long 0x10++0x3 line.long 0x0 "TIMER0_CAP,Timer0 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register.When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x14++0xF line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register" bitfld.long 0x0 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x= 0~3) pin,1: Event Counter input source is from USB internal.." bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect.When first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function.Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1.." bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" newline bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit.This bit enables the Tx_EXT capture pin input function." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.." line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register" bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag.This bit indicates the timer external capture interrupt flag status..Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" line.long 0x8 "TIMER0_TRGCTL,Timer0 Trigger Control Register" bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit.This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.." line.long 0xC "TIMER0_ALTCTL,Timer0 Alternative Control Register" bitfld.long 0xC 0. "FUNCSEL,Function Selection.Note: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function" group.long 0x40++0x1B line.long 0x0 "TIMER0_PWMCTL,Timer0 PWM Control Register" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect).PWM output pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x0 16. "OUTMODE,PWM Output Mode.This bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit.Note: If IMMLDEN is enabled CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.." newline bitfld.long 0x0 8. "CTRLD,Center Re-load.In up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1" bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?" bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running" line.long 0x4 "TIMER0_PWMCLKSRC,Timer0 PWM Counter Clock Source Register" bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select.The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event..Note: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?" line.long 0x8 "TIMER0_PWMCLKPSC,Timer0 PWM Counter Clock Pre-scale Register" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source." line.long 0xC "TIMER0_PWMCNTCLR,Timer0 PWM Clear Counter Register" bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit.It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.." line.long 0x10 "TIMER0_PWMPERIOD,Timer0 PWM Period Register" hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register.In up count type: PWM counter counts from 0 to PERIOD and restarts from 0..In down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD..In up-down count type: PWM counter counts from 0 to PERIOD then.." line.long 0x14 "TIMER0_PWMCMPDAT,Timer0 PWM Comparator Register" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.PWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert." line.long 0x18 "TIMER0_PWMDTCTL,Timer0 PWM Dead-time Control Register" bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.." bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect).Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following two formulas: .Note: This register is write protected. Refer to SYS_REGLCTL register." rgroup.long 0x5C++0x3 line.long 0x0 "TIMER0_PWMCNT,Timer0 PWM Counter Register" bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only).User can monitor CNT to know the current counter value in 16-bit period counter." group.long 0x60++0x1B line.long 0x0 "TIMER0_PWMMSKEN,Timer0 PWM Output Mask Enable Register" bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit.The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.." bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit.The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.." line.long 0x4 "TIMER0_PWMMSK,Timer0 PWM Output Mask Data Control Register" bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1" bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0" line.long 0x8 "TIMER0_PWMBNF,Timer0 PWM Brake Pin Noise Filter Register" bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,?,?" bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.." newline bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count.The fields is used to control the active noise filter sample time." "0,1,2,3,4,5,6,7" bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?" newline bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled" line.long 0xC "TIMER0_PWMFAILBRK,Timer0 PWM System Fail Brake Control Register" bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.." bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled" newline bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.." line.long 0x10 "TIMER0_PWMBRKCTL,Timer0 PWM Brake Control Register" bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when TIMERx_PWM brake..,?,?" bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when TIMERx_PWM brake..,?,?" newline bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.." bitfld.long 0x10 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as level-detect brake source..,1: TM_BRAKEx pin event as level-detect brake source.." newline bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.." bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.." newline bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.." bitfld.long 0x10 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as edge-detect brake source..,1: TM_BRAKEx pin event as edge-detect brake source.." newline bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.." bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.." line.long 0x14 "TIMER0_PWMPOLCTL,Timer0 PWM Pin Output Polar Control Register" bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled" bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled" line.long 0x18 "TIMER0_PWMPOEN,Timer0 PWM Pin Output Enable Register" bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode" bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode" wgroup.long 0x7C++0x3 line.long 0x0 "TIMER0_PWMSWBRK,Timer0 PWM Software Trigger Brake Control Register" bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" group.long 0x80++0x17 line.long 0x0 "TIMER0_PWMINTEN0,Timer0 PWM Interrupt Enable Register 0" bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit.Note: In up-down count type period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "TIMER0_PWMINTEN1,Timer0 PWM Interrupt Enable Register 1" bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled" bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled" line.long 0x8 "TIMER0_PWMINTSTS0,Timer0 PWM Interrupt Status Register 0" bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPDIF flag in down count type..Note2: This bit is cleared by writing.." "0,1" bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type...Note2: This bit is.." "0,1" newline bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches PERIOD..Note1: When in up-down count type PIF flag means the center point flag of current PWM period..Note2: This bit is cleared by writing 1 to it." "0,1" bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches zero..Note: This bit is cleared by writing 1 to it." "0,1" line.long 0xC "TIMER0_PWMINTSTS1,Timer0 PWM Interrupt Status Register 1" rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state" rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state" newline rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only).Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state" rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only).Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state" newline bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event did not happen,1: PWMx_CH1 level-detect brake event happened" bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event did not happen,1: PWMx_CH0 level-detect brake event happened" newline bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened" bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened" line.long 0x10 "TIMER0_PWMADCTS,Timer0 PWM ADC Trigger Source Select Register" bitfld.long 0x10 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion Disabled,1: PWM counter event trigger ADC conversion Enabled" bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),?,?,?,?,?,?" line.long 0x14 "TIMER0_PWMSCTL,Timer0 PWM Synchronous Control Register" bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select.Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0..Note2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.." bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?" wgroup.long 0x98++0x3 line.long 0x0 "TIMER0_PWMSTRG,Timer0 PWM Synchronous Trigger Register" bitfld.long 0x0 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only).PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1" group.long 0x9C++0x3 line.long 0x0 "TIMER0_PWMSTATUS,Timer0 PWM Status Register" bitfld.long 0x0 16. "ADCTRGF,Trigger ADC Start Conversion Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter event trigger ADC start conversion..,1: PWM counter event trigger ADC start conversion.." bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value" rgroup.long 0xA0++0x7 line.long 0x0 "TIMER0_PWMPBUF,Timer0 PWM Period Buffer Register" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only).Used as PERIOD active register." line.long 0x4 "TIMER0_PWMCMPBUF,Timer0 PWM Comparator Buffer Register" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only).Used as CMP active register." group.long 0x100++0xF line.long 0x0 "TIMER1_CTL,Timer1 Control Register" bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit.Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit.Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit .This bit is for external counting pin function enabled. .Note: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" newline bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit.If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit.If the updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode Disabled,1: The behavior selection in periodic mode Enabled" newline bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit.Setting this bit will enable the inter-timer trigger capture function..The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter.Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value." line.long 0x4 "TIMER1_CMP,Timer1 Comparator Register" hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value.CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1..Note1: Never write 0x0 or 0x1 in CMPDAT field .." line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register" bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag.This bit indicates the interrupt wake-up flag status of timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value" line.long 0xC "TIMER1_CNT,Timer1 Data Register" rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only).This bit indicates if the counter reset operation active..When user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register.Read operation:.Read this register to get CNT value. For example:.If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24-bit counter value..If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT.." rgroup.long 0x110++0x3 line.long 0x0 "TIMER1_CAP,Timer1 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register.When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x114++0xF line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register" bitfld.long 0x0 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x= 0~3) pin,1: Event Counter input source is from USB internal.." bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect.When first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function.Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1.." bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" newline bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit.This bit enables the Tx_EXT capture pin input function." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.." line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register" bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag.This bit indicates the timer external capture interrupt flag status..Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" line.long 0x8 "TIMER1_TRGCTL,Timer1 Trigger Control Register" bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit.This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.." line.long 0xC "TIMER1_ALTCTL,Timer1 Alternative Control Register" bitfld.long 0xC 0. "FUNCSEL,Function Selection.Note: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function" group.long 0x140++0x1B line.long 0x0 "TIMER1_PWMCTL,Timer1 PWM Control Register" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect).PWM output pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x0 16. "OUTMODE,PWM Output Mode.This bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit.Note: If IMMLDEN is enabled CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.." newline bitfld.long 0x0 8. "CTRLD,Center Re-load.In up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1" bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?" bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running" line.long 0x4 "TIMER1_PWMCLKSRC,Timer1 PWM Counter Clock Source Register" bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select.The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event..Note: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?" line.long 0x8 "TIMER1_PWMCLKPSC,Timer1 PWM Counter Clock Pre-scale Register" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source." line.long 0xC "TIMER1_PWMCNTCLR,Timer1 PWM Clear Counter Register" bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit.It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.." line.long 0x10 "TIMER1_PWMPERIOD,Timer1 PWM Period Register" hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register.In up count type: PWM counter counts from 0 to PERIOD and restarts from 0..In down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD..In up-down count type: PWM counter counts from 0 to PERIOD then.." line.long 0x14 "TIMER1_PWMCMPDAT,Timer1 PWM Comparator Register" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.PWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert." line.long 0x18 "TIMER1_PWMDTCTL,Timer1 PWM Dead-time Control Register" bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.." bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect).Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following two formulas: .Note: This register is write protected. Refer to SYS_REGLCTL register." rgroup.long 0x15C++0x3 line.long 0x0 "TIMER1_PWMCNT,Timer1 PWM Counter Register" bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only).User can monitor CNT to know the current counter value in 16-bit period counter." group.long 0x160++0x1B line.long 0x0 "TIMER1_PWMMSKEN,Timer1 PWM Output Mask Enable Register" bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit.The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.." bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit.The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.." line.long 0x4 "TIMER1_PWMMSK,Timer1 PWM Output Mask Data Control Register" bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1" bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0" line.long 0x8 "TIMER1_PWMBNF,Timer1 PWM Brake Pin Noise Filter Register" bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,?,?" bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.." newline bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count.The fields is used to control the active noise filter sample time." "0,1,2,3,4,5,6,7" bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?" newline bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled" line.long 0xC "TIMER1_PWMFAILBRK,Timer1 PWM System Fail Brake Control Register" bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.." bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled" newline bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.." line.long 0x10 "TIMER1_PWMBRKCTL,Timer1 PWM Brake Control Register" bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when TIMERx_PWM brake..,?,?" bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when TIMERx_PWM brake..,?,?" newline bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.." bitfld.long 0x10 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as level-detect brake source..,1: TM_BRAKEx pin event as level-detect brake source.." newline bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.." bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.." newline bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.." bitfld.long 0x10 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as edge-detect brake source..,1: TM_BRAKEx pin event as edge-detect brake source.." newline bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.." bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.." line.long 0x14 "TIMER1_PWMPOLCTL,Timer1 PWM Pin Output Polar Control Register" bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled" bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled" line.long 0x18 "TIMER1_PWMPOEN,Timer1 PWM Pin Output Enable Register" bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode" bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode" wgroup.long 0x17C++0x3 line.long 0x0 "TIMER1_PWMSWBRK,Timer1 PWM Software Trigger Brake Control Register" bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" group.long 0x180++0x17 line.long 0x0 "TIMER1_PWMINTEN0,Timer1 PWM Interrupt Enable Register 0" bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit.Note: In up-down count type period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "TIMER1_PWMINTEN1,Timer1 PWM Interrupt Enable Register 1" bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled" bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled" line.long 0x8 "TIMER1_PWMINTSTS0,Timer1 PWM Interrupt Status Register 0" bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPDIF flag in down count type..Note2: This bit is cleared by writing.." "0,1" bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type...Note2: This bit is.." "0,1" newline bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches PERIOD..Note1: When in up-down count type PIF flag means the center point flag of current PWM period..Note2: This bit is cleared by writing 1 to it." "0,1" bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches zero..Note: This bit is cleared by writing 1 to it." "0,1" line.long 0xC "TIMER1_PWMINTSTS1,Timer1 PWM Interrupt Status Register 1" rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state" rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state" newline rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only).Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state" rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only).Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state" newline bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event did not happen,1: PWMx_CH1 level-detect brake event happened" bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event did not happen,1: PWMx_CH0 level-detect brake event happened" newline bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened" bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened" line.long 0x10 "TIMER1_PWMADCTS,Timer1 PWM ADC Trigger Source Select Register" bitfld.long 0x10 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion Disabled,1: PWM counter event trigger ADC conversion Enabled" bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),?,?,?,?,?,?" line.long 0x14 "TIMER1_PWMSCTL,Timer1 PWM Synchronous Control Register" bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select.Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0..Note2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.." bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?" group.long 0x19C++0x3 line.long 0x0 "TIMER1_PWMSTATUS,Timer1 PWM Status Register" bitfld.long 0x0 16. "ADCTRGF,Trigger ADC Start Conversion Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter event trigger ADC start conversion..,1: PWM counter event trigger ADC start conversion.." bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value" rgroup.long 0x1A0++0x7 line.long 0x0 "TIMER1_PWMPBUF,Timer1 PWM Period Buffer Register" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only).Used as PERIOD active register." line.long 0x4 "TIMER1_PWMCMPBUF,Timer1 PWM Comparator Buffer Register" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only).Used as CMP active register." tree.end tree "TMR23" base ad:0x40110000 group.long 0x0++0xF line.long 0x0 "TIMER2_CTL,Timer2 Control Register" bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit.Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit.Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit .This bit is for external counting pin function enabled. .Note: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" newline bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit.If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit.If the updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode Disabled,1: The behavior selection in periodic mode Enabled" newline bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit.Setting this bit will enable the inter-timer trigger capture function..The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter.Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value." line.long 0x4 "TIMER2_CMP,Timer2 Comparator Register" hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value.CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1..Note1: Never write 0x0 or 0x1 in CMPDAT field .." line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register" bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag.This bit indicates the interrupt wake-up flag status of timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value" line.long 0xC "TIMER2_CNT,Timer2 Data Register" rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only).This bit indicates if the counter reset operation active..When user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register.Read operation:.Read this register to get CNT value. For example:.If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24-bit counter value..If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT.." rgroup.long 0x10++0x3 line.long 0x0 "TIMER2_CAP,Timer2 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register.When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x14++0xF line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register" bitfld.long 0x0 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x= 0~3) pin,1: Event Counter input source is from USB internal.." bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect.When first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function.Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1.." bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" newline bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit.This bit enables the Tx_EXT capture pin input function." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.." line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register" bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag.This bit indicates the timer external capture interrupt flag status..Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" line.long 0x8 "TIMER2_TRGCTL,Timer2 Trigger Control Register" bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit.This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.." line.long 0xC "TIMER2_ALTCTL,Timer2 Alternative Control Register" bitfld.long 0xC 0. "FUNCSEL,Function Selection.Note: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function" group.long 0x40++0x1B line.long 0x0 "TIMER2_PWMCTL,Timer2 PWM Control Register" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect).PWM output pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x0 16. "OUTMODE,PWM Output Mode.This bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit.Note: If IMMLDEN is enabled CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.." newline bitfld.long 0x0 8. "CTRLD,Center Re-load.In up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1" bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?" bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running" line.long 0x4 "TIMER2_PWMCLKSRC,Timer2 PWM Counter Clock Source Register" bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select.The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event..Note: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?" line.long 0x8 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source." line.long 0xC "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register" bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit.It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.." line.long 0x10 "TIMER2_PWMPERIOD,Timer2 PWM Period Register" hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register.In up count type: PWM counter counts from 0 to PERIOD and restarts from 0..In down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD..In up-down count type: PWM counter counts from 0 to PERIOD then.." line.long 0x14 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.PWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert." line.long 0x18 "TIMER2_PWMDTCTL,Timer2 PWM Dead-time Control Register" bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.." bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect).Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following two formulas: .Note: This register is write protected. Refer to SYS_REGLCTL register." rgroup.long 0x5C++0x3 line.long 0x0 "TIMER2_PWMCNT,Timer2 PWM Counter Register" bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only).User can monitor CNT to know the current counter value in 16-bit period counter." group.long 0x60++0x1B line.long 0x0 "TIMER2_PWMMSKEN,Timer2 PWM Output Mask Enable Register" bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit.The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.." bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit.The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.." line.long 0x4 "TIMER2_PWMMSK,Timer2 PWM Output Mask Data Control Register" bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1" bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0" line.long 0x8 "TIMER2_PWMBNF,Timer2 PWM Brake Pin Noise Filter Register" bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,?,?" bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.." newline bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count.The fields is used to control the active noise filter sample time." "0,1,2,3,4,5,6,7" bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?" newline bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled" line.long 0xC "TIMER2_PWMFAILBRK,Timer2 PWM System Fail Brake Control Register" bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.." bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled" newline bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.." line.long 0x10 "TIMER2_PWMBRKCTL,Timer2 PWM Brake Control Register" bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when TIMERx_PWM brake..,?,?" bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when TIMERx_PWM brake..,?,?" newline bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.." bitfld.long 0x10 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as level-detect brake source..,1: TM_BRAKEx pin event as level-detect brake source.." newline bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.." bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.." newline bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.." bitfld.long 0x10 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as edge-detect brake source..,1: TM_BRAKEx pin event as edge-detect brake source.." newline bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.." bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.." line.long 0x14 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register" bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled" bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled" line.long 0x18 "TIMER2_PWMPOEN,Timer2 PWM Pin Output Enable Register" bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode" bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode" wgroup.long 0x7C++0x3 line.long 0x0 "TIMER2_PWMSWBRK,Timer2 PWM Software Trigger Brake Control Register" bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" group.long 0x80++0x17 line.long 0x0 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0" bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit.Note: In up-down count type period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "TIMER2_PWMINTEN1,Timer2 PWM Interrupt Enable Register 1" bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled" bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled" line.long 0x8 "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0" bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPDIF flag in down count type..Note2: This bit is cleared by writing.." "0,1" bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type...Note2: This bit is.." "0,1" newline bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches PERIOD..Note1: When in up-down count type PIF flag means the center point flag of current PWM period..Note2: This bit is cleared by writing 1 to it." "0,1" bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches zero..Note: This bit is cleared by writing 1 to it." "0,1" line.long 0xC "TIMER2_PWMINTSTS1,Timer2 PWM Interrupt Status Register 1" rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state" rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state" newline rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only).Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state" rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only).Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state" newline bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event did not happen,1: PWMx_CH1 level-detect brake event happened" bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event did not happen,1: PWMx_CH0 level-detect brake event happened" newline bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened" bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened" line.long 0x10 "TIMER2_PWMADCTS,Timer2 PWM ADC Trigger Source Select Register" bitfld.long 0x10 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion Disabled,1: PWM counter event trigger ADC conversion Enabled" bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),?,?,?,?,?,?" line.long 0x14 "TIMER2_PWMSCTL,Timer2 PWM Synchronous Control Register" bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select.Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0..Note2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.." bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?" wgroup.long 0x98++0x3 line.long 0x0 "TIMER2_PWMSTRG,Timer2 PWM Synchronous Trigger Register" bitfld.long 0x0 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only).PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1" group.long 0x9C++0x3 line.long 0x0 "TIMER2_PWMSTATUS,Timer2 PWM Status Register" bitfld.long 0x0 16. "ADCTRGF,Trigger ADC Start Conversion Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter event trigger ADC start conversion..,1: PWM counter event trigger ADC start conversion.." bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value" rgroup.long 0xA0++0x7 line.long 0x0 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only).Used as PERIOD active register." line.long 0x4 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only).Used as CMP active register." group.long 0x100++0xF line.long 0x0 "TIMER3_CTL,Timer3 Control Register" bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect).TIMER counter will keep going no matter CPU is held by ICE or not..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit.Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit.Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only).This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit .This bit is for external counting pin function enabled. .Note: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" newline bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit.If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit.If the updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode Disabled,1: The behavior selection in periodic mode Enabled" newline bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit.Setting this bit will enable the inter-timer trigger capture function..The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled" hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter.Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value." line.long 0x4 "TIMER3_CMP,Timer3 Comparator Register" hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value.CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1..Note1: Never write 0x0 or 0x1 in CMPDAT field .." line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register" bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag.This bit indicates the interrupt wake-up flag status of timer..Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value" line.long 0xC "TIMER3_CNT,Timer3 Data Register" rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only).This bit indicates if the counter reset operation active..When user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register.Read operation:.Read this register to get CNT value. For example:.If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24-bit counter value..If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT.." rgroup.long 0x110++0x3 line.long 0x0 "TIMER3_CAP,Timer3 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register.When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.." group.long 0x114++0xF line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register" bitfld.long 0x0 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x= 0~3) pin,1: Event Counter input source is from USB internal.." bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect.When first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function.Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1.." bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit.Note: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" newline bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit.This bit enables the Tx_EXT capture pin input function." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.." line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register" bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag.This bit indicates the timer external capture interrupt flag status..Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" line.long 0x8 "TIMER3_TRGCTL,Timer3 Trigger Control Register" bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit.If this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit.This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.." line.long 0xC "TIMER3_ALTCTL,Timer3 Alternative Control Register" bitfld.long 0xC 0. "FUNCSEL,Function Selection.Note: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically." "0: Timer controller is used as timer function,1: Timer controller is used as PWM function" group.long 0x140++0x1B line.long 0x0 "TIMER3_PWMCTL,Timer3 PWM Control Register" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect).PWM output pin will keep output no matter ICE debug mode acknowledged or not..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect).If debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. .Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline bitfld.long 0x0 16. "OUTMODE,PWM Output Mode.This bit controls the output mode of corresponding PWM channel." "0: PWM independent mode,1: PWM complementary mode" bitfld.long 0x0 9. "IMMLDEN,Immediately Load Enable Bit.Note: If IMMLDEN is enabled CTRLD will be invalid." "0: PERIOD will load to PBUF when current PWM period..,1: PERIOD/CMP will load to PBUF/CMPBUF immediately.." newline bitfld.long 0x0 8. "CTRLD,Center Re-load.In up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period." "0,1" bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode" newline bitfld.long 0x0 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,?,?" bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running" line.long 0x4 "TIMER3_PWMCLKSRC,Timer3 PWM Counter Clock Source Register" bitfld.long 0x4 0.--2. "CLKSRC,PWM Counter Clock Source Select.The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event..Note: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,?,?,?,?,?,?" line.long 0x8 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale .The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source." line.long 0xC "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register" bitfld.long 0xC 0. "CNTCLR,Clear PWM Counter Control Bit.It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.." line.long 0x10 "TIMER3_PWMPERIOD,Timer3 PWM Period Register" hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register.In up count type: PWM counter counts from 0 to PERIOD and restarts from 0..In down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD..In up-down count type: PWM counter counts from 0 to PERIOD then.." line.long 0x14 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register" hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register.PWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert." line.long 0x18 "TIMER3_PWMDTCTL,Timer3 PWM Dead-time Control Register" bitfld.long 0x18 24. "DTCKSEL,Dead-time Clock Select (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from TMRx_PWMCLK without..,1: Dead-time clock source from TMRx_PWMCLK with.." bitfld.long 0x18 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect).Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive the outputs of PWMx_CH0 and PWMx_CH1 are complementary.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x18 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect).The dead-time can be calculated from the following two formulas: .Note: This register is write protected. Refer to SYS_REGLCTL register." rgroup.long 0x15C++0x3 line.long 0x0 "TIMER3_PWMCNT,Timer3 PWM Counter Register" bitfld.long 0x0 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only).User can monitor CNT to know the current counter value in 16-bit period counter." group.long 0x160++0x1B line.long 0x0 "TIMER3_PWMMSKEN,Timer3 PWM Output Mask Enable Register" bitfld.long 0x0 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit.The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data." "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.." bitfld.long 0x0 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit.The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data." "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.." line.long 0x4 "TIMER3_PWMMSK,Timer3 PWM Output Mask Data Control Register" bitfld.long 0x4 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1" bitfld.long 0x4 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0" line.long 0x8 "TIMER3_PWMBNF,Timer3 PWM Brake Pin Noise Filter Register" bitfld.long 0x8 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,?,?" bitfld.long 0x8 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.." newline bitfld.long 0x8 4.--6. "BRKFCNT,Brake Pin Noise Filter Count.The fields is used to control the active noise filter sample time." "0,1,2,3,4,5,6,7" bitfld.long 0x8 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?" newline bitfld.long 0x8 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled" line.long 0xC "TIMER3_PWMFAILBRK,Timer3 PWM System Fail Brake Control Register" bitfld.long 0xC 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.." bitfld.long 0xC 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled" newline bitfld.long 0xC 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail detection..,1: Brake Function triggered by clock fail detection.." line.long 0x10 "TIMER3_PWMBRKCTL,Timer3 PWM Brake Control Register" bitfld.long 0x10 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH1..,1: PWMx_CH1 output tri-state when TIMERx_PWM brake..,?,?" bitfld.long 0x10 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TIMERx_PWM brake event will not affect PWMx_CH0..,1: PWMx_CH0 output tri-state when TIMERx_PWM brake..,?,?" newline bitfld.long 0x10 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.." bitfld.long 0x10 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as level-detect brake source..,1: TM_BRAKEx pin event as level-detect brake source.." newline bitfld.long 0x10 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.." bitfld.long 0x10 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.." newline bitfld.long 0x10 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.." bitfld.long 0x10 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect).Note: This register is write protected. Refer to SYS_REGLCTL register." "0: TM_BRAKEx pin event as edge-detect brake source..,1: TM_BRAKEx pin event as edge-detect brake source.." newline bitfld.long 0x10 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP1_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.." bitfld.long 0x10 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect).Note1: Only internal ACMP0_O signal from low to high will be detected as brake event..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.." line.long 0x14 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register" bitfld.long 0x14 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH1 output pin." "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled" bitfld.long 0x14 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit.The bit is used to control polarity state of PWMx_CH0 output pin." "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled" line.long 0x18 "TIMER3_PWMPOEN,Timer3 PWM Pin Output Enable Register" bitfld.long 0x18 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode" bitfld.long 0x18 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode" wgroup.long 0x17C++0x3 line.long 0x0 "TIMER3_PWMSWBRK,Timer3 PWM Software Trigger Brake Control Register" bitfld.long 0x0 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" bitfld.long 0x0 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect).Write 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. .Note: This register is.." "0,1" group.long 0x180++0x17 line.long 0x0 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0" bitfld.long 0x0 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x0 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x0 1. "PIEN,PWM Period Point Interrupt Enable Bit.Note: In up-down count type period point means the center point of current PWM period." "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x0 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" line.long 0x4 "TIMER3_PWMINTEN1,Timer3 PWM Interrupt Enable Register 1" bitfld.long 0x4 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled" bitfld.long 0x4 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect).Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled" line.long 0x8 "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0" bitfld.long 0x8 3. "CMPDIF,PWM Compare Down Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPDIF flag in down count type..Note2: This bit is cleared by writing.." "0,1" bitfld.long 0x8 2. "CMPUIF,PWM Compare Up Count Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP..Note1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type...Note2: This bit is.." "0,1" newline bitfld.long 0x8 1. "PIF,PWM Period Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches PERIOD..Note1: When in up-down count type PIF flag means the center point flag of current PWM period..Note2: This bit is cleared by writing 1 to it." "0,1" bitfld.long 0x8 0. "ZIF,PWM Zero Point Interrupt Flag.This bit is set by hardware when TIMERx_PWM counter reaches zero..Note: This bit is cleared by writing 1 to it." "0,1" line.long 0xC "TIMER3_PWMINTSTS1,Timer3 PWM Interrupt Status Register 1" rbitfld.long 0xC 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state" rbitfld.long 0xC 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only).Note: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state" newline rbitfld.long 0xC 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only).Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period." "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state" rbitfld.long 0xC 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only).Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period." "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state" newline bitfld.long 0xC 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 level-detect brake event did not happen,1: PWMx_CH1 level-detect brake event happened" bitfld.long 0xC 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 level-detect brake event did not happen,1: PWMx_CH0 level-detect brake event happened" newline bitfld.long 0xC 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened" bitfld.long 0xC 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect).Note1: This bit is cleared by writing 1 to it..Note2: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened" line.long 0x10 "TIMER3_PWMADCTS,Timer3 PWM ADC Trigger Source Select Register" bitfld.long 0x10 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion Disabled,1: PWM counter event trigger ADC conversion Enabled" bitfld.long 0x10 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),?,?,?,?,?,?" line.long 0x14 "TIMER3_PWMSCTL,Timer3 PWM Synchronous Control Register" bitfld.long 0x14 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select.Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0..Note2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.." bitfld.long 0x14 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,?,?" group.long 0x19C++0x3 line.long 0x0 "TIMER3_PWMSTATUS,Timer3 PWM Status Register" bitfld.long 0x0 16. "ADCTRGF,Trigger ADC Start Conversion Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter event trigger ADC start conversion..,1: PWM counter event trigger ADC start conversion.." bitfld.long 0x0 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag.Note: This bit is cleared by writing 1 to it." "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value" rgroup.long 0x1A0++0x7 line.long 0x0 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only).Used as PERIOD active register." line.long 0x4 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only).Used as CMP active register." tree.end endif tree.end sif (cpuis("NUC029?AE")) base ad:0x40050000 elif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) base ad:0x0 endif tree "UART (Universal Asynchronous Receiver/Transmitter)" sif (cpuis("NUC029?AE")) rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Bits (Read Only).By reading this register the UART Controller will return an 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Bits.By writing to this register the UART sends out an 8-bit data through the TX pin (LSB first)." group.long 0x4++0x17 line.long 0x0 "UA_IER,UART Interrupt Enable Control Register" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Control.Note: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Control.Note: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" newline bitfld.long 0x0 11. "TIME_OUT_EN,Time-out Counter Enable Control" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x0 6. "WAKE_EN,Wake-up CPU Function Enable Control.Note: when the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode." "0: UART wake-up function Disabled,1: UART Wake-up function Enabled" newline bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Control" "0: INT_BUF_ERR Masked Disabled,1: INT_BUF_ERR Enabled" bitfld.long 0x0 4. "RTO_IEN,RX Time-out Interrupt Enable Control" "0: TOUT_INT Masked off,1: TOUT_INT Enabled" newline bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Control" "0: MODEM_INT Masked off,1: MODEM_INT Enabled" bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Control" "0: RLS_INT Masked off,1: RLS_INT Enabled" newline bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Control" "0: THRE_INT Masked off,1: THRE_INT Enabled" bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Control" "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level (for Auto-flow Control Use).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Control.The receiver is disabled or not (setting 1 to disable the receiver)..Note1: This field is only used for RS-485 Normal Multi-drop mode. It should be programmed firstly to avoid receiving unknown data before RS-485_NMM.." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (RDA_INT) Trigger Level.When the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable an interrupt will generated)." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The TX internal state machine and pointers reset" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: The RX internal state machine and pointers reset" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0: Break control Disabled,1: Break control Enabled" bitfld.long 0x8 5. "SPE,Stick Parity Enable Control" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Control.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Control" "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number of 'STOP bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,?,?" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only).This bit mirror from RTS pin output of voltage logic status." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state" bitfld.long 0xC 9. "LEV_RTS,RTS Pin Active Level.This bit defines the active level state of RTS pin output..Note1: Refer to Figure 6.1310 and Figure 6.1311 UART function mode..Note2: Refer to Figure 6.1314 and Figure 6.1315 for RS-485 function mode." "0: RTS pin output is high level active,1: RTS pin output is low level active" newline bitfld.long 0xC 1. "RTSn,RTS (Request-To-Send) Signal Control.This bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration..Note1: This RTS signal control bit is not effective when RTS auto-flow control.." "0: RTS signal is active,1: RTS signal is inactive" line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Pin Active Level.This bit defines the active level state of CTS pin input..Note: Refer to Figure 6.139" "0: CTS pin input is high level active,1: CTS pin input is low level active" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only).This bit mirror from CTS pin input of voltage logic status..Note: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline bitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag.This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1..Note: This bit is cleared by writing 1 to it." "0: CTS input has not change state,1: CTS input has change state" line.long 0x14 "UA_FSR,UART FIFO Status Register" rbitfld.long 0x14 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x14 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag.If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1..Note: This bit is cleared by writing 1 to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x14 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x14 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO is empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x14 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TX_POINTER decreases one..The.." rbitfld.long 0x14 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x14 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x14 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RX_POINTER increases one. When one byte of RX FIFO is read by CPU RX_POINTER decreases one..The Maximum value.." newline rbitfld.long 0x14 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" rbitfld.long 0x14 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit follows the last data bit or parity bit is detected as a logic 0). .Note: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated" newline rbitfld.long 0x14 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'." "0: No parity error is generated,1: Parity error is generated.Note: This bit is read.." bitfld.long 0x14 3. "RS_485_ADD_DETF,RS-485 Address Byte Detection Flag .Note1: This field is used for RS-485 function mode..Note2: This bit is cleared by writing 1 to it." "0,1" newline bitfld.long 0x14 0. "RX_OVER_IF,RX Overflow Error Interrupt Flag.This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes this bit will be set..Note: This bit is cleared by writing 1 to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow" rgroup.long 0x1C++0x3 line.long 0x0 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x0 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1." "0: No buffer error interrupt is generated,1: buffer error interrupt is generated" bitfld.long 0x0 12. "TOUT_INT,Time-out Interrupt Indicator (Read Only).This bit is set if RTO_IEN and TOUT_IF are both set to 1." "0: No Time-out interrupt is generated,1: Time-out interrupt is generated" newline bitfld.long 0x0 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEM_IEN and MODEM_IF are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" bitfld.long 0x0 10. "RLS_INT,Receive Line Status Interrupt (Read Only).This bit is set if RLS_IEN and RLS_IF are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" newline bitfld.long 0x0 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN and THRE_IF are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" bitfld.long 0x0 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN and RDA_IF are both set to 1..This bit is set if RDA_IEN and RDA_IF are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" newline bitfld.long 0x0 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. .When BUF_ERR_IF is set the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled the buffer error.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" bitfld.long 0x0 4. "TOUT_IF,Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled the Tout interrupt will be generated..Note:.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x0 3. "MODEM_IF,MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x0 2. "RLS_IF,Receive Line Interrupt Flag (Read Only).This bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If RLS_IEN (UA_IER [2]) is enabled the RLS interrupt will be.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x0 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only).This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" bitfld.long 0x0 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA interrupt will be generated. .Note: This bit is read only and it.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x13 line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value.This field is used to program the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator" line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Control.Note: When in IrDA mode this bit must be disabled." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal 1..Refer to section 'UART Controller Baud Rate Generator' for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X" hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,INV_RX" "0: No inversion,1: Inverse RX input signal" bitfld.long 0x8 5. "INV_TX,INV_TX" "0: No inversion,1: Inverse TX output signal" newline bitfld.long 0x8 1. "TX_SELECT,TX_SELECT" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value.This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Control.This bit is used to enable RS-485 Address Detection mode..Note: This field is used for RS-485 any operation mode." "0: RS-485 address detection mode Disabled,1: RS-485 address detection mode Enabled" newline bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) Control.Note: This bit cannot be active with RS485_NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.." bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: This bit cannot be active with RS485_NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.." newline bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) Control.Note: This bit cannot be active with RS485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Selection" "0: UART function mode,1: Reserved,?,?" endif sif (cpuis("NUC029?AN")) tree "UART0" base ad:0x40050000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return an 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing to this register the UART will send out an 8-bit data through the TX pin (LSB first)." group.long 0x4++0x13 line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable.When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: Disable CTS auto flow control,1: Enable CTS auto flow control" bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable.When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert RTS signal." "0: Disable RTS auto flow control,1: Enable RTS auto flow control" newline bitfld.long 0x0 11. "TIME_OUT_EN,Time Out Counter Enable" "0: Disable Time-out counter,1: Enable Time-out counter" bitfld.long 0x0 8. "LIN_RX_BRK_IEN,LIN RX Break Field Detected Interrupt Enable.Note: This field is used for LIN function mode." "0: Mask off Lin bus RX break filed interrupt,1: Enable Lin bus RX break filed interrupt" newline bitfld.long 0x0 6. "WAKE_EN,Wake Up CPU Function Enable" "0: Disable UART wake up CPU function,1: Enable wake up function when the system is in.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable" "0: Mask off INT_BUF_ERR,1: Enable INT_BUF_ERR" newline bitfld.long 0x0 4. "RTO_IEN,RX Time Out Interrupt Enable" "0: Mask off INT_TOUT,1: Enable INT_TOUT" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable" "0: Mask off INT_MODEM,1: Enable INT_MODEM" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable" "0: Mask off INT_RLS,1: Enable INT_RLS" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable" "0: Mask off INT_THRE,1: Enable INT_THRE" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable." "0: Mask off INT_RDA,1: Enable INT_RDA" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level for Auto-flow Control Use" bitfld.long 0x4 8. "RX_DIS,Receiver Disable register..The receiver is disabled or not (set 1 is disable receiver).Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Enable Receiver,1: Disable Receiver" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level" bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note: This bit will auto clear needs at least 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the TX internal.." newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note: This bit will auto clear needs at least 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the RX internal.." line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable" "0: Disable stick parity,1: When bits PBE EPE and SPE are set the parity bit.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable.This bit has effect only when bit 3 (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or..,1: Even number of logic 1's are transmitted or.." bitfld.long 0x8 3. "PBE,Parity Bit Enable" "0: Parity bit is not generated (transmit data) or..,1: Parity bit is generated or checked between the.." newline bitfld.long 0x8 2. "NSB,Number of 'STOP bit'" "0: 1 STOP bit,1: 2 STOP bits (1.5 STOP bits if WLS[1:0]=00)" bitfld.long 0x8 0.--1. "WLS,Word Length Select" "0,1,2,3" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only).This bit is the output pin status of RTS." "0,1" bitfld.long 0xC 9. "LEV_RTS,RTS Trigger Level.This bit can change the RTS trigger level." "0: low level triggered,1: high level triggered" newline bitfld.long 0xC 1. "RTS,RTS (Request-To-Send) Signal" "0: Drive RTS pin to logic 1 (If the LEV_RTS set to..,1: Drive RTS pin to logic 0 (If the LEV_RTS set to.." line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Trigger Level.This bit can change the CTS trigger level." "0: low level triggered,1: high level triggered" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only).This bit is the pin status of CTS when UART clock is enabled and CTS multi-function port is selected." "0,1" newline rbitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag (Read Only).This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1..Software can write 1 to clear this bit to zero" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).Bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted..Bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. .Note: This bit is read only but can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..This bit is set when TX_POINTER is equal to 16 otherwise is cleared by hardware." "0,1" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO.." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO full or not..This bit is set when RX_POINTER is equal to 16 otherwise is cleared by hardware." "0,1" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RX_POINTER increases one. When one byte of RX FIFO is read by CPU RX_POINTER decreases one..When RX_POINTER is.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to a logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0,1" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic 0) and is reset whenever the CPU.." "0,1" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to.." "0,1" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only).Note: This field is used for RS-485 function mode..Note: This bit is read only but can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16 bytes of UART0/UART1 this bit will be set..Note: This bit is read only but can be.." "0,1" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 15. "LIN_RX_BREAK_INT,LIN Bus RX Break Field Detected Interrupt Indicator (Read Only).This bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1." "0: No LIN RX Break interrupt is generated,1: The LIN RX Break interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1." "0: No buffer error interrupt is generated,1: The buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN and TOUT_IF are both set to 1." "0: No Tout interrupt is generated,1: The Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEM_IEN and MODEM_IF are both set to 1." "0: No Modem interrupt is generated,1: The Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only). .This bit is set if RLS_IEN and RLS_IF are both set to 1." "0: No RLS interrupt is generated,1: The RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)..This bit is set if THRE_IEN and THRE_IF are both set to 1." "0: No THRE interrupt is generated,1: The THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)..This bit is set if RDA_IEN and RDA_IF are both set to 1." "0: No RDA interrupt is generated,1: The RDA interrupt is generated" bitfld.long 0x4 7. "LIN_RX_BREAK_IF,LIN Bus RX Break Field Detected Flag (Read Only).This bit is set when RX received LIN Break Field. If UA_IER [LIN_RX_BRK_IEN] is enabled the LIN RX Break interrupt will be generated..Note: This bit is read only but can be cleared by.." "0,1" newline bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF ) is set. When BUF_ERR_IF is set the transfer is not.." "0,1" bitfld.long 0x4 4. "TOUT_IF,Time Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0,1" bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only)..This bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will be.." "0,1" newline bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only). .This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled the THRE interrupt will be generated..Note: This bit is.." "0,1" bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)..When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled the RDA interrupt will be generated. .Note: This bit is read only and it.." "0,1" group.long 0x20++0x13 line.long 0x0 "UA_TOR,UART Time Out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay time value .This field is use to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time Out Interrupt Comparator" line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable.Refer to the table below for more information..Note: When in IrDA mode this bit must disable." "0: Disable divider X (the equation of M = 16),1: Enable divider X (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X equal 1.Refer to the Table 6.114 below for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X" hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicated the baud rate divider" line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,INV_RX" "0: No inversion,1: Inverse RX input signal" bitfld.long 0x8 5. "INV_TX,INV_TX" "0: No inversion,1: Inverse TX output signal" newline bitfld.long 0x8 1. "TX_SELECT,TX_SELECT" "0: Enable IrDA receiver,1: Enable IrDA transmitter" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address match value register.This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable.This bit is use to enable RS-485 address detection mode. .Note: This field is used for RS-485 any operation mode." "0: Disable address detection mode,1: Enable address detection mode" newline bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: Disable RS-485 Auto Direction Operation Mode (AUO),1: Enable RS-485 Auto Direction Operation Mode (AUO)" bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It can't be active with RS-485_NMM operation mode." "0: Disable RS-485 Auto Address Detection Operation..,1: Enable RS-485 Auto Address Detection Operation.." newline bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM).Note: It can't be active with RS-485_AAD operation mode." "0: Disable RS-485 Normal Multi-drop Operation Mode..,1: Enable RS-485 Normal Multi-drop Operation Mode.." bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: Disable LIN TX Break Mode,1: Enable LIN TX Break Mode" newline bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable" "0: Disable LIN RX mode,1: Enable LIN RX mode" hexmask.long.byte 0xC 0.--3. 1. "UA_LIN_BKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note: This break field length is UA_LIN_BKFL + 2" line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable" "0: UART Function,1: Enable LIN Function,?,?" tree.end tree "UART1" base ad:0x40150000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return an 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing to this register the UART will send out an 8-bit data through the TX pin (LSB first)." group.long 0x4++0x13 line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable.When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: Disable CTS auto flow control,1: Enable CTS auto flow control" bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable.When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert RTS signal." "0: Disable RTS auto flow control,1: Enable RTS auto flow control" newline bitfld.long 0x0 11. "TIME_OUT_EN,Time Out Counter Enable" "0: Disable Time-out counter,1: Enable Time-out counter" bitfld.long 0x0 8. "LIN_RX_BRK_IEN,LIN RX Break Field Detected Interrupt Enable.Note: This field is used for LIN function mode." "0: Mask off Lin bus RX break filed interrupt,1: Enable Lin bus RX break filed interrupt" newline bitfld.long 0x0 6. "WAKE_EN,Wake Up CPU Function Enable" "0: Disable UART wake up CPU function,1: Enable wake up function when the system is in.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable" "0: Mask off INT_BUF_ERR,1: Enable INT_BUF_ERR" newline bitfld.long 0x0 4. "RTO_IEN,RX Time Out Interrupt Enable" "0: Mask off INT_TOUT,1: Enable INT_TOUT" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable" "0: Mask off INT_MODEM,1: Enable INT_MODEM" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable" "0: Mask off INT_RLS,1: Enable INT_RLS" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable" "0: Mask off INT_THRE,1: Enable INT_THRE" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable." "0: Mask off INT_RDA,1: Enable INT_RDA" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level for Auto-flow Control Use" bitfld.long 0x4 8. "RX_DIS,Receiver Disable register..The receiver is disabled or not (set 1 is disable receiver).Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Enable Receiver,1: Disable Receiver" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level" bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note: This bit will auto clear needs at least 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the TX internal.." newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note: This bit will auto clear needs at least 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the RX internal.." line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable" "0: Disable stick parity,1: When bits PBE EPE and SPE are set the parity bit.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable.This bit has effect only when bit 3 (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or..,1: Even number of logic 1's are transmitted or.." bitfld.long 0x8 3. "PBE,Parity Bit Enable" "0: Parity bit is not generated (transmit data) or..,1: Parity bit is generated or checked between the.." newline bitfld.long 0x8 2. "NSB,Number of 'STOP bit'" "0: 1 STOP bit,1: 2 STOP bits (1.5 STOP bits if WLS[1:0]=00)" bitfld.long 0x8 0.--1. "WLS,Word Length Select" "0,1,2,3" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only).This bit is the output pin status of RTS." "0,1" bitfld.long 0xC 9. "LEV_RTS,RTS Trigger Level.This bit can change the RTS trigger level." "0: low level triggered,1: high level triggered" newline bitfld.long 0xC 1. "RTS,RTS (Request-To-Send) Signal" "0: Drive RTS pin to logic 1 (If the LEV_RTS set to..,1: Drive RTS pin to logic 0 (If the LEV_RTS set to.." line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Trigger Level.This bit can change the CTS trigger level." "0: low level triggered,1: high level triggered" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only).This bit is the pin status of CTS when UART clock is enabled and CTS multi-function port is selected." "0,1" newline rbitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag (Read Only).This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1..Software can write 1 to clear this bit to zero" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).Bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted..Bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. .Note: This bit is read only but can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..This bit is set when TX_POINTER is equal to 16 otherwise is cleared by hardware." "0,1" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO.." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO full or not..This bit is set when RX_POINTER is equal to 16 otherwise is cleared by hardware." "0,1" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RX_POINTER increases one. When one byte of RX FIFO is read by CPU RX_POINTER decreases one..When RX_POINTER is.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to a logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0,1" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic 0) and is reset whenever the CPU.." "0,1" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to.." "0,1" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only).Note: This field is used for RS-485 function mode..Note: This bit is read only but can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16 bytes of UART0/UART1 this bit will be set..Note: This bit is read only but can be.." "0,1" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 15. "LIN_RX_BREAK_INT,LIN Bus RX Break Field Detected Interrupt Indicator (Read Only).This bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1." "0: No LIN RX Break interrupt is generated,1: The LIN RX Break interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1." "0: No buffer error interrupt is generated,1: The buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN and TOUT_IF are both set to 1." "0: No Tout interrupt is generated,1: The Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEM_IEN and MODEM_IF are both set to 1." "0: No Modem interrupt is generated,1: The Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only). .This bit is set if RLS_IEN and RLS_IF are both set to 1." "0: No RLS interrupt is generated,1: The RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)..This bit is set if THRE_IEN and THRE_IF are both set to 1." "0: No THRE interrupt is generated,1: The THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)..This bit is set if RDA_IEN and RDA_IF are both set to 1." "0: No RDA interrupt is generated,1: The RDA interrupt is generated" bitfld.long 0x4 7. "LIN_RX_BREAK_IF,LIN Bus RX Break Field Detected Flag (Read Only).This bit is set when RX received LIN Break Field. If UA_IER [LIN_RX_BRK_IEN] is enabled the LIN RX Break interrupt will be generated..Note: This bit is read only but can be cleared by.." "0,1" newline bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF ) is set. When BUF_ERR_IF is set the transfer is not.." "0,1" bitfld.long 0x4 4. "TOUT_IF,Time Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0,1" bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only)..This bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will be.." "0,1" newline bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only). .This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled the THRE interrupt will be generated..Note: This bit is.." "0,1" bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)..When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled the RDA interrupt will be generated. .Note: This bit is read only and it.." "0,1" group.long 0x20++0x13 line.long 0x0 "UA_TOR,UART Time Out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay time value .This field is use to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time Out Interrupt Comparator" line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable.Refer to the table below for more information..Note: When in IrDA mode this bit must disable." "0: Disable divider X (the equation of M = 16),1: Enable divider X (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X equal 1.Refer to the Table 6.114 below for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X" hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicated the baud rate divider" line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,INV_RX" "0: No inversion,1: Inverse RX input signal" bitfld.long 0x8 5. "INV_TX,INV_TX" "0: No inversion,1: Inverse TX output signal" newline bitfld.long 0x8 1. "TX_SELECT,TX_SELECT" "0: Enable IrDA receiver,1: Enable IrDA transmitter" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address match value register.This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable.This bit is use to enable RS-485 address detection mode. .Note: This field is used for RS-485 any operation mode." "0: Disable address detection mode,1: Enable address detection mode" newline bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: Disable RS-485 Auto Direction Operation Mode (AUO),1: Enable RS-485 Auto Direction Operation Mode (AUO)" bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It can't be active with RS-485_NMM operation mode." "0: Disable RS-485 Auto Address Detection Operation..,1: Enable RS-485 Auto Address Detection Operation.." newline bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM).Note: It can't be active with RS-485_AAD operation mode." "0: Disable RS-485 Normal Multi-drop Operation Mode..,1: Enable RS-485 Normal Multi-drop Operation Mode.." bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: Disable LIN TX Break Mode,1: Enable LIN TX Break Mode" newline bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable" "0: Disable LIN RX mode,1: Enable LIN RX mode" hexmask.long.byte 0xC 0.--3. 1. "UA_LIN_BKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note: This break field length is UA_LIN_BKFL + 2" line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable" "0: UART Function,1: Enable LIN Function,?,?" tree.end endif sif (cpuis("NUC029?DE")) tree "UART0" base ad:0x40050000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0x13 line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control." "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" newline bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol." "0: Time-out counter Disabled,1: Time-out counter Enabled" newline bitfld.long 0x0 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control.Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control." "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol." "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol." "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)." "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol." "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol." "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol." "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel).When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Coontrol." "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Coontrol.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Coontrol." "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'." "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection." "0: Word length is 5-bit,1: Word length is 6-bit,?,?" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only) ( Available In UART0/UART1 Channel).This bit mirror from RTS pin output of voltage logic status.." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state" bitfld.long 0xC 9. "LEV_RTS,RTS Pin Active Level ( Available In UART0/UART1 Channel).This bit defines the active level state of RTS pin output..Note1: Refer to Figure 692 and Figure 693 for UART function mode..Note2: Refer to Figure 6103 and Figure 6104 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active" newline bitfld.long 0xC 1. "RTS,RTS (Request-To-Send) Signal Control (Available In UART0/UART1 Channel).This bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration..Note1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive" line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Pin Active Level.This bit defines the active level state of CTS pin input..Note: Refer to Figure 691 for more information." "0: CTS pin input is high level active,1: CTS pin input is low level active" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only) .This bit mirror from CTS pin input of voltage logic status..Note: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline rbitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag (Read Only).This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1..Note: This bit is read only but can be cleared by writing '1' to it." "0: CTS input has not change state,1: CTS input has change state" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2).Note: This bit is cleared automatically when TX FIFO/TX Buffer is not.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2).Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow..TX Buffer is not..,1: TX FIFO is overflow..TX Buffer is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO is full or not. (UART0/UART1/UART2).This bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: TX FIFO is not full..TX Buffer is not full,1: TX FIFO is full..TX Buffer is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of TX Buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not (UART0/UART1/UART2). .Note: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: RX FIFO is not full..RX buffer is not full,1: RX FIFO is full..RX bufferis full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of RX Buffer has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty..RX Buffer is not empty,1: RX FIFO is empty..RX Buffer is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1).Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only .." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) .Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x0 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) .This bit is set to logic '1' when auto-baud rate detect function is finished. .Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow. .If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only but.." "0: RX FIFO is not overflow..RX Buffer is not..,1: RX FIFO is overflow..RX Buffer is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only).This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data wake-up" bitfld.long 0x4 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only).Note1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2).Note: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]) LIN_BKDET_F (UA_LIN_SR[9]) BIT_ERR_F (UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all.." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 6. "WKIF,UART Wake-Up Flag (Read Only).This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1..Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF" bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x1B line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator." line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Coontrol.Refer to Table 624 UART Baud Rate Equation for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 624 UART Baud Rate Equation for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X." hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control." "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control." "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol." "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1).This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0xC 18. "ABRDEN,Auto-Baud Rate Detect Enable Control.This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0xC 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1).This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" newline bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1).Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2).Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)." "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2).This field indicates a 4-bit LIN TX break field count..Note1: This break field length is LIN_BKFL + 1.." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Coontrol." "0: UART function Enabled,1: LIN function Enabled. (Available in..,?,?" line.long 0x14 "UA_LIN_CTL,UART LIN Control Register" hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register.If the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field...Note1: User can fill any.." bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select." "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length..Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?" hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]..Note2: This.." newline bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable Coontrol." "0: Bit error detection function Disabled,1: Bit error detection Enabled" bitfld.long 0x14 11. "LIN_RX_DIS,LIN Receiver Disable Bit." "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable Coontrol." "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable Coontrol." "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable Coontrol.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22])..Note1: These registers are shadow registers of.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable Coontrol.Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Coontrol.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this.." "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.." bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Coontrol.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Coontrol." "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable Coontrol." "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x18 "UA_LIN_SR,UART LIN Status Register" rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only).At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set.." "0,1" rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only).This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only).This bit is set by hardware when receipted frame ID parity is not correct.." "0: No active,1: Receipted frame ID parity is not correct" newline rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only).This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' .." "0: LIN header error not detected,1: LIN header error detected" rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only).This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" tree.end tree "UART1" base ad:0x40150000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0x13 line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control." "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" newline bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol." "0: Time-out counter Disabled,1: Time-out counter Enabled" newline bitfld.long 0x0 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control.Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control." "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol." "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol." "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)." "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol." "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol." "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol." "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel).When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Coontrol." "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Coontrol.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Coontrol." "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'." "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection." "0: Word length is 5-bit,1: Word length is 6-bit,?,?" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only) ( Available In UART0/UART1 Channel).This bit mirror from RTS pin output of voltage logic status.." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state" bitfld.long 0xC 9. "LEV_RTS,RTS Pin Active Level ( Available In UART0/UART1 Channel).This bit defines the active level state of RTS pin output..Note1: Refer to Figure 692 and Figure 693 for UART function mode..Note2: Refer to Figure 6103 and Figure 6104 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active" newline bitfld.long 0xC 1. "RTS,RTS (Request-To-Send) Signal Control (Available In UART0/UART1 Channel).This bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration..Note1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive" line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Pin Active Level.This bit defines the active level state of CTS pin input..Note: Refer to Figure 691 for more information." "0: CTS pin input is high level active,1: CTS pin input is low level active" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only) .This bit mirror from CTS pin input of voltage logic status..Note: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline rbitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag (Read Only).This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1..Note: This bit is read only but can be cleared by writing '1' to it." "0: CTS input has not change state,1: CTS input has change state" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2).Note: This bit is cleared automatically when TX FIFO/TX Buffer is not.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2).Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow..TX Buffer is not..,1: TX FIFO is overflow..TX Buffer is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO is full or not. (UART0/UART1/UART2).This bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: TX FIFO is not full..TX Buffer is not full,1: TX FIFO is full..TX Buffer is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of TX Buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not (UART0/UART1/UART2). .Note: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: RX FIFO is not full..RX buffer is not full,1: RX FIFO is full..RX bufferis full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of RX Buffer has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty..RX Buffer is not empty,1: RX FIFO is empty..RX Buffer is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1).Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only .." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) .Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x0 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) .This bit is set to logic '1' when auto-baud rate detect function is finished. .Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow. .If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only but.." "0: RX FIFO is not overflow..RX Buffer is not..,1: RX FIFO is overflow..RX Buffer is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only).This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data wake-up" bitfld.long 0x4 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only).Note1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2).Note: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]) LIN_BKDET_F (UA_LIN_SR[9]) BIT_ERR_F (UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all.." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 6. "WKIF,UART Wake-Up Flag (Read Only).This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1..Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF" bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x1B line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator." line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Coontrol.Refer to Table 624 UART Baud Rate Equation for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 624 UART Baud Rate Equation for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X." hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control." "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control." "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol." "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1).This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0xC 18. "ABRDEN,Auto-Baud Rate Detect Enable Control.This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0xC 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1).This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" newline bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1).Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2).Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)." "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2).This field indicates a 4-bit LIN TX break field count..Note1: This break field length is LIN_BKFL + 1.." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Coontrol." "0: UART function Enabled,1: LIN function Enabled. (Available in..,?,?" line.long 0x14 "UA_LIN_CTL,UART LIN Control Register" hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register.If the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field...Note1: User can fill any.." bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select." "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length..Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?" hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]..Note2: This.." newline bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable Coontrol." "0: Bit error detection function Disabled,1: Bit error detection Enabled" bitfld.long 0x14 11. "LIN_RX_DIS,LIN Receiver Disable Bit." "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable Coontrol." "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable Coontrol." "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable Coontrol.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22])..Note1: These registers are shadow registers of.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable Coontrol.Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Coontrol.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this.." "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.." bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Coontrol.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Coontrol." "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable Coontrol." "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x18 "UA_LIN_SR,UART LIN Status Register" rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only).At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set.." "0,1" rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only).This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only).This bit is set by hardware when receipted frame ID parity is not correct.." "0: No active,1: Receipted frame ID parity is not correct" newline rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only).This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' .." "0: LIN header error not detected,1: LIN header error detected" rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only).This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" tree.end tree "UART2" base ad:0x40154000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0xB line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control." "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" newline bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol." "0: Time-out counter Disabled,1: Time-out counter Enabled" newline bitfld.long 0x0 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control.Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control." "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol." "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol." "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)." "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol." "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol." "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol." "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel).When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Coontrol." "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Coontrol.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Coontrol." "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'." "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection." "0: Word length is 5-bit,1: Word length is 6-bit,?,?" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2).Note: This bit is cleared automatically when TX FIFO/TX Buffer is not.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2).Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow..TX Buffer is not..,1: TX FIFO is overflow..TX Buffer is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO is full or not. (UART0/UART1/UART2).This bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: TX FIFO is not full..TX Buffer is not full,1: TX FIFO is full..TX Buffer is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of TX Buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not (UART0/UART1/UART2). .Note: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: RX FIFO is not full..RX buffer is not full,1: RX FIFO is full..RX bufferis full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of RX Buffer has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty..RX Buffer is not empty,1: RX FIFO is empty..RX Buffer is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1).Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only .." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) .Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x0 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) .This bit is set to logic '1' when auto-baud rate detect function is finished. .Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow. .If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only but.." "0: RX FIFO is not overflow..RX Buffer is not..,1: RX FIFO is overflow..RX Buffer is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only).This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data wake-up" bitfld.long 0x4 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only).Note1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2).Note: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]) LIN_BKDET_F (UA_LIN_SR[9]) BIT_ERR_F (UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all.." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 6. "WKIF,UART Wake-Up Flag (Read Only).This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1..Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF" bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x1B line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator." line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Coontrol.Refer to Table 624 UART Baud Rate Equation for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 624 UART Baud Rate Equation for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X." hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control." "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control." "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol." "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1).This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0xC 18. "ABRDEN,Auto-Baud Rate Detect Enable Control.This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0xC 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1).This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" newline bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1).Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2).Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)." "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2).This field indicates a 4-bit LIN TX break field count..Note1: This break field length is LIN_BKFL + 1.." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Coontrol." "0: UART function Enabled,1: LIN function Enabled. (Available in..,?,?" line.long 0x14 "UA_LIN_CTL,UART LIN Control Register" hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register.If the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field...Note1: User can fill any.." bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select." "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length..Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?" hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]..Note2: This.." newline bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable Coontrol." "0: Bit error detection function Disabled,1: Bit error detection Enabled" bitfld.long 0x14 11. "LIN_RX_DIS,LIN Receiver Disable Bit." "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable Coontrol." "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable Coontrol." "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable Coontrol.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22])..Note1: These registers are shadow registers of.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable Coontrol.Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Coontrol.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this.." "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.." bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Coontrol.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Coontrol." "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable Coontrol." "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x18 "UA_LIN_SR,UART LIN Status Register" rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only).At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set.." "0,1" rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only).This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only).This bit is set by hardware when receipted frame ID parity is not correct.." "0: No active,1: Receipted frame ID parity is not correct" newline rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only).This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' .." "0: LIN header error not detected,1: LIN header error detected" rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only).This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" tree.end endif sif (cpuis("NUC029?DE")) tree "UART3" base ad:0x40054000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0xB line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control." "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" newline bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol." "0: Time-out counter Disabled,1: Time-out counter Enabled" newline bitfld.long 0x0 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control.Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control." "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol." "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol." "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)." "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol." "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol." "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol." "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel).When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Coontrol." "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Coontrol.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Coontrol." "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'." "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection." "0: Word length is 5-bit,1: Word length is 6-bit,?,?" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2).Note: This bit is cleared automatically when TX FIFO/TX Buffer is not.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2).Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow..TX Buffer is not..,1: TX FIFO is overflow..TX Buffer is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO is full or not. (UART0/UART1/UART2).This bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: TX FIFO is not full..TX Buffer is not full,1: TX FIFO is full..TX Buffer is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of TX Buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not (UART0/UART1/UART2). .Note: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: RX FIFO is not full..RX buffer is not full,1: RX FIFO is full..RX bufferis full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of RX Buffer has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty..RX Buffer is not empty,1: RX FIFO is empty..RX Buffer is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1).Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only .." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) .Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x0 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) .This bit is set to logic '1' when auto-baud rate detect function is finished. .Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow. .If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only but.." "0: RX FIFO is not overflow..RX Buffer is not..,1: RX FIFO is overflow..RX Buffer is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only).This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data wake-up" bitfld.long 0x4 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only).Note1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2).Note: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]) LIN_BKDET_F (UA_LIN_SR[9]) BIT_ERR_F (UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all.." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 6. "WKIF,UART Wake-Up Flag (Read Only).This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1..Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF" bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x13 line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator." line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Coontrol.Refer to Table 624 UART Baud Rate Equation for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 624 UART Baud Rate Equation for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X." hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control." "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control." "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol." "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1).This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0xC 18. "ABRDEN,Auto-Baud Rate Detect Enable Control.This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0xC 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1).This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" newline bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1).Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2).Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)." "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2).This field indicates a 4-bit LIN TX break field count..Note1: This break field length is LIN_BKFL + 1.." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Coontrol." "0: UART function Enabled,1: LIN function Enabled. (Available in..,?,?" tree.end tree "UART4" base ad:0x40058000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0xB line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control." "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" newline bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol." "0: Time-out counter Disabled,1: Time-out counter Enabled" newline bitfld.long 0x0 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control.Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control." "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol." "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol." "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)." "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol." "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol." "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol." "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel).When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Coontrol." "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Coontrol.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Coontrol." "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'." "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection." "0: Word length is 5-bit,1: Word length is 6-bit,?,?" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2).Note: This bit is cleared automatically when TX FIFO/TX Buffer is not.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2).Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow..TX Buffer is not..,1: TX FIFO is overflow..TX Buffer is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO is full or not. (UART0/UART1/UART2).This bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: TX FIFO is not full..TX Buffer is not full,1: TX FIFO is full..TX Buffer is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of TX Buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not (UART0/UART1/UART2). .Note: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: RX FIFO is not full..RX buffer is not full,1: RX FIFO is full..RX bufferis full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of RX Buffer has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty..RX Buffer is not empty,1: RX FIFO is empty..RX Buffer is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1).Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only .." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) .Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x0 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) .This bit is set to logic '1' when auto-baud rate detect function is finished. .Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow. .If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only but.." "0: RX FIFO is not overflow..RX Buffer is not..,1: RX FIFO is overflow..RX Buffer is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only).This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data wake-up" bitfld.long 0x4 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only).Note1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2).Note: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]) LIN_BKDET_F (UA_LIN_SR[9]) BIT_ERR_F (UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all.." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 6. "WKIF,UART Wake-Up Flag (Read Only).This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1..Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF" bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x13 line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator." line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Coontrol.Refer to Table 624 UART Baud Rate Equation for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 624 UART Baud Rate Equation for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X." hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control." "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control." "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol." "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1).This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0xC 18. "ABRDEN,Auto-Baud Rate Detect Enable Control.This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0xC 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1).This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" newline bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1).Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2).Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)." "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2).This field indicates a 4-bit LIN TX break field count..Note1: This break field length is LIN_BKFL + 1.." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Coontrol." "0: UART function Enabled,1: LIN function Enabled. (Available in..,?,?" tree.end tree "UART5" base ad:0x40158000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0xB line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 18. "ABRIEN,Auto-Baud Rate Interrupt Enable Control." "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Coontrol (Available In UART0/UART1 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" newline bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Coontrol ( Available In UART0/UART1 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Coontrol." "0: Time-out counter Disabled,1: Time-out counter Enabled" newline bitfld.long 0x0 10. "WKDATIEN,Incoming Data Wake-Up Interrupt Enable Control.Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Coontrol.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WKCTSIEN,NCTS Wake-Up Interrupt Enable Control." "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Coontrol." "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Coontrol." "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Coontrol (Available In UART0/UART1 Channel)." "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Coontrol." "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Coontrol." "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Coontrol." "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel).When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated).." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Coontrol." "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Coontrol.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Coontrol." "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'." "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection." "0: Word length is 5-bit,1: Word length is 6-bit,?,?" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2).Note: This bit is cleared automatically when TX FIFO/TX Buffer is not.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2).Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow..TX Buffer is not..,1: TX FIFO is overflow..TX Buffer is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO is full or not. (UART0/UART1/UART2).This bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: TX FIFO is not full..TX Buffer is not full,1: TX FIFO is full..TX Buffer is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of TX Buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when.." "0: TX FIFO is not empty..TX Buffer is not empty,1: TX FIFO is empty..TX Buffer is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not (UART0/UART1/UART2). .Note: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5) otherwise is cleared by hardware." "0: RX FIFO is not full..RX buffer is not full,1: RX FIFO is full..RX bufferis full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not. (UART0/UART1/UART2).Note: When the last byte of RX Buffer has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty..RX Buffer is not empty,1: RX FIFO is empty..RX Buffer is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1).Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only .." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 2. "ABRDTOIF,Auto-Baud Rate Time-Out Interrupt (Read Only) .Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x0 1. "ABRDIF,Auto-Baud Rate Detect Interrupt (Read Only) .This bit is set to logic '1' when auto-baud rate detect function is finished. .Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow. .If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only but.." "0: RX FIFO is not overflow..RX Buffer is not..,1: RX FIFO is overflow..RX Buffer is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 17. "DATWKIF,Data Wake-Up Interrupt Flag (Read Only).This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATIEN (UA_IER[10]) is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by data wake-up" bitfld.long 0x4 16. "CTSWKIF,NCTS Wake-Up Interrupt Flag (Read Only).Note1: If WKCTSIEN (UA_IER[6])is enabled the wake-up interrupt is generated..Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1." "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)(UART0/UARt1/UART2).Note: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]) LIN_BKDET_F (UA_LIN_SR[9]) BIT_ERR_F (UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all.." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 6. "WKIF,UART Wake-Up Flag (Read Only).This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1..Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF" bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x13 line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator." line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Coontrol.Refer to Table 624 UART Baud Rate Equation for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 624 UART Baud Rate Equation for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X." hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider." line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control." "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control." "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Coontrol." "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register (Available In UART0/UART1).This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 19.--20. "ABRDBITS,Auto-Baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0xC 18. "ABRDEN,Auto-Baud Rate Detect Enable Control.This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0xC 17. "ABRIF,Auto-Baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. .Note:.." "0,1" newline bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Coontrol (Available In UART0/UART1).This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1).Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" newline bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1).Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Coontrol (Available In UART0/UART1/UART2).Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Coontrol (Available In UART0/UART1/UART2)." "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length (Available In UART0/UART1/UART2).This field indicates a 4-bit LIN TX break field count..Note1: This break field length is LIN_BKFL + 1.." line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Coontrol." "0: UART function Enabled,1: LIN function Enabled. (Available in..,?,?" tree.end endif sif (cpuis("NUC029?EE")) tree "UART0" base ad:0x40050000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0x13 line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 15. "DMA_RX_EN,RX DMA Enable Bit (Not Available In UART2 Channel).This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled" bitfld.long 0x0 14. "DMA_TX_EN,TX DMA Enable Bit (Not Available In UART2 Channel).This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled" newline bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" newline bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Bit.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WAKE_EN,UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip is.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Bit" "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)" "0: MODEM_INT Masked off,1: MODEM_INT Enabled." newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit" "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit" "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver).Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level.When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated)." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Bit" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Bit.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Bit" "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'" "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,?,?" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only) (Not Available In UART2 Channel).This bit mirror from RTS pin output of voltage logic status." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state" bitfld.long 0xC 9. "LEV_RTS,RTS Pin Active Level (Not Available In UART2 Channel).This bit defines the active level state of RTS pin output..Note1: Refer to Figure 6.136 and Figure 6.137 for UART function mode..Note2: Refer to Figure 6.1317 And Figure 6.1318 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active" newline bitfld.long 0xC 1. "RTS,RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel).This bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration..Note1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive" line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Pin Active Level.This bit defines the active level state of CTS pin input..Note: Refer to Figure 6.135 for more information" "0: CTS pin input is high level active,1: CTS pin input is low level active" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only) (Not Available In UART2 Channel).This bit mirror from CTS pin input of voltage logic status..Note: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline rbitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag (Read Only) (Not Available In UART2 Channel).This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1..Note: This bit is read only but.." "0: CTS input has not change state,1: CTS input has change state" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1..Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..This bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) .Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only but can be cleared by.." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only .." "0: RX FIFO is not overflow,1: RX FIFO is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode" bitfld.long 0x4 28. "HW_TOUT_INT,In DMA Mode Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode" newline bitfld.long 0x4 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel).This bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode" bitfld.long 0x4 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only).This bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode" newline bitfld.long 0x4 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" bitfld.long 0x4 20. "HW_TOUT_IF,In DMA Mode Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x4 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x4 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only).This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). If RLS_IEN (UA_IER.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only).Note: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]) LIN_BKDET_F(UA_LIN_SR[9]) BIT_ERR_F(UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5])is set the transfer is not correct. If BUF_ERR_IEN (UA_IER.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated.0 = No.." bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled the Tout interrupt will be generated..Note:.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA interrupt will be generated..Note: This bit is read.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x1B line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator" line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Bit.Refer to Table 6.132 for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 6.132 for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X" hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider" line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control" "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control" "0: None inverse transmitting signal.,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,TX_SELECT" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register .This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit.This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) .Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) .Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" newline bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: This break field length is UA_LIN_BKFL + 1" line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Bit" "0: UART function Enabled,1: LIN function Enabled,?,?" line.long 0x14 "UA_LIN_CTL,UART LIN Control Register" hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register.If the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field...Note1: User can fill any.." bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length..Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?" hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]..Note2: This.." newline bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled" bitfld.long 0x14 11. "LIN_RX_DIS,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable Bit.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22])..Note1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit.Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this field.." "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.." bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x18 "UA_LIN_SR,UART LIN Status Register" rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only).At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set." "0,1" rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only).This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only).This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct" newline rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only).This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' .." "0: LIN header error not detected,1: LIN header error detected" rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only).This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" tree.end tree "UART1" base ad:0x40150000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0x13 line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 15. "DMA_RX_EN,RX DMA Enable Bit (Not Available In UART2 Channel).This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled" bitfld.long 0x0 14. "DMA_TX_EN,TX DMA Enable Bit (Not Available In UART2 Channel).This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled" newline bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" newline bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Bit.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WAKE_EN,UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip is.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Bit" "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)" "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit" "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit" "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver).Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level.When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated)." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Bit" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Bit.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Bit" "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'" "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,?,?" line.long 0xC "UA_MCR,UART Modem Control Register" rbitfld.long 0xC 13. "RTS_ST,RTS Pin State (Read Only) (Not Available In UART2 Channel).This bit mirror from RTS pin output of voltage logic status." "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state" bitfld.long 0xC 9. "LEV_RTS,RTS Pin Active Level (Not Available In UART2 Channel).This bit defines the active level state of RTS pin output..Note1: Refer to Figure 6.136 and Figure 6.137 for UART function mode..Note2: Refer to Figure 6.1317 And Figure 6.1318 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active" newline bitfld.long 0xC 1. "RTS,RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel).This bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration..Note1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive" line.long 0x10 "UA_MSR,UART Modem Status Register" bitfld.long 0x10 8. "LEV_CTS,CTS Pin Active Level.This bit defines the active level state of CTS pin input..Note: Refer to Figure 6.135 for more information" "0: CTS pin input is high level active,1: CTS pin input is low level active" rbitfld.long 0x10 4. "CTS_ST,CTS Pin Status (Read Only) (Not Available In UART2 Channel).This bit mirror from CTS pin input of voltage logic status..Note: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline rbitfld.long 0x10 0. "DCTSF,Detect CTS State Change Flag (Read Only) (Not Available In UART2 Channel).This bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1..Note: This bit is read only but.." "0: CTS input has not change state,1: CTS input has change state" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1..Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..This bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) .Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only but can be cleared by.." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only .." "0: RX FIFO is not overflow,1: RX FIFO is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode" bitfld.long 0x4 28. "HW_TOUT_INT,In DMA Mode Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode" newline bitfld.long 0x4 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel).This bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode" bitfld.long 0x4 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only).This bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode" newline bitfld.long 0x4 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" bitfld.long 0x4 20. "HW_TOUT_IF,In DMA Mode Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x4 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x4 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only).This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). If RLS_IEN (UA_IER.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only).Note: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]) LIN_BKDET_F(UA_LIN_SR[9]) BIT_ERR_F(UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5])is set the transfer is not correct. If BUF_ERR_IEN (UA_IER.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated.0 = No.." bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled the Tout interrupt will be generated..Note:.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA interrupt will be generated..Note: This bit is read.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x1B line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator" line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Bit.Refer to Table 6.132 for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 6.132 for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X" hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider" line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control" "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control" "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,TX_SELECT" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register .This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit.This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) .Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) .Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" newline bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: This break field length is UA_LIN_BKFL + 1" line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Bit" "0: UART function Enabled,1: LIN function Enabled,?,?" line.long 0x14 "UA_LIN_CTL,UART LIN Control Register" hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register.If the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field...Note1: User can fill any.." bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length..Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?" hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]..Note2: This.." newline bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled" bitfld.long 0x14 11. "LIN_RX_DIS,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable Bit.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22])..Note1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit.Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this field.." "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.." bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x18 "UA_LIN_SR,UART LIN Status Register" rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only).At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set." "0,1" rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only).This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only).This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct" newline rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only).This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' .." "0: LIN header error not detected,1: LIN header error detected" rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only).This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" tree.end tree "UART2" base ad:0x40154000 rgroup.long 0x0++0x3 line.long 0x0 "UA_RBR,UART Receive Buffer Register" hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only).By reading this register the UART will return the 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UA_THR,UART Transmit Holding Register" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin." group.long 0x4++0xB line.long 0x0 "UA_IER,UART Interrupt Enable Register" bitfld.long 0x0 15. "DMA_RX_EN,RX DMA Enable Bit (Not Available In UART2 Channel).This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled" bitfld.long 0x0 14. "DMA_TX_EN,TX DMA Enable Bit (Not Available In UART2 Channel).This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled" newline bitfld.long 0x0 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel).When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled" bitfld.long 0x0 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel).When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled" newline bitfld.long 0x0 11. "TIME_OUT_EN,Time-Out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled" bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable Bit.Note: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled" newline bitfld.long 0x0 6. "WAKE_EN,UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip is.." bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled" newline bitfld.long 0x0 4. "TOUT_IEN,RX Time-Out Interrupt Enable Bit" "0: TOUT_INT Masked off,1: TOUT_INT Enabled" bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)" "0: MODEM_INT Masked off,1: MODEM_INT Enabled" newline bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit" "0: RLS_INT Masked off,1: RLS_INT Enabled" bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: THRE_INT Masked off,1: THRE_INT Enabled" newline bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit" "0: RDA_INT Masked off,1: RDA_INT Enabled" line.long 0x4 "UA_FCR,UART FIFO Control Register" hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel).Note: This field is used for RTS auto-flow control." bitfld.long 0x4 8. "RX_DIS,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver).Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level.When the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated)." bitfld.long 0x4 2. "TFR,TX Field Software Reset.When TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x4 1. "RFR,RX Field Software Reset.When RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note: This bit will automatically clear at least 3 UART peripherial clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x8 "UA_LCR,UART Line Control Register" bitfld.long 0x8 6. "BCB,Break Control Bit.When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1" bitfld.long 0x8 5. "SPE,Stick Parity Enable Bit" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.." newline bitfld.long 0x8 4. "EPE,Even Parity Enable Bit.This bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x8 3. "PBE,Parity Bit Enable Bit" "0: No parity bit,1: Parity bit is generated on each outgoing.." newline bitfld.long 0x8 2. "NSB,Number Of 'STOP Bit'" "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x8 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,?,?" rgroup.long 0x18++0x7 line.long 0x0 "UA_FSR,UART FIFO Status Register" bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty" bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only).If TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1..Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..This bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.." bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO is full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one..The Maximum.." newline bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only).This bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only).This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit..Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) .Note1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode..Note2: This bit is read only but can be cleared by.." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only).This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set..Note: This bit is read only .." "0: RX FIFO is not overflow,1: RX FIFO is overflow" line.long 0x4 "UA_ISR,UART Interrupt Status Register" bitfld.long 0x4 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode" bitfld.long 0x4 28. "HW_TOUT_INT,In DMA Mode Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode" newline bitfld.long 0x4 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel).This bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode" bitfld.long 0x4 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only).This bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode" newline bitfld.long 0x4 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" bitfld.long 0x4 20. "HW_TOUT_IF,In DMA Mode Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x4 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x4 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only).This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). If RLS_IEN (UA_IER.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline bitfld.long 0x4 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only).This bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated" bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel).This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only).Note: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]) LIN_BKDET_F(UA_LIN_SR[9]) BIT_ERR_F(UA_LIN_SR[9]) LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared." "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.." newline bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5])is set the transfer is not correct. If BUF_ERR_IEN (UA_IER.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated.0 = No.." bitfld.long 0x4 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled the Tout interrupt will be generated..Note:.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" newline bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel).Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" newline bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) .This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled the RDA interrupt will be generated..Note: This bit is read.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x1B line.long 0x0 "UA_TOR,UART Time-out Register" hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit." hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-Out Interrupt Comparator" line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable Bit.Refer to Table 6.132 for more information..Note: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.." bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal To 1.Refer to Table 6.132 for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.." newline hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X" hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider" line.long 0x8 "UA_IRCR,UART IrDA Control Register" bitfld.long 0x8 6. "INV_RX,IrDA Inverse Receive Input Signal Control" "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x8 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control" "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x8 1. "TX_SELECT,TX_SELECT" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register" hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register .This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit.This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) .Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled" bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) .Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" newline bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: This break field length is UA_LIN_BKFL + 1" line.long 0x10 "UA_FUN_SEL,UART Function Select Register" bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable Bit" "0: UART function Enabled,1: LIN function Enabled,?,?" line.long 0x14 "UA_LIN_CTL,UART LIN Control Register" hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register.If the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field...Note1: User can fill any.." bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length..Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?" hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]..Note2: This.." newline bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled" bitfld.long 0x14 11. "LIN_RX_DIS,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable Bit.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22])..Note1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit.Note: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this field.." "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.." bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x18 "UA_LIN_SR,UART LIN Status Register" rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only).At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set." "0,1" rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only).This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only).This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct" newline rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only).This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' .." "0: LIN header error not detected,1: LIN header error detected" rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only).This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" tree.end endif sif (cpuis("NUC029?GE")) tree "UART0" base ad:0x40050000 group.long 0x0++0x4B line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register" bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer.Write Operation:.By writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1" hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer.Write Operation:.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD..Read.." line.long 0x4 "UART_INTEN,UART Interrupt Enable Register" bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit.If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled" bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" newline bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit.This bit can enable or disable RX PDMA service..Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled" bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit.This bit can enable or disable TX PDMA service." "0: TX PDMA Disabled,1: TX PDMA Enabled" newline bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit.Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit.Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" newline bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled" bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit.Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" newline bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" newline bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled" bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled" newline bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled" newline bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" line.long 0x8 "UART_FIFO,UART FIFO Control Register" hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use.Note: This field is used for auto nRTS flow control." bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level.When the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)." bitfld.long 0x8 2. "TXRST,TX Field Software Reset.When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note1: This bit will automatically clear at least 3 UART peripheral clock cycles..Note2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x8 1. "RXRST,RX Field Software Reset.When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note1: This bit will automatically clear at least 3 UART peripheral clock cycles..Note2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0xC "UART_LINE,UART Line Control Register" bitfld.long 0xC 9. "RXDINV,RX Data Inverted.Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller..Note2:.." "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled" bitfld.long 0xC 8. "TXDINV,TX Data Inverted.Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller..Note2:.." "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled" newline bitfld.long 0xC 7. "PSS,Parity Bit Source Selection.The parity bit can be selected to be generated and checked automatically or by software..Note1: This bit has effect only when PBE (UART_LINE[3]) is set..Note2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software" bitfld.long 0xC 6. "BCB,Break Control Bit.Note: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled" newline bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit.Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled" bitfld.long 0xC 4. "EPE,Even Parity Enable Bit.Note: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit.Note: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled" bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." newline bitfld.long 0xC 0.--1. "WLS,Word Length Selection.This field sets UART word length." "0: 5 bits,1: 6 bits,?,?" line.long 0x10 "UART_MODEM,UART Modem Control Register" rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only).This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state" bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level.This bit defines the active level state of nRTS pin output..Note1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode..Note2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode..Note3: Before.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active. (Default)" newline bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control.This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration..Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive" line.long 0x14 "UART_MODEMSTS,UART Modem Status Register" bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level.This bit defines the active level state of nCTS pin input..Note: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)" rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only).This bit mirror from nCTS pin input of voltage logic status..Note: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" newline bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag.This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1..Note: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state" line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register" rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only).This bit indicates TX and RX are active or inactive..Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller can not transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)" rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only).This bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)" newline rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag.If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1..Note: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one..The Maximum.." rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one..The Maximum value shown in RXPTR is.." newline bitfld.long 0x18 6. "BIF,Break Interrupt Flag.This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x18 5. "FEF,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)..Note: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x18 4. "PEF,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'..Note: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag.Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode..Note2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag.This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow..Note: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag.This bit is set to logic '1' when auto-baud rate detect function is finished..Note: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag.This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set..Note: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow" line.long 0x1C "UART_INTSTS,UART Interrupt Status Register" rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only).This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated" rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) .This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated" newline rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only).This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode" rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only).This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode" newline rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode" rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only).This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode" newline rbitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only).This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated" rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.." newline rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.." rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode" newline rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only).This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode" rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" newline rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only).This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated" rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only).This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated" rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated." newline rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag.Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.." newline rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only).This bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1..Note: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated" rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated" rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only).This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated..Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" line.long 0x20 "UART_TOUT,UART Time-out Register" hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time." hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator" line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register" bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1.This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1" bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0.This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1" newline hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1.This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.223." hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider. This filed is used in baud rate calculation. .Note: The detail description is shown in Table 6.223." line.long 0x28 "UART_IRDA,UART IrDA Control Register" bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal .Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)" bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal .Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal" newline bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit.Note: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))." "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register" hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value .This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit.Note: This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated" newline bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit.This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function (AUD) .Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).." newline bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) .Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: This break field length is BRKFL + 1." line.long 0x30 "UART_FUNCSEL,UART Function Select Register" bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit.Setting this bit can disable TX and RX..Note: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled" bitfld.long 0x30 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?" line.long 0x34 "UART_LINCTL,UART LIN Control Register (Only for UART0 and UART1)" hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits.If the parity generated by hardware user fill ID0~ID5 (PID [29:24] ) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field..Note1: User can fill any 8-bit value to this.." bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length .Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?" hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length .This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." newline bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled" bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22])..Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]);.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit.Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.." bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x38 "UART_LINSTS,UART LIN Status Register (Only for UART0 and UART1)" bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag .At TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected" bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag.This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag .This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct" newline bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag.This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame error in.." "0: LIN header error not detected,1: LIN header error detected" bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag.This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register" bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten.These 9-bits are used to define the relative bit is compensated or not. .BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit." line.long 0x40 "UART_WKCTL,UART Wake-up Control Register" bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit.Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.." bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit.Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode.and ADDRDEN (UART_ALTCTL[15]) is set to 1." "0: RS-485 Address Match (AAD mode) wake-up system..,1: RS-485 Address Match (AAD mode) wake-up system.." newline bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.." bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." newline bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled when the.." line.long 0x44 "UART_WKSTS,UART Wake-up Status Register" bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag.This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up..Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Received.." bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag.This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode)..Note1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.." newline bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag.This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up ..Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Received.." bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag.This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'..Note2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Incoming.." newline bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag.This bit is set if chip wake-up from power-down state by nCTS wake-up..Note1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'..Note2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" line.long 0x48 "UART_DWKCOMP,UART Imcoming Data Wake-up Compensation Register" hexmask.long.word 0x48 0.--15. 1. "STCOMP,Start Bit Compensation Value.These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode..Note: It is valid only when WKDATEN.." tree.end tree "UART1" base ad:0x40150000 group.long 0x0++0x4B line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register" bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer.Write Operation:.By writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1" hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer.Write Operation:.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD..Read.." line.long 0x4 "UART_INTEN,UART Interrupt Enable Register" bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit.If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled" bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" newline bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit.This bit can enable or disable RX PDMA service..Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled" bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit.This bit can enable or disable TX PDMA service." "0: TX PDMA Disabled,1: TX PDMA Enabled" newline bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit.Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit.Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" newline bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled" bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit.Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" newline bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" newline bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled" bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled" newline bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled" newline bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" line.long 0x8 "UART_FIFO,UART FIFO Control Register" hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use.Note: This field is used for auto nRTS flow control." bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level.When the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)." bitfld.long 0x8 2. "TXRST,TX Field Software Reset.When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note1: This bit will automatically clear at least 3 UART peripheral clock cycles..Note2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x8 1. "RXRST,RX Field Software Reset.When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note1: This bit will automatically clear at least 3 UART peripheral clock cycles..Note2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0xC "UART_LINE,UART Line Control Register" bitfld.long 0xC 9. "RXDINV,RX Data Inverted.Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller..Note2:.." "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled" bitfld.long 0xC 8. "TXDINV,TX Data Inverted.Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller..Note2:.." "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled" newline bitfld.long 0xC 7. "PSS,Parity Bit Source Selection.The parity bit can be selected to be generated and checked automatically or by software..Note1: This bit has effect only when PBE (UART_LINE[3]) is set..Note2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software" bitfld.long 0xC 6. "BCB,Break Control Bit.Note: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled" newline bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit.Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled" bitfld.long 0xC 4. "EPE,Even Parity Enable Bit.Note: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit.Note: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled" bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." newline bitfld.long 0xC 0.--1. "WLS,Word Length Selection.This field sets UART word length." "0: 5 bits,1: 6 bits,?,?" line.long 0x10 "UART_MODEM,UART Modem Control Register" rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only).This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state" bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level.This bit defines the active level state of nRTS pin output..Note1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode..Note2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode..Note3: Before.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active. (Default)" newline bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control.This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration..Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive" line.long 0x14 "UART_MODEMSTS,UART Modem Status Register" bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level.This bit defines the active level state of nCTS pin input..Note: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)" rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only).This bit mirror from nCTS pin input of voltage logic status..Note: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" newline bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag.This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1..Note: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state" line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register" rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only).This bit indicates TX and RX are active or inactive..Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller can not transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)" rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only).This bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)" newline rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag.If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1..Note: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one..The Maximum.." rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one..The Maximum value shown in RXPTR is.." newline bitfld.long 0x18 6. "BIF,Break Interrupt Flag.This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x18 5. "FEF,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)..Note: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x18 4. "PEF,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'..Note: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag.Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode..Note2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag.This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow..Note: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag.This bit is set to logic '1' when auto-baud rate detect function is finished..Note: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag.This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set..Note: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow" line.long 0x1C "UART_INTSTS,UART Interrupt Status Register" rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only).This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated" rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) .This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated" newline rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only).This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode" rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only).This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode" newline rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode" rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only).This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode" newline rbitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only).This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated" rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.." newline rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.." rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode" newline rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only).This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode" rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" newline rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only).This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated" rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only).This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated" rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag.Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.." newline rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only).This bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1..Note: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated" rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated" rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only).This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated..Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" line.long 0x20 "UART_TOUT,UART Time-out Register" hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time." hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator" line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register" bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1.This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1" bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0.This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1" newline hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1.This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.223." hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider. This filed is used in baud rate calculation. .Note: The detail description is shown in Table 6.223." line.long 0x28 "UART_IRDA,UART IrDA Control Register" bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal .Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)" bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal .Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal" newline bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit.Note: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))." "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register" hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value .This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length .Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit.Note: This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated" newline bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit.This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function (AUD) .Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).." newline bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) .Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: This break field length is BRKFL + 1." line.long 0x30 "UART_FUNCSEL,UART Function Select Register" bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit.Setting this bit can disable TX and RX..Note: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled" bitfld.long 0x30 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?" line.long 0x34 "UART_LINCTL,UART LIN Control Register (Only for UART0 and UART1)" hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits.If the parity generated by hardware user fill ID0~ID5 (PID [29:24] ) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field..Note1: User can fill any 8-bit value to this.." bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length .Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?" hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length .This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." newline bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled" bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22])..Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]);.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit.Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.." bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x38 "UART_LINSTS,UART LIN Status Register (Only for UART0 and UART1)" bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag .At TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected" bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag.This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag .This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct" newline bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag.This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame error in.." "0: LIN header error not detected,1: LIN header error detected" bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag.This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register" bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten.These 9-bits are used to define the relative bit is compensated or not. .BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit." line.long 0x40 "UART_WKCTL,UART Wake-up Control Register" bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit.Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.." bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit.Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode.and ADDRDEN (UART_ALTCTL[15]) is set to 1." "0: RS-485 Address Match (AAD mode) wake-up system..,1: RS-485 Address Match (AAD mode) wake-up system.." newline bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.." bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." newline bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled when the.." line.long 0x44 "UART_WKSTS,UART Wake-up Status Register" bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag.This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up..Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Received.." bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag.This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode)..Note1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.." newline bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag.This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up ..Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Received.." bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag.This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'..Note2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Incoming.." newline bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag.This bit is set if chip wake-up from power-down state by nCTS wake-up..Note1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'..Note2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" line.long 0x48 "UART_DWKCOMP,UART Imcoming Data Wake-up Compensation Register" hexmask.long.word 0x48 0.--15. 1. "STCOMP,Start Bit Compensation Value.These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode..Note: It is valid only when WKDATEN.." tree.end tree "UART2" base ad:0x40154000 group.long 0x0++0x4B line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register" bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer.Write Operation:.By writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1" hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer.Write Operation:.By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD..Read.." line.long 0x4 "UART_INTEN,UART Interrupt Enable Register" bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit.If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled" bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" newline bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit.This bit can enable or disable RX PDMA service..Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled" bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit.This bit can enable or disable TX PDMA service." "0: TX PDMA Disabled,1: TX PDMA Enabled" newline bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit.Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit.Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" newline bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled" bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit.Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" newline bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" newline bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled" bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled" newline bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled" newline bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" line.long 0x8 "UART_FIFO,UART FIFO Control Register" hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use.Note: This field is used for auto nRTS flow control." bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit.The receiver is disabled or not (set 1 to disable receiver)..Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled" newline hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level.When the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)." bitfld.long 0x8 2. "TXRST,TX Field Software Reset.When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared..Note1: This bit will automatically clear at least 3 UART peripheral clock cycles..Note2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x8 1. "RXRST,RX Field Software Reset.When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared..Note1: This bit will automatically clear at least 3 UART peripheral clock cycles..Note2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0xC "UART_LINE,UART Line Control Register" bitfld.long 0xC 9. "RXDINV,RX Data Inverted.Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller..Note2:.." "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled" bitfld.long 0xC 8. "TXDINV,TX Data Inverted.Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller..Note2:.." "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled" newline bitfld.long 0xC 7. "PSS,Parity Bit Source Selection.The parity bit can be selected to be generated and checked automatically or by software..Note1: This bit has effect only when PBE (UART_LINE[3]) is set..Note2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software" bitfld.long 0xC 6. "BCB,Break Control Bit.Note: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled" newline bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit.Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled" bitfld.long 0xC 4. "EPE,Even Parity Enable Bit.Note: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit.Note: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled" bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." newline bitfld.long 0xC 0.--1. "WLS,Word Length Selection.This field sets UART word length." "0: 5 bits,1: 6 bits,?,?" line.long 0x10 "UART_MODEM,UART Modem Control Register" rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only).This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state" bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level.This bit defines the active level state of nRTS pin output..Note1: Refer to Figure 6.2313 and Figure 6.2314 for UART function mode..Note2: Refer to Figure 6.2324 and Figure 6.2325 for RS-485 function mode..Note3: Before.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active. (Default)" newline bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control.This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration..Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive" line.long 0x14 "UART_MODEMSTS,UART Modem Status Register" bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level.This bit defines the active level state of nCTS pin input..Note: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)" rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only).This bit mirror from nCTS pin input of voltage logic status..Note: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" newline bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag.This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1..Note: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state" line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register" rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only).This bit indicates TX and RX are active or inactive..Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller can not transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)" rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only).This bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)" newline rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only).This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted..Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag.If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1..Note: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only).This bit indicates TX FIFO full or not..Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only).This bit indicates TX FIFO empty or not..Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only).This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one..The Maximum.." rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only).This bit initiates RX FIFO full or not..Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only).This bit initiate RX FIFO empty or not..Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only).This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one..The Maximum value shown in RXPTR is.." newline bitfld.long 0x18 6. "BIF,Break Interrupt Flag.This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x18 5. "FEF,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)..Note: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x18 4. "PEF,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'..Note: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag.Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode..Note2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: Receiver detects a data that is an address bit.." newline bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag.This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow..Note: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag.This bit is set to logic '1' when auto-baud rate detect function is finished..Note: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag.This bit is set when RX FIFO overflow..If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set..Note: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow" line.long 0x1C "UART_INTSTS,UART Interrupt Status Register" rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only).This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated" rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) .This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated" newline rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only).This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode" rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only).This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode" newline rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode" rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only).This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode" newline rbitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only).This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated" rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only).This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.." newline rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.." rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode" newline rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only).This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode" rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only).This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" newline rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only).This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated" rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only).This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only).This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated" rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only).This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) .This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated" rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only).This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only).This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag.Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.." newline rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only).This bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1..Note: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated" rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only).This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only).This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated" rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only).Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only) .This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only).This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated..Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated..Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" line.long 0x20 "UART_TOUT,UART Time-out Register" hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value .This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time." hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator" line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register" bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1.This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1" bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0.This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1" newline hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1.This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.233." hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider.The field indicates the baud rate divider. This filed is used in baud rate calculation. .Note: The detail description is shown in Table 6.233." line.long 0x28 "UART_IRDA,UART IrDA Control Register" bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal .Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)" bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal .Note1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal" newline bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit.Note: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))." "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register" hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value .This field contains the RS-485 address match values..Note: This field is used for RS-485 auto address detection mode." bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length .Note : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" newline bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit.Note : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) .This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated" newline bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit.This bit is used to enable RS-485 Address Detection mode. .Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function (AUD) .Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).." newline bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD).Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) .Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit.Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length.This field indicates a 4-bit LIN TX break field count..Note1: This break field length is BRKFL + 1." line.long 0x30 "UART_FUNCSEL,UART Function Select Register" bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit.Setting this bit can disable TX and RX..Note: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled" bitfld.long 0x30 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?" line.long 0x34 "UART_LINCTL,UART LIN Control Register (Only for UART0 and UART1)" hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits.If the parity generated by hardware user fill ID0~ID5 (PID [29:24] ) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field..Note1: User can fill any 8-bit value to this.." bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?" newline bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length .Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?" hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length .This field indicates a 4-bit LIN TX break field count..Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." newline bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled" bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit.The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22])..Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]);.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit.Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.23.5.10 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled" newline bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit.Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) .Note3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.." bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit.Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1)..Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" newline bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" line.long 0x38 "UART_LINSTS,UART LIN Status Register (Only for UART0 and UART1)" bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag .At TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected" bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag.This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field.This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag .This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct" newline bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag.This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame error in.." "0: LIN header error not detected,1: LIN header error detected" bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag.This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it..Note3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register" bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten.These 9-bits are used to define the relative bit is compensated or not. .BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit." line.long 0x40 "UART_WKCTL,UART Wake-up Control Register" bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit.Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.." bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit.Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode.and ADDRDEN (UART_ALTCTL[15]) is set to 1." "0: RS-485 Address Match (AAD mode) wake-up system..,1: RS-485 Address Match (AAD mode) wake-up system.." newline bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.." bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.." newline bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled when the.." line.long 0x44 "UART_WKSTS,UART Wake-up Status Register" bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag.This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up..Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Received.." bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag.This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode)..Note1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.." newline bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag.This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up ..Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Received.." bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag.This bit is set if chip wake-up from power-down state by data wake-up..Note1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'..Note2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by Incoming.." newline bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag.This bit is set if chip wake-up from power-down state by nCTS wake-up..Note1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'..Note2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS wake-up" line.long 0x48 "UART_DWKCOMP,UART Imcoming Data Wake-up Compensation Register" hexmask.long.word 0x48 0.--15. 1. "STCOMP,Start Bit Compensation Value.These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode..Note: It is valid only when WKDATEN.." tree.end endif tree.end sif (cpuis("NUC029?EE")||cpuis("NUC029?GE")) tree "USBD (USB Device Controller)" base ad:0x40060000 sif (cpuis("NUC029?EE")) group.long 0x0++0xB line.long 0x0 "USB_INTEN,USB Interrupt Enable Register" bitfld.long 0x0 15. "INNAK_EN,Active NAK Function And Its Status In IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS.." bitfld.long 0x0 8. "WAKEUP_EN,Wake-Up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled" newline bitfld.long 0x0 3. "WAKEUP_IE,USB Wake-Up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" bitfld.long 0x0 2. "FLDET_IE,Floating Detection Interrupt Enable Bit" "0: Floating detection Interrupt Disabled,1: Floating detection Interrupt Enabled" newline bitfld.long 0x0 1. "USB_IE,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled" bitfld.long 0x0 0. "BUS_IE,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled" line.long 0x4 "USB_INTSTS,USB Interrupt Event Status Register" bitfld.long 0x4 31. "SETUP,Setup Event Status" "0: No Setup event,1: SETUP event occurred cleared by write 1 to.." bitfld.long 0x4 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred on endpoint 7,1: USB event occurred on Endpoint 7 check.." newline bitfld.long 0x4 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred on endpoint 6,1: USB event occurred on Endpoint 6 check.." bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred on endpoint 5,1: USB event occurred on Endpoint 5 check.." newline bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred on endpoint 4,1: USB event occurred on Endpoint 4 check.." bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred on endpoint 3,1: USB event occurred on Endpoint 3 check.." newline bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred on endpoint 2,1: USB event occurred on Endpoint 2 check.." bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred on endpoint 1,1: USB event occurred on Endpoint 1 check.." newline bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred on endpoint 0,1: USB event occurred on Endpoint 0 check.." bitfld.long 0x4 4. "SOSOF_STS,Start of Frame Interrupt Status" "0: SOF event does not occur,1: SOF event occurred cleared by write 1 to.." newline bitfld.long 0x4 3. "WAKEUP_STS,Wake-Up Interrupt Status" "0: No Wake-up event occurred,1: Wake-up event occurred cleared by write 1 to.." bitfld.long 0x4 2. "FLDET_STS,Floating Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.." newline bitfld.long 0x4 1. "USB_STS,USB Event Interrupt Status.The USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus." "0: No USB event occurred,1: USB event occurred check EPSTS0~7 to know which.." bitfld.long 0x4 0. "BUS_STS,BUS Interrupt Status.The BUS event means that there is one of the suspense or the resume function in the bus." "0: No BUS event occurred,1: Bus event occurred; check USB_ATTR[3:0] to know.." line.long 0x8 "USB_FADDR,USB Device Function Address Register" hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB Device Function Address" rgroup.long 0xC++0x3 line.long 0x0 "USB_EPSTS,USB Endpoint Status Register" bitfld.long 0x0 29.--31. "EPSTS7,Endpoint 7 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 26.--28. "EPSTS6,Endpoint 6 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 23.--25. "EPSTS5,Endpoint 5 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 20.--22. "EPSTS4,Endpoint 4 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 17.--19. "EPSTS3,Endpoint 3 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 14.--16. "EPSTS2,Endpoint 2 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 11.--13. "EPSTS1,Endpoint 1 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "EPSTS0,Endpoint 0 Bus Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 7. "OVERRUN,Overrun.It indicates that the received data is over the maximum payload number or not." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.." group.long 0x10++0x3 line.long 0x0 "USB_ATTR,USB Bus Status and Attribution Register" bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.." bitfld.long 0x0 9. "PWRDN,Power-Down PHY Transceiver Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver" newline bitfld.long 0x0 8. "DPPU_EN,Pull-Up Resistor On USB_D+ Enable Bit" "0: Pull-up resistor in USB_D+ pin Disabled,1: Pull-up resistor in USB_D+ pin Enabled" bitfld.long 0x0 7. "USB_EN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled" newline bitfld.long 0x0 5. "RWAKEUP,Remote Wake-Up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D- high).." bitfld.long 0x0 4. "PHY_EN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled" newline bitfld.long 0x0 3. "TIMEOUT,Time-Out Status.Note: This bit is read only." "0: No time-out,1: No Bus response more than 18 bits time" bitfld.long 0x0 2. "RESUME,Resume Status.Note: This bit is read only." "0: No bus resume,1: Resume from suspend" newline bitfld.long 0x0 1. "SUSPEND,Suspend Status.Note: This bit is read only." "0: Bus no suspend,1: Bus idle more than 3ms either cable is plugged.." bitfld.long 0x0 0. "USBRST,USB Reset Status.Note: This bit is read only." "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) is presented.." rgroup.long 0x14++0x3 line.long 0x0 "USB_FLDET,USB Floating Detection Register" bitfld.long 0x0 0. "FLDET,Device Floating Detected" "0: Controller is not attached into the USB host,1: Controller is attached into the BUS" group.long 0x18++0x3 line.long 0x0 "USB_STBUFSEG,Setup Token Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "STBUFSEG,Setup Token Buffer Segmentation.It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is.USB_SRAM address + {STBUFSEG[8:3] 3'b000} .Note: It is used for SETUP.." group.long 0x90++0x3 line.long 0x0 "USB_DRVSE0,USB Drive SE0 Control Register" bitfld.long 0x0 0. "DRVSE0,Drive Single Ended Zero In USB Bus.The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low." "0: None,1: Force USB PHY transceiver to drive SE0" group.long 0x500++0x7F line.long 0x0 "USB_BUFSEG0,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x4 "USB_MXPLD0,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x8 "USB_CFG0,Endpoint 0 Configuration Register" bitfld.long 0x8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x8 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0xC "USB_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0xC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0xC 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x10 "USB_BUFSEG1,Endpoint 1 Buffer Segmentation Register" hexmask.long.byte 0x10 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x14 "USB_MXPLD1,Endpoint 1 Maximal Payload Register" hexmask.long.word 0x14 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x18 "USB_CFG1,Endpoint 1 Configuration Register" bitfld.long 0x18 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x18 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x18 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x18 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x1C "USB_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x1C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x1C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x20 "USB_BUFSEG2,Endpoint 2 Buffer Segmentation Register" hexmask.long.byte 0x20 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x24 "USB_MXPLD2,Endpoint 2 Maximal Payload Register" hexmask.long.word 0x24 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x28 "USB_CFG2,Endpoint 2 Configuration Register" bitfld.long 0x28 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x28 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x28 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x28 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x2C "USB_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x2C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x2C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x30 "USB_BUFSEG3,Endpoint 3 Buffer Segmentation Register" hexmask.long.byte 0x30 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x34 "USB_MXPLD3,Endpoint 3 Maximal Payload Register" hexmask.long.word 0x34 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x38 "USB_CFG3,Endpoint 3 Configuration Register" bitfld.long 0x38 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x38 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x38 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x38 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x3C "USB_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x3C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x3C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x40 "USB_BUFSEG4,Endpoint 4 Buffer Segmentation Register" hexmask.long.byte 0x40 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x44 "USB_MXPLD4,Endpoint 4 Maximal Payload Register" hexmask.long.word 0x44 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x48 "USB_CFG4,Endpoint 4 Configuration Register" bitfld.long 0x48 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x48 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x48 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x48 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x4C "USB_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x4C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x4C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x50 "USB_BUFSEG5,Endpoint 5 Buffer Segmentation Register" hexmask.long.byte 0x50 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x54 "USB_MXPLD5,Endpoint 5 Maximal Payload Register" hexmask.long.word 0x54 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x58 "USB_CFG5,Endpoint 5 Configuration Register" bitfld.long 0x58 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x58 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x58 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x58 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x5C "USB_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x5C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x5C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x60 "USB_BUFSEG6,Endpoint 6 Buffer Segmentation Register" hexmask.long.byte 0x60 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x64 "USB_MXPLD6,Endpoint 6 Maximal Payload Register" hexmask.long.word 0x64 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x68 "USB_CFG6,Endpoint 6 Configuration Register" bitfld.long 0x68 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x68 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x68 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x68 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x68 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x6C "USB_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x6C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x6C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" line.long 0x70 "USB_BUFSEG7,Endpoint 7 Buffer Segmentation Register" hexmask.long.byte 0x70 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USB_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section 5.4.4.7.." line.long 0x74 "USB_MXPLD7,Endpoint 7 Maximal Payload Register" hexmask.long.word 0x74 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x78 "USB_CFG7,Endpoint 7 Configuration Register" bitfld.long 0x78 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x78 7. "DSQ_SYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x78 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x78 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x78 0.--3. 1. "EP_NUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint." line.long 0x7C "USB_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x7C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x7C 0. "CLRRDY,Clear Ready.When the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to turn it off and it.." "0,1" endif sif (cpuis("NUC029?GE")) group.long 0x0++0xB line.long 0x0 "USBD_INTEN,USB Device Interrupt Enable Register" bitfld.long 0x0 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS.." bitfld.long 0x0 8. "WKEN,Wake-up Function Enable Bit" "0: USB Wake-up Function Disabled,1: USB Wake-up Function Enabled" newline bitfld.long 0x0 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled" bitfld.long 0x0 3. "WKIDLEIEN,USB Wake-up Idle Interrupt Enable Bit" "0: Wake-up Idle Interrupt Disabled,1: Wake-up Idle Interrupt Enabled" newline bitfld.long 0x0 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS Detection Interrupt Disabled,1: VBUS Detection Interrupt Enabled" bitfld.long 0x0 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB Event Interrupt Disabled,1: USB Event Interrupt Enabled" newline bitfld.long 0x0 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS Event Interrupt Disabled,1: BUS Event Interrupt Enabled" line.long 0x4 "USBD_INTSTS,USB Device Interrupt Event Status Register" bitfld.long 0x4 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by write 1 to.." bitfld.long 0x4 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.." newline bitfld.long 0x4 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.." bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.." newline bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.." bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.." newline bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.." bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.." newline bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.." bitfld.long 0x4 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event does not occur,1: SOF event occurred cleared by write 1 to.." newline bitfld.long 0x4 3. "WKIDLEIF,No-event-wake-up Interrupt Status" "0: WKIDLE event does not occur,1: No-event-wake-up event occurred cleared by write.." bitfld.long 0x4 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.." newline bitfld.long 0x4 1. "USBIF,USB Event Interrupt Status.The USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus." "0: No USB event occurred,1: USB event occurred check EPSTS0~5[2:0] to know.." bitfld.long 0x4 0. "BUSIF,BUS Interrupt Status.The BUS event means that there is one of the suspense or the resume function in the bus." "0: No BUS event occurred,1: Bus event occurred; check USBD_ATTR[3:0] and.." line.long 0x8 "USBD_FADDR,USB Device Function Address Register" hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB Device Function Address" rgroup.long 0xC++0x3 line.long 0x0 "USBD_EPSTS,USB Device Endpoint Status Register" bitfld.long 0x0 29.--31. "EPSTS7,Endpoint 7 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 26.--28. "EPSTS6,Endpoint 6 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 23.--25. "EPSTS5,Endpoint 5 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 20.--22. "EPSTS4,Endpoint 4 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 17.--19. "EPSTS3,Endpoint 3 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 14.--16. "EPSTS2,Endpoint 2 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 11.--13. "EPSTS1,Endpoint 1 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "EPSTS0,Endpoint 0 Status.These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 7. "OV,Overrun.It indicates that the received data is over the maximum payload number or not." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.." group.long 0x10++0x3 line.long 0x0 "USBD_ATTR,USB Device Bus Status and Attribution Register" rbitfld.long 0x0 13. "L1RESUME,LPM L1 Resume (Read Only)" "0: Bus no LPM L1 state resume,1: LPM L1 state Resume from LPM L1 state suspend" rbitfld.long 0x0 12. "L1SUSPEND,LPM L1 Suspend (Read Only)" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM command.." newline bitfld.long 0x0 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: the valid LPM Token will be NYET,1: the valid LPM Token will be ACK" bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.." newline bitfld.long 0x0 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active" bitfld.long 0x0 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled" newline bitfld.long 0x0 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).." bitfld.long 0x0 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled" newline rbitfld.long 0x0 3. "TOUT,Time-out Status (Read Only)" "0: No time-out,1: No Bus response more than 18 bits time" rbitfld.long 0x0 2. "RESUME,Resume Status (Read Only)" "0: No bus resume,1: Resume from suspend" newline rbitfld.long 0x0 1. "SUSPEND,Suspend Status (Read Only)" "0: No Bus suspend,1: Bus idle more than 3ms either cable is plugged.." rbitfld.long 0x0 0. "USBRST,USB Reset Status (Read Only)" "0: No Bus reset,1: Bus reset when SE0 (single-ended 0) more than.." rgroup.long 0x14++0x3 line.long 0x0 "USBD_VBUSDET,USB Device VBUS Detection Register" bitfld.long 0x0 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host" group.long 0x18++0x3 line.long 0x0 "USBD_STBUFSEG,Setup Token Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "STBUFSEG,SETUP Token Buffer Segmentation.It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is.USBD_SRAM address + {STBUFSEG[8:3] 3'b000} .Note: It is used for SETUP.." rgroup.long 0x88++0x3 line.long 0x0 "USBD_LPMATTR,USB LPM Attribution Register" bitfld.long 0x0 8. "LPMRWAKUP,LPM Remote Wakeup.This bit contains the bRemoteWake value received with last ACK LPM Token" "0,1" hexmask.long.byte 0x0 4.--7. 1. "LPMBESL,LPM Best Effort Service Latency.These bits contain the BESL value received with last ACK LPM Token" newline hexmask.long.byte 0x0 0.--3. 1. "LPMLINKSTS,LPM Link State.These bits contain the bLinkState received with last ACK LPM Token" endif rgroup.long 0x8C++0x3 line.long 0x0 "USBD_FN,USB Frame Number Register" hexmask.long.word 0x0 0.--10. 1. "FN,Frame Number.These bits contain the 11-bits frame number in the last received SOF packet." sif (cpuis("NUC029?GE")) group.long 0x90++0x3 line.long 0x0 "USBD_SE0,USB Device Drive SE0 Control Register" bitfld.long 0x0 0. "SE0,Drive Single Ended Zero in USB Bus.The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low." "0: Normal operation,1: Force USB PHY transceiver to drive SE0" group.long 0x500++0x7F line.long 0x0 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x4 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x8 "USBD_CFG0,Endpoint 0 Configuration Register" bitfld.long 0x8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x8 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x8 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x8 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0xC "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0xC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0xC 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x10 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register" hexmask.long.byte 0x10 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x14 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register" hexmask.long.word 0x14 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x18 "USBD_CFG1,Endpoint 1 Configuration Register" bitfld.long 0x18 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x18 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x18 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x18 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x1C "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x1C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x1C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x20 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register" hexmask.long.byte 0x20 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x24 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register" hexmask.long.word 0x24 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x28 "USBD_CFG2,Endpoint 2 Configuration Register" bitfld.long 0x28 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x28 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x28 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x28 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x2C "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x2C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x2C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x30 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register" hexmask.long.byte 0x30 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x34 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register" hexmask.long.word 0x34 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x38 "USBD_CFG3,Endpoint 3 Configuration Register" bitfld.long 0x38 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x38 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x38 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x38 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x3C "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x3C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x3C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x40 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register" hexmask.long.byte 0x40 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x44 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register" hexmask.long.word 0x44 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x48 "USBD_CFG4,Endpoint 4 Configuration Register" bitfld.long 0x48 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x48 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x48 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x48 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x4C "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x4C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x4C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x50 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register" hexmask.long.byte 0x50 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x54 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register" hexmask.long.word 0x54 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x58 "USBD_CFG5,Endpoint 5 Configuration Register" bitfld.long 0x58 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x58 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x58 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x58 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x5C "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x5C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x5C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x60 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register" hexmask.long.byte 0x60 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x64 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register" hexmask.long.word 0x64 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x68 "USBD_CFG6,Endpoint 6 Configuration Register" bitfld.long 0x68 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x68 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x68 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x68 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x68 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x6C "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x6C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x6C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x70 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register" hexmask.long.byte 0x70 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation.It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is.USBD_SRAM address + { BUFSEG[8:3] 3'b000}.Refer to the section Figure.." line.long 0x74 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register" hexmask.long.word 0x74 0.--8. 1. "MXPLD,Maximal Payload.Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x78 "USBD_CFG7,Endpoint 7 Configuration Register" bitfld.long 0x78 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x78 7. "DSQSYNC,Data Sequence Synchronization.Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x78 5.--6. "STATE,Endpoint State" "0: Endpoint Disabled,1: Out endpoint,?,?" bitfld.long 0x78 4. "ISOCH,Isochronous Endpoint.This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x78 0.--3. 1. "EPNUM,Endpoint Number.These bits are used to define the endpoint number of the current endpoint" line.long 0x7C "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x7C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x7C 0. "CLRRDY,Clear Ready.When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" endif tree.end endif sif (cpuis("NUC029?GE")) tree "USCI (Universal Serial Control Interface)" base ad:0x0 tree "UI2C (I2C Mode)" tree "UI2C0" base ad:0x40070000 group.long 0x0++0x3 line.long 0x0 "UI2C_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" group.long 0x8++0x3 line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider.Note: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.." hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter.This bit field defines the divide ratio of the sample clock fSAMP_CLK..Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value." newline bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled" bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?" newline bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x2C++0x3 line.long 0x0 "UI2C_LINECTL,USCI Line Control Register" hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 8-bit transmit data for transmission." rgroup.long 0x34++0x3 line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer..Note1: In I2C protocol only use RXDAT[7:0].." group.long 0x44++0x23 line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0" hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address.In I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.." line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1" hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address.In I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.." line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0" hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask.USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .." line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1" hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask.USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .." line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register" bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register" bitfld.long 0x14 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register" bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled" hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle.This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. .Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.." newline bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit.This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus..Note: Depending on the.." "0: Monitor mode Disabled,1: Monitor mode Enabled" bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit.This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.." newline bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger.When a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active" bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled" newline bitfld.long 0x18 3. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1" newline bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1" bitfld.long 0x18 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled" bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))." "0: The error interrupt Disabled,1: The error interrupt Enabled" newline bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled" bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master." "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled" newline bitfld.long 0x1C 2. "STORIEN,Stop Condition Received Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if a stop condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled" bitfld.long 0x1C 1. "STARIEN,Start Condition Received Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if a start condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled" newline bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit.In I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled" line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register" bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost.This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode..Note: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.." bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.." newline bitfld.long 0x20 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done.Note: This bit can't release when WKIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.." bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status.This bit indicates that a slave read request has been detected..Note: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave read request has not been detected,1: A slave read request has been detected" newline bitfld.long 0x20 14. "SLASEL,Slave Select Status.This bit indicates that this device has been selected as slave..Note: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave" bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag.It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received" newline bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag.It is cleared by software writing 1 into this bit.Note: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: An I2C error has been detected" bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: An arbitration has not been lost,1: An arbitration has been lost" newline bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: A non - acknowledge has not been received,1: A non - acknowledge has been received" bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: A stop condition has not yet been detected,1: A stop condition has been detected" newline bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag.This bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected" bitfld.long 0x20 6. "ONBUSY,On Bus Busy.Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy" newline bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred" group.long 0x88++0x7 line.long 0x0 "UI2C_ADMAT,I2C Slave Match Address Register" bitfld.long 0x0 1. "ADMAT1,USCI Address 1 Match Status.When address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1" bitfld.long 0x0 0. "ADMAT0,USCI Address 0 Match Status.When address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1" line.long 0x4 "UI2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.byte 0x4 6.--11. 1. "HTCTL,Hold Time Configure Control.This field is used to generate the delay timing between SCL falling edge SDA edge in.transmission mode." hexmask.long.byte 0x4 0.--5. 1. "STCTL,Setup Time Configure Control.This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.." tree.end tree "UI2C1" base ad:0x40170000 group.long 0x0++0x3 line.long 0x0 "UI2C_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" group.long 0x8++0x3 line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider.Note: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.." hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter.This bit field defines the divide ratio of the sample clock fSAMP_CLK..Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value." newline bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled" bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?" newline bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x2C++0x3 line.long 0x0 "UI2C_LINECTL,USCI Line Control Register" hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 8-bit transmit data for transmission." rgroup.long 0x34++0x3 line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer..Note1: In I2C protocol only use RXDAT[7:0].." group.long 0x44++0x23 line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0" hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address.In I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.." line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1" hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address.In I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.." line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0" hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask.USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .." line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1" hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask.USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .." line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register" bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register" bitfld.long 0x14 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register" bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled" hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle.This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. .Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.." newline bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit.This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus..Note: Depending on the.." "0: Monitor mode Disabled,1: Monitor mode Enabled" bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit.This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.." newline bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger.When a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active" bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled" newline bitfld.long 0x18 3. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1" newline bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1" bitfld.long 0x18 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled" bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))." "0: The error interrupt Disabled,1: The error interrupt Enabled" newline bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled" bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master." "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled" newline bitfld.long 0x1C 2. "STORIEN,Stop Condition Received Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if a stop condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled" bitfld.long 0x1C 1. "STARIEN,Start Condition Received Interrupt Enable Bit.This bit enables the generation of a protocol interrupt if a start condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled" newline bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit.In I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled" line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register" bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost.This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode..Note: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.." bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.." newline bitfld.long 0x20 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done.Note: This bit can't release when WKIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.." bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status.This bit indicates that a slave read request has been detected..Note: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave read request has not been detected,1: A slave read request has been detected" newline bitfld.long 0x20 14. "SLASEL,Slave Select Status.This bit indicates that this device has been selected as slave..Note: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave" bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag.It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received" newline bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag.It is cleared by software writing 1 into this bit.Note: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: An I2C error has been detected" bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: An arbitration has not been lost,1: An arbitration has been lost" newline bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: A non - acknowledge has not been received,1: A non - acknowledge has been received" bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: A stop condition has not yet been detected,1: A stop condition has been detected" newline bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag.This bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected" bitfld.long 0x20 6. "ONBUSY,On Bus Busy.Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy" newline bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred" group.long 0x88++0x7 line.long 0x0 "UI2C_ADMAT,I2C Slave Match Address Register" bitfld.long 0x0 1. "ADMAT1,USCI Address 1 Match Status.When address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1" bitfld.long 0x0 0. "ADMAT0,USCI Address 0 Match Status.When address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1" line.long 0x4 "UI2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.byte 0x4 6.--11. 1. "HTCTL,Hold Time Configure Control.This field is used to generate the delay timing between SCL falling edge SDA edge in.transmission mode." hexmask.long.byte 0x4 0.--5. 1. "STCTL,Setup Time Configure Control.This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.." tree.end tree "UI2C2" base ad:0x40074000 group.long 0x0++0x3 line.long 0x0 "UI2C_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" group.long 0x8++0x3 line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider.Note: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.." hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter.This bit field defines the divide ratio of the sample clock fSAMP_CLK..Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value." newline bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled" bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?" newline bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x2C++0x3 line.long 0x0 "UI2C_LINECTL,USCI Line Control Register" hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission." rgroup.long 0x34++0x3 line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer..Note 1: In I2C protocol only use RXDAT[7:0].." group.long 0x44++0x23 line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0" hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address.In I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.." line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1" hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address.In I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.." line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0" hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask.USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .." line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1" hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask.USCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .." line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register" bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register" bitfld.long 0x14 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register" bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol disable,1: I2C Protocol enable" hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle.This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. .Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.." newline bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit.This bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus..Note: Depending on the.." "0: The monitor mode is disabled,1: The monitor mode is enabled" bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit.This bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.." newline bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger.When a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active" bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function is disabled,1: Address match 10 bit function is enabled" newline bitfld.long 0x18 3. "STA,I2C START Control.Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1" newline bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1" bitfld.long 0x18 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Control.This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt is disabled,1: The acknowledge interrupt is enabled" bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Control.This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))." "0: The error interrupt is disabled,1: The error interrupt is enabled" newline bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Control.This bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt is disabled,1: The arbitration lost interrupt is enabled" bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Control.This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master." "0: The non - acknowledge interrupt is disabled,1: The non - acknowledge interrupt is enabled" newline bitfld.long 0x1C 2. "STORIEN,Stop Condition Received Interrupt Enable Control.This bit enables the generation of a protocol interrupt if a stop condition is detected." "0: The stop condition interrupt is disabled,1: The stop condition interrupt is enabled" bitfld.long 0x1C 1. "STARIEN,Start Condition Received Interrupt Enable Control.This bit enables the generation of a protocol interrupt if a start condition is detected." "0: The start condition interrupt is disabled,1: The start condition interrupt is enabled" newline bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Control.In I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt is disabled,1: The time-out interrupt is enabled" line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register" bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost.This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode..Note: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.." bitfld.long 0x20 18. "BUSHANG,Bus Hang-up.This bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission" newline bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.." bitfld.long 0x20 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done.Note: This bit can't release when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.." newline bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status.This bit indicates that a slave read request has been detected..Note: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave read request has not been detected,1: A slave read request has been detected" bitfld.long 0x20 14. "SLASEL,Slave Select Status.This bit indicates that this device has been selected as slave..Note: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave" newline bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag.It is cleared by software writing one into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received" bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag.It is cleared by software writing one into this bit.Note: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: An I2C error has been detected" newline bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag.It is cleared by software writing one into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost" bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag.It is cleared by software writing one into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received" newline bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag.It is cleared by software writing one into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected" bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag.This bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave mode..It.." "0: A start condition has not yet been detected,1: A start condition has been detected" newline bitfld.long 0x20 6. "ONBUSY,On Bus Busy.Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy" bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag.Note: It is cleared by software writing one into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred" group.long 0x88++0x7 line.long 0x0 "UI2C_ADMAT,I2C Slave Match Address Register" bitfld.long 0x0 1. "ADMAT1,USCI Address 1 Match Status Register.When address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1" bitfld.long 0x0 0. "ADMAT0,USCI Address 0 Match Status Register.When address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1" line.long 0x4 "UI2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.byte 0x4 6.--11. 1. "HTCTL,Hold Time Configure Control Register.This field is used to generate the delay timing between SCL falling edge SDA edge in.transmission mode." hexmask.long.byte 0x4 0.--5. 1. "STCTL,Setup Time Configure Control Register.This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.." tree.end tree.end tree "USPI (SPI Mode)" tree "USPI0" base ad:0x40070000 group.long 0x0++0xB line.long 0x0 "USPI_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register" bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled" bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled" newline bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled" bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled" line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider.Note: I2C function the minimum value of CLKDIV is 8." bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled" bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?" newline bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x10++0x3 line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal..Note: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x20++0x3 line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x28++0x7 line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." line.long 0x4 "USPI_LINECTL,USCI Line Control Register" hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection.This bit defines the relation between the internal control signal and the output control signal..Note: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.." newline bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection.This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted" bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register" bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field." rgroup.long 0x34++0x3 line.long 0x0 "USPI_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer.Reserved." group.long 0x38++0x3 line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x0 17. "RXRST,Receive Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.." bitfld.long 0x0 16. "TXRST,Transmit Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.." bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer .Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.." bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled" rgroup.long 0x3C++0x3 line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status.This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.." bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" newline bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.." bitfld.long 0x0 3. "RXOVIF,Receive Buffer Overrun Interrupt Status.This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected" newline bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x54++0x13 line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register" bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x0 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" newline bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register" bitfld.long 0x4 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register" bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled" bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave).This bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under-run event..,1: The output data level is 1 if TX under-run event.." newline hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only).In Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.." bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection.This bit field describes how receive and transmit data is shifted in and out..Other values are reserved..Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval (Master Only).This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode.This bit field defines the SCLK idle status data transmit and data receive edge." "0,1,2,3" newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.." bitfld.long 0x8 2. "SS,Slave Select Control (Master Only).If AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state..Note: In SPI protocol the.." "0,1" newline bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only).The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode" line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit.If data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: The Slave mode bit count error interrupt Disabled,1: The Slave mode bit count error interrupt Enabled" bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit.In SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled" newline bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit.This bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled" bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit.This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled" line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only).In Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs" rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state" newline rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only).This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1" bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only).This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit.Note: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active" newline bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only).This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit.Note: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive" bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only).Note: It is cleared by software write 1 to this bit." "0: Slave bit count error event does not occur,1: Slave bit count error event occurs" newline bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only).Note: This bit is cleared by software writing 1 to it." "0: Slave time-out event did not occur,1: Slave time-out event occurred" bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Receive end event does not occur,1: Receive end event occurred" newline bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Receive start event did not occur,1: Receive start event occurred" bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Transmit end event did not occur,1: Transmit end event occurred" newline bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Transmit start event did not occur,1: Transmit start event occurred" tree.end tree "USPI1" base ad:0x40170000 group.long 0x0++0xB line.long 0x0 "USPI_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register" bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled" bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled" newline bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled" bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled" line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider.Note: I2C function the minimum value of CLKDIV is 8." bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled" bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?" newline bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x10++0x3 line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal..Note: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x20++0x3 line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x28++0x7 line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." line.long 0x4 "USPI_LINECTL,USCI Line Control Register" hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection.This bit defines the relation between the internal control signal and the output control signal..Note: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.." newline bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection.This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted" bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register" bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field." rgroup.long 0x34++0x3 line.long 0x0 "USPI_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer.Reserved." group.long 0x38++0x3 line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x0 17. "RXRST,Receive Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.." bitfld.long 0x0 16. "TXRST,Transmit Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.." bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer .Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.." bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled" rgroup.long 0x3C++0x3 line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status.This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.." bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" newline bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.." bitfld.long 0x0 3. "RXOVIF,Receive Buffer Overrun Interrupt Status.This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected" newline bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x54++0x13 line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register" bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x0 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" newline bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register" bitfld.long 0x4 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register" bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled" bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave).This bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under-run event..,1: The output data level is 1 if TX under-run event.." newline hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only).In Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.." bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection.This bit field describes how receive and transmit data is shifted in and out..Other values are reserved..Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval (Master Only).This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode.This bit field defines the SCLK idle status data transmit and data receive edge." "0,1,2,3" newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.." bitfld.long 0x8 2. "SS,Slave Select Control (Master Only).If AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state..Note: In SPI protocol the.." "0,1" newline bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only).The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode" line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit.If data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: The Slave mode bit count error interrupt Disabled,1: The Slave mode bit count error interrupt Enabled" bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit.In SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled" newline bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit.This bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled" bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit.This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled" line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only).In Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs" rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state" newline rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only).This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1" bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only).This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit.Note: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active" newline bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only).This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit.Note: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive" bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only).Note: It is cleared by software write 1 to this bit." "0: Slave bit count error event does not occur,1: Slave bit count error event occurs" newline bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only).Note: This bit is cleared by software writing 1 to it." "0: Slave time-out event did not occur,1: Slave time-out event occurred" bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Receive end event does not occur,1: Receive end event occurred" newline bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Receive start event did not occur,1: Receive start event occurred" bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Transmit end event did not occur,1: Transmit end event occurred" newline bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag.Note: This bit is cleared by software writing 1 to it." "0: Transmit start event did not occur,1: Transmit start event occurred" tree.end tree "USPI2" base ad:0x40074000 group.long 0x0++0xB line.long 0x0 "USPI_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register" bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled" bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled" newline bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled" bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled" line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider.Note: I2C function the minimum value of CLKDIV is 8." bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled" bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?" newline bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x10++0x3 line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal..Note: In SPI protocol we suggest this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol we.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x20++0x3 line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol we.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x28++0x7 line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit..Note: In SPI protocol we suggest this bit should be.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." line.long 0x4 "USPI_LINECTL,USCI Line Control Register" hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection.This bit defines the relation between the internal control signal and the output control signal..Note: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.." newline bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection.This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted" bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register" bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field." rgroup.long 0x34++0x3 line.long 0x0 "USPI_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer." group.long 0x38++0x3 line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x0 17. "RXRST,Receive Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.." bitfld.long 0x0 16. "TXRST,Transmit Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.." bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Control" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer .Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.." bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled" rgroup.long 0x3C++0x3 line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status.This bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.." bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" newline bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.." bitfld.long 0x0 3. "RXOVIF,Receive Buffer Overrun Interrupt Status.This bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected" newline bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x54++0x13 line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register" bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x0 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" newline bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register" bitfld.long 0x4 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register" bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled" bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave).This bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under-run event..,1: The output data level is 1 if TX under-run event.." newline hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only).In Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.." bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection.This bit field describes how receive and transmit data is shifted in and out..Other values are reserved..Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval (Master Only).This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.." bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode.This bit field defines the SCLK idle status data transmit and data receive edge." "0,1,2,3" newline bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.." bitfld.long 0x8 2. "SS,Slave Select Control (Master Only).If AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state..Note: In SPI protocol the.." "0,1" newline bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only).The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode" line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Control.If data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: The Slave mode bit count error interrupt Disabled,1: The Slave mode bit count error interrupt Enabled" bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Control.In SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled" newline bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Control.This bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled" bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Control.This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled" line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only).In Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs" rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state" newline rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only).This bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1" bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only).This bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit.Note: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active" newline bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only).This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit.Note: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive" bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only).Note: It is cleared by software writes 1 to this bit." "0: Slave bit count error event does not occur,1: Slave bit count error event occurs" newline bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only).Note: It is cleared by software writes 1 to this bit" "0: Slave time-out event does not occur,1: Slave time-out event occurs" bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag.Note: It is cleared by software writes 1 to this bit" "0: Receive end event does not occur,1: Receive end event occurs" newline bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag.Note: It is cleared by software writes 1 to this bit" "0: Receive start event does not occur,1: Receive start event occurs" bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag.Note: It is cleared by software writes 1 to this bit" "0: Transmit end event does not occur,1: Transmit end event occurs" newline bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag.Note: It is cleared by software writes 1 to this bit" "0: Transmit start event does not occur,1: Transmit start event occurs" tree.end tree.end tree "UUART (UART Mode)" tree "UUART0" base ad:0x40070000 group.long 0x0++0xB line.long 0x0 "UUART_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register" bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled" bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled" newline bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled" bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled" line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider.Note: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.." hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter.This bit field defines the divide ratio of the sample clock fSAMP_CLK..Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value." newline bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK" newline bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Timing measurement counter Disabled,1: Timing measurement counter Enabled" bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?" newline bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x10++0x3 line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode.This bit field selects which edge actives the trigger event of input data signal..Note: In UART function mode it is suggested to set this bit field as 10." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" newline bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x20++0x3 line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x28++0x7 line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." line.long 0x4 "UUART_LINECTL,USCI Line Control Register" hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection.This bit defines the relation between the internal control signal and the output control signal..Note: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.." newline bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection.This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.." bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission." rgroup.long 0x34++0x3 line.long 0x0 "UUART_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer..Note: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])." group.long 0x38++0x3 line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x0 17. "RXRST,Receive Reset.Note1: It is cleared automatically after one PCLK cycle..Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: Reset the receive-related counters state machine.." bitfld.long 0x0 16. "TXRST,Transmit Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.." bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer .Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.." rgroup.long 0x3C++0x3 line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty" newline bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status.This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.." bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" newline bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x54++0x13 line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register" bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register" bitfld.long 0x4 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register" bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled" bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit.Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled" newline bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit.Note: Refer to RS-485 Support section for detail information." "0: Stick parity Disabled,1: Stick parity Enabled" hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval .This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.." newline hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter.These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode." bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled" newline bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled" bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit.Note: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit.When nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART will reassert nRTS signal..Note1: This bit is used for nRTS auto direction control for RS485..Note2: This bit.." "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled" bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit.When nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit.Note: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit.Note: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit.This bit defines the parity bit is enabled in an UART frame." "0: The parity bit Disabled,1: The parity bit Enabled" bitfld.long 0x8 0. "STOPB,Stop Bits.This bit defines the number of stop bits in an UART frame." "0: The number of stop bits is 1,1: The number of stop bits is 2" line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit.Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled" bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only).This bit is used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only).This bit is used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high" newline bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status .This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun" rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) .This bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY" newline bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag .This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done" bitfld.long 0x10 7. "BREAK,Break Flag.This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits)..Note:.." "0: No Break is generated,1: Break is generated in the receiver bus" newline bitfld.long 0x10 6. "FRMERR,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)..Note: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated" bitfld.long 0x10 5. "PARITYERR,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'..Note: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated" newline bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag.Note: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred" bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag.Note: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred" newline bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag.Note: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred" bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag.Note1: It is cleared by software writing 1 into this bit..Note2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: A transmit start interrupt status has occurred" tree.end tree "UUART1" base ad:0x40170000 group.long 0x0++0xB line.long 0x0 "UUART_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register" bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled" bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled" newline bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled" bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled" line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider.Note: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.." hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter.This bit field defines the divide ratio of the sample clock fSAMP_CLK..Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value." newline bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK" newline bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Timing measurement counter Disabled,1: Timing measurement counter Enabled" bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?" newline bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x10++0x3 line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode.This bit field selects which edge actives the trigger event of input data signal..Note: In UART function mode it is suggested to set this bit field as 10." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" newline bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x20++0x3 line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x28++0x7 line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." line.long 0x4 "UUART_LINECTL,USCI Line Control Register" hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection.This bit defines the relation between the internal control signal and the output control signal..Note: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.." newline bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection.This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.." bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission." rgroup.long 0x34++0x3 line.long 0x0 "UUART_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer..Note: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])." group.long 0x38++0x3 line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x0 17. "RXRST,Receive Reset.Note1: It is cleared automatically after one PCLK cycle..Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: Reset the receive-related counters state machine.." bitfld.long 0x0 16. "TXRST,Transmit Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.." bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer .Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.." rgroup.long 0x3C++0x3 line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty" newline bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status.This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.." bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" newline bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x54++0x13 line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register" bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register" bitfld.long 0x4 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register" bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled" bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit.Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled" newline bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit.Note: Refer to RS-485 Support section for detail information." "0: Stick parity Disabled,1: Stick parity Enabled" hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval .This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.." newline hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter.These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode." bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled" newline bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled" bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit.Note: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit.When nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART will reassert nRTS signal..Note1: This bit is used for nRTS auto direction control for RS485..Note2: This bit.." "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled" bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit.When nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit.Note: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit.Note: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit.This bit defines the parity bit is enabled in an UART frame." "0: The parity bit Disabled,1: The parity bit Enabled" bitfld.long 0x8 0. "STOPB,Stop Bits.This bit defines the number of stop bits in an UART frame." "0: The number of stop bits is 1,1: The number of stop bits is 2" line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit.Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled" bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only).This bit is used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only).This bit is used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high" newline bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status .This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun" rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) .This bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY" newline bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag .This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done" bitfld.long 0x10 7. "BREAK,Break Flag.This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits)..Note:.." "0: No Break is generated,1: Break is generated in the receiver bus" newline bitfld.long 0x10 6. "FRMERR,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)..Note: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated" bitfld.long 0x10 5. "PARITYERR,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'..Note: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated" newline bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag.Note: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred" bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag.Note: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred" newline bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag.Note: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred" bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag.Note1: It is cleared by software writing 1 into this bit..Note2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: A transmit start interrupt status has occurred" tree.end tree "UUART2" base ad:0x40074000 group.long 0x0++0xB line.long 0x0 "UUART_CTL,USCI Control Register" bitfld.long 0x0 0.--2. "FUNMODE,Function Mode.This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?" line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register" bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled" bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled" newline bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled" bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit.This bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled" line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider.Note: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.." hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter.This bit field defines the divide ratio of the sample clock fSAMP_CLK..Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value." newline bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK" newline bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit.This bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled" bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection.This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?" newline bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection.This bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection.This bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved." group.long 0x10++0x3 line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode.This bit field selects which edge actives the trigger event of input data signal..Note: In UART function mode it is suggested to set this bit field as 10." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" newline bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x20++0x3 line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection.This bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." group.long 0x28++0x7 line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection.This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.." line.long 0x4 "UUART_LINECTL,USCI Line Control Register" hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission.This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits..0x0: The data word.." bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection.This bit defines the relation between the internal control signal and the output control signal..Note: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.." newline bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection.This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.." bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x3 line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data.Software can use this bit field to write 16-bit transmit data for transmission." rgroup.long 0x34++0x3 line.long 0x0 "UUART_RXDAT,USCI Receive Data Register" hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data.This bit field monitors the received data which stored in receive data buffer..Note: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])." group.long 0x38++0x3 line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x0 17. "RXRST,Receive Reset.Note 1: It is cleared automatically after one PCLK cycle..Note 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle" bitfld.long 0x0 16. "TXRST,Transmit Reset.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer.Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.." bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Control" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer .Note: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.." rgroup.long 0x3C++0x3 line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty" newline bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status.This bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.." bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" group.long 0x54++0x13 line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register" bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register" bitfld.long 0x4 0. "WKF,Wake-up Flag.When chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1" line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register" bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled" bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit.Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled" newline bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit.Note: Refer to RS-485 Support section for detail information." "0: Stick parity Disabled,1: Stick parity Enabled" hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval .This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.." newline hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter.These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode." bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled" newline bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled" bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit.Note: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit.When nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART will reassert nRTS signal..Note 1: This bit is used for nRTS auto direction control for RS485..Note 2: This bit.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.." bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit.When nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit.Note: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit.Note: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit.This bit defines the parity bit is enabled in an UART frame." "0: The parity bit Disabled,1: The parity bit Enabled" bitfld.long 0x8 0. "STOPB,Stop Bits.This bit defines the number of stop bits in an UART frame." "0: The number of stop bits is 1,1: The number of stop bits is 2" line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit.Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled" bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only).This bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only).This bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high" newline bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status .This bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF" rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) .This bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY" newline bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag .This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done" bitfld.long 0x10 7. "BREAK,Break Flag.This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits)..Note:.." "0: No Break is generated,1: Break is generated in the receiver bus" newline bitfld.long 0x10 6. "FRMERR,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)..Note: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated" bitfld.long 0x10 5. "PARITYERR,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'..Note: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated" newline bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag.Note: It is cleared by software writing one into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred" bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag.Note: It is cleared by software writing one into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred" newline bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag.Note: It is cleared by software writing one into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred" bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag.Note 1: It is cleared by software writing one into this bit..Note 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.." tree.end tree.end tree.end endif tree "WDT (Watchdog Timer)" base ad:0x40004000 sif (cpuis("NUC029?AE")||cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) group.long 0x0++0x3 line.long 0x0 "WTCR,Watchdog Timer Control Register" bitfld.long 0x0 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable Control (Write Protect).WDT up counter will keep going no matter CPU is hanging by ICE or not." "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled" sif (cpuis("NUC029?AE")) bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Interval Selection.These three bits select the time-out interval for the Watchdog Timer." "0: 24 * TWDT,1: 26 * TWDT,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?AN")) bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Interval Select (write protection bits)" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Time-Out Interval Selection (Write Protect).These three bits select the time-out interval period for the WDT.." "0: 24 *TWDT,1: 26 * TWDT,?,?,?,?,?,?" newline endif sif (cpuis("NUC029?EE")) bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Time-Out Interval Selection (Write Protect).These three bits select the time-out interval period for the WDT." "0: 24 *TWDT,1: 26 * TWDT,?,?,?,?,?,?" newline endif bitfld.long 0x0 7. "WTE,Watchdog Timer Enable Control (Write Protect)" "0: WDT Disabled. (This action will reset the..,1: WDT Enabled" newline bitfld.long 0x0 6. "WTIE,Watchdog Timer Time-out Interrupt Enable Control (Write Protect).If this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled" bitfld.long 0x0 5. "WTWKF,Watchdog Timer Time-out Wake-up Flag.This bit indicates the interrupt wake-up flag status of WDT..Note: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.." newline bitfld.long 0x0 4. "WTWKE,Watchdog Timer Time-out Wake-up Function Control (Write Protect).If this bit is set to 1 while WTIF is generated to 1 and WTIE enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip..Note: Chip can be woken-up.." "0: Wake-up trigger event Disabled if WDT time-out..,1: Wake-up trigger event Enabled if WDT time-out.." bitfld.long 0x0 3. "WTIF,Watchdog Timer Time-out Interrupt Flag.This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval..Note: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred" newline bitfld.long 0x0 2. "WTRF,Watchdog Timer Time-out Reset Flag.This bit indicates the system has been reset by WDT time-out reset or not..Note: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred" bitfld.long 0x0 1. "WTRE,Watchdog Timer Time-out Reset Enable Control (Write Protect).Setting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled" newline bitfld.long 0x0 0. "WTR,Reset Watchdog Timer Up Counter (Write Protect).Note: This bit will be automatically cleared by hardware." "0: No effect,1: Reset the internal 18-bit WDT up counter value" endif sif (cpuis("NUC029?AN")) group.long 0x4++0x3 line.long 0x0 "WTCRALT,Watchdog Timer Alternative Control Register" bitfld.long 0x0 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Select (Write-protection Bits).When WDT time-out happened software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset.." "0: Watchdog Timer reset delay period is (1024+2) *..,1: Watchdog Timer reset delay period is (128+2) *..,?,?" endif sif (cpuis("NUC029?DE")) group.long 0x4++0x3 line.long 0x0 "WTCRALT,Watchdog Timer Alternative Control Register" bitfld.long 0x0 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Selection (Write Protect).When WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. User can select a suitable value of WDT Reset Delay Period.." "0: Watchdog Timer Reset Delay Period is 1026 *..,1: Watchdog Timer Reset Delay Period is 130 * WDT_CLK,?,?" endif sif (cpuis("NUC029?EE")) group.long 0x4++0x3 line.long 0x0 "WTCRALT,Watchdog Timer Alternative Control Register" bitfld.long 0x0 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Selection (Write Protect).When WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. User can select a suitable value of WDT Reset Delay Period.." "0: Watchdog Timer Reset Delay Period is 1026 *..,1: Watchdog Timer Reset Delay Period is 130 * WDT_CLK,?,?" endif sif (cpuis("NUC029?GE")) group.long 0x0++0x7 line.long 0x0 "WDT_CTL,WDT Control Register" bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect).WDT up counter will keep going no matter CPU is held by ICE or not..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled" rbitfld.long 0x0 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only).If user execute enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not..Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.." newline bitfld.long 0x0 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect).These three bits select the time-out interval period after WDT starts counting..Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?,?,?,?,?,?" bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect).Note1: This bit is write protected. Refer to the SYS_REGLCTL register..Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active user can read SYNC (WDT_CTL[30]) to check enabe/disable.." "0: Set WDT counter stop and internal up counter..,1: Set WDT counter start" newline bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect).If this bit is enabled when WDT time-out event occurs the IF (WDT_CTL[3]) will be set to 1 and WDT time-out interrupt signal is generated and inform to CPU. .Note: This bit is write protected." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled" bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag (Write Protect).This bit indicates the WDT time-out event has triggered chip wake-up or not..Note: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode when.." newline bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect).If this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will generate a.." "0: Trigger wake-up event function Disabled if WDT..,1: Trigger wake-up event function Enabled if WDT.." bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag.This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.Note: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt event did not occur,1: WDT time-out interrupt event occurred" newline bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag.This bit indicates the system has been reset by WDT time-out reset system event or not..Note: This bit is cleared by writing 1 to it." "0: WDT time-out reset system event did not occur,1: WDT time-out reset system event has been occurred" bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect).Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires..Note: This bit is write.." "0: WDT time-out reset system function Disabled,1: WDT time-out reset system function Enabled" line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register" bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Period Selection (Write Protect).When WDT time-out event happened user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred. User can select a suitable setting of.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,?,?" wgroup.long 0x8++0x3 line.long 0x0 "WDT_RSTCNT,WDT Reset Counter Register" hexmask.long 0x0 0.--31. 1. "RSTCNT,WDT Reset Counter Register.Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0..Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.Reserved." endif tree.end sif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")||cpuis("NUC029?GE")) tree "WWDT (Window Watchdog Timer)" base ad:0x40004100 sif (cpuis("NUC029?AN")||cpuis("NUC029?DE")||cpuis("NUC029?EE")) wgroup.long 0x0++0x3 line.long 0x0 "WWDTRLD,Window Watchdog Timer Reload Counter Register" hexmask.long 0x0 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register.Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. .Note: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and.." group.long 0x4++0x7 line.long 0x0 "WWDTCR,Window Watchdog Timer Control Register" bitfld.long 0x0 31. "DBGACK_WWDT,ICE debug mode acknowledge Disable" "0: WWDT counter stopped if system is in Debug mode,1: WWDT still counted even system is in Debug mode" hexmask.long.byte 0x0 16.--21. 1. "WINCMP,WWDT Window Compare Register.Set this register to adjust the valid reload window. .Note: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If Software writes WWDTRLD when current.." newline sif (cpuis("NUC029?AN")) hexmask.long.byte 0x0 8.--11. 1. "PERIODSEL,WWDT Pre-scale Period Select" endif sif (cpuis("NUC029?DE")) hexmask.long.byte 0x0 8.--11. 1. "PERIODSEL,WWDT Counter Prescale Period Selection." newline endif sif (cpuis("NUC029?EE")) hexmask.long.byte 0x0 8.--11. 1. "PERIODSEL,WWDT Counter Prescale Period Selection" endif bitfld.long 0x0 1. "WWDTIE,WWDT Interrupt Enable.Setting this bit to enable the Window Watchdog Timer time-out interrupt function." "0: WWDT time-out interrupt function Disabled if..,1: WWDT time-out interrupt function Enabled if.." newline bitfld.long 0x0 0. "WWDTEN,WWDT Enable.Set this bit to enable Window Watchdog Timer counter counting." "0: Window Watchdog Timer counter is stopped,1: Window Watchdog Timer counter is starting counting" line.long 0x4 "WWDTSR,Window Watchdog Timer Status Register" sif (cpuis("NUC029?AN")) bitfld.long 0x4 1. "WWDTRF,WWDT Reset Flag.When WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value larger than WINCMP chip will be reset and this bit is set to 1. This bit will be cleared to 0 by writing 1 to itself." "0,1" bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag.When current WWDT counter value matches to WWCMP this bit is set to 1. This bit will be cleared by writing 1 to itself." "0,1" newline endif sif (cpuis("NUC029?DE")) bitfld.long 0x4 1. "WWDTRF,WWDT Time-Out Reset Flag.This bit indicates the system has been reset by WWDT time-out reset or not..Note: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred" endif sif (cpuis("NUC029?EE")) bitfld.long 0x4 1. "WWDTRF,WWDT Time-Out Reset Flag.This bit indicates the system has been reset by WWDT time-out reset or not..Note: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred" newline bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag.This bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value..Note: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches WINCMP value" endif rgroup.long 0xC++0x3 line.long 0x0 "WWDTCVR,Window Watchdog Timer Counter Value Register" hexmask.long.byte 0x0 0.--5. 1. "WWDTCVAL,WWDT Counter Value.This register reflects the current WWDT counter value and this register is read only" endif sif (cpuis("NUC029?GE")) wgroup.long 0x0++0x3 line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register" hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register.Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F..Note1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT.." group.long 0x4++0x7 line.long 0x0 "WWDT_CTL,WWDT Control Register" bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit.The WWDT down counter will keep counting no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled" hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare Value.Set this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated..Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is.." newline hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection" bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit.If this bit is enabled when WWDTIF (WWDT_STATUS[0]) is set to 1 the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt disabled,1: WWDT counter compare match interrupt enabled" newline bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit.Set this bit to start WWDT counter counting." "0: WWDT counter is stopped,1: WWDT counter is starting counting" line.long 0x4 "WWDT_STATUS,WWDT Status Register" bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset System Flag.If this bit is set to 1 it indicates that system has been reset by WWDT counter time-out reset system event..Note: This bit is cleared by writing 1 to it." "0: WWDT time-out reset system event did not occur,1: WWDT time-out reset system event occurred" bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag.This bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])..Note: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT CNTDAT matches the CMPDAT" rgroup.long 0xC++0x3 line.long 0x0 "WWDT_CNT,WWDT Counter Value Register" hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value.CNTDAT will be updated continuously." endif tree.end endif AUTOINDENT.OFF