; --------------------------------------------------------------------------------
; @Title: netX90MPW-APP On-Chip Peripherals
; @Props: Released
; @Author: KOL, PEG, KRZ
; @Changelog: 2018-06-18 KOL
;             2019-12-20 PEG
;             2022-10-26 KRZ
; @Manufacturer: HILSCHER - Hilscher GmbH
; @Doc: SVD generated (SVD2PER 1.8.6), based on:
;       regdef_netx90_MPW_arm_app.svd (Ver. 1.0)
; @Core: Cortex-M4F
; @Chip: NETX90MPW
; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pernetx90mpwapp.per 15392 2022-11-07 14:56:11Z pegold $

tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ABORT"
base ad:0xFF401600
group.long 0x00++0x03
line.long 0x00 "abort_base,Start-address of abort generating address area"
group.long 0x0C++0x03
line.long 0x00 "abort_end,End-address of abort generating address area"
tree.end
tree "ADC_SEQ"
base ad:0xFF4016C0
group.long 0x00++0x03
line.long 0x00 "adc_seq_start,ADC start register: The bits start_adc0 and start_adc1 are write enables for the preceeding bits respectively"
bitfld.long 0x00 20.--25. "tt_add_adc1,Tracking Time Addon of ADC1: Time that 3rd ADC_CLK edge is delayed (in steps of cfg_clock-period)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 19. "ref_adc1,Reference Select of ADC1" "0: use internal reference,1: use VREF_ADC as reference"
newline
bitfld.long 0x00 17.--18. "sel_adc1,Multiplexer Input Select of ADC1" "0: Vin2,1: Vin3,2: Vref/2,3: Vref"
bitfld.long 0x00 16. "start_adc1,Start ADC1: Setting this bit to 1 starts ADC control state machine for ADC1" "0,1"
newline
bitfld.long 0x00 4.--9. "tt_add_adc0,Tracking Time Addon of ADC0: Time that 3rd ADC_CLK edge is delayed (in steps of cfg_clock-period)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 3. "ref_adc0,Reference Select of ADC0" "0: use internal reference,1: use VREF_ADC as reference"
newline
bitfld.long 0x00 1.--2. "sel_adc0,Multiplexer Input Select of ADC0" "0: Vin0,1: Vin1,2: ,3: Vref"
bitfld.long 0x00 0. "start_adc0,Start ADC0: Setting this bit to 1 starts ADC control state machine for ADC0" "0,1"
group.long 0x04++0x03
line.long 0x00 "adc_seq_cfg,ADC general config register: This register is for static config values of ADC"
bitfld.long 0x00 4. "sync_sample_start_if_restart_both,Synchronous start of sampling at restart of both ADCs: This option should be activated for debug purposes only! Due to cfg_clock-adc1_shift the sampling times of ADC0 and ADC1 might be a bit longer than defined in.." "0,1"
bitfld.long 0x00 3. "debug,Debug mode: Activate Debug Mode which directly controls ADC via debug register" "0: Debug is inactive,1: Debug Mode is active"
newline
bitfld.long 0x00 2. "buffer_enable,Enable of Vref at ADCs" "0,1"
bitfld.long 0x00 1. "reset_n,Low active reset of ADC and state machine: There are no constraints on reset length" "0: Soft-Reset is active,1: Soft-Reset is inactive"
newline
bitfld.long 0x00 0. "enable,Power-down mode of ADC" "0: Disable ADC (Power-down),1: Enable ADC (Power up)"
group.long 0x08++0x03
line.long 0x00 "adc_seq_cfg_clock,ADC config register for ADC clock (same for both ADCs)"
bitfld.long 0x00 3.--5. "adc1_shift,ADC1 Shift: To avoid cross-talk the posedge of ADC1 will be shifted" "0: 0ns,1: 10ns,2: 20ns,3: 30ns,4: 40ns,5: 50ns,6: 60ns,7: 70ns"
bitfld.long 0x00 0.--2. "period,Clock Period" "0: 20ns,1: 30ns,2: 40ns,3: 50ns,4: 60ns,5: 70ns,6: 80ns,7: 90ns"
rgroup.long 0x0C++0x03
line.long 0x00 "adc_seq_status,ADC status register"
bitfld.long 0x00 6. "adc_clock_running,at least one ADC_CLK is running" "0,1"
bitfld.long 0x00 5. "adc1_data,ADC1 data is ready to be read" "0,1"
newline
bitfld.long 0x00 4. "adc0_data,ADC0 data is ready to be read" "0,1"
bitfld.long 0x00 3. "adc1_running,ADC1 is running" "0,1"
newline
bitfld.long 0x00 2. "adc0_running,ADC0 is running" "0,1"
bitfld.long 0x00 1. "adc1_sample,ADC1 is sampling data" "0,1"
newline
bitfld.long 0x00 0. "adc0_sample,ADC0 is sampling data" "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "adc_seq_adc_data0,ADC0 value"
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
rgroup.long 0x14++0x03
line.long 0x00 "adc_seq_adc_data1,ADC1 value"
hexmask.long.word 0x00 0.--11. 1. "val,Sampled value"
group.long 0x18++0x03
line.long 0x00 "adc_seq_debug,Debug Mode register: If cgf-debug is enabled this register directly controls inputs of both ADCs"
bitfld.long 0x00 14. "adc1_set_mux3,ADC1_SET_MUX3 signal" "0,1"
bitfld.long 0x00 13. "adc1_set_mux2,ADC1_SET_MUX2 signal" "0,1"
newline
bitfld.long 0x00 12. "adc1_set_mux1,ADC1_SET_MUX1 signal" "0,1"
bitfld.long 0x00 11. "adc1_set_mux0,ADC1_SET_MUX0 signal" "0,1"
newline
bitfld.long 0x00 10. "adc1_use_ref_vdd3,ADC1_USE_REF_VDD3 signal" "0,1"
bitfld.long 0x00 9. "adc1_soc,ADC1_SOC signal" "0,1"
newline
bitfld.long 0x00 8. "adc1_clk,ADC1 is sampling data" "0,1"
bitfld.long 0x00 6. "adc0_set_mux3,ADC0_SET_MUX3 signal" "0,1"
newline
bitfld.long 0x00 5. "adc0_set_mux2,ADC0_SET_MUX2 signal" "0,1"
bitfld.long 0x00 4. "adc0_set_mux1,ADC0_SET_MUX1 signal" "0,1"
newline
bitfld.long 0x00 3. "adc0_set_mux0,ADC0_SET_MUX0 signal" "0,1"
bitfld.long 0x00 2. "adc0_use_ref_vdd3,ADC0_USE_REF_VDD3 signal" "0,1"
newline
bitfld.long 0x00 1. "adc0_soc,ADC0_SOC signal" "0,1"
bitfld.long 0x00 0. "adc0_clk,ADC0 is sampling data" "0,1"
group.long 0x1C++0x03
line.long 0x00 "adc_seq_irq_raw,Raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 3. "adc1_data_finish,Data of ADC1 is ready to be read" "0,1"
bitfld.long 0x00 2. "adc0_data_finish,Data of ADC0 is ready to be read" "0,1"
newline
bitfld.long 0x00 1. "adc1_sample_finish,Sampling phase of ADC1 is finished ADC1 can be restarted" "0,1"
bitfld.long 0x00 0. "adc0_sample_finish,Sampling phase of ADC0 is finished ADC0 can be restarted" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "adc_seq_irq_masked,Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC)"
bitfld.long 0x00 3. "adc1_data_finish,Data of ADC1 is ready to be read" "0,1"
bitfld.long 0x00 2. "adc0_data_finish,Data of ADC0 is ready to be read" "0,1"
newline
bitfld.long 0x00 1. "adc1_sample_finish,Sampling phase of ADC1 is finished ADC1 can be restarted" "0,1"
bitfld.long 0x00 0. "adc0_sample_finish,Sampling phase of ADC0 is finished ADC0 can be restarted" "0,1"
group.long 0x24++0x03
line.long 0x00 "adc_seq_irq_mask_set,IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 3. "adc1_data_finish,Data of ADC1 is ready to be read" "0,1"
bitfld.long 0x00 2. "adc0_data_finish,Data of ADC0 is ready to be read" "0,1"
newline
bitfld.long 0x00 1. "adc1_sample_finish,Sampling phase of ADC1 is finished ADC1 can be restarted" "0,1"
bitfld.long 0x00 0. "adc0_sample_finish,Sampling phase of ADC0 is finished ADC0 can be restarted" "0,1"
group.long 0x28++0x03
line.long 0x00 "adc_seq_irq_mask_reset,IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source)"
bitfld.long 0x00 3. "adc1_data_finish,Data of ADC1 is ready to be read" "0,1"
bitfld.long 0x00 2. "adc0_data_finish,Data of ADC0 is ready to be read" "0,1"
newline
bitfld.long 0x00 1. "adc1_sample_finish,Sampling phase of ADC1 is finished ADC1 can be restarted" "0,1"
bitfld.long 0x00 0. "adc0_sample_finish,Sampling phase of ADC0 is finished ADC0 can be restarted" "0,1"
tree.end
tree "AES"
base ad:0xFF080080
group.long 0x00++0x03
line.long 0x00 "aes_cfg,AES config register"
bitfld.long 0x00 20. "out_fifo_dma_burst_only,Generate DMAC burst signal only (output FIFO)" "0,1"
bitfld.long 0x00 19. "out_fifo_dma_en,Enable DMAC control signals for the output FIFO" "0,1"
bitfld.long 0x00 18. "in_fifo_dma_burst_only,Generate DMAC burst signal only (input FIFO)" "0,1"
bitfld.long 0x00 17. "in_fifo_dma_en,Enable DMAC control signals for the input FIFO" "0,1"
newline
bitfld.long 0x00 11.--16. "out_fifo_wm,Output FIFO watermark level (0..63) used for out_fifo_wm interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5.--10. "in_fifo_wm,Input FIFO watermark level (0..63) used for in_fifo_wm interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4. "key_exp_start,Start AES key expansion After writing '1' this bit will automatically be reset" "0,1"
bitfld.long 0x00 2.--3. "key_len,AES key length" "0: 128 bit,1: 192 bit,2: 256 bit,3: reserved"
newline
bitfld.long 0x00 1. "mode,AES core operation mode" "0: Encrypt,1: Decrypt"
bitfld.long 0x00 0. "enable,Enables the AES core operation" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "aes_stat,AES status register"
bitfld.long 0x00 27. "out_fifo_overflow,Output FIFO was overflown set aes_cfg-enable=0 to reset this bit Note: overflow is only a theoretical FIFO status because the hardware logic of the AES core won't put data into the FIFO when it's full" "0,1"
bitfld.long 0x00 26. "out_fifo_underrun,Output FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 25. "out_fifo_not_full,Output FIFO is not full" "0,1"
bitfld.long 0x00 24. "out_fifo_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 23. "out_fifo_not_empty,Output FIFO is not empty" "0,1"
bitfld.long 0x00 22. "out_fifo_empty,Output FIFO is empty" "0,1"
hexmask.long.byte 0x00 15.--21. 1. "out_fifo_fill,Fill level of output FIFO in bytes (0..64)"
bitfld.long 0x00 14. "in_fifo_overflow,Input FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
newline
bitfld.long 0x00 13. "in_fifo_underrun,Input FIFO was underrun set aes_cfg-enable=0 to reset this bit Note: underrun is only a theoretical FIFO status because the hardware logic of the AES core won't fetch data from the FIFO when it's empty" "0,1"
bitfld.long 0x00 12. "in_fifo_not_full,Input FIFO is not full" "0,1"
bitfld.long 0x00 11. "in_fifo_full,Input FIFO is full" "0,1"
bitfld.long 0x00 10. "in_fifo_not_empty,Input FIFO is not empty" "0,1"
newline
bitfld.long 0x00 9. "in_fifo_empty,Input FIFO is empty" "0,1"
hexmask.long.byte 0x00 2.--8. 1. "in_fifo_fill,Fill level of input FIFO in bytes (0..64)"
bitfld.long 0x00 1. "op_ready,Set when AES operation ready i.e" "0,1"
bitfld.long 0x00 0. "key_exp_ready,Set when key expansion procedure is done" "0,1"
group.long 0x08++0x03
line.long 0x00 "aes_irq_raw,AES raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 15. "out_fifo_overflow,Output FIFO was overflown set aes_cfg-enable=0 to reset this bit Note: overflow is only a theoretical FIFO status because the hardware logic of the AES core won't put data into the FIFO when it's full" "0,1"
bitfld.long 0x00 14. "out_fifo_underrun,Output FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 13. "out_fifo_not_full,Output FIFO is not full" "0,1"
bitfld.long 0x00 12. "out_fifo_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 11. "out_fifo_not_empty,Output FIFO is not empty" "0,1"
bitfld.long 0x00 10. "out_fifo_empty,Output FIFO is empty" "0,1"
bitfld.long 0x00 9. "out_fifo_wm,Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')" "0,1"
bitfld.long 0x00 8. "in_fifo_overflow,Input FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
newline
bitfld.long 0x00 7. "in_fifo_underrun,Input FIFO was underrun set aes_cfg-enable=0 to reset this bit Note: underrun is only a theoretical FIFO status because the hardware logic of the AES core won't fetch data from the FIFO when it's empty" "0,1"
bitfld.long 0x00 6. "in_fifo_not_full,Input FIFO is not full" "0,1"
bitfld.long 0x00 5. "in_fifo_full,Input FIFO is full" "0,1"
bitfld.long 0x00 4. "in_fifo_not_empty,Input FIFO is not empty" "0,1"
newline
bitfld.long 0x00 3. "in_fifo_empty,Input FIFO is empty" "0,1"
bitfld.long 0x00 2. "in_fifo_wm,Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')" "0,1"
bitfld.long 0x00 1. "op_ready,Set when AES operation ready i.e" "0,1"
bitfld.long 0x00 0. "key_exp_ready,Set when key expansion procedure is done" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "aes_irq_masked,AES masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 15. "out_fifo_overflow,Output FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 14. "out_fifo_underrun,Output FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 13. "out_fifo_not_full,Output FIFO is not full" "0,1"
bitfld.long 0x00 12. "out_fifo_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 11. "out_fifo_not_empty,Output FIFO is not empty" "0,1"
bitfld.long 0x00 10. "out_fifo_empty,Output FIFO is empty" "0,1"
bitfld.long 0x00 9. "out_fifo_wm,Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')" "0,1"
bitfld.long 0x00 8. "in_fifo_overflow,Input FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
newline
bitfld.long 0x00 7. "in_fifo_underrun,Input FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 6. "in_fifo_not_full,Input FIFO is not full" "0,1"
bitfld.long 0x00 5. "in_fifo_full,Input FIFO is full" "0,1"
bitfld.long 0x00 4. "in_fifo_not_empty,Input FIFO is not empty" "0,1"
newline
bitfld.long 0x00 3. "in_fifo_empty,Input FIFO is empty" "0,1"
bitfld.long 0x00 2. "in_fifo_wm,Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')" "0,1"
bitfld.long 0x00 1. "op_ready,Set when AES operation ready i.e" "0,1"
bitfld.long 0x00 0. "key_exp_ready,Set when key expansion procedure is done" "0,1"
group.long 0x10++0x03
line.long 0x00 "aes_irq_msk_set,AES IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 15. "out_fifo_overflow,Output FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 14. "out_fifo_underrun,Output FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 13. "out_fifo_not_full,Output FIFO is not full" "0,1"
bitfld.long 0x00 12. "out_fifo_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 11. "out_fifo_not_empty,Output FIFO is not empty" "0,1"
bitfld.long 0x00 10. "out_fifo_empty,Output FIFO is empty" "0,1"
bitfld.long 0x00 9. "out_fifo_wm,Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')" "0,1"
bitfld.long 0x00 8. "in_fifo_overflow,Input FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
newline
bitfld.long 0x00 7. "in_fifo_underrun,Input FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 6. "in_fifo_not_full,Input FIFO is not full" "0,1"
bitfld.long 0x00 5. "in_fifo_full,Input FIFO is full" "0,1"
bitfld.long 0x00 4. "in_fifo_not_empty,Input FIFO is not empty" "0,1"
newline
bitfld.long 0x00 3. "in_fifo_empty,Input FIFO is empty" "0,1"
bitfld.long 0x00 2. "in_fifo_wm,Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')" "0,1"
bitfld.long 0x00 1. "op_ready,Set when AES operation ready i.e" "0,1"
bitfld.long 0x00 0. "key_exp_ready,Set when key expansion procedure is done" "0,1"
group.long 0x14++0x03
line.long 0x00 "aes_irq_msk_reset,AES IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 15. "out_fifo_overflow,Output FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 14. "out_fifo_underrun,Output FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 13. "out_fifo_not_full,Output FIFO is not full" "0,1"
bitfld.long 0x00 12. "out_fifo_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 11. "out_fifo_not_empty,Output FIFO is not empty" "0,1"
bitfld.long 0x00 10. "out_fifo_empty,Output FIFO is empty" "0,1"
bitfld.long 0x00 9. "out_fifo_wm,Fill level of output FIFO is above watermark (see crypt_aes_cfg bits 'out_fifo_wm')" "0,1"
bitfld.long 0x00 8. "in_fifo_overflow,Input FIFO was overflown set aes_cfg-enable=0 to reset this bit" "0,1"
newline
bitfld.long 0x00 7. "in_fifo_underrun,Input FIFO was underrun set aes_cfg-enable=0 to reset this bit" "0,1"
bitfld.long 0x00 6. "in_fifo_not_full,Input FIFO is not full" "0,1"
bitfld.long 0x00 5. "in_fifo_full,Input FIFO is full" "0,1"
bitfld.long 0x00 4. "in_fifo_not_empty,Input FIFO is not empty" "0,1"
newline
bitfld.long 0x00 3. "in_fifo_empty,Input FIFO is empty" "0,1"
bitfld.long 0x00 2. "in_fifo_wm,Fill level of input FIFO is below or equal watermark (see crypt_aes_cfg bits 'in_fifo_wm')" "0,1"
bitfld.long 0x00 1. "op_ready,Set when AES operation ready i.e" "0,1"
bitfld.long 0x00 0. "key_exp_ready,Set when key expansion procedure is done" "0,1"
group.long 0x18++0x03
line.long 0x00 "aes_key0,AES key register 0"
hexmask.long 0x00 0.--31. 1. "val,key bits 31..0"
group.long 0x1C++0x03
line.long 0x00 "aes_key1,AES key register 1"
hexmask.long 0x00 0.--31. 1. "val,key bits 63..32"
group.long 0x20++0x03
line.long 0x00 "aes_key2,AES key register 2"
hexmask.long 0x00 0.--31. 1. "val,key bits 95..64"
group.long 0x24++0x03
line.long 0x00 "aes_key3,AES key register 3"
hexmask.long 0x00 0.--31. 1. "val,key bits 127..96"
group.long 0x28++0x03
line.long 0x00 "aes_key4,AES key register 4"
hexmask.long 0x00 0.--31. 1. "val,key bits 159..128"
group.long 0x2C++0x03
line.long 0x00 "aes_key5,AES key register 5"
hexmask.long 0x00 0.--31. 1. "val,key bits 191..160"
group.long 0x30++0x03
line.long 0x00 "aes_key6,AES key register 6"
hexmask.long 0x00 0.--31. 1. "val,key bits 223..192"
group.long 0x34++0x03
line.long 0x00 "aes_key7,AES key register 7"
hexmask.long 0x00 0.--31. 1. "val,key bits 255..224"
wgroup.long 0x38++0x03
line.long 0x00 "aes_din,AES FIFO input Unlike all other registers this address can be written with DWord(32 Bit) Word(16 Bit) or Byte acccss"
hexmask.long 0x00 0.--31. 1. "val,data bits"
rgroup.long 0x3C++0x03
line.long 0x00 "aes_dout,AES FIFO output"
hexmask.long 0x00 0.--31. 1. "val,data bits"
tree.end
tree "ASIC_CTRL"
base ad:0xFF401200
rgroup.long 0x00++0x03
line.long 0x00 "io_config0,IO Config0 Register: reserved for COM side"
hexmask.long 0x00 0.--31. 1. "val,reserved"
rgroup.long 0x04++0x03
line.long 0x00 "io_config0_mask,IO Config0 Mask Register: reserved for COM side"
hexmask.long 0x00 0.--31. 1. "val,reserved"
rgroup.long 0x08++0x03
line.long 0x00 "io_config1,IO Config1 Register: reserved for COM side"
hexmask.long 0x00 0.--31. 1. "val,reserved"
rgroup.long 0x0C++0x03
line.long 0x00 "io_config1_mask,IO Config1 Mask Register: reserved for COM side"
hexmask.long 0x00 0.--31. 1. "val,reserved"
rgroup.long 0x10++0x03
line.long 0x00 "io_config2,IO Config2 Register: reserved for COM side"
hexmask.long 0x00 0.--31. 1. "val,reserved"
rgroup.long 0x14++0x03
line.long 0x00 "io_config2_mask,IO Config2 Mask Register: reserved for COM side"
hexmask.long 0x00 0.--31. 1. "val,reserved"
group.long 0x18++0x03
line.long 0x00 "io_config3,IO Config3 Register: Selects of output pin multiplexing"
bitfld.long 0x00 15. "sel_biss1_mo,select pad BISS ch 1 MO (s. pinning table)" "0,1"
newline
bitfld.long 0x00 14. "sel_biss1,select pads BISS ch 1 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 13. "sel_biss0_mo,select pad BISS ch 0 MO (s. pinning table)" "0,1"
newline
bitfld.long 0x00 12. "sel_biss0,select pads BISS ch 0 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 11. "sel_endat1_devel,select pads EnDAT ch 1 development function (s. pinning table) Note: EnDAT development function outputs are delayed by one sys-clk" "0,1"
newline
bitfld.long 0x00 10. "sel_endat1,select pads EnDAT ch 1 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 9. "sel_endat0_devel,select pads EnDAT ch 0 development function (s. pinning table) Note: EnDAT development function outputs are delayed by one sys-clk" "0,1"
newline
bitfld.long 0x00 8. "sel_endat0,select pads EnDAT ch 0 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_gpio7,select pad for gpio7 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 6. "sel_gpio6,select pad for gpio6 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 5. "sel_gpio5,select pad for gpio5 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 4. "sel_gpio4,select pad for gpio4 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 3. "sel_gpio3,select pad for gpio3 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 2. "sel_gpio2,select pad for gpio2 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 1. "sel_gpio1,select pad for gpio1 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 0. "sel_gpio0,select pad for gpio0 (s. pinning table) and deactivate this function via MMIOs" "0,1"
group.long 0x1C++0x03
line.long 0x00 "io_config3_mask,IO Config3 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
bitfld.long 0x00 15. "sel_biss1_mo,select pad BISS ch 1 MO (s. pinning table)" "0,1"
newline
bitfld.long 0x00 14. "sel_biss1,select pads BISS ch 1 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 13. "sel_biss0_mo,select pad BISS ch 0 MO (s. pinning table)" "0,1"
newline
bitfld.long 0x00 12. "sel_biss0,select pads BISS ch 0 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 11. "sel_endat1_devel,select pads EnDAT ch 1 development function (s. pinning table)" "0,1"
newline
bitfld.long 0x00 10. "sel_endat1,select pads EnDAT ch 1 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 9. "sel_endat0_devel,select pads EnDAT ch 0 development function (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_endat0,select pads EnDAT ch 0 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_gpio7,select pad for gpio7 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 6. "sel_gpio6,select pad for gpio6 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 5. "sel_gpio5,select pad for gpio5 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 4. "sel_gpio4,select pad for gpio4 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 3. "sel_gpio3,select pad for gpio3 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 2. "sel_gpio2,select pad for gpio2 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 1. "sel_gpio1,select pad for gpio1 (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 0. "sel_gpio0,select pad for gpio0 (s. pinning table) and deactivate this function via MMIOs" "0,1"
group.long 0x20++0x03
line.long 0x00 "io_config4,IO Config4 Register: Selects of output pin multiplexing"
bitfld.long 0x00 11. "sel_can1_app,select pad for can1_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 10. "sel_can0_app,select pad for can0_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 9. "sel_spi2_app_cs2,select pad for 3rd chip select of spi2_app (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_spi2_app_cs1,select pad for 2nd chip select of spi2_app (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_spi2_app,select pads for spi2_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 6. "sel_spi0_app_cs1,select pad for 2nd chip select of spi0_app (s. pinning table)" "0,1"
newline
bitfld.long 0x00 5. "sel_spi0_app,select pads for spi0_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 4. "sel_uart_xpic_app_rctsn,select pads for uart_xpic_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 3. "sel_uart_xpic_app,select pads for uart_xpic_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 2. "sel_uart_app_rctsn,select pads for uart_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 1. "sel_uart_app,select pads for uart_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 0. "sel_i2c_app,select pads for i2c_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
group.long 0x24++0x03
line.long 0x00 "io_config4_mask,IO Config4 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
bitfld.long 0x00 11. "sel_can1_app,select pad for can1_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 10. "sel_can0_app,select pad for can0_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 9. "sel_spi2_app_cs2,select pad for 3rd chip select of spi2_app (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_spi2_app_cs1,select pad for 2nd chip select of spi2_app (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_spi2_app,select pads for spi2_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 6. "sel_spi0_app_cs1,select pad for 2nd chip select of spi0_app (s. pinning table)" "0,1"
newline
bitfld.long 0x00 5. "sel_spi0_app,select pads for spi0_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 4. "sel_uart_xpic_app_rctsn,select pads for uart_xpic_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 3. "sel_uart_xpic_app,select pads for uart_xpic_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 2. "sel_uart_app_rctsn,select pads for uart_app RTS/CTS signals (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 1. "sel_uart_app,select pads for uart_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
newline
bitfld.long 0x00 0. "sel_i2c_app,select pads for i2c_app (s. pinning table) and deactivate this function via MMIOs" "0,1"
group.long 0x28++0x03
line.long 0x00 "io_config5,IO Config5 Register: Selects of output pin multiplexing"
bitfld.long 0x00 15. "sel_mled11,select pad for mled11 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 14. "sel_mled10,select pad for mled10 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 13. "sel_mled9,select pad for mled9 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 12. "sel_mled8,select pad for mled8 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 11. "sel_mled7,select pad for mled7 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 10. "sel_mled6,select pad for mled6 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 9. "sel_mled5,select pad for mled5 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_mled4,select pad for mled4 (s. pinning table)" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "sel_pio_app,select pads for pio_app (s. pinning table)"
group.long 0x2C++0x03
line.long 0x00 "io_config5_mask,IO Config5 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
bitfld.long 0x00 15. "sel_mled11,select pad for mled11 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 14. "sel_mled10,select pad for mled10 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 13. "sel_mled9,select pad for mled9 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 12. "sel_mled8,select pad for mled8 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 11. "sel_mled7,select pad for mled7 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 10. "sel_mled6,select pad for mled6 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 9. "sel_mled5,select pad for mled5 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_mled4,select pad for mled4 (s. pinning table)" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "sel_pio_app,select pads for pio_app (s. pinning table)"
group.long 0x30++0x03
line.long 0x00 "io_config6,IO Config6 Register: Selects of output pin multiplexing"
bitfld.long 0x00 9. "sel_io_link7,select pads for IO-Link7 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_io_link6,select pads for IO-Link6 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_io_link5,select pads for IO-Link5 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 6. "sel_io_link4,select pads for IO-Link4 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 5. "sel_io_link3,select pads for IO-Link3 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 4. "sel_io_link2,select pads for IO-Link2 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 3. "sel_io_link1b,select pads for IO-Link1 at position B (s. pinning table)" "0,1"
newline
bitfld.long 0x00 2. "sel_io_link1,select pads for IO-Link1 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 1. "sel_io_link0b,select pads for IO-Link0 at position B (s. pinning table)" "0,1"
newline
bitfld.long 0x00 0. "sel_io_link0,select pads for IO-Link0 (s. pinning table)" "0,1"
group.long 0x34++0x03
line.long 0x00 "io_config6_mask,IO Config6 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
bitfld.long 0x00 9. "sel_io_link7,select pads for IO-Link7 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 8. "sel_io_link6,select pads for IO-Link6 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_io_link5,select pads for IO-Link5 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 6. "sel_io_link4,select pads for IO-Link4 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 5. "sel_io_link3,select pads for IO-Link3 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 4. "sel_io_link2,select pads for IO-Link2 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 3. "sel_io_link1b,select pads for IO-Link1 at position B (s. pinning table)" "0,1"
newline
bitfld.long 0x00 2. "sel_io_link1,select pads for IO-Link1 (s. pinning table)" "0,1"
newline
bitfld.long 0x00 1. "sel_io_link0b,select pads for IO-Link0 at position B (s. pinning table)" "0,1"
newline
bitfld.long 0x00 0. "sel_io_link0,select pads for IO-Link0 (s. pinning table)" "0,1"
group.long 0x38++0x03
line.long 0x00 "io_config7,IO Config7 Register: Selects of output pin multiplexing"
bitfld.long 0x00 8. "sel_sqi_cs2,select pad for 3rd chip select of sqi (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_sqi_cs1,select pad for 2nd chip select of sqi (s. pinning table)" "0,1"
newline
bitfld.long 0x00 5.--6. "sel_eth_mdio,select connection for MIIMU MDIO interface used by ETH" "0: connect to multiplexmatrix,1: connect to external eth_mdio position A (s,2: connect to external MII_MDIO/MDC pins (s..,3: connect to internal PHY"
newline
bitfld.long 0x00 0.--4. "sel_eth_cfg,select connection of ETH MII pins" "0: no select,1: select pads for ETH RMII (rxd[1:0] rxdv rxer,2: select pads for ETH RX only mode (rxclk..,3: select pads for ETH minimum data transfer in..,4: select also pads for ETH rxclk pin for mac mode,5: select also pads for ETH RX error signal (rxer),6: select also pads for ETH collision and carrier,7: select also pads for ETH TX error signal (txer),8: ETH position B,9: ETH position B,10: ETH position B,11: ETH position B,12: ETH position B,13: ETH position B,14: ETH position B,15: connect to internal PHY0 if PHY0 not used by,16: connect to internal PHY1 if PHY1 not used by,17: connect to internal LVDS0 if LVDS0 not used by,18: connect to internal LVDS1 if LVDS1 not used by,?..."
group.long 0x3C++0x03
line.long 0x00 "io_config7_mask,IO Config7 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
bitfld.long 0x00 8. "sel_sqi_cs2,select pad for 3rd chip select of sqi (s. pinning table)" "0,1"
newline
bitfld.long 0x00 7. "sel_sqi_cs1,select pad for 2nd chip select of sqi (s. pinning table)" "0,1"
newline
bitfld.long 0x00 5.--6. "sel_eth_mdio,select connection for MIIMU MDIO interface used by ETH" "0,1,2,3"
newline
bitfld.long 0x00 0.--4. "sel_eth_cfg,select connection of ETH MII pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40++0x03
line.long 0x00 "io_config8,IO Config8 Register: Selects of output pin multiplexing"
bitfld.long 0x00 0.--1. "sel_arm_trace_cfg,select pins for CoreSight Tracing" "0: Disable Trace,1: Trace with 1 data line,2: Trace with 2 data lines,3: Trace with 4 data lines"
group.long 0x44++0x03
line.long 0x00 "io_config8_mask,IO Config8 Mask Register: This register might be used to lock special IO configurations for restricted netX devices"
bitfld.long 0x00 0.--1. "sel_arm_trace_cfg,select pins for CoreSight Tracing" "0,1,2,3"
group.long 0x50++0x03
line.long 0x00 "clock_enable0,Global Clock Enable Register: Use this registers to disable modules completely for power saving purposes"
bitfld.long 0x00 13. "dpm,enables clock for DPM" "0,1"
newline
bitfld.long 0x00 12. "debug,enables clock for Coresight Debugging" "0,1"
newline
bitfld.long 0x00 11. "arm_app,enables clock for ARM-APP" "0,1"
newline
bitfld.long 0x00 10. "dma_com,enables clock for COM DMA-Ctrl" "0,1"
newline
bitfld.long 0x00 9. "xpic0,enables clock for XPIC0" "0,1"
newline
bitfld.long 0x00 8. "xc_misc,enables clock for misc" "0,1"
newline
bitfld.long 0x00 7. "fb1,enables clock for fieldbus1" "0: use external xm1_eclk to resample xMAC outputs,1: use internally generated fb1clk to resample"
newline
bitfld.long 0x00 6. "fb0,enables clock for fieldbus0" "0: use external xm0_eclk to resample xMAC outputs,1: use internally generated fb0clk to resample"
newline
bitfld.long 0x00 5. "xmac1,enables clock for xMAC1" "0,1"
newline
bitfld.long 0x00 4. "xmac0,enables clock for xMAC0" "0,1"
newline
bitfld.long 0x00 3. "tpec1,enables clock for tPEC1" "0,1"
newline
bitfld.long 0x00 2. "tpec0,enables clock for tPEC0" "0,1"
newline
bitfld.long 0x00 1. "rpec1,enables clock for rPEC1" "0,1"
newline
bitfld.long 0x00 0. "rpec0,enables clock for rPEC0" "0,1"
group.long 0x54++0x03
line.long 0x00 "clock_enable0_mask,Global Clock Enable Mask Register: This register might be used to lock clock_enable0 register"
bitfld.long 0x00 13. "dpm,enables clock for DPM" "0,1"
newline
bitfld.long 0x00 12. "debug,enables clock for Coresight Debugging" "0,1"
newline
bitfld.long 0x00 11. "arm_app,enables clock for ARM-APP" "0,1"
newline
bitfld.long 0x00 10. "dma_com,enables clock for COM DMA-Ctrl" "0,1"
newline
bitfld.long 0x00 9. "xpic0,enables clock for XPIC0" "0,1"
newline
bitfld.long 0x00 8. "xc_misc,enables clock for misc" "0,1"
newline
bitfld.long 0x00 7. "fb1,enables clock for fieldbus1" "0,1"
newline
bitfld.long 0x00 6. "fb0,enables clock for fieldbus0" "0,1"
newline
bitfld.long 0x00 5. "xmac1,enables clock for xMAC1" "0,1"
newline
bitfld.long 0x00 4. "xmac0,enables clock for xMAC0" "0,1"
newline
bitfld.long 0x00 3. "tpec1,enables clock for tPEC1" "0,1"
newline
bitfld.long 0x00 2. "tpec0,enables clock for tPEC0" "0,1"
newline
bitfld.long 0x00 1. "rpec1,enables clock for rPEC1" "0,1"
newline
bitfld.long 0x00 0. "rpec0,enables clock for rPEC0" "0,1"
group.long 0x58++0x03
line.long 0x00 "clock_enable1,Global Clock Enable Register: Use this registers to disable modules completely for power saving purposes"
bitfld.long 0x00 2. "crypt,enables clock for CRYPT Unit" "0,1"
newline
bitfld.long 0x00 1. "dma_app,enables clock for APP DMA-Ctrl" "0,1"
newline
bitfld.long 0x00 0. "xpic1,enables clock for XPIC1" "0,1"
group.long 0x5C++0x03
line.long 0x00 "clock_enable1_mask,Global Clock Enable Mask Register: This register might be used to lock clock_enable1 register"
bitfld.long 0x00 2. "crypt,enables clock for CRYPT Unit" "0,1"
newline
bitfld.long 0x00 1. "dma_app,enables clock for APP DMA-Ctrl" "0,1"
newline
bitfld.long 0x00 0. "xpic1,enables clock for XPIC1" "0,1"
group.long 0x60++0x03
line.long 0x00 "reset_ctrl,Reset Control Register: This register controls the reset functions of the netX chip and indicates the reset state"
bitfld.long 0x00 27. "rst_out_n_in_ro,Status of reset pin (RST_OUT_N)" "0,1"
newline
bitfld.long 0x00 26. "EN_RES_REQ_OUT,This bit enables the driving of the programmable reset output RST_OUT_N" "0,1"
newline
bitfld.long 0x00 25. "RES_REQ_OUT,Software reset for external devices: This bit controls the level of the RST_OUT_N output for normal operation" "0,1"
newline
bitfld.long 0x00 24. "RES_REQ_FIRMWARE,Software reset: Writing a 1 will reset the whole system - except logic and register bits which are only reset on power-on-reset" "0,1"
newline
bitfld.long 0x00 23. "FIRMWARE_STATUS3,Readable and writable bit to save the firmware status only a power-on-reset will clear this bit" "0,1"
newline
bitfld.long 0x00 22. "FIRMWARE_STATUS2,Readable and writable bit to save the firmware status only a power-on-reset will clear this bit" "0,1"
newline
bitfld.long 0x00 21. "FIRMWARE_STATUS1,Readable and writable bit to save the firmware status only a power-on-reset will clear this bit" "0,1"
newline
bitfld.long 0x00 20. "FIRMWARE_STATUS0,Readable and writable bit to save the firmware status only a power-on-reset will clear this bit" "0,1"
newline
bitfld.long 0x00 5. "RES_ARM_APP,Reset status: A reset was performed by the SYSRESETREQ of the App ARM" "0,1"
newline
bitfld.long 0x00 4. "RES_ARM_COM,Reset status: A reset was performed by the SYSRESETREQ of the Com ARM" "0,1"
newline
bitfld.long 0x00 3. "RES_FIRMWARE,Reset status: A software reset was performed by the RES_REQ_FIRMWARE bit of this register" "0,1"
newline
bitfld.long 0x00 2. "RES_HOST,Reset status: A software reset was performed by an external host by the DPM interface" "0,1"
newline
bitfld.long 0x00 1. "RES_WDOG,Reset status: A reset was performed by the system watchdog" "0,1"
newline
bitfld.long 0x00 0. "RES_IN,Reset status: A reset was performed by the external pin (RST_IN_N)" "0,1"
rgroup.long 0x64++0x03
line.long 0x00 "ahbl_master_ready,All AHBL master ready signals"
hexmask.long.tbyte 0x00 0.--18. 1. "val,netx ahbl_master readys (0-18) M_DPM0 0 M_DPM1 1 M_XC01_d 2 M_XC01_s 3 M_IPC_MASTER 4 M_IDPM_MASTER 5 M_DEBUG_MASTER 6 M_XPIC_COM_d 7 M_XPIC_COM_i 8 M_XPIC_APP_d 9 M_XPIC_APP_i 10 M_ARM_COM_d 11 M_ARM_COM_i 12 M_ARM_COM_s 13 M_ARM_APP_d 14.."
rgroup.long 0x74++0x03
line.long 0x00 "system_status,netX System Status Register"
bitfld.long 0x00 16. "lic_err_abort_status,Current status of netX licence abort" "0,1"
newline
bitfld.long 0x00 11. "quick_count,Testmode 'quick_count' is activated by BSCAN JTAG TAP controller -&gt diverse internal counters count faster (RTC-clock-divider PLL-stby-controller ...)" "0,1"
newline
bitfld.long 0x00 10. "pll_bypass,Testmode 'pll_bypass' is activated by BSCAN JTAG TAP controller -&gt 400MHz-PLL is bypassed PLL output is unused 400MHz-Clocks (clk400 clk400_2sdram) is directly connected to XTALIN" "0,1"
newline
bitfld.long 0x00 9. "pw_bod_ok,Power watch brown-out detection status" "0,1"
newline
bitfld.long 0x00 8. "testmode,sampled netx TESTMODE input for production test purpose" "0,1"
newline
bitfld.long 0x00 1. "extbus_to_irq_status,Current status of HIF-Extension Bus Ready Timeout IRQ" "0,1"
newline
bitfld.long 0x00 0. "lic_err_irq_status,Current status of netX licence error IRQ" "0,1"
group.long 0x78++0x03
line.long 0x00 "systime_feth_ctrl,Select systime for FETH"
bitfld.long 0x00 0.--1. "feth,Systime for FETH" "0: systime_com,1: systime_com_uc,2: systime_app,?..."
group.long 0x80++0x03
line.long 0x00 "systime_gpio_app_ctrl,Select systime for GPIO_APP"
bitfld.long 0x00 0.--1. "gpio_app,Systime for GPIO_APP" "0: systime_com,1: systime_com_uc,2: systime_app,?..."
group.long 0x84++0x03
line.long 0x00 "only_porn,Firmware Status register: This register is not Reset by SW resets only PORn will reset this register"
hexmask.long 0x00 0.--31. 1. "only_porn,netX Firmware status"
group.long 0x88++0x03
line.long 0x00 "only_porn_rom,Firmware Status register for handling boot/rom-code issues: This register is not Reset by SW resets only PORn will reset this register"
hexmask.long 0x00 0.--31. 1. "val,netX Firmware status"
group.long 0x8C++0x03
line.long 0x00 "netx_version,netX Revision Register: This register contains information about netX hardware and bootloader revision"
abitfld.long 0x00 0.--31. "netx_version,netX revision number: Hardware reset values of netX version register is" "0x00000001=1: netx50,0x00000002=2: netx5_mpw,0x00000005=5: netx51/52,0x00000006=6: reserved,0x00000007=7: netx6,0x00000008=8: netx4000_relaxed,0x00000009=9: reserved,0x0000000A=10: netx4000,0x0000000B=11: reserved,0x0000000C=12: netxtiny_mpw,0x0000000D=13: netx90 Further netX,0x00000041=65: netx5,0x00000042=66: netx51/52,0x00000050=80: netx10"
group.long 0x90++0x03
line.long 0x00 "netx_status,netX Legacy System Status Configuration Register"
bitfld.long 0x00 25. "RUN_DRV,Driver enable for RUN LED" "0,1"
newline
bitfld.long 0x00 24. "RDY_DRV,Driver enable for RDY LED" "0,1"
newline
bitfld.long 0x00 19. "RUN_POL,Output polarity RUN LED outsig = RUN exor RUN_POL" "0,1"
newline
bitfld.long 0x00 18. "RDY_POL,Output polarity RDY LED outsig = RDY exor RDY_POL" "0,1"
newline
bitfld.long 0x00 17. "RUN_IN,Physical input signal level at RUN pin (read-only)" "0,1"
newline
bitfld.long 0x00 16. "RDY_IN,Physical input signal level at RDY pin (read-only)" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "NETX_STA_CODE,netX Status Code"
newline
bitfld.long 0x00 4.--7. "HOST_STATE_ro,Host Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "NETX_STATE,User defined status bits" "0,1,2,3"
newline
bitfld.long 0x00 1. "RUN,Signal Level of the RUN LED output" "0,1"
newline
bitfld.long 0x00 0. "RDY,Signal level of the RDY LED output" "0,1"
group.long 0x94++0x03
line.long 0x00 "rdy_run_cfg,netX Legacy RDY/RUN IO System Status Configuration Register"
bitfld.long 0x00 25. "RUN_DRV,Driver enable for RUN LED" "0,1"
newline
bitfld.long 0x00 24. "RDY_DRV,Driver enable for RDY LED" "0,1"
newline
bitfld.long 0x00 19. "RUN_POL,Output polarity RUN LED outsig = RUN exor RUN_POL" "0,1"
newline
bitfld.long 0x00 18. "RDY_POL,Output polarity RDY LED outsig = RDY exor RDY_POL" "0,1"
newline
bitfld.long 0x00 17. "RUN_IN,Physical input signal level at RUN pin (read-only)" "0,1"
newline
bitfld.long 0x00 16. "RDY_IN,Physical input signal level at RDY pin (read-only)" "0,1"
newline
bitfld.long 0x00 1. "RUN,Signal Level of the RUN LED output" "0,1"
newline
bitfld.long 0x00 0. "RDY,Signal level of the RDY LED output" "0,1"
group.long 0x98++0x03
line.long 0x00 "firewall_cfg_hifmem_sdram,Firewall configuration register for the HIFMEM_SDRAM NETX AHB channel"
bitfld.long 0x00 9. "abort_en_app,TBD: abort enable for APP side masters Note: Only the following COM-side masters support ERROR-response handling: ARM_APP DMAC_APP" "0,1"
newline
bitfld.long 0x00 8. "abort_en_com,TBD: abort enable for COM side masters for denied accesss" "0: no ERROR response to COM side masters,1: ERROR response to COM side masters on denied"
newline
bitfld.long 0x00 5. "rp_app,read permission for APP side masters" "0,1"
newline
bitfld.long 0x00 4. "rp_com,read permission for COM side masters" "0: deny read access,1: permit read access"
newline
bitfld.long 0x00 1. "wp_app,write permission for APP side masters" "0,1"
newline
bitfld.long 0x00 0. "wp_com,write permission for COM side masters" "0: deny write access,1: permit write access"
group.long 0x9C++0x03
line.long 0x00 "firewall_cfg_hifmem_amem,Firewall configuration register for the HIFMEM_AMEM NETX AHB channel"
bitfld.long 0x00 9. "abort_en_app,TBD: abort enable for APP side masters Note: Only the following COM-side masters support ERROR-response handling: ARM_APP DMAC_APP" "0,1"
newline
bitfld.long 0x00 8. "abort_en_com,TBD: abort enable for COM side masters for denied accesss" "0: no ERROR response to COM side masters,1: ERROR response to COM side masters on denied"
newline
bitfld.long 0x00 5. "rp_app,read permission for APP side masters" "0,1"
newline
bitfld.long 0x00 4. "rp_com,read permission for COM side masters" "0: deny read access,1: permit read access"
newline
bitfld.long 0x00 1. "wp_app,write permission for APP side masters" "0,1"
newline
bitfld.long 0x00 0. "wp_com,write permission for COM side masters" "0: deny write access,1: permit write access"
group.long 0xA0++0x03
line.long 0x00 "firewall_cfg_sqirom,Firewall configuration register for the SQIROM NETX AHB channel"
bitfld.long 0x00 9. "abort_en_app,TBD: abort enable for APP side masters Note: Only the following COM-side masters support ERROR-response handling: ARM_APP DMAC_APP" "0,1"
newline
bitfld.long 0x00 8. "abort_en_com,TBD: abort enable for COM side masters for denied accesss" "0: no ERROR response to COM side masters,1: ERROR response to COM side masters on denied"
newline
bitfld.long 0x00 5. "rp_app,read permission for APP side masters" "0,1"
newline
bitfld.long 0x00 4. "rp_com,read permission for COM side masters" "0: deny read access,1: permit read access"
newline
bitfld.long 0x00 1. "wp_app,write permission for APP side masters" "0,1"
newline
bitfld.long 0x00 0. "wp_com,write permission for COM side masters" "0: deny write access,1: permit write access"
group.long 0xA4++0x03
line.long 0x00 "firewall_cfg_crypt,Firewall configuration register for the CRYPT NETX AHB channel"
bitfld.long 0x00 9. "abort_en_app,TBD: abort enable for APP side masters Note: Only the following COM-side masters support ERROR-response handling: ARM_APP DMAC_APP" "0,1"
newline
bitfld.long 0x00 8. "abort_en_com,TBD: abort enable for COM side masters for denied accesss" "0: no ERROR response to COM side masters,1: ERROR response to COM side masters on denied"
newline
bitfld.long 0x00 5. "rp_app,read permission for APP side masters" "0,1"
newline
bitfld.long 0x00 4. "rp_com,read permission for COM side masters" "0: deny read access,1: permit read access"
newline
bitfld.long 0x00 1. "wp_app,write permission for APP side masters" "0,1"
newline
bitfld.long 0x00 0. "wp_com,write permission for COM side masters" "0: deny write access,1: permit write access"
group.long 0xA8++0x03
line.long 0x00 "misc_asic_ctrl,TBD: anpassen/ausbauen Miscellaneous ASIC Control Register: This register is lockable by asic_ctrl_com_netx_lock-lock_register"
bitfld.long 0x00 3. "lic_err_delay_en,Random Delay between a detected license error and abort-generation/change to tainted mode" "0,1"
newline
bitfld.long 0x00 2. "lic_err_irq_en,In case of a detected license error ARM-IRQ will be generated" "0,1"
newline
bitfld.long 0x00 1. "lic_err_abort_en,In case of a detected license error ARM-Abort will be generated on the next data write (no data loss caused)" "0,1"
newline
bitfld.long 0x00 0. "lic_err_taint_en,In case of a detected license error system clock will be reduced to 80MHz Tainted mode can be left when this bit is disabled or at unprotected phase after power-on-reset by a valid LICCHECK sequence" "0,1"
group.long 0xC0++0x03
line.long 0x00 "asic_ctrl_access_key,ASIC Control Locking access-key Register: Writing to any register in the asic_ctrl or mmio_ctrl address area is only possible after setting the correct key here to avoid unmeant changes e.g"
hexmask.long.word 0x00 0.--15. 1. "access_key,Locking access-key for next write access"
group.long 0xC8++0x03
line.long 0x00 "asic_ctrl_irq_raw,ASIC_CTRL raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 8. "bod_fail,Voltage at BOD pad dropped below threshold" "0,1"
newline
bitfld.long 0x00 7. "firewall_crypt_app,Firewall of crypt blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 6. "firewall_crypt_com,Firewall of crypt blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 5. "firewall_sqirom_app,Firewall of sqirom blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 4. "firewall_sqirom_com,Firewall of sqirom blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 3. "firewall_hifmem_amem_app,Firewall of hifmem_amem blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 2. "firewall_hifmem_amem_com,Firewall of hifmem_amem blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 1. "firewall_hifmem_sdram_app,Firewall of hifmem_sdram blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 0. "firewall_hifmem_sdram_com,Firewall of hifmem_sdram blocked a request of COM side" "0,1"
rgroup.long 0xCC++0x03
line.long 0x00 "asic_ctrl_irq_masked,ASIC_CTRL masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 8. "bod_fail,Voltage at BOD pad dropped below threshold" "0,1"
newline
bitfld.long 0x00 7. "firewall_crypt_app,Firewall of crypt blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 6. "firewall_crypt_com,Firewall of crypt blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 5. "firewall_sqirom_app,Firewall of sqirom blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 4. "firewall_sqirom_com,Firewall of sqirom blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 3. "firewall_hifmem_amem_app,Firewall of hifmem_amem blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 2. "firewall_hifmem_amem_com,Firewall of hifmem_amem blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 1. "firewall_hifmem_sdram_app,Firewall of hifmem_sdram blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 0. "firewall_hifmem_sdram_com,Firewall of hifmem_sdram blocked a request of COM side" "0,1"
group.long 0xD0++0x03
line.long 0x00 "asic_ctrl_irq_mask_set,ASIC_CTRL IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 8. "bod_fail,Voltage at BOD pad dropped below threshold" "0,1"
newline
bitfld.long 0x00 7. "firewall_crypt_app,Firewall of crypt blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 6. "firewall_crypt_com,Firewall of crypt blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 5. "firewall_sqirom_app,Firewall of sqirom blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 4. "firewall_sqirom_com,Firewall of sqirom blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 3. "firewall_hifmem_amem_app,Firewall of hifmem_amem blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 2. "firewall_hifmem_amem_com,Firewall of hifmem_amem blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 1. "firewall_hifmem_sdram_app,Firewall of hifmem_sdram blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 0. "firewall_hifmem_sdram_com,Firewall of hifmem_sdram blocked a request of COM side" "0,1"
group.long 0xD4++0x03
line.long 0x00 "asic_ctrl_irq_mask_reset,ASIC_CTRL IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 8. "bod_fail,Voltage at BOD pad dropped below threshold" "0,1"
newline
bitfld.long 0x00 7. "firewall_crypt_app,Firewall of crypt blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 6. "firewall_crypt_com,Firewall of crypt blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 5. "firewall_sqirom_app,Firewall of sqirom blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 4. "firewall_sqirom_com,Firewall of sqirom blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 3. "firewall_hifmem_amem_app,Firewall of hifmem_amem blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 2. "firewall_hifmem_amem_com,Firewall of hifmem_amem blocked a request of COM side" "0,1"
newline
bitfld.long 0x00 1. "firewall_hifmem_sdram_app,Firewall of hifmem_sdram blocked a request of APP side" "0,1"
newline
bitfld.long 0x00 0. "firewall_hifmem_sdram_com,Firewall of hifmem_sdram blocked a request of COM side" "0,1"
tree.end
tree "BISS_CTRL0_APP"
base ad:0xFF801D00
group.long 0x00++0x03
line.long 0x00 "biss_ctrl_trigger_cfg,BiSS trigger configuration"
bitfld.long 0x00 0.--3. "sel,Trigger source select This bit field configures which event is connected to the GETSENS signal of the BiSS core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "biss_ctrl_trigger,BiSS trigger"
bitfld.long 0x00 0. "manual,Manual trigger" "0,1"
group.long 0x08++0x03
line.long 0x00 "biss_ctrl_irq_raw,BiSS raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "biss_ctrl_irq_masked,BiSS masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
group.long 0x10++0x03
line.long 0x00 "biss_ctrl_irq_msk_set,BiSS IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
group.long 0x14++0x03
line.long 0x00 "biss_ctrl_irq_msk_reset,BiSS IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
tree.end
tree "BISS_CTRL1_APP"
base ad:0xFF801D20
group.long 0x00++0x03
line.long 0x00 "biss_ctrl_trigger_cfg,BiSS trigger configuration"
bitfld.long 0x00 0.--3. "sel,Trigger source select This bit field configures which event is connected to the GETSENS signal of the BiSS core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "biss_ctrl_trigger,BiSS trigger"
bitfld.long 0x00 0. "manual,Manual trigger" "0,1"
group.long 0x08++0x03
line.long 0x00 "biss_ctrl_irq_raw,BiSS raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "biss_ctrl_irq_masked,BiSS masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
group.long 0x10++0x03
line.long 0x00 "biss_ctrl_irq_msk_set,BiSS IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
group.long 0x14++0x03
line.long 0x00 "biss_ctrl_irq_msk_reset,BiSS IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 1. "err,Error signal from the BiSS core" "0,1"
bitfld.long 0x00 0. "eot,End-Of-Transmission signal from the BiSS core" "0,1"
tree.end
tree "BISS0_APP"
base ad:0xFF801B00
group.long 0x00++0x03
line.long 0x00 "biss_scdata0_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA0_0,Slave0 (SCD)single cycle data[31:0]"
group.long 0x04++0x03
line.long 0x00 "biss_scdata0_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA0_1,Slave0 (SCD)single cycle data[63:32]"
group.long 0x08++0x03
line.long 0x00 "biss_scdata1_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA1_0,Slave1 (SCD)single cycle data[31:0]"
group.long 0x0C++0x03
line.long 0x00 "biss_scdata1_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA1_1,Slave1 (SCD)single cycle data[63:32]"
group.long 0x10++0x03
line.long 0x00 "biss_scdata2_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA2_0,Slave2 (SCD)single cycle data[31:0]"
group.long 0x14++0x03
line.long 0x00 "biss_scdata2_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA2_1,Slave2 (SCD)single cycle data[63:32]"
group.long 0x18++0x03
line.long 0x00 "biss_scdata3_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA3_0,Slave3 (SCD)single cycle data[31:0]"
group.long 0x1C++0x03
line.long 0x00 "biss_scdata3_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA3_1,Slave3 (SCD)single cycle data[63:32]"
group.long 0x20++0x03
line.long 0x00 "biss_scdata4_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA4_0,Slave4 (SCD)single cycle data[31:0]"
group.long 0x24++0x03
line.long 0x00 "biss_scdata4_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA4_1,Slave4 (SCD)single cycle data[63:32]"
group.long 0x28++0x03
line.long 0x00 "biss_scdata5_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA5_0,Slave5 (SCD)single cycle data[31:0]"
group.long 0x2C++0x03
line.long 0x00 "biss_scdata5_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA5_1,Slave5 (SCD)single cycle data[63:32]"
group.long 0x30++0x03
line.long 0x00 "biss_scdata6_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA6_0,Slave6 (SCD)single cycle data[31:0]"
group.long 0x34++0x03
line.long 0x00 "biss_scdata6_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA6_1,Slave6 (SCD)single cycle data[63:32]"
group.long 0x38++0x03
line.long 0x00 "biss_scdata7_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA7_0,Slave0 (SCD)single cycle data[31:0]"
group.long 0x3C++0x03
line.long 0x00 "biss_scdata7_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA7_1,Slave7 (SCD)single cycle data[63:32]"
group.long 0x80++0x03
line.long 0x00 "biss_rdata0,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA0,- Using register access in control communication RDATA0: register data DWord0 - Using command/instructions in control communication IDS: ID-Select command/instruction addressing combinable"
group.long 0x84++0x03
line.long 0x00 "biss_rdata1,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA1,register data DWord1"
group.long 0x88++0x03
line.long 0x00 "biss_rdata2,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA2,register data DWord2"
group.long 0x8C++0x03
line.long 0x00 "biss_rdata3,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA3,register data DWord3"
group.long 0x90++0x03
line.long 0x00 "biss_rdata4,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA4,register data DWord4"
group.long 0x94++0x03
line.long 0x00 "biss_rdata5,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA5,register data DWord5"
group.long 0x98++0x03
line.long 0x00 "biss_rdata6,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA6,register data DWord6"
group.long 0x9C++0x03
line.long 0x00 "biss_rdata7,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA7,register data DWord7"
group.long 0xA0++0x03
line.long 0x00 "biss_rdata8,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA8,register data DWord8"
group.long 0xA4++0x03
line.long 0x00 "biss_rdata9,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA9,register data DWord9"
group.long 0xA8++0x03
line.long 0x00 "biss_rdata10,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA10,register data DWord10"
group.long 0xAC++0x03
line.long 0x00 "biss_rdata11,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA11,register data DWord11"
group.long 0xB0++0x03
line.long 0x00 "biss_rdata12,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA12,register data DWord12"
group.long 0xB4++0x03
line.long 0x00 "biss_rdata13,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA13,register data DWord13"
group.long 0xB8++0x03
line.long 0x00 "biss_rdata14,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA14,register data DWord14"
group.long 0xBC++0x03
line.long 0x00 "biss_rdata15,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA15,register data DWord15"
group.long 0xC0++0x03
line.long 0x00 "biss_sc0,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART0,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS0,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY0,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP0,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD0,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN0,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xC4++0x03
line.long 0x00 "biss_sc1,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART1,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS1,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY1,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP1,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD1,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN1,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xC8++0x03
line.long 0x00 "biss_sc2,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART2,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS2,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY2,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP2,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD2,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN2,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xCC++0x03
line.long 0x00 "biss_sc3,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART3,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS3,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY3,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP3,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD3,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN3,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xD0++0x03
line.long 0x00 "biss_sc4,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART4,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS4,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY4,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP4,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD4,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN4,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xD4++0x03
line.long 0x00 "biss_sc5,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART5,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS5,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY5,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP5,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD5,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN5,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xD8++0x03
line.long 0x00 "biss_sc6,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART6,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS6,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY6,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP6,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD6,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN6,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xDC++0x03
line.long 0x00 "biss_sc7,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART7,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS7,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY7,- SELCRCx == 0 (SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP7,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSC7,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN7,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xE0++0x03
line.long 0x00 "biss_ccc0,Register Communication Configuration"
bitfld.long 0x00 24.--29. "REGNUM,Register data count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "WNR,Register access read/write selector" "0: read register data,1: write register data"
newline
hexmask.long.byte 0x00 16.--22. 1. "REGADR,Register access start address 0x00"
group.long 0xE4++0x03
line.long 0x00 "biss_ccc1_mc0,Register Communication Configuration / Master Configuration"
bitfld.long 0x00 25. "NOCRC,CRC for SCD not to be stored in RAM" "0: CRC of SCD is stored RAM (only applicable with,1: CRC of SCD not to be stored in RAM"
bitfld.long 0x00 24. "SINGLEBANK,Use of only one RAM bank for SCD" "0: two RAM banks are used for SCD,1: one RAM bank is used for SCD"
newline
bitfld.long 0x00 21.--23. "FREQR,Frequency division register communication BiSS B 0" "0: FreqSens/2,1: FreqSens/4,2: FreqSens/8,3: FreqSens/16,4: FreqSens/32,5: FreqSens/64,6: FreqSens/128,7: FreqSens/256"
bitfld.long 0x00 16.--20. "FREQS,Frequency division" "0: fCLK/2,1: fCLK/4,2: fCLK/6,3: fCLK/8,?,?,?,?,?,9: fCLK/20,?,?,?,13: fCLK/28,14: fCLK/30,15: fCLK/32,16: not permitted,17: fCLK/40,18: fCLK/60,19: fCLK/80,?,?,?,?,?,?,?,?,?,29: fCLK/280,30: fCLK/300,31: fCLK/320"
newline
bitfld.long 0x00 15. "CTS,Register transmission or instruction selector" "0: command/instruction communication,1: register communication"
bitfld.long 0x00 14. "REGVERS,BiSS model A/B or C selector - Using register access in control communication" "0: not applicable with command/instruction,1: command communication BiSS C"
newline
bitfld.long 0x00 12.--13. "CMD,- Using register access in control communication SLAVEID[2:1]: slave selector bit2_1 - Using command/instructions in control communication Command of access slave 0x00" "0,1,2,3"
bitfld.long 0x00 11. "IDA_TEST,- Using register access in control communication SLAVEID[0]: slave selector bit0 - Using command/instructions in control communication IDA_TEST: command/instruction execution control" "0: the slaves feedback (IDA) is tested before,1: immediate execution"
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bitfld.long 0x00 9. "EN_MO,Enable output at MOx for actuator data or delayed start bit" "0: MO forced to low,1: Parameterized processing time by master on MO"
bitfld.long 0x00 8. "HOLDCDM,Hold CDM(control data master)" "0: clock line high at end of cycle,1: clock line constant with CDM bit until start of"
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bitfld.long 0x00 0.--1. "CHSEL,Channel selector" "0: channel 1 used for control communication..,1: channel 1 used for control communication..,2: channel 2 used for control communication..,3: channel 1 2 used for control communication"
group.long 0xE8++0x03
line.long 0x00 "biss_mc1,Master Configuration"
abitfld.long 0x00 24.--31. "VERSION,Device identifier" "0x83=131: iC-MB3,0x84=132: iC-MB4"
abitfld.long 0x00 16.--23. "REVISION,Revision" "0x10=16: Z(first,0x11=17: Z1,0x12=18: Y"
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hexmask.long.byte 0x00 8.--15. 1. "MO_BUSY,Delay of start bit at output MOx 0x00"
abitfld.long 0x00 0.--7. "FREQAGS,AutoGetSens Frequency division 0x00" "0x7B=123: fCLK/(20*(FREQAGS(6:0)+1)),0x7C=124: AGSMIN( the master automatically..,0x7F=127: AGSINFINITE( the master does not..,0xFF=255: fCLK/(625*(FREQAGS(6:0)+1))"
group.long 0xEC++0x03
line.long 0x00 "biss_cc_sl,Channel Configuration"
abitfld.long 0x00 24.--31. "ACTnSENS,Sensor or actuator data selector" "0x00=0: all slaves are sensors,0x01=1: slave 0 is actuator,0x02=2: slave 1 is actuator,0x04=4: slave 2 is actuator,0x08=8: slave 3 is actuator,0x10=16: slave 4 is actuator,0x20=32: slave 5 is actuator,0x40=64: slave 6 is actuator,0x80=128: slave 7 is actuator,0xFF=255: all slaves are actuators"
bitfld.long 0x00 10.--11. "CFGCH2,Channel 2 configuration" "0: BiSS B,1: BiSS C,2: SSI,3: channel is"
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bitfld.long 0x00 8.--9. "CFGCH1,Channel 1 configuration" "0: BiSS B,1: BiSS C,2: SSI,3: channel is"
bitfld.long 0x00 4. "SLAVELOC5,Slave location" "0: slaves 4-7 are connected to channel 1,1: slaves 4-7 are connected to channel 2(only"
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bitfld.long 0x00 0.--3. "cc_sl_reserved1,no field descpription" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF0++0x03
line.long 0x00 "biss_status0,Status Information"
bitfld.long 0x00 31. "CDMTIMEOUT,CDM(Control Data Master) timeout reached" "0: CDMTIMEOUT not reached,1: CDMTIMEOUT reached"
bitfld.long 0x00 30. "CDSSEL,CDS(Control Data Slave) bit from the selected channel" "0,1"
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bitfld.long 0x00 24.--29. "REGBYTES,Number of valid register data transmission in case of error" "0: after transfer,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: after transfer"
bitfld.long 0x00 23. "SVALID7,SCDATA7 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 21. "SVALID6,SCDATA6 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 19. "SVALID5,SCDATA5 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 17. "SVALID4,SCDATA4 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 15. "SVALID3,SCDATA3 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 13. "SVALID2,SCDATA2 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 11. "SVALID1,SCDATA1 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 9. "SVALID0,SCDATA0 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 7. "nERR,Transmission error (error at NER pin)" "0: error,1: no error It"
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bitfld.long 0x00 6. "nAGSERR,AGS error" "0: AGS(Automatic Get Sensor data) watchdog error,1: no AGS watchdog error An AGS watchdog error is"
bitfld.long 0x00 5. "nDELAYERR,Missing start bit during register communication" "0: delay error,1: no delay error"
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bitfld.long 0x00 4. "nSCDERR,Error in single cycle data transmission" "0: error in last single cycle data transmission,1: no error in last single cycle data transmission"
bitfld.long 0x00 3. "nREGERR,Error in register data transmission" "0: error in last register data transmission,1: no error in last register data transmission"
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bitfld.long 0x00 2. "REGEND,Register data transmission completed" "0: no valid register data available,1: register data transmission completed"
bitfld.long 0x00 1. "status0_reserved1,reserved" "0,1"
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bitfld.long 0x00 0. "EOT,Data transmission completed" "0: data transmission active,1: data transmission finished"
group.long 0xF4++0x03
line.long 0x00 "biss_ir,Instruction Register"
bitfld.long 0x00 15. "MAVO,Not selected MA line control level" "0: low definition of unselected(CHSEL) MA clock..,1: high definition of unselected(CHSEL) MA clock"
bitfld.long 0x00 14. "MAFO,Not selected MA line control selection" "0: controlling unselected(CHSEL) MA clock line,1: controlling unselected(CHSEL) MA clock line"
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bitfld.long 0x00 13. "MAVS,Selected MA line control level" "0: low definition of selected(CHSEL) MA clock..,1: high definition of selected(CHSEL) MA clock.."
bitfld.long 0x00 12. "MAFS,Selected MA line control selection" "0: controlling selected/CHSEL) MA clock line:..,1: controlling selected(CHSEL) MA clock line"
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bitfld.long 0x00 10.--11. "CFGIF,Configure physical interface" "0: TTL,1: CMOS,2: RS422,3: LVDS"
bitfld.long 0x00 9. "ENTEST,Enable test interface" "0: device in normal operation mode,1: device in test mode"
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bitfld.long 0x00 8. "CLKENI,Enable internal clock" "0: the master clock is generated by an external,1: the master clock is generated by the basic.."
bitfld.long 0x00 7. "BREAK,Data transmission interrupt" "0: no change,1: abort data transmission"
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bitfld.long 0x00 6. "HOLDBANK,RAM bank control" "0: no bank switching lock permitted,1: bank switching lock permitted During the.."
bitfld.long 0x00 5. "SWBANK,Switch RAM banks" "0: RAM banks are not switched,1: RAM banks are switched"
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bitfld.long 0x00 4. "INIT,Start INIT sequence" "0: no changes on the data channel,1: initialize data channel"
bitfld.long 0x00 1.--3. "INSTR,SCD control instruction 0b010 : CDM = 0 0b001 : CDM = 1 0b100 0b110: register communication condition: CDMTIMEOUT = 1 0b111 : register communication(reduced protocol) condition: CDMTIMEOUT = 1 The transmission of sensor data can be triggered via.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "AGS,AutoGetSens(Automatic Get Sensordata)" "0: no automatic data transmission,1: - start of data transmission after TIMEOUTSENS"
rgroup.long 0xF8++0x03
line.long 0x00 "biss_status1,Status Information"
bitfld.long 0x00 24. "SWBANKFAILS,Bank switching status" "0: bank switching(SCD) successful,1: bank switching(SCD) not successful"
bitfld.long 0x00 1. "CDS1,CDS bit of channel 1" "0: CDS = 0,1: CDS = 1"
newline
bitfld.long 0x00 0. "SL1,Current SL line level of channel 1" "0: SL line level low,1: SL line level high"
tree.end
tree "BISS1_APP"
base ad:0xFF801C00
group.long 0x00++0x03
line.long 0x00 "biss_scdata0_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA0_0,Slave0 (SCD)single cycle data[31:0]"
group.long 0x04++0x03
line.long 0x00 "biss_scdata0_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA0_1,Slave0 (SCD)single cycle data[63:32]"
group.long 0x08++0x03
line.long 0x00 "biss_scdata1_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA1_0,Slave1 (SCD)single cycle data[31:0]"
group.long 0x0C++0x03
line.long 0x00 "biss_scdata1_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA1_1,Slave1 (SCD)single cycle data[63:32]"
group.long 0x10++0x03
line.long 0x00 "biss_scdata2_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA2_0,Slave2 (SCD)single cycle data[31:0]"
group.long 0x14++0x03
line.long 0x00 "biss_scdata2_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA2_1,Slave2 (SCD)single cycle data[63:32]"
group.long 0x18++0x03
line.long 0x00 "biss_scdata3_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA3_0,Slave3 (SCD)single cycle data[31:0]"
group.long 0x1C++0x03
line.long 0x00 "biss_scdata3_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA3_1,Slave3 (SCD)single cycle data[63:32]"
group.long 0x20++0x03
line.long 0x00 "biss_scdata4_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA4_0,Slave4 (SCD)single cycle data[31:0]"
group.long 0x24++0x03
line.long 0x00 "biss_scdata4_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA4_1,Slave4 (SCD)single cycle data[63:32]"
group.long 0x28++0x03
line.long 0x00 "biss_scdata5_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA5_0,Slave5 (SCD)single cycle data[31:0]"
group.long 0x2C++0x03
line.long 0x00 "biss_scdata5_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA5_1,Slave5 (SCD)single cycle data[63:32]"
group.long 0x30++0x03
line.long 0x00 "biss_scdata6_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA6_0,Slave6 (SCD)single cycle data[31:0]"
group.long 0x34++0x03
line.long 0x00 "biss_scdata6_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA6_1,Slave6 (SCD)single cycle data[63:32]"
group.long 0x38++0x03
line.long 0x00 "biss_scdata7_0,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA7_0,Slave0 (SCD)single cycle data[31:0]"
group.long 0x3C++0x03
line.long 0x00 "biss_scdata7_1,Sensor and Actuator Data"
hexmask.long 0x00 0.--31. 1. "SCDATA7_1,Slave7 (SCD)single cycle data[63:32]"
group.long 0x80++0x03
line.long 0x00 "biss_rdata0,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA0,- Using register access in control communication RDATA0: register data DWord0 - Using command/instructions in control communication IDS: ID-Select command/instruction addressing combinable"
group.long 0x84++0x03
line.long 0x00 "biss_rdata1,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA1,register data DWord1"
group.long 0x88++0x03
line.long 0x00 "biss_rdata2,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA2,register data DWord2"
group.long 0x8C++0x03
line.long 0x00 "biss_rdata3,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA3,register data DWord3"
group.long 0x90++0x03
line.long 0x00 "biss_rdata4,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA4,register data DWord4"
group.long 0x94++0x03
line.long 0x00 "biss_rdata5,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA5,register data DWord5"
group.long 0x98++0x03
line.long 0x00 "biss_rdata6,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA6,register data DWord6"
group.long 0x9C++0x03
line.long 0x00 "biss_rdata7,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA7,register data DWord7"
group.long 0xA0++0x03
line.long 0x00 "biss_rdata8,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA8,register data DWord8"
group.long 0xA4++0x03
line.long 0x00 "biss_rdata9,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA9,register data DWord9"
group.long 0xA8++0x03
line.long 0x00 "biss_rdata10,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA10,register data DWord10"
group.long 0xAC++0x03
line.long 0x00 "biss_rdata11,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA11,register data DWord11"
group.long 0xB0++0x03
line.long 0x00 "biss_rdata12,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA12,register data DWord12"
group.long 0xB4++0x03
line.long 0x00 "biss_rdata13,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA13,register data DWord13"
group.long 0xB8++0x03
line.long 0x00 "biss_rdata14,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA14,register data DWord14"
group.long 0xBC++0x03
line.long 0x00 "biss_rdata15,Register Data"
hexmask.long 0x00 0.--31. 1. "RDATA15,register data DWord15"
group.long 0xC0++0x03
line.long 0x00 "biss_sc0,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART0,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS0,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
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abitfld.long 0x00 8.--14. "SCRCPOLY0,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP0,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD0,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN0,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xC4++0x03
line.long 0x00 "biss_sc1,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART1,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS1,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY1,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP1,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD1,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN1,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xC8++0x03
line.long 0x00 "biss_sc2,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART2,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS2,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY2,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP2,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD2,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN2,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xCC++0x03
line.long 0x00 "biss_sc3,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART3,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS3,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY3,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP3,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD3,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN3,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xD0++0x03
line.long 0x00 "biss_sc4,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART4,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS4,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY4,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP4,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD4,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN4,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xD4++0x03
line.long 0x00 "biss_sc5,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART5,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS5,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY5,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP5,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD5,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN5,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xD8++0x03
line.long 0x00 "biss_sc6,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART6,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS6,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY6,- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP6,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
newline
bitfld.long 0x00 6. "ENSCD6,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN6,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xDC++0x03
line.long 0x00 "biss_sc7,Slave Configuration"
hexmask.long.word 0x00 16.--31. 1. "SCRCSTART7,Start value for polynomial SCD CRC calculation"
bitfld.long 0x00 15. "SELCRCS7,Selection between polynomial or length for SCD CRC polynomial" "0: CRC bit length in SCRCLENx (see SCRCPOLYx)..,1: CRC polynomial(7:1) in SCRCPOLYx"
newline
abitfld.long 0x00 8.--14. "SCRCPOLY7,- SELCRCx == 0 (SCRCLENx: polynomial selection by length for SCD CRC check)" "0x00=0: CRC polynomial 0x00 not applicable with..,0x03=3: CRC polynomial =,0x7F=127: CRC polynomial for single cycle data ="
bitfld.long 0x00 7. "LSTOP7,- BISS mode(LSTOPx = Actuator stop bit control)" "0: SSI single cycle data binary coded,1: SSI single cycle data gray coded"
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bitfld.long 0x00 6. "ENSC7,Enable single cycle data" "0: single cycle data not available,1: single cycle data available"
bitfld.long 0x00 0.--5. "SCDLEN7,Single cycle data length" "0: single cycle data length = 1,1: single cycle data length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: single cycle data length = 63,63: single cycle data length = 64"
group.long 0xE0++0x03
line.long 0x00 "biss_ccc0,Register Communication Configuration"
bitfld.long 0x00 24.--29. "REGNUM,Register data count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "WNR,Register access read/write selector" "0: read register data,1: write register data"
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hexmask.long.byte 0x00 16.--22. 1. "REGADR,Register access start address 0x00"
group.long 0xE4++0x03
line.long 0x00 "biss_ccc1_mc0,Register Communication Configuration / Master Configuration"
bitfld.long 0x00 25. "NOCRC,CRC for SCD not to be stored in RAM" "0: CRC of SCD is stored RAM (only applicable with,1: CRC of SCD not to be stored in RAM"
bitfld.long 0x00 24. "SINGLEBANK,Use of only one RAM bank for SCD" "0: two RAM banks are used for SCD,1: one RAM bank is used for SCD"
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bitfld.long 0x00 21.--23. "FREQR,Frequency division register communication BiSS B 0" "0: FreqSens/2,1: FreqSens/4,2: FreqSens/8,3: FreqSens/16,4: FreqSens/32,5: FreqSens/64,6: FreqSens/128,7: FreqSens/256"
bitfld.long 0x00 16.--20. "FREQS,Frequency division" "0: fCLK/2,1: fCLK/4,2: fCLK/6,3: fCLK/8,?,?,?,?,?,9: fCLK/20,?,?,?,13: fCLK/28,14: fCLK/30,15: fCLK/32,16: not permitted,17: fCLK/40,18: fCLK/60,19: fCLK/80,?,?,?,?,?,?,?,?,?,29: fCLK/280,30: fCLK/300,31: fCLK/320"
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bitfld.long 0x00 15. "CTS,Register transmission or instruction selector" "0: command/instruction communication,1: register communication"
bitfld.long 0x00 14. "REGVERS,BiSS model A/B or C selector - Using register access in control communication" "0: not applicable with command/instruction,1: command communication BiSS C"
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bitfld.long 0x00 12.--13. "CMD,- Using register access in control communication SLAVEID[2:1]: slave selector bit2_1 - Using command/instructions in control communication Command of access slave 0x00" "0,1,2,3"
bitfld.long 0x00 11. "IDA_TEST,- Using register access in control communication SLAVEID[0]: slave selector bit0 - Using command/instructions in control communication IDA_TEST: command/instruction execution control" "0: the slaves feedback (IDA) is tested before,1: immediate execution"
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bitfld.long 0x00 9. "EN_MO,Enable output at MOx for actuator data or delayed start bit" "0: MO forced to low,1: Parameterized processing time by master on MO"
bitfld.long 0x00 8. "HOLDCDM,Hold CDM(control data master)" "0: clock line high at end of cycle,1: clock line constant with CDM bit until start of"
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bitfld.long 0x00 0.--1. "CHSEL,Channel selector" "0: channel 1 used for control communication..,1: channel 1 used for control communication..,2: channel 2 used for control communication..,3: channel 1 2 used for control communication"
group.long 0xE8++0x03
line.long 0x00 "biss_mc1,Master Configuration"
abitfld.long 0x00 24.--31. "VERSION,Device identifier" "0x83=131: iC-MB3,0x84=132: iC-MB4"
abitfld.long 0x00 16.--23. "REVISION,Revision" "0x10=16: Z(first,0x11=17: Z1,0x12=18: Y"
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hexmask.long.byte 0x00 8.--15. 1. "MO_BUSY,Delay of start bit at output MOx 0x00"
abitfld.long 0x00 0.--7. "FREQAGS,AutoGetSens Frequency division 0x00" "0x7B=123: fCLK/(20*(FREQAGS(6:0)+1)),0x7C=124: AGSMIN( the master automatically..,0x7F=127: AGSINFINITE( the master does not..,0xFF=255: fCLK/(625*(FREQAGS(6:0)+1))"
group.long 0xEC++0x03
line.long 0x00 "biss_cc_sl,Channel Configuration"
abitfld.long 0x00 24.--31. "ACTnSENS,Sensor or actuator data selector" "0x00=0: all slaves are sensors,0x01=1: slave 0 is actuator,0x02=2: slave 1 is actuator,0x04=4: slave 2 is actuator,0x08=8: slave 3 is actuator,0x10=16: slave 4 is actuator,0x20=32: slave 5 is actuator,0x40=64: slave 6 is actuator,0x80=128: slave 7 is actuator,0xFF=255: all slaves are actuators"
bitfld.long 0x00 10.--11. "CFGCH2,Channel 2 configuration" "0: BiSS B,1: BiSS C,2: SSI,3: channel is"
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bitfld.long 0x00 8.--9. "CFGCH1,Channel 1 configuration" "0: BiSS B,1: BiSS C,2: SSI,3: channel is"
bitfld.long 0x00 4. "SLAVELOC5,Slave location" "0: slaves 4-7 are connected to channel 1,1: slaves 4-7 are connected to channel 2(only"
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bitfld.long 0x00 0.--3. "cc_sl_reserved1,no field descpription" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF0++0x03
line.long 0x00 "biss_status0,Status Information"
bitfld.long 0x00 31. "CDMTIMEOUT,CDM(Control Data Master) timeout reached" "0: CDMTIMEOUT not reached,1: CDMTIMEOUT reached"
bitfld.long 0x00 30. "CDSSEL,CDS(Control Data Slave) bit from the selected channel" "0,1"
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bitfld.long 0x00 24.--29. "REGBYTES,Number of valid register data transmission in case of error" "0: after transfer,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: after transfer"
bitfld.long 0x00 23. "SVALID7,SCDATA7 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 21. "SVALID6,SCDATA6 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 19. "SVALID5,SCDATA5 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 17. "SVALID4,SCDATA4 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 15. "SVALID3,SCDATA3 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 13. "SVALID2,SCDATA2 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 11. "SVALID1,SCDATA1 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
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bitfld.long 0x00 9. "SVALID0,SCDATA0 validity indication" "0: SCD invalid,1: SCD valid The SVALIDx bit"
bitfld.long 0x00 7. "nERR,Transmission error (error at NER pin)" "0: error,1: no error It"
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bitfld.long 0x00 6. "nAGSERR,AGS error" "0: AGS(Automatic Get Sensor data) watchdog error,1: no AGS watchdog error An AGS watchdog error is"
bitfld.long 0x00 5. "nDELAYERR,Missing start bit during register communication" "0: delay error,1: no delay error"
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bitfld.long 0x00 4. "nSCDERR,Error in single cycle data transmission" "0: error in last single cycle data transmission,1: no error in last single cycle data transmission"
bitfld.long 0x00 3. "nREGERR,Error in register data transmission" "0: error in last register data transmission,1: no error in last register data transmission"
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bitfld.long 0x00 2. "REGEND,Register data transmission completed" "0: no valid register data available,1: register data transmission completed"
bitfld.long 0x00 1. "status0_reserved1,reserved" "0,1"
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bitfld.long 0x00 0. "EOT,Data transmission completed" "0: data transmission active,1: data transmission finished"
group.long 0xF4++0x03
line.long 0x00 "biss_ir,Instruction Register"
bitfld.long 0x00 15. "MAVO,Not selected MA line control level" "0: low definition of unselected(CHSEL) MA clock..,1: high definition of unselected(CHSEL) MA clock"
bitfld.long 0x00 14. "MAFO,Not selected MA line control selection" "0: controlling unselected(CHSEL) MA clock line,1: controlling unselected(CHSEL) MA clock line"
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bitfld.long 0x00 13. "MAVS,Selected MA line control level" "0: low definition of selected(CHSEL) MA clock..,1: high definition of selected(CHSEL) MA clock.."
bitfld.long 0x00 12. "MAFS,Selected MA line control selection" "0: controlling selected/CHSEL) MA clock line:..,1: controlling selected(CHSEL) MA clock line"
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bitfld.long 0x00 10.--11. "CFGIF,Configure physical interface" "0: TTL,1: CMOS,2: RS422,3: LVDS"
bitfld.long 0x00 9. "ENTEST,Enable test interface" "0: device in normal operation mode,1: device in test mode"
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bitfld.long 0x00 8. "CLKENI,Enable internal clock" "0: the master clock is generated by an external,1: the master clock is generated by the basic.."
bitfld.long 0x00 7. "BREAK,Data transmission interrupt" "0: no change,1: abort data transmission"
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bitfld.long 0x00 6. "HOLDBANK,RAM bank control" "0: no bank switching lock permitted,1: bank switching lock permitted During the.."
bitfld.long 0x00 5. "SWBANK,Switch RAM banks" "0: RAM banks are not switched,1: RAM banks are switched"
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bitfld.long 0x00 4. "INIT,Start INIT sequence" "0: no changes on the data channel,1: initialize data channel"
bitfld.long 0x00 1.--3. "INSTR,SCD control instruction 0b010 : CDM = 0 0b001 : CDM = 1 0b100 0b110: register communication condition: CDMTIMEOUT = 1 0b111 : register communication(reduced protocol) condition: CDMTIMEOUT = 1 The transmission of sensor data can be triggered via.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "AGS,AutoGetSens(Automatic Get Sensordata)" "0: no automatic data transmission,1: - start of data transmission after TIMEOUTSENS"
rgroup.long 0xF8++0x03
line.long 0x00 "biss_status1,Status Information"
bitfld.long 0x00 24. "SWBANKFAILS,Bank switching status" "0: bank switching(SCD) successful,1: bank switching(SCD) not successful"
bitfld.long 0x00 1. "CDS1,CDS bit of channel 1" "0: CDS = 0,1: CDS = 1"
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bitfld.long 0x00 0. "SL1,Current SL line level of channel 1" "0: SL line level low,1: SL line level high"
tree.end
tree "CAN_CTRL0_APP"
base ad:0xFF801900
group.long 0x00++0x03
line.long 0x00 "canctrl_mode,CAN mode register"
bitfld.long 0x00 3. "acceptance_mode,Acceptance Filter Mode 1 single the single acceptance filter option is enabled (one filter with the length of 32 bit is active) 0 dual the dual acceptance filter option is enabled (two filters each with the length of 16 bit are active)" "0,1"
bitfld.long 0x00 2. "selftest,Self Test Mode 1 self test in this mode a full node test is possible without any other active node on the bus using the self reception request command the CAN controller will perform a successful transmission even if there is no acknowledge.." "0,1"
bitfld.long 0x00 1. "listen_mode,Listen Only Mode 1 listen only in this mode the CAN controller would give no acknowledge to the CAN-bus even if a message is received successfully the error counters are stopped at the current value 0 normal" "0,1"
bitfld.long 0x00 0. "reset_mode,Reset Mode 1 reset detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode 0 normal on the `1-to-0' transition of the reset mode bit the CAN controller returns to the.." "0,1"
wgroup.long 0x04++0x03
line.long 0x00 "canctrl_command,CAN command register"
bitfld.long 0x00 4. "self_rx_request,Self Reception Request self-clearing 1 present a message shall be transmitted and received simultaneously Setting tx_request and self_rx_request simultaneously will ignore the set self_rx_request bit" "0,1"
bitfld.long 0x00 3. "clr_overrun,Clear Data Overrun self-clearing 1 clear the data overrun status bit is cleared shall be used together with release_rx_buf to release invalid buffer" "0,1"
bitfld.long 0x00 2. "release_rx_buf,Release Receive Buffer self-clearing 1 released the receive buffer representing the message memory space in the RXFIFO is released" "0,1"
bitfld.long 0x00 1. "abort_tx,Abort Transmission self-clearing 1 present if not already in progress a pending transmission request is cancelled Setting the command bits tx_request and abort_tx simultaneously results in sending the transmit message once" "0,1"
bitfld.long 0x00 0. "tx_request,Transmission Request self-clearing 1 present a message shall be transmitted" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "canctrl_status,CAN status register"
bitfld.long 0x00 7. "bus_status,Bus Status 1 bus-off the CAN controller is not involved in bus activities 0 bus-on the CAN controller is involved in bus activities" "0,1"
bitfld.long 0x00 6. "error_status,Error Status 1 error at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR) 0 ok both error counters are below the warning limit" "0,1"
bitfld.long 0x00 5. "tx_status,Transmit Status 1 transmit the CAN controller is transmitting a message 0 idle" "0,1"
bitfld.long 0x00 4. "rx_status,Receive Status 1 receive the CAN controller is receiving a message 0 idle" "0,1"
bitfld.long 0x00 3. "tx_complete,Transmission Complete 1 complete last requested transmission has been successfully completed 0 incomplete previously requested transmission is not yet completed" "0,1"
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bitfld.long 0x00 2. "tx_buf_status,Transmit Buffer Status 1 released the CPU may write a message into the transmit buffer 0 locked the CPU cannot access the transmit buffer a message is either waiting for transmission or is in the process of being transmitted" "0,1"
bitfld.long 0x00 1. "overrun,Data Overrun Status 1 overrun a message was lost because there was not enough space for that message in the RXFIFO 0 absent no data overrun has occurred since the last clear data overrun command was given" "0,1"
bitfld.long 0x00 0. "rx_buf_status,Receive Buffer Status 1 full one or more complete messages are available in the RXFIFO 0 empty no message is available" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "canctrl_irq,CAN interrupt register reading the register will clear all bits except rx_irq"
bitfld.long 0x00 7. "bus_error_irq,Bus Error Interrupt 1 set this bit is set when the CAN controller detects an error on the CAN-bus and the bus_error_irq_en bit is set within the interrupt enable register will only get active again if canctrl_err_code_capture register is.." "0,1"
bitfld.long 0x00 6. "arb_lost_irq,Arbitration Lost Interrupt 1 set this bit is set when the CAN controller lost the arbitration and becomes a receiver and the arb_lost_irq_en bit is set within the interrupt enable register will only get active again if.." "0,1"
bitfld.long 0x00 5. "err_passive_irq,Error Passive Interrupt 1 set this bit is set whenever the CAN controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the CAN controller is in the error passive status.." "0,1"
bitfld.long 0x00 3. "overrun_irq,Data Overrun Interrup 1 set this bit is set on a `0-to-1' transition of the data overrun status bit and the overrun_irq_en bit is set within the interrupt enable register 0 reset" "0,1"
bitfld.long 0x00 2. "warning_irq,Error Warning Interrupt 1 set this bit is set on every change (set and clear) of either the error status or bus status bits and the warning_irq_en bit is set within the interrupt enable register 0 reset" "0,1"
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bitfld.long 0x00 1. "tx_irq,Transmit Interrupt 1 set this bit is set whenever the transmit buffer status changes from `0-to-1' (released) and the tx_irq_en bit is set within the interrupt enable register 0 reset" "0,1"
bitfld.long 0x00 0. "rx_irq,Receive Interrupt 1 set this bit is set while the receive FIFO is not empty and the rx_irq_en bit is set within the interrupt enable register 0 reset no more message is available within the RXFIFO" "0,1"
group.long 0x10++0x03
line.long 0x00 "canctrl_irq_en,CAN interrupt enable register in not extended mode: acceptance_code_0"
bitfld.long 0x00 7. "bus_error_irq_en,Bus Error Interrupt Enable 1 enabled if an bus error has been detected the CAN controller requests the respective interrupt 0 disabled" "0,1"
bitfld.long 0x00 6. "arb_lost_irq_en,Arbitration Lost Interrupt Enable 1 enabled if the CAN controller has lost arbitration the respective interrupt is requested 0 disabled" "0,1"
bitfld.long 0x00 5. "err_passive_irq_en,Error Passive Interrupt Enable 1 enabled if the error status of the CAN controller changes from error active to error passive or vice versa the respective interrupt is requested 0 disabled" "0,1"
bitfld.long 0x00 3. "overrun_irq_en,Data Overrun Interrupt Enable 1 enabled if the data overrun status bit is set (see status register Table 14) the CAN controller requests the respective interrupt 0 disabled" "0,1"
bitfld.long 0x00 2. "warning_irq_en,Error Warning Interrupt Enable 1 enabled if the error or bus status change (see status register) the CAN controller requests the respective interrupt 0 disabled" "0,1"
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bitfld.long 0x00 1. "tx_irq_en,Transmit Interrupt Enable 1 enabled when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command) the CAN controller requests the respective interrupt 0 disabled" "0,1"
bitfld.long 0x00 0. "rx_irq_en,Receive Interrupt Enable 1 enabled when the receive buffer status is `full' the CAN controller requests the respective interrupt 0 disabled" "0,1"
group.long 0x14++0x03
line.long 0x00 "canctrl_not_extended_acceptance_mask0,CAN not extended acceptance mask register"
group.long 0x18++0x03
line.long 0x00 "canctrl_bus_timing0,CAN bus timing register 0 only writable in reset mode in not extended mode: acceptance_mask_0"
bitfld.long 0x00 9.--10. "sync_jump_width,Synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers any bus controller must re-synchronize on any relevant signal edge of the current transmission" "0,1,2,3"
hexmask.long.word 0x00 0.--8. 1. "prescaler,Baud Rate Prescaler The period of the CAN system clock tscl is programmable and determines the individual bit timing"
group.long 0x1C++0x03
line.long 0x00 "canctrl_bus_timing1,CAN bus timing register 1 only writable in reset mode"
bitfld.long 0x00 8.--12. "tseg2,Time Segment 2 (TSEG2) TSEG2 determine the number of clock cycles per bit period and the location of the sample point where: tTSEG2 = tscl * (tseg2 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "oversampling,Sampling 1 triple the bus is sampled three times recommended for low/medium speed buses (class A and B) where filtering spikes on the bus line is beneficial 0 single the bus is sampled once recommended for high speed buses (SAE class C)" "0,1"
bitfld.long 0x00 0.--5. "tseg1,Time Segment 1 (TSEG1) TSEG1 determine the number of clock cycles per bit period and the location of the sample point where: tSYNCSEG = 1 * tscl tTSEG1 = tscl * (tseg1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x28++0x03
line.long 0x00 "canctrl_not_extended_data0,CAN not extended data register"
rgroup.long 0x2C++0x03
line.long 0x00 "canctrl_arb_lost_capture,CAN arbitration lost capture register This register contains information about the bit position of losing arbitration"
bitfld.long 0x00 0.--4. "position,Positon where arbitration was lost { | Decimal value Position 00 arbitration lost in bit 1 of identifier 01 arbitration lost in bit 2 of identifier 02 arbitration lost in bit 3 of identifier 03 arbitration lost in bit 4 of identifier 04.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x30++0x03
line.long 0x00 "canctrl_err_code_capture,CAN error code capture register This register contains information about the type and location of errors on the bus"
bitfld.long 0x00 6.--7. "err_code,Error code { | Binary value Code 00 bit error 01 form error 10 stuff error 11 other type of error }" "0,1,2,3"
bitfld.long 0x00 5. "direction,Direction 1 RX error occurred during reception 0 TX error occurred during transmission" "0,1"
bitfld.long 0x00 0.--4. "segment,Frame segment where error was detected { | Binary value Segment 00011 start of frame 00010 ID.28 to ID.21 00110 ID.20 to ID.18 00100 bit SRTR 00101 bit IDE 00111 ID.17 to ID.13 01111 ID.12 to ID.5 01110 ID.4 to ID.0 01100 bit RTR 01101 reser ved.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "canctrl_err_warning_limit,CAN error warning limit register only writable in reset mode in not extended mode: data3"
hexmask.long.byte 0x00 0.--7. 1. "limit,error warning limit"
group.long 0x38++0x03
line.long 0x00 "canctrl_rx_error_cnt,CAN RX error counter register only writable in reset mode The RX error counter register reflects the current value of the receive error counter"
hexmask.long.byte 0x00 0.--7. 1. "rx_err,rx error counter"
group.long 0x3C++0x03
line.long 0x00 "canctrl_tx_error_cnt,CAN TX error counter register only writable in reset mode The TX error counter register reflects the current value of the transmit error counter"
hexmask.long.byte 0x00 0.--7. 1. "tx_err,tx error counter"
group.long 0x40++0x03
line.long 0x00 "canctrl_data0,CAN data register 0 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x44++0x03
line.long 0x00 "canctrl_data1,CAN data register 1 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x48++0x03
line.long 0x00 "canctrl_data2,CAN data register 2 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x4C++0x03
line.long 0x00 "canctrl_data3,CAN data register 3 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x50++0x03
line.long 0x00 "canctrl_data4,CAN data register 4 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x54++0x03
line.long 0x00 "canctrl_data5,CAN data register 5 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x58++0x03
line.long 0x00 "canctrl_data6,CAN data register 6 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x5C++0x03
line.long 0x00 "canctrl_data7,CAN data register 7 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x60++0x03
line.long 0x00 "canctrl_data8,CAN data register 8 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x64++0x03
line.long 0x00 "canctrl_data9,CAN data register 9 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x68++0x03
line.long 0x00 "canctrl_data10,CAN data register 10 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x6C++0x03
line.long 0x00 "canctrl_data11,CAN data register 11 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x70++0x03
line.long 0x00 "canctrl_data12,CAN data register 12 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
rgroup.long 0x74++0x03
line.long 0x00 "canctrl_rx_message_cnt,CAN RX message counter register Reflects the number of messages available within the RXFIFO"
hexmask.long.byte 0x00 0.--6. 1. "rx_msg_cnt,rx message counter"
rgroup.long 0x7C++0x03
line.long 0x00 "canctrl_mode_control,CAN mode control register only writable in reset mode"
bitfld.long 0x00 7. "mode," "0,1"
tree.end
tree "CAN_CTRL1_APP"
base ad:0xFF801980
group.long 0x00++0x03
line.long 0x00 "canctrl_mode,CAN mode register"
bitfld.long 0x00 3. "acceptance_mode,Acceptance Filter Mode 1 single the single acceptance filter option is enabled (one filter with the length of 32 bit is active) 0 dual the dual acceptance filter option is enabled (two filters each with the length of 16 bit are active)" "0,1"
bitfld.long 0x00 2. "selftest,Self Test Mode 1 self test in this mode a full node test is possible without any other active node on the bus using the self reception request command the CAN controller will perform a successful transmission even if there is no acknowledge.." "0,1"
bitfld.long 0x00 1. "listen_mode,Listen Only Mode 1 listen only in this mode the CAN controller would give no acknowledge to the CAN-bus even if a message is received successfully the error counters are stopped at the current value 0 normal" "0,1"
bitfld.long 0x00 0. "reset_mode,Reset Mode 1 reset detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode 0 normal on the `1-to-0' transition of the reset mode bit the CAN controller returns to the.." "0,1"
wgroup.long 0x04++0x03
line.long 0x00 "canctrl_command,CAN command register"
bitfld.long 0x00 4. "self_rx_request,Self Reception Request self-clearing 1 present a message shall be transmitted and received simultaneously Setting tx_request and self_rx_request simultaneously will ignore the set self_rx_request bit" "0,1"
bitfld.long 0x00 3. "clr_overrun,Clear Data Overrun self-clearing 1 clear the data overrun status bit is cleared shall be used together with release_rx_buf to release invalid buffer" "0,1"
bitfld.long 0x00 2. "release_rx_buf,Release Receive Buffer self-clearing 1 released the receive buffer representing the message memory space in the RXFIFO is released" "0,1"
bitfld.long 0x00 1. "abort_tx,Abort Transmission self-clearing 1 present if not already in progress a pending transmission request is cancelled Setting the command bits tx_request and abort_tx simultaneously results in sending the transmit message once" "0,1"
bitfld.long 0x00 0. "tx_request,Transmission Request self-clearing 1 present a message shall be transmitted" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "canctrl_status,CAN status register"
bitfld.long 0x00 7. "bus_status,Bus Status 1 bus-off the CAN controller is not involved in bus activities 0 bus-on the CAN controller is involved in bus activities" "0,1"
bitfld.long 0x00 6. "error_status,Error Status 1 error at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR) 0 ok both error counters are below the warning limit" "0,1"
bitfld.long 0x00 5. "tx_status,Transmit Status 1 transmit the CAN controller is transmitting a message 0 idle" "0,1"
bitfld.long 0x00 4. "rx_status,Receive Status 1 receive the CAN controller is receiving a message 0 idle" "0,1"
bitfld.long 0x00 3. "tx_complete,Transmission Complete 1 complete last requested transmission has been successfully completed 0 incomplete previously requested transmission is not yet completed" "0,1"
newline
bitfld.long 0x00 2. "tx_buf_status,Transmit Buffer Status 1 released the CPU may write a message into the transmit buffer 0 locked the CPU cannot access the transmit buffer a message is either waiting for transmission or is in the process of being transmitted" "0,1"
bitfld.long 0x00 1. "overrun,Data Overrun Status 1 overrun a message was lost because there was not enough space for that message in the RXFIFO 0 absent no data overrun has occurred since the last clear data overrun command was given" "0,1"
bitfld.long 0x00 0. "rx_buf_status,Receive Buffer Status 1 full one or more complete messages are available in the RXFIFO 0 empty no message is available" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "canctrl_irq,CAN interrupt register reading the register will clear all bits except rx_irq"
bitfld.long 0x00 7. "bus_error_irq,Bus Error Interrupt 1 set this bit is set when the CAN controller detects an error on the CAN-bus and the bus_error_irq_en bit is set within the interrupt enable register will only get active again if canctrl_err_code_capture register is.." "0,1"
bitfld.long 0x00 6. "arb_lost_irq,Arbitration Lost Interrupt 1 set this bit is set when the CAN controller lost the arbitration and becomes a receiver and the arb_lost_irq_en bit is set within the interrupt enable register will only get active again if.." "0,1"
bitfld.long 0x00 5. "err_passive_irq,Error Passive Interrupt 1 set this bit is set whenever the CAN controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the CAN controller is in the error passive status.." "0,1"
bitfld.long 0x00 3. "overrun_irq,Data Overrun Interrup 1 set this bit is set on a `0-to-1' transition of the data overrun status bit and the overrun_irq_en bit is set within the interrupt enable register 0 reset" "0,1"
bitfld.long 0x00 2. "warning_irq,Error Warning Interrupt 1 set this bit is set on every change (set and clear) of either the error status or bus status bits and the warning_irq_en bit is set within the interrupt enable register 0 reset" "0,1"
newline
bitfld.long 0x00 1. "tx_irq,Transmit Interrupt 1 set this bit is set whenever the transmit buffer status changes from `0-to-1' (released) and the tx_irq_en bit is set within the interrupt enable register 0 reset" "0,1"
bitfld.long 0x00 0. "rx_irq,Receive Interrupt 1 set this bit is set while the receive FIFO is not empty and the rx_irq_en bit is set within the interrupt enable register 0 reset no more message is available within the RXFIFO" "0,1"
group.long 0x10++0x03
line.long 0x00 "canctrl_irq_en,CAN interrupt enable register in not extended mode: acceptance_code_0"
bitfld.long 0x00 7. "bus_error_irq_en,Bus Error Interrupt Enable 1 enabled if an bus error has been detected the CAN controller requests the respective interrupt 0 disabled" "0,1"
bitfld.long 0x00 6. "arb_lost_irq_en,Arbitration Lost Interrupt Enable 1 enabled if the CAN controller has lost arbitration the respective interrupt is requested 0 disabled" "0,1"
bitfld.long 0x00 5. "err_passive_irq_en,Error Passive Interrupt Enable 1 enabled if the error status of the CAN controller changes from error active to error passive or vice versa the respective interrupt is requested 0 disabled" "0,1"
bitfld.long 0x00 3. "overrun_irq_en,Data Overrun Interrupt Enable 1 enabled if the data overrun status bit is set (see status register Table 14) the CAN controller requests the respective interrupt 0 disabled" "0,1"
bitfld.long 0x00 2. "warning_irq_en,Error Warning Interrupt Enable 1 enabled if the error or bus status change (see status register) the CAN controller requests the respective interrupt 0 disabled" "0,1"
newline
bitfld.long 0x00 1. "tx_irq_en,Transmit Interrupt Enable 1 enabled when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command) the CAN controller requests the respective interrupt 0 disabled" "0,1"
bitfld.long 0x00 0. "rx_irq_en,Receive Interrupt Enable 1 enabled when the receive buffer status is `full' the CAN controller requests the respective interrupt 0 disabled" "0,1"
group.long 0x14++0x03
line.long 0x00 "canctrl_not_extended_acceptance_mask0,CAN not extended acceptance mask register"
group.long 0x18++0x03
line.long 0x00 "canctrl_bus_timing0,CAN bus timing register 0 only writable in reset mode in not extended mode: acceptance_mask_0"
bitfld.long 0x00 9.--10. "sync_jump_width,Synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers any bus controller must re-synchronize on any relevant signal edge of the current transmission" "0,1,2,3"
hexmask.long.word 0x00 0.--8. 1. "prescaler,Baud Rate Prescaler The period of the CAN system clock tscl is programmable and determines the individual bit timing"
group.long 0x1C++0x03
line.long 0x00 "canctrl_bus_timing1,CAN bus timing register 1 only writable in reset mode"
bitfld.long 0x00 8.--12. "tseg2,Time Segment 2 (TSEG2) TSEG2 determine the number of clock cycles per bit period and the location of the sample point where: tTSEG2 = tscl * (tseg2 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "oversampling,Sampling 1 triple the bus is sampled three times recommended for low/medium speed buses (class A and B) where filtering spikes on the bus line is beneficial 0 single the bus is sampled once recommended for high speed buses (SAE class C)" "0,1"
bitfld.long 0x00 0.--5. "tseg1,Time Segment 1 (TSEG1) TSEG1 determine the number of clock cycles per bit period and the location of the sample point where: tSYNCSEG = 1 * tscl tTSEG1 = tscl * (tseg1 + 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x28++0x03
line.long 0x00 "canctrl_not_extended_data0,CAN not extended data register"
rgroup.long 0x2C++0x03
line.long 0x00 "canctrl_arb_lost_capture,CAN arbitration lost capture register This register contains information about the bit position of losing arbitration"
bitfld.long 0x00 0.--4. "position,Positon where arbitration was lost { | Decimal value Position 00 arbitration lost in bit 1 of identifier 01 arbitration lost in bit 2 of identifier 02 arbitration lost in bit 3 of identifier 03 arbitration lost in bit 4 of identifier 04.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x30++0x03
line.long 0x00 "canctrl_err_code_capture,CAN error code capture register This register contains information about the type and location of errors on the bus"
bitfld.long 0x00 6.--7. "err_code,Error code { | Binary value Code 00 bit error 01 form error 10 stuff error 11 other type of error }" "0,1,2,3"
bitfld.long 0x00 5. "direction,Direction 1 RX error occurred during reception 0 TX error occurred during transmission" "0,1"
bitfld.long 0x00 0.--4. "segment,Frame segment where error was detected { | Binary value Segment 00011 start of frame 00010 ID.28 to ID.21 00110 ID.20 to ID.18 00100 bit SRTR 00101 bit IDE 00111 ID.17 to ID.13 01111 ID.12 to ID.5 01110 ID.4 to ID.0 01100 bit RTR 01101 reser ved.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "canctrl_err_warning_limit,CAN error warning limit register only writable in reset mode in not extended mode: data3"
hexmask.long.byte 0x00 0.--7. 1. "limit,error warning limit"
group.long 0x38++0x03
line.long 0x00 "canctrl_rx_error_cnt,CAN RX error counter register only writable in reset mode The RX error counter register reflects the current value of the receive error counter"
hexmask.long.byte 0x00 0.--7. 1. "rx_err,rx error counter"
group.long 0x3C++0x03
line.long 0x00 "canctrl_tx_error_cnt,CAN TX error counter register only writable in reset mode The TX error counter register reflects the current value of the transmit error counter"
hexmask.long.byte 0x00 0.--7. 1. "tx_err,tx error counter"
group.long 0x40++0x03
line.long 0x00 "canctrl_data0,CAN data register 0 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x44++0x03
line.long 0x00 "canctrl_data1,CAN data register 1 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x48++0x03
line.long 0x00 "canctrl_data2,CAN data register 2 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x4C++0x03
line.long 0x00 "canctrl_data3,CAN data register 3 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance code)"
group.long 0x50++0x03
line.long 0x00 "canctrl_data4,CAN data register 4 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x54++0x03
line.long 0x00 "canctrl_data5,CAN data register 5 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x58++0x03
line.long 0x00 "canctrl_data6,CAN data register 6 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x5C++0x03
line.long 0x00 "canctrl_data7,CAN data register 7 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data tx data or acceptance mask)"
group.long 0x60++0x03
line.long 0x00 "canctrl_data8,CAN data register 8 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x64++0x03
line.long 0x00 "canctrl_data9,CAN data register 9 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x68++0x03
line.long 0x00 "canctrl_data10,CAN data register 10 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x6C++0x03
line.long 0x00 "canctrl_data11,CAN data register 11 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
group.long 0x70++0x03
line.long 0x00 "canctrl_data12,CAN data register 12 This register has multiple functions depending on reset mode and read or write access"
hexmask.long.byte 0x00 0.--7. 1. "data,register content (rx data or tx data)"
rgroup.long 0x74++0x03
line.long 0x00 "canctrl_rx_message_cnt,CAN RX message counter register Reflects the number of messages available within the RXFIFO"
hexmask.long.byte 0x00 0.--6. 1. "rx_msg_cnt,rx message counter"
rgroup.long 0x7C++0x03
line.long 0x00 "canctrl_mode_control,CAN mode control register only writable in reset mode"
bitfld.long 0x00 7. "mode," "0,1"
tree.end
tree "CM4_MISC_CTRL"
base ad:0xE0043000
rgroup.long 0x00++0x03
line.long 0x00 "cm4_misc_ctrl_cpu_info,CPU information register Provides a processor identification mechanism to distinguish between Com ARM and App ARM"
bitfld.long 0x00 1. "fpu,CPU has FPU If '0' all cm4_misc_ctrl_fpu_* registers have no effect and are read as zero" "0,1"
bitfld.long 0x00 0. "id,CPU identification" "0: Com ARM,1: App ARM"
group.long 0x04++0x03
line.long 0x00 "cm4_misc_ctrl_fpu_irq_raw,FPU raw IRQ Read access shows status of unmasked IRQs"
bitfld.long 0x00 5. "idc,Input denormal (ARM-specific exception)" "0,1"
bitfld.long 0x00 4. "ioc,Invalid operation (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 3. "dzc,Division by zero (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 2. "ofc,Overflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 1. "ufc,Underflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 0. "ixc,Inexact (IEEE 754-2008 defined exception)" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "cm4_misc_ctrl_fpu_irq_masked,FPU masked IRQ Shows status of masked IRQs"
bitfld.long 0x00 5. "idc,Input denormal (ARM-specific exception)" "0,1"
bitfld.long 0x00 4. "ioc,Invalid operation (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 3. "dzc,Division by zero (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 2. "ofc,Overflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 1. "ufc,Underflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 0. "ixc,Inexact (IEEE 754-2008 defined exception)" "0,1"
group.long 0x0C++0x03
line.long 0x00 "cm4_misc_ctrl_fpu_irq_msk_set,FPU IRQ mask set The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 5. "idc,Input denormal (ARM-specific exception)" "0,1"
bitfld.long 0x00 4. "ioc,Invalid operation (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 3. "dzc,Division by zero (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 2. "ofc,Overflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 1. "ufc,Underflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 0. "ixc,Inexact (IEEE 754-2008 defined exception)" "0,1"
group.long 0x10++0x03
line.long 0x00 "cm4_misc_ctrl_fpu_irq_msk_reset,FPU IRQ mask reset This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 5. "idc,Input denormal (ARM-specific exception)" "0,1"
bitfld.long 0x00 4. "ioc,Invalid operation (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 3. "dzc,Division by zero (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 2. "ofc,Overflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 1. "ufc,Underflow (IEEE 754-2008 defined exception)" "0,1"
bitfld.long 0x00 0. "ixc,Inexact (IEEE 754-2008 defined exception)" "0,1"
tree.end
tree "CM4_SCS"
base ad:0xE000E000
group.long 0x08++0x03
line.long 0x00 "cm4_scs_actlr,Auxiliary control register"
group.long 0x10++0x03
line.long 0x00 "cm4_scs_stcsr,SysTick control and status register"
group.long 0x14++0x03
line.long 0x00 "cm4_scs_strvr,SysTick Reload Value register"
group.long 0x18++0x03
line.long 0x00 "cm4_scs_stcvr,SysTick current value register"
rgroup.long 0x1C++0x03
line.long 0x00 "cm4_scs_stcr,SysTick calibration value register"
group.long 0x100++0x03
line.long 0x00 "cm4_scs_nvic_iser0,Interrupt set-enable register 0 Enables or reads the enable state of a group of interrupts"
hexmask.long 0x00 0.--31. 1. "setena,For register cm4_scs_nvic_iser[n] enables or shows the current enabled state of interrupt (m+(32*n))"
group.long 0x104++0x03
line.long 0x00 "cm4_scs_nvic_iser1,Interrupt set-enable register 1 Enables or reads the enable state of a group of interrupts"
hexmask.long 0x00 0.--31. 1. "setena,For register cm4_scs_nvic_iser[n] enables or shows the current enabled state of interrupt (m+(32*n))"
group.long 0x108++0x03
line.long 0x00 "cm4_scs_nvic_iser2,Interrupt set-enable register 2 Enables or reads the enable state of a group of interrupts"
hexmask.long 0x00 0.--31. 1. "setena,For register cm4_scs_nvic_iser[n] enables or shows the current enabled state of interrupt (m+(32*n))"
group.long 0x180++0x03
line.long 0x00 "cm4_scs_nvic_icer0,Interrupt clear-enable register 0 Disables or reads the enable state of a group of interrupts"
hexmask.long 0x00 0.--31. 1. "clrena,For register cm4_scs_nvic_icer[n] disables or shows the current enabled state of interrupt (m+(32*n))"
group.long 0x184++0x03
line.long 0x00 "cm4_scs_nvic_icer1,Interrupt clear-enable register 1 Disables or reads the enable state of a group of interrupts"
hexmask.long 0x00 0.--31. 1. "clrena,For register cm4_scs_nvic_icer[n] disables or shows the current enabled state of interrupt (m+(32*n))"
group.long 0x188++0x03
line.long 0x00 "cm4_scs_nvic_icer2,Interrupt clear-enable register 2 Disables or reads the enable state of a group of interrupts"
hexmask.long 0x00 0.--31. 1. "clrena,For register cm4_scs_nvic_icer[n] disables or shows the current enabled state of interrupt (m+(32*n))"
group.long 0x200++0x03
line.long 0x00 "cm4_scs_nvic_ispr0,Interrupt set-pending register 0 For a group of interrupts changes interrupt status to pending or shows the current pending status"
hexmask.long 0x00 0.--31. 1. "setpend,For register cm4_scs_nvic_ispr[n] changes the state of interrupt (m+(32*n)) to pending or shows whether the state of the interrupt is pending"
group.long 0x204++0x03
line.long 0x00 "cm4_scs_nvic_ispr1,Interrupt set-pending register 1 For a group of interrupts changes interrupt status to pending or shows the current pending status"
hexmask.long 0x00 0.--31. 1. "setpend,For register cm4_scs_nvic_ispr[n] changes the state of interrupt (m+(32*n)) to pending or shows whether the state of the interrupt is pending"
group.long 0x208++0x03
line.long 0x00 "cm4_scs_nvic_ispr2,Interrupt set-pending register 2 For a group of interrupts changes interrupt status to pending or shows the current pending status"
hexmask.long 0x00 0.--31. 1. "setpend,For register cm4_scs_nvic_ispr[n] changes the state of interrupt (m+(32*n)) to pending or shows whether the state of the interrupt is pending"
group.long 0x280++0x03
line.long 0x00 "cm4_scs_nvic_icpr0,Interrupt clear-pending register 0 For a group of interrupts clears the interrupt pending status or shows the current pending status"
hexmask.long 0x00 0.--31. 1. "clrpend,For register cm4_scs_nvic_ispr[n] clears the pending state of interrupt (m+(32*n)) or shows whether the state of the interrupt is pending"
group.long 0x284++0x03
line.long 0x00 "cm4_scs_nvic_icpr1,Interrupt clear-pending register 1 For a group of interrupts clears the interrupt pending status or shows the current pending status"
hexmask.long 0x00 0.--31. 1. "clrpend,For register cm4_scs_nvic_ispr[n] clears the pending state of interrupt (m+(32*n)) or shows whether the state of the interrupt is pending"
group.long 0x288++0x03
line.long 0x00 "cm4_scs_nvic_icpr2,Interrupt clear-pending register 2 For a group of interrupts clears the interrupt pending status or shows the current pending status"
hexmask.long 0x00 0.--31. 1. "clrpend,For register cm4_scs_nvic_ispr[n] clears the pending state of interrupt (m+(32*n)) or shows whether the state of the interrupt is pending"
rgroup.long 0x300++0x03
line.long 0x00 "cm4_scs_nvic_iabr0,Interrupt active bit register 0 For a group of 32 interrupts shows whether each interrupt is active"
hexmask.long 0x00 0.--31. 1. "active,For register cm4_scs_nvic_iabr[n] shows whether interrupt (m+(32*n)) is active"
rgroup.long 0x304++0x03
line.long 0x00 "cm4_scs_nvic_iabr1,Interrupt active bit register 1 For a group of 32 interrupts shows whether each interrupt is active"
hexmask.long 0x00 0.--31. 1. "active,For register cm4_scs_nvic_iabr[n] shows whether interrupt (m+(32*n)) is active"
rgroup.long 0x308++0x03
line.long 0x00 "cm4_scs_nvic_iabr2,Interrupt active bit register 2 For a group of 32 interrupts shows whether each interrupt is active"
hexmask.long 0x00 0.--31. 1. "active,For register cm4_scs_nvic_iabr[n] shows whether interrupt (m+(32*n)) is active"
group.long 0x400++0x03
line.long 0x00 "cm4_scs_nvic_ipr0,Interrupt priority register 0 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x404++0x03
line.long 0x00 "cm4_scs_nvic_ipr1,Interrupt priority register 1 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x408++0x03
line.long 0x00 "cm4_scs_nvic_ipr2,Interrupt priority register 2 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x40C++0x03
line.long 0x00 "cm4_scs_nvic_ipr3,Interrupt priority register 3 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x410++0x03
line.long 0x00 "cm4_scs_nvic_ipr4,Interrupt priority register 4 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x414++0x03
line.long 0x00 "cm4_scs_nvic_ipr5,Interrupt priority register 5 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x418++0x03
line.long 0x00 "cm4_scs_nvic_ipr6,Interrupt priority register 6 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x41C++0x03
line.long 0x00 "cm4_scs_nvic_ipr7,Interrupt priority register 7 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x420++0x03
line.long 0x00 "cm4_scs_nvic_ipr8,Interrupt priority register 8 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x424++0x03
line.long 0x00 "cm4_scs_nvic_ipr9,Interrupt priority register 9 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x428++0x03
line.long 0x00 "cm4_scs_nvic_ipr10,Interrupt priority register 10 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x42C++0x03
line.long 0x00 "cm4_scs_nvic_ipr11,Interrupt priority register 11 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x430++0x03
line.long 0x00 "cm4_scs_nvic_ipr12,Interrupt priority register 12 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x434++0x03
line.long 0x00 "cm4_scs_nvic_ipr13,Interrupt priority register 13 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x438++0x03
line.long 0x00 "cm4_scs_nvic_ipr14,Interrupt priority register 14 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x43C++0x03
line.long 0x00 "cm4_scs_nvic_ipr15,Interrupt priority register 15 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
group.long 0x440++0x03
line.long 0x00 "cm4_scs_nvic_ipr16,Interrupt priority register 16 Sets or reads interrupt priorities"
hexmask.long.byte 0x00 24.--31. 1. "pri_n3,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+3"
hexmask.long.byte 0x00 16.--23. 1. "pri_n2,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+2"
newline
hexmask.long.byte 0x00 8.--15. 1. "pri_n1,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n+1"
hexmask.long.byte 0x00 0.--7. 1. "pri_n0,For register cm4_scs_nvic_ipr[n] priority of interrupt number 4n"
rgroup.long 0xD00++0x03
line.long 0x00 "cm4_scs_cpuid,CPUID base register"
group.long 0xD04++0x03
line.long 0x00 "cm4_scs_icsr,Interrupt control and state register"
group.long 0xD08++0x03
line.long 0x00 "cm4_scs_vtor,Vector table offset register Holds the vector table address"
hexmask.long 0x00 7.--31. 1. "tbloff,Bits[31:7] of the vector table address"
group.long 0xD0C++0x03
line.long 0x00 "cm4_scs_aircr,Application interrupt and reset control reister Sets or returns interrupt control data"
hexmask.long.word 0x00 16.--31. 1. "vectkey,Vector Key"
bitfld.long 0x00 15. "endianness,Indicates the memory system endianness" "0: Little endian,1: Big endian"
newline
bitfld.long 0x00 8.--10. "prigroup,Priority grouping indicates the binary point position" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "sysresetreq,System Reset Request" "0,1"
newline
bitfld.long 0x00 1. "vectclractive,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "0,1"
bitfld.long 0x00 0. "vectreset,Writing 1 to this bit causes a local system reset" "0,1"
group.long 0xD10++0x03
line.long 0x00 "cm4_scs_scr,System control Register"
group.long 0xD14++0x03
line.long 0x00 "cm4_scs_ccr,Configuration and control Register"
repeat 3. (strings "1" "2" "3" )(list 0x00 0x04 0x08 )
group.long ($2+0xD18)++0x03
line.long 0x00 "cm4_scs_shpr$1,System Handler Priority Register $1"
repeat.end
group.long 0xD24++0x03
line.long 0x00 "cm4_scs_shcsr,System Handler Control and State Register"
group.long 0xD28++0x03
line.long 0x00 "cm4_scs_cfsr,Configurable Fault Status Register Contains the three Configurable Fault Status Registers"
bitfld.long 0x00 25. "ufsr_divbyzero,Divide by zero error has occurred" "0,1"
bitfld.long 0x00 24. "ufsr_unaligned,Unaligned access error has occurred" "0,1"
newline
bitfld.long 0x00 19. "ufsr_nocp,A coprocessor access error has occurred" "0,1"
bitfld.long 0x00 18. "ufsr_invpc,An integrity check error has occurred on EXC_RETURN" "0,1"
newline
bitfld.long 0x00 17. "ufsr_invstate,Instruction executed with invalid EPSR.T or EPSR.IT field" "0,1"
bitfld.long 0x00 16. "ufsr_undefinstr,The processor has attempted to execute an undefined instruction" "0,1"
newline
bitfld.long 0x00 15. "bfsr_bfarvalid,BFAR has valid contents" "0,1"
bitfld.long 0x00 13. "bfsr_lsperr,A bus fault occurred during FP lazy state preservation" "0,1"
newline
bitfld.long 0x00 12. "bfsr_stkerr,A derived bus fault has occurred on exception entry" "0,1"
bitfld.long 0x00 11. "bfsr_unstkerr,A derived bus fault has occurred on exception return" "0,1"
newline
bitfld.long 0x00 10. "bfsr_impreciserr,Imprecise data access error has occurred" "0,1"
bitfld.long 0x00 9. "bfsr_preciserr,A precise data access error has occurred and the processor has written the faulting address to the BFAR" "0,1"
newline
bitfld.long 0x00 8. "bfsr_ibuserr,A bus fault on an instruction prefetch has occurred" "0,1"
bitfld.long 0x00 7. "mmfsr_mmarvalid,MMFAR has valid contents" "0,1"
newline
bitfld.long 0x00 5. "mmfsr_lsperr,A MemManage fault occurred during FP lazy state preservation" "0,1"
bitfld.long 0x00 4. "mmfsr_mstkerr,A derived MemManage fault occurred on exception entry" "0,1"
newline
bitfld.long 0x00 3. "mmfsr_munstkerr,A derived MemManage fault occurred on exception return" "0,1"
bitfld.long 0x00 1. "mmfsr_daccviol,Data access violation" "0,1"
newline
bitfld.long 0x00 0. "mmfsr_iaccviol,MPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred" "0,1"
group.long 0xD2C++0x03
line.long 0x00 "cm4_scs_hfsr,HardFault Status Register"
group.long 0xD30++0x03
line.long 0x00 "cm4_scs_dfsr,Debug fault status Register Shows which debug event occurred"
bitfld.long 0x00 4. "external,Indicates a debug event generated because of the assertion of an external debug request" "0,1"
bitfld.long 0x00 3. "vcatch,Indicates triggering of a Vector catch" "0,1"
newline
bitfld.long 0x00 2. "dwttrap,Indicates a debug event generated by the DWT" "0,1"
bitfld.long 0x00 1. "bkpt,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "0,1"
newline
bitfld.long 0x00 0. "halted,Indicates a debug event generated by either: - A C_HALT or C_STEP request triggered by a write to the DHCSR" "0,1"
group.long 0xD34++0x03
line.long 0x00 "cm4_scs_mmfar,MemManage Faul Address Register"
group.long 0xD38++0x03
line.long 0x00 "cm4_scs_bfar,BusFault Address Register"
group.long 0xD3C++0x03
line.long 0x00 "cm4_scs_afsr,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "cm4_scs_cpacr,Coprocessor Access Control Register"
group.long 0xDF0++0x03
line.long 0x00 "cm4_scs_dhcsr,Debug halting control and status register Controls halting debug"
bitfld.long 0x00 25. "s_reset_st,Indicates whether the processor has been reset since the last read of DHCSR" "0,1"
bitfld.long 0x00 24. "s_retire_st,Set to 1 every time the processor retires one or more instructions" "0,1"
newline
bitfld.long 0x00 19. "s_lockup,Indicates whether the processor is locked up because of an unrecoverable exception" "0,1"
bitfld.long 0x00 18. "s_sleep,Indicates whether the processor is sleeping" "0,1"
newline
bitfld.long 0x00 17. "s_halt,Indicates whether the processor is in Debug state" "0,1"
bitfld.long 0x00 16. "s_regrdy,A handshake flag for transfers through the DCRDR: - Writing to DCRSR clears the bit to 0" "0,1"
newline
bitfld.long 0x00 5. "c_snapstall,Allow imprecise entry to Debug state" "0: No action,1: Allow imprecise entry to Debug"
bitfld.long 0x00 3. "c_maskints,When debug is enabled the debugger can write to this bit to mask PendSV SysTick and external configurable interrupts" "0: Do not mask,1: Mask PendSV SysTick and external"
newline
bitfld.long 0x00 2. "c_step,Processor step bit" "0: No effect,1: Single step enabled"
bitfld.long 0x00 1. "c_halt,Processor halt bit" "0: Causes the processor to leave Debug state if in,1: Halt the processor"
newline
bitfld.long 0x00 0. "c_debugen,Halting debug enable bit" "0,1"
wgroup.long 0xDF4++0x03
line.long 0x00 "cm4_scs_dcrsr,Debug core register selector register With the DCRDR the DCRSR provides debug access to the ARM core registers special-purpose registers and Floating-point extension registers"
bitfld.long 0x00 16. "regwnr,Specifies the access type for the transfer" "0: ,1: "
hexmask.long.byte 0x00 0.--6. 1. "regsel,Specifies the ARM core register special-purpose register or Floating-point extension register to transfer: { | 0 - 12 ARM core registers R0-R12. 13 The current SP. See also values 17 (MSP) and 18 (PSP). 14 LR. 15 DebugReturnAddress. 16 xPSR. 17.."
group.long 0xDF8++0x03
line.long 0x00 "cm4_scs_dcrdr,Debug core register data register With the DCRSR the DCRDR provides debug access to the ARM core registers special-purpose registers and Floating-point extension registers"
hexmask.long 0x00 0.--31. 1. "dbgtmp,Data temporary cache for reading and writing the ARM core registers special-purpose registers and Floating-point extension registers"
group.long 0xDFC++0x03
line.long 0x00 "cm4_scs_demcr,Debug exception and monitor control register Manages vector catch behavior and DebugMonitor handling when debugging"
bitfld.long 0x00 24. "trcena,Global enable for all DWT and ITM features" "0: - DWT registers return UNKNOWN values on reads,1: DWT and ITM units enabled"
bitfld.long 0x00 19. "mon_req,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 18. "mon_step,When MON_EN is set to 0 this feature is disabled and the processor ignores MON_STEP" "0: Do not step the processor,1: Step the processor"
bitfld.long 0x00 17. "mon_pend,Sets or clears the pending state of the DebugMonitor exception" "0: Clear the status of the DebugMonitor exception,1: Set the status of the DebugMonitor exception to"
newline
bitfld.long 0x00 16. "mon_en,Enable the DebugMonitor exception" "0,1"
bitfld.long 0x00 10. "vc_harderr,Enable halting debug trap on a HardFault exception" "0,1"
newline
bitfld.long 0x00 9. "vc_interr,Enable halting debug trap on a fault occurring during exception entry or exception return" "0,1"
bitfld.long 0x00 8. "vc_buserr,Enable halting debug trap on a BusFault exception" "0,1"
newline
bitfld.long 0x00 7. "vc_staterr,Enable halting debug trap on a UsageFault exception caused by a state information error for example an Undefined Instruction exception" "0,1"
bitfld.long 0x00 6. "vc_chkerr,Enable halting debug trap on a UsageFault exception caused by a checking error for example an alignment check error" "0,1"
newline
bitfld.long 0x00 5. "vc_nocperr,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "0,1"
bitfld.long 0x00 4. "vc_mmerr,Enable halting debug trap on a MemManage exception" "0,1"
newline
bitfld.long 0x00 0. "vc_corereset,Enable Reset Vector Catch" "0,1"
repeat 5. (strings "4" "0" "1" "2" "3" )(list 0x00 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0xFD0)++0x03
line.long 0x00 "cm4_scs_pidr$1,Peripheral ID Register $1"
repeat.end
rgroup.long 0xFF0++0x03
line.long 0x00 "cm4_scs_cidr0,Component ID Register 0"
hexmask.long.byte 0x00 0.--7. 1. "prmbl_0,Preamble byte 0"
rgroup.long 0xFF4++0x03
line.long 0x00 "cm4_scs_cidr1,Component ID Register 1"
bitfld.long 0x00 4.--7. "class,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "prmbl_1,Preamble bits[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFF8++0x03
line.long 0x00 "cm4_scs_cidr2,Component ID Register 2"
hexmask.long.byte 0x00 0.--7. 1. "prmbl_2,Preamble byte 2"
rgroup.long 0xFFC++0x03
line.long 0x00 "cm4_scs_cidr3,Component ID Register 3"
hexmask.long.byte 0x00 0.--7. 1. "prmbl_3,Preamble byte 3"
tree.end
tree "DMAC_APP_CH"
repeat 3. (list 0. 1. 2.) (list ad:0xFF800100 ad:0xFF800120 ad:0xFF800140)
tree "DMAC_APP_CH$1"
base $2
group.long 0x00++0x03
line.long 0x00 "dmac_chsrc_ad,channel source address registers"
hexmask.long 0x00 0.--31. 1. "DMACCHSRCADDR,DMA source address"
group.long 0x04++0x03
line.long 0x00 "dmac_chdest_ad,channel destination address registers"
hexmask.long 0x00 0.--31. 1. "DMACCHDESTADDR,DMA destination address"
group.long 0x08++0x03
line.long 0x00 "dmac_chlink,channel linked list item register"
hexmask.long 0x00 2.--31. 1. "LLIADDR,Linked list item"
group.long 0x0C++0x03
line.long 0x00 "dmac_chctrl,channel control registers"
bitfld.long 0x00 31. "I,Terminal count interrupt enable bit" "0,1"
bitfld.long 0x00 28.--30. "Prot,Protection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 27. "DI,Destination increment" "0,1"
bitfld.long 0x00 26. "SI,Source increment" "0,1"
newline
bitfld.long 0x00 24. "ARM_EQ,Set equal behaviour to arm implementation This bit should always be set to 1 (default of 0 is from historical reasons)" "0,1"
bitfld.long 0x00 21.--23. "DWidth,Destination transfer width: The source and destination widths can be different from each other" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 18.--20. "SWidth,Source transfer width: The source and destination widths can be different from each other" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15.--17. "DBSize,Destination burst size: Indicates the number of transfers which make up a destination burst transfer request" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "SBSize,Source burst size: Indicates the number of transfers which make up a source burst" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "TransferSize,Transfer size: For writes this field indicates the number of (Source width) transfers to perform when the DMAC is the flow controller"
group.long 0x10++0x03
line.long 0x00 "dmac_chcfg,channel configuration registers"
bitfld.long 0x00 18. "H,Halt" "0: allow DMA requests,1: ignore further source DMA requests"
bitfld.long 0x00 17. "A,Active" "0: there is no data in the FIFO of the channel,1: the FIFO of the channel has data"
newline
bitfld.long 0x00 16. "L,Lock" "0,1"
bitfld.long 0x00 15. "ITC,Terminal count interrupt mask" "0,1"
newline
bitfld.long 0x00 14. "IE,Interrupt error mask" "0,1"
bitfld.long 0x00 11.--13. "FlowCntrl,Flow control and transfer type" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--9. "DestPeripheral,Destination peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "SrcPeripheral,Source peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "E,Channel enable" "0: channel disabled,1: channel enabled"
tree.end
repeat.end
tree.end
tree "DMAC_APP_REG"
base ad:0xFF800800
rgroup.long 0x00++0x03
line.long 0x00 "dmac_int_status,interrupt status register"
bitfld.long 0x00 2. "DMACINT_ch2,Status of DMA channel" "0,1"
bitfld.long 0x00 1. "DMACINT_ch1,Status of DMA channel" "0,1"
bitfld.long 0x00 0. "DMACINT_ch0,Status of DMA channel" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "dmac_inttc_status,interrupt terminal count status register"
bitfld.long 0x00 2. "DMACINTTC_ch2,Status of DMA channel" "0,1"
bitfld.long 0x00 1. "DMACINTTC_ch1,Status of DMA channel" "0,1"
bitfld.long 0x00 0. "DMACINTTC_ch0,Status of DMA channel" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "dmac_inttc_clear,interrupt terminal count clear register"
bitfld.long 0x00 2. "DMACINTTCCLR_ch2,Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 2 1'b0 have no effect" "0,1"
bitfld.long 0x00 1. "DMACINTTCCLR_ch1,Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 1 1'b0 have no effect" "0,1"
bitfld.long 0x00 0. "DMACINTTCCLR_ch0,Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 0 1'b0 have no effect" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "dmac_interr_status,interrupt error status register"
bitfld.long 0x00 2. "DMACINTERR_ch2,Status of DMA channel" "0,1"
bitfld.long 0x00 1. "DMACINTERR_ch1,Status of DMA channel" "0,1"
bitfld.long 0x00 0. "DMACINTERR_ch0,Status of DMA channel" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "dmac_interr_clear,interrupt error clear register"
bitfld.long 0x00 2. "DMACINTERRCLR_ch2,Writing a 1'b1 Bit clears the error interrupt of the specific channel 2 1'b0 have no effect" "0,1"
bitfld.long 0x00 1. "DMACINTERRCLR_ch1,Writing a 1'b1 Bit clears the error interrupt of the specific channel 1 1'b0 have no effect" "0,1"
bitfld.long 0x00 0. "DMACINTERRCLR_ch0,Writing a 1'b1 Bit clears the error interrupt of the specific channel 0 1'b0 have no effect" "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "dmac_rawinttc_status,raw interrupt terminal count status register"
bitfld.long 0x00 2. "DMACRAWINTTC_ch2,Status of DMA channel" "0,1"
bitfld.long 0x00 1. "DMACRAWINTTC_ch1,Status of DMA channel" "0,1"
bitfld.long 0x00 0. "DMACRAWINTTC_ch0,Status of DMA channel" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "dmac_rawinterr_status,raw interrupt error status register"
bitfld.long 0x00 2. "DMACRAWINTERR_ch2,Status of DMA channel" "0,1"
bitfld.long 0x00 1. "DMACRAWINTERR_ch1,Status of DMA channel" "0,1"
bitfld.long 0x00 0. "DMACRAWINTERR_ch0,Status of DMA channel" "0,1"
rgroup.long 0x1C++0x03
line.long 0x00 "dmac_enabled_channel,channel enable register"
bitfld.long 0x00 2. "DMACENABLEDCHNS_ch2,Status DMA channel 2 enable" "0,1"
bitfld.long 0x00 1. "DMACENABLEDCHNS_ch1,Status DMA channel 1 enable" "0,1"
bitfld.long 0x00 0. "DMACENABLEDCHNS_ch0,Status DMA channel 0 enable" "0,1"
group.long 0x20++0x03
line.long 0x00 "dmac_softb_req,software burst request register"
hexmask.long.word 0x00 0.--15. 1. "DMACSoftBReq,Software burst request"
group.long 0x24++0x03
line.long 0x00 "dmac_softs_req,software single request register"
hexmask.long.word 0x00 0.--15. 1. "DMACSoftSReq,Software single request"
group.long 0x28++0x03
line.long 0x00 "dmac_softlb_req,software last burst request register"
hexmask.long.word 0x00 0.--15. 1. "DMACSoftLBReq,Software last burst request"
group.long 0x2C++0x03
line.long 0x00 "dmac_softls_req,software last single request register"
hexmask.long.word 0x00 0.--15. 1. "DMACSoftLSReq,Software last single request"
group.long 0x30++0x03
line.long 0x00 "dmac_config,configuration register"
bitfld.long 0x00 0. "DMACENABLE,DMAC enable" "0: disabled,1: enabled"
group.long 0x34++0x03
line.long 0x00 "dmac_sync,sync register DMA synchronization logic for DMA request signals enabled or disabled A 1'b0 bit indicates that the synchronization logic for the DMACBREQ[15:0] DMACSREQ[15:0] DMACLBREQ[15:0] and DMACLSREQ[15:0] request signals is enabled"
hexmask.long.word 0x00 0.--15. 1. "DIS_SYNC,Disable sync register peripheral requests"
tree.end
tree "DMAC_MUX_APP"
base ad:0xFF801000
group.long 0x00++0x03
line.long 0x00 "dmac_mux_peripheral_input_sel0,Peripheral input select for DMAC input channel 0 This register configures which peripheral should be connected to DMAC's input channel 0"
bitfld.long 0x00 0.--5. "index,Index of the peripheral to be connected to DMAC's input channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "dmac_mux_peripheral_input_sel1,Peripheral input select for DMAC input channel 1 This register configures which peripheral should be connected to DMAC's input channel 1"
bitfld.long 0x00 0.--5. "index,Index of the peripheral to be connected to DMAC's input channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "dmac_mux_peripheral_input_sel2,Peripheral input select for DMAC input channel 2 This register configures which peripheral should be connected to DMAC's input channel 2"
bitfld.long 0x00 0.--5. "index,Index of the peripheral to be connected to DMAC's input channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "dmac_mux_peripheral_input_sel3,Peripheral input select for DMAC input channel 3 This register configures which peripheral should be connected to DMAC's input channel 3"
bitfld.long 0x00 0.--5. "index,Index of the peripheral to be connected to DMAC's input channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "dmac_mux_peripheral_input_sel4,Peripheral input select for DMAC input channel 4 This register configures which peripheral should be connected to DMAC's input channel 4"
bitfld.long 0x00 0.--5. "index,Index of the peripheral to be connected to DMAC's input channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "dmac_mux_peripheral_input_sel5,Peripheral input select for DMAC input channel 5 This register configures which peripheral should be connected to DMAC's input channel 5"
bitfld.long 0x00 0.--5. "index,Index of the peripheral to be connected to DMAC's input channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ECC_CTRL_APP"
base ad:0xFF801200
group.long 0x00++0x03
line.long 0x00 "ecc_ctrl_intram0_ctrl,INTRAM0 syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x04++0x03
line.long 0x00 "ecc_ctrl_intram1_ctrl,INTRAM1 syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x08++0x03
line.long 0x00 "ecc_ctrl_intram2_ctrl,INTRAM2 syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ecc_ctrl_intram3_ctrl,INTRAM3 syndrome manipulation register"
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x10++0x03
line.long 0x00 "ecc_ctrl_intram4_ctrl,INTRAM4 syndrome manipulation register"
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x14++0x03
line.long 0x00 "ecc_ctrl_intram5_ctrl,INTRAM5 syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x18++0x03
line.long 0x00 "ecc_ctrl_intram6_ctrl,INTRAM6 syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x1C++0x03
line.long 0x00 "ecc_ctrl_intram7_ctrl,INTRAM7 syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x20++0x03
line.long 0x00 "ecc_ctrl_intramhs_ctrl,INTRAMHS syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x24++0x03
line.long 0x00 "ecc_ctrl_xc0_rpec0_pram_ctrl,XC0_RPEC0_PRAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x28++0x03
line.long 0x00 "ecc_ctrl_xc0_rpec1_pram_ctrl,XC0_RPEC1_PRAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ecc_ctrl_xc0_tpec0_pram_ctrl,XC0_TPEC0_PRAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x30++0x03
line.long 0x00 "ecc_ctrl_xc0_tpec1_pram_ctrl,XC0_TPEC1_PRAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x34++0x03
line.long 0x00 "ecc_ctrl_xc0_dpram0_ctrl,XC0_DPRAM0 syndrome manipulation register"
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x38++0x03
line.long 0x00 "ecc_ctrl_xc0_dpram1_ctrl,XC0_DPRAM1 syndrome manipulation register"
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x3C++0x03
line.long 0x00 "ecc_ctrl_xc0_rpu0_ram_ctrl,XC0_RPU0_RAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x40++0x03
line.long 0x00 "ecc_ctrl_xc0_rpu1_ram_ctrl,XC0_RPU1_RAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x44++0x03
line.long 0x00 "ecc_ctrl_xc0_tpu0_ram_ctrl,XC0_TPU0_RAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x48++0x03
line.long 0x00 "ecc_ctrl_xc0_tpu1_ram_ctrl,XC0_TPU1_RAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x4C++0x03
line.long 0x00 "ecc_ctrl_xc0_pfifo_ctrl,XC0_PFIFO syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x50++0x03
line.long 0x00 "ecc_ctrl_xpic0_pram_ctrl,XPIC0_PRAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x54++0x03
line.long 0x00 "ecc_ctrl_xpic1_pram_ctrl,XPIC1_PRAM syndrome manipulation register"
hexmask.long.byte 0x00 1.--7. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x58++0x03
line.long 0x00 "ecc_ctrl_xpic0_dram_ctrl,XPIC0_DRAM syndrome manipulation register"
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ecc_ctrl_xpic1_dram_ctrl,XPIC1_DRAM syndrome manipulation register"
bitfld.long 0x00 1.--5. "syndrome_inv,Inverts syndrome bits for ECC testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x60++0x03
line.long 0x00 "ecc_ctrl_iflash0_ctrl,IFLASH0 syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x64++0x03
line.long 0x00 "ecc_ctrl_iflash1_ctrl,IFLASH1 syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
group.long 0x68++0x03
line.long 0x00 "ecc_ctrl_iflash2_ctrl,IFLASH2 syndrome manipulation register"
hexmask.long.byte 0x00 1.--8. 1. "syndrome_inv,Inverts syndrome bits for ECC testing"
bitfld.long 0x00 0. "enable,enable ECC" "0,1"
rgroup.long 0x6C++0x03
line.long 0x00 "ecc_ctrl_intram0_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 15.--20. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC single bit error"
rgroup.long 0x70++0x03
line.long 0x00 "ecc_ctrl_intram1_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 15.--20. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC single bit error"
rgroup.long 0x74++0x03
line.long 0x00 "ecc_ctrl_intram2_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 15.--20. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC single bit error"
rgroup.long 0x78++0x03
line.long 0x00 "ecc_ctrl_intram3_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 14.--18. "add_addr,Number of master that started errorneous RAM access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "address,Address of last ECC single bit error"
rgroup.long 0x7C++0x03
line.long 0x00 "ecc_ctrl_intram4_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 14.--18. "add_addr,Number of master that started errorneous RAM access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "address,Address of last ECC single bit error"
rgroup.long 0x80++0x03
line.long 0x00 "ecc_ctrl_intram5_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC single bit error"
rgroup.long 0x84++0x03
line.long 0x00 "ecc_ctrl_intram6_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC single bit error"
rgroup.long 0x88++0x03
line.long 0x00 "ecc_ctrl_intram7_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC single bit error"
rgroup.long 0x8C++0x03
line.long 0x00 "ecc_ctrl_intramhs_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC single bit error"
rgroup.long 0x90++0x03
line.long 0x00 "ecc_ctrl_xc0_rpec0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0x94++0x03
line.long 0x00 "ecc_ctrl_xc0_rpec1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0x98++0x03
line.long 0x00 "ecc_ctrl_xc0_tpec0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0x9C++0x03
line.long 0x00 "ecc_ctrl_xc0_tpec1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0xA0++0x03
line.long 0x00 "ecc_ctrl_xc0_rpu0_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
rgroup.long 0xA4++0x03
line.long 0x00 "ecc_ctrl_xc0_rpu1_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
rgroup.long 0xA8++0x03
line.long 0x00 "ecc_ctrl_xc0_tpu0_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
rgroup.long 0xAC++0x03
line.long 0x00 "ecc_ctrl_xc0_tpu1_ram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC single bit error"
rgroup.long 0xB0++0x03
line.long 0x00 "ecc_ctrl_xpic0_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0xB4++0x03
line.long 0x00 "ecc_ctrl_xpic1_pram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0xB8++0x03
line.long 0x00 "ecc_ctrl_xpic0_dram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0xBC++0x03
line.long 0x00 "ecc_ctrl_xpic1_dram_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC single bit error"
rgroup.long 0xC0++0x03
line.long 0x00 "ecc_ctrl_iflash0_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC single bit error"
rgroup.long 0xC4++0x03
line.long 0x00 "ecc_ctrl_iflash1_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC single bit error"
rgroup.long 0xC8++0x03
line.long 0x00 "ecc_ctrl_iflash2_addr_sbe,RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC single bit error"
rgroup.long 0xCC++0x03
line.long 0x00 "ecc_ctrl_intram0_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 15.--20. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC double bit error"
rgroup.long 0xD0++0x03
line.long 0x00 "ecc_ctrl_intram1_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 15.--20. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC double bit error"
rgroup.long 0xD4++0x03
line.long 0x00 "ecc_ctrl_intram2_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 15.--20. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC double bit error"
rgroup.long 0xD8++0x03
line.long 0x00 "ecc_ctrl_intram3_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 14.--18. "add_addr,Number of master that started errorneous RAM access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "address,Address of last ECC double bit error"
rgroup.long 0xDC++0x03
line.long 0x00 "ecc_ctrl_intram4_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 14.--18. "add_addr,Number of master that started errorneous RAM access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "address,Address of last ECC double bit error"
rgroup.long 0xE0++0x03
line.long 0x00 "ecc_ctrl_intram5_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC double bit error"
rgroup.long 0xE4++0x03
line.long 0x00 "ecc_ctrl_intram6_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC double bit error"
rgroup.long 0xE8++0x03
line.long 0x00 "ecc_ctrl_intram7_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC double bit error"
rgroup.long 0xEC++0x03
line.long 0x00 "ecc_ctrl_intramhs_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
bitfld.long 0x00 13.--18. "add_addr,RAM readmodwrite(1) and number of master that started errorneous RAM access(5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--12. 1. "address,Address of last ECC double bit error"
rgroup.long 0xF0++0x03
line.long 0x00 "ecc_ctrl_xc0_rpec0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0xF4++0x03
line.long 0x00 "ecc_ctrl_xc0_rpec1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0xF8++0x03
line.long 0x00 "ecc_ctrl_xc0_tpec0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0xFC++0x03
line.long 0x00 "ecc_ctrl_xc0_tpec1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0x100++0x03
line.long 0x00 "ecc_ctrl_xc0_rpu0_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
rgroup.long 0x104++0x03
line.long 0x00 "ecc_ctrl_xc0_rpu1_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
rgroup.long 0x108++0x03
line.long 0x00 "ecc_ctrl_xc0_tpu0_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
rgroup.long 0x10C++0x03
line.long 0x00 "ecc_ctrl_xc0_tpu1_ram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.byte 0x00 0.--6. 1. "address,Address of last ECC double bit error"
rgroup.long 0x110++0x03
line.long 0x00 "ecc_ctrl_xpic0_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0x114++0x03
line.long 0x00 "ecc_ctrl_xpic1_pram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0x118++0x03
line.long 0x00 "ecc_ctrl_xpic0_dram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0x11C++0x03
line.long 0x00 "ecc_ctrl_xpic1_dram_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--10. 1. "address,Address of last ECC double bit error"
rgroup.long 0x120++0x03
line.long 0x00 "ecc_ctrl_iflash0_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC double bit error"
rgroup.long 0x124++0x03
line.long 0x00 "ecc_ctrl_iflash1_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC double bit error"
rgroup.long 0x128++0x03
line.long 0x00 "ecc_ctrl_iflash2_addr_dbe,RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured"
hexmask.long.word 0x00 0.--14. 1. "address,Address of last ECC double bit error"
group.long 0x12C++0x03
line.long 0x00 "ecc_ctrl_status_sbe,ECC status SBE: This register collects single bit error (SBE) status information"
bitfld.long 0x00 26. "iflash2,IFLASH2 Single Bit Error occured" "0,1"
bitfld.long 0x00 25. "iflash1,IFLASH1 Single Bit Error occured" "0,1"
bitfld.long 0x00 24. "iflash0,IFLASH0 Single Bit Error occured" "0,1"
bitfld.long 0x00 23. "xpic1_dram,XPIC1_DRAM Single Bit Error occured" "0,1"
bitfld.long 0x00 22. "xpic0_dram,XPIC0_DRAM Single Bit Error occured" "0,1"
bitfld.long 0x00 21. "xpic1_pram,XPIC1_PRAM Single Bit Error occured" "0,1"
newline
bitfld.long 0x00 20. "xpic0_pram,XPIC0_PRAM Single Bit Error occured" "0,1"
bitfld.long 0x00 19. "xc0_pfifo,XC0_PFIFO Single Bit Error occured" "0,1"
bitfld.long 0x00 18. "xc0_tpu1_ram,XC0_TPU1_RAM Single Bit Error occured" "0,1"
bitfld.long 0x00 17. "xc0_tpu0_ram,XC0_TPU0_RAM Single Bit Error occured" "0,1"
bitfld.long 0x00 16. "xc0_rpu1_ram,XC0_RPU1_RAM Single Bit Error occured" "0,1"
bitfld.long 0x00 15. "xc0_rpu0_ram,XC0_RPU0_RAM Single Bit Error occured" "0,1"
newline
bitfld.long 0x00 14. "xc0_dpram1,XC0_DPRAM1 Single Bit Error occured" "0,1"
bitfld.long 0x00 13. "xc0_dpram0,XC0_DPRAM0 Single Bit Error occured" "0,1"
bitfld.long 0x00 12. "xc0_tpec1_pram,XC0_TPEC1_PRAM Single Bit Error occured" "0,1"
bitfld.long 0x00 11. "xc0_tpec0_pram,XC0_TPEC0_PRAM Single Bit Error occured" "0,1"
bitfld.long 0x00 10. "xc0_rpec1_pram,XC0_RPEC1_PRAM Single Bit Error occured" "0,1"
bitfld.long 0x00 9. "xc0_rpec0_pram,XC0_RPEC0_PRAM Single Bit Error occured" "0,1"
newline
bitfld.long 0x00 8. "intramhs,INTRAMHS Single Bit Error occured" "0,1"
bitfld.long 0x00 7. "intram7,INTRAM7 Single Bit Error occured" "0,1"
bitfld.long 0x00 6. "intram6,INTRAM6 Single Bit Error occured" "0,1"
bitfld.long 0x00 5. "intram5,INTRAM5 Single Bit Error occured" "0,1"
bitfld.long 0x00 4. "intram4,INTRAM4 Single Bit Error occured" "0,1"
bitfld.long 0x00 3. "intram3,INTRAM3 Single Bit Error occured" "0,1"
newline
bitfld.long 0x00 2. "intram2,INTRAM2 Single Bit Error occured" "0,1"
bitfld.long 0x00 1. "intram1,INTRAM1 Single Bit Error occured" "0,1"
bitfld.long 0x00 0. "intram0,INTRAM0 Single Bit Error occured" "0,1"
group.long 0x130++0x03
line.long 0x00 "ecc_ctrl_status_dbe,ECC status DBE: This register collects double bit error (DBE) status information"
bitfld.long 0x00 26. "iflash2,IFLASH2 Double Bit Error occured" "0,1"
bitfld.long 0x00 25. "iflash1,IFLASH1 Double Bit Error occured" "0,1"
bitfld.long 0x00 24. "iflash0,IFLASH0 Double Bit Error occured" "0,1"
bitfld.long 0x00 23. "xpic1_dram,XPIC1_DRAM Double Bit Error occured" "0,1"
bitfld.long 0x00 22. "xpic0_dram,XPIC0_DRAM Double Bit Error occured" "0,1"
bitfld.long 0x00 21. "xpic1_pram,XPIC1_PRAM Double Bit Error occured" "0,1"
newline
bitfld.long 0x00 20. "xpic0_pram,XPIC0_PRAM Double Bit Error occured" "0,1"
bitfld.long 0x00 19. "xc0_pfifo,XC0_PFIFO Double Bit Error occured" "0,1"
bitfld.long 0x00 18. "xc0_tpu1_ram,XC0_TPU1_RAM Double Bit Error occured" "0,1"
bitfld.long 0x00 17. "xc0_tpu0_ram,XC0_TPU0_RAM Double Bit Error occured" "0,1"
bitfld.long 0x00 16. "xc0_rpu1_ram,XC0_RPU1_RAM Double Bit Error occured" "0,1"
bitfld.long 0x00 15. "xc0_rpu0_ram,XC0_RPU0_RAM Double Bit Error occured" "0,1"
newline
bitfld.long 0x00 14. "xc0_dpram1,XC0_DPRAM1 Double Bit Error occured" "0,1"
bitfld.long 0x00 13. "xc0_dpram0,XC0_DPRAM0 Double Bit Error occured" "0,1"
bitfld.long 0x00 12. "xc0_tpec1_pram,XC0_TPEC1_PRAM Double Bit Error occured" "0,1"
bitfld.long 0x00 11. "xc0_tpec0_pram,XC0_TPEC0_PRAM Double Bit Error occured" "0,1"
bitfld.long 0x00 10. "xc0_rpec1_pram,XC0_RPEC1_PRAM Double Bit Error occured" "0,1"
bitfld.long 0x00 9. "xc0_rpec0_pram,XC0_RPEC0_PRAM Double Bit Error occured" "0,1"
newline
bitfld.long 0x00 8. "intramhs,INTRAMHS Double Bit Error occured" "0,1"
bitfld.long 0x00 7. "intram7,INTRAM7 Double Bit Error occured" "0,1"
bitfld.long 0x00 6. "intram6,INTRAM6 Double Bit Error occured" "0,1"
bitfld.long 0x00 5. "intram5,INTRAM5 Double Bit Error occured" "0,1"
bitfld.long 0x00 4. "intram4,INTRAM4 Double Bit Error occured" "0,1"
bitfld.long 0x00 3. "intram3,INTRAM3 Double Bit Error occured" "0,1"
newline
bitfld.long 0x00 2. "intram2,INTRAM2 Double Bit Error occured" "0,1"
bitfld.long 0x00 1. "intram1,INTRAM1 Double Bit Error occured" "0,1"
bitfld.long 0x00 0. "intram0,INTRAM0 Double Bit Error occured" "0,1"
tree.end
tree "ENDAT_CTRL0_APP"
base ad:0xFF801780
group.long 0x00++0x03
line.long 0x00 "endat_ctrl_trigger_cfg,EnDat trigger configuration"
bitfld.long 0x00 0.--3. "sel,Trigger source select This bit field configures which event is connected to the strobe signal of the EnDat core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "endat_ctrl_trigger,EnDat trigger"
bitfld.long 0x00 0. "manual,Manual trigger" "0,1"
group.long 0x08++0x03
line.long 0x00 "endat_ctrl_strobe_cfg,EnDat strobe pulse form configuration"
hexmask.long.byte 0x00 8.--15. 1. "high_len,Length of the high phase (i.e. inactive phase) of the strobe signal The high phase will be the programmed value + 1 clock cycle"
hexmask.long.byte 0x00 0.--7. 1. "low_len,Length of the low phase (i.e. active phase) of the strobe signal The low phase will be the programmed value + 1 clock cycle"
tree.end
tree "ENDAT_CTRL1_APP"
base ad:0xFF801790
group.long 0x00++0x03
line.long 0x00 "endat_ctrl_trigger_cfg,EnDat trigger configuration"
bitfld.long 0x00 0.--3. "sel,Trigger source select This bit field configures which event is connected to the strobe signal of the EnDat core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "endat_ctrl_trigger,EnDat trigger"
bitfld.long 0x00 0. "manual,Manual trigger" "0,1"
group.long 0x08++0x03
line.long 0x00 "endat_ctrl_strobe_cfg,EnDat strobe pulse form configuration"
hexmask.long.byte 0x00 8.--15. 1. "high_len,Length of the high phase (i.e. inactive phase) of the strobe signal The high phase will be the programmed value + 1 clock cycle"
hexmask.long.byte 0x00 0.--7. 1. "low_len,Length of the low phase (i.e. active phase) of the strobe signal The low phase will be the programmed value + 1 clock cycle"
tree.end
tree "ENDAT0_APP"
base ad:0xFF801700
group.long 0x00++0x03
line.long 0x00 "endat_send,Send register The send register contains data to be transmitted to the EnDat encoder"
bitfld.long 0x00 24.--29. "byte4,Mode bits M[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 16.--23. 1. "byte3,MRS code / Address / Port address A[7:0]"
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hexmask.long.byte 0x00 8.--15. 1. "byte2,Parameters / Instructions D[15:0]"
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hexmask.long.byte 0x00 0.--7. 1. "byte1,Parameters / Instructions D[7:0]"
rgroup.long 0x04++0x03
line.long 0x00 "endat_receive1_0,Receive register 1 Depending on the transmitted type 2.1 mode command receive register 1 contains different data"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
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hexmask.long.byte 0x00 16.--23. 1. "byte3,"
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hexmask.long.byte 0x00 8.--15. 1. "byte2,"
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hexmask.long.byte 0x00 0.--7. 1. "byte1,"
rgroup.long 0x08++0x03
line.long 0x00 "endat_receive1_1,Receive register 1"
hexmask.long.byte 0x00 16.--23. 1. "byte7,"
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hexmask.long.byte 0x00 8.--15. 1. "byte6,"
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hexmask.long.byte 0x00 0.--7. 1. "byte5,"
rgroup.long 0x0C++0x03
line.long 0x00 "endat_receive2,Receive register 2 If a type 2.2 mode command was sent receive register 2 will contain the contents of additional information 2 and its CRC"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
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hexmask.long.byte 0x00 16.--23. 1. "byte3,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte1,"
rgroup.long 0x10++0x03
line.long 0x00 "endat_receive3,Receive register 3 If a type 2.2 mode command was sent receive register 3 will contain the contents of additional information 1 and its CRC"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
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hexmask.long.byte 0x00 16.--23. 1. "byte3,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,"
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hexmask.long.byte 0x00 0.--7. 1. "byte1,"
group.long 0x14++0x03
line.long 0x00 "endat_conf1,Configuration register 1"
bitfld.long 0x00 30.--31. "endat_ssi,These two bits set either the EnDat (0x2) or the SSI (0x1) transmission mode" "0,1,2,3"
newline
bitfld.long 0x00 29. "ic_reset,Setting of this bit has the effect that the entire interface component is reset to its initial state" "0,1"
newline
bitfld.long 0x00 26.--28. "f_sys,The system frequency actually used must be selected here" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24. "delay_comp,Delay compensation" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "cable_prop_time,The cable propagation time determined by the interface component is stored here"
newline
bitfld.long 0x00 15. "auto_reset,Autom" "0,1"
newline
bitfld.long 0x00 14. "reset_window,The set bit allows resetting of the status and error register only within a defined time period" "0,1"
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bitfld.long 0x00 8.--13. "data_word_len,Here the data word length is set binary with 6 bits for EnDat or SSI" "?,?,?,?,?,?,?,?,8: Data word length = 13 bits = 00,?,?,?,?,13: Data word length = 48 bits = 11 0000,?..."
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bitfld.long 0x00 4.--7. "f_tclk,Setting (4 bit) of transmission rate for EnDat and SSI from 100 kHz to 1 MHz (SSI) or 16 MHz (EnDat)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2. "endat_cont_clk_mode,This bit is used to select the EnDat continuous clock mode" "0,1"
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bitfld.long 0x00 1. "uncond_transfer,This bit defines the unconditional data transfer to receive registers 1 2 3 4 on completion of a data transmission process despite a flag being set in the status register" "0,1"
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bitfld.long 0x00 0. "hw_strobe," "0,1"
group.long 0x18++0x03
line.long 0x00 "endat_conf2,Configuration register 2"
hexmask.long.byte 0x00 24.--31. 1. "hw_strobe_delay,Here the application can enter a value for the HW strobe delay"
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bitfld.long 0x00 22. "rtm,Activates the recovery time measurement that is then performed after each EnDat transmission with the mode command 1-1 Encoder transmit position value and selection of memory area with MRS code 0x43 (selection of 2nd word of position value 2)" "0,1"
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bitfld.long 0x00 19.--21. "filter,The digital filter for the Data_RC data input can be adjusted in eight steps (3 bits) as shown in the table below" "0: Off Setting,1: 3 Setting,2: 4 Setting,3: 5 Setting,4: 6 Setting,5: 10 Setting,6: 20 Setting,7: 40 Setting 000 001 010 011"
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bitfld.long 0x00 16.--18. "t_st,This time is to be set in accordance with EnDat specification" "0: 0.5 * TCLK Setting,1: 0.5 us Setting,2: 1 us Setting,3: 1.5 us Setting,4: 2 us Setting,5: 4 us Setting,6: 8 us Setting,7: 10 us"
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hexmask.long.byte 0x00 8.--15. 1. "watchdog,256 different watchdog time values can be set"
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hexmask.long.byte 0x00 0.--7. 1. "timer_for_sampling_rate,256 different sampling rates can be set"
group.long 0x1C++0x03
line.long 0x00 "endat_conf3,Configuration register 3"
bitfld.long 0x00 15. "speed,(optional) This bit allows selection of the register width for velocity" "0,1"
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bitfld.long 0x00 8. "dw,This bit allows a double-word query to be selected with SSI transmission" "0,1"
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bitfld.long 0x00 3.--7. "singleturn_res,Here the number of steps per revolution is set to binary with 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 2. "gray_to_binary,In SSI transmission mode Gray code values can be converted here to binary code values" "0,1"
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bitfld.long 0x00 1. "format,Here the transmission format for SSI transmission is selected" "0,1"
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bitfld.long 0x00 0. "parity,Here the parity check for SSI transmission is selected" "0,1"
group.long 0x20++0x03
line.long 0x00 "endat_stat,Status register The status bits are created by the sequencing controller of the interface component as required"
bitfld.long 0x00 31. "ready,If the ready bit is set the status register is completely updated" "0,1"
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bitfld.long 0x00 30. "ready_for_strobe,This bit reports that data transmission has ended and that the EnDat protocol automation machine is ready for the next transmission" "0,1"
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bitfld.long 0x00 29. "speed_ready,(optional)" "0,1"
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bitfld.long 0x00 28. "rtm_stop,This bit indicates the end of the recovery time if conf2(22)=1 during EnDat transmission with mode command 1-1 Encoder transmit position value and selection of memory area with MRS code 0x43 (selection of 2nd word of position value 2)" "0,1"
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bitfld.long 0x00 27. "rtm_start,This bit indicates the beginning of the recovery time if conf2(22)=1 during EnDat transmission with mode command 1-1 Encoder transmit position value and selection of memory area with MRS code 0x43 (selection of 2nd word of position value 2)" "0,1"
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bitfld.long 0x00 23. "prop_time_measurement,(LZM)" "0,1"
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bitfld.long 0x00 22. "delay_comp,(LZK)" "0,1"
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bitfld.long 0x00 18. "f_type3,Type II error (transmission layer) triggers F type III" "0,1"
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bitfld.long 0x00 17. "watchdog,Reports triggering of the watchdog" "0,1"
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bitfld.long 0x00 16. "spike,Reports that a Spike was detected at the data input port" "0,1"
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bitfld.long 0x00 15. "wrn,Contains the WRN status bit as transmitted in the EnDat protocol" "0,1"
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bitfld.long 0x00 14. "rm,Contains the RM status bit as transmitted in the EnDat protocol" "0,1"
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bitfld.long 0x00 13. "busy,Contains the Busy status bit as transmitted in the EnDat protocol" "0,1"
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bitfld.long 0x00 12. "crc_zi2,During EnDat transmissions this bit indicates the result of the CRC checking of additional information (ZI2)" "0,1"
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bitfld.long 0x00 11. "crc_zi1,During EnDat transmissions this bit indicates the result of the CRC checking of additional information (ZI1)" "0,1"
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bitfld.long 0x00 10. "error2,Contains the /Error 2 status bit from the EnDat protocol (only with EnDat2.2 commands)" "0,1"
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bitfld.long 0x00 9. "receive3_reg,This status flag indicates that the data in Receive-Reg3 has been updated" "0,1"
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bitfld.long 0x00 8. "receive2_reg,This status flag indicates that the data in Receive-Reg 2 (3) has been updated" "0,1"
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bitfld.long 0x00 7. "ir7,This bit indicates the state of input pin /IR7" "0,1"
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bitfld.long 0x00 6. "ir6,This bit indicates an H/L edge at input pin /IR6" "0,1"
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bitfld.long 0x00 5. "mrs_adr,The occurrence of an addressing or acknowledgement error is shown here as described in the EnDat Interface specification" "0,1"
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bitfld.long 0x00 4. "f_type2,Shows type II error handling in accordance with the EnDat specification at Annex A2" "0,1"
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bitfld.long 0x00 3. "f_type1,Shows type I error handling in accordance with the EnDat specification at Annex A2" "0,1"
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bitfld.long 0x00 2. "crcpw_parity,This bit has two meanings" "0,1"
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bitfld.long 0x00 1. "error1,The status bit error1 from the EnDat protocol is entered here" "0,1"
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bitfld.long 0x00 0. "receive1_reg,This status flag indicates that the data in Receive-Reg 1 has been updated" "0,1"
group.long 0x24++0x03
line.long 0x00 "endat_int,Interrupt mask The interrupt mask register is for the masking of the status registers interrupt sources"
bitfld.long 0x00 31. "ready," "0,1"
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bitfld.long 0x00 29. "speed_ready," "0,1"
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bitfld.long 0x00 18. "f_type3," "0,1"
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bitfld.long 0x00 17. "watchdog," "0,1"
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bitfld.long 0x00 16. "spike," "0,1"
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bitfld.long 0x00 15. "wrn," "0,1"
newline
bitfld.long 0x00 14. "RM," "0,1"
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bitfld.long 0x00 13. "busy," "0,1"
newline
bitfld.long 0x00 12. "crc_zi2," "0,1"
newline
bitfld.long 0x00 11. "crc_zi1," "0,1"
newline
bitfld.long 0x00 10. "error2," "0,1"
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bitfld.long 0x00 9. "receive3_reg," "0,1"
newline
bitfld.long 0x00 8. "receive2_reg," "0,1"
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bitfld.long 0x00 7. "ir7," "0,1"
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bitfld.long 0x00 6. "ir6," "0,1"
newline
bitfld.long 0x00 5. "mrs_adr," "0,1"
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bitfld.long 0x00 4. "f_type2," "0,1"
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bitfld.long 0x00 3. "f_type1," "0,1"
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bitfld.long 0x00 2. "crcpw_parity," "0,1"
newline
bitfld.long 0x00 1. "error1," "0,1"
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bitfld.long 0x00 0. "receive1_reg," "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "endat_test1,Test register 1"
hexmask.long.tbyte 0x00 10.--31. 1. "ic_test_values,"
newline
bitfld.long 0x00 4.--9. "enDat_automation_engine," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1.--2. "status_zi,Allows testing of the IC-internal automation machine" "?,1: 01 IC sends clocks for one unit of additional,2: 10 IC sends clocks for two units of additional,?..."
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bitfld.long 0x00 0. "dl_high,For control of the EnDat automation machine" "0,1"
group.long 0x2C++0x03
line.long 0x00 "endat_test2,Test register 2"
hexmask.long.word 0x00 16.--31. 1. "ic_test_data,RTM value - Counter value of the recovery time measurement if conf2(22)=1"
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bitfld.long 0x00 14.--15. "sel_test_mux3,(For testing at IC manufacturing site internal resources can be read via test register 3) Write value test register" "0,1,2,3"
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bitfld.long 0x00 12.--13. "sel_test_mux2,(For testing at IC manufacturing site internal resources can be read via test register 4) Test_Mode_Divider =" "0: Selection of test multiplexer,?,2: Test value quotient (divider) = 00 Test value,?..."
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bitfld.long 0x00 11. "test_mode_divider,(For testing at IC manufacturing site internal resources can be read via test register 4) Standard operating mode = 0 Test mode active = 1" "0,1"
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bitfld.long 0x00 8.--10. "selection_add_info,The number of required additional information units (ZI) can also be selected manually(alternatively to implemented ZI automation resources) Automated resources active = 0 00 IC sends clocks for one unit of additional information" "?,1: 0 01 IC sends clocks for one unit of additional,2: 0 10 IC sends clocks for two units of..,?..."
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bitfld.long 0x00 7. "ic_test_mode,The IC can be switched to a special test mode allowing the testing of internal modules Standard application mode = 0 Special test mode = 1" "0,1"
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bitfld.long 0x00 4.--5. "sel_test_mux,(for testing at IC manufacturing site internal resources can be read) Standard operating mode = 00 Central pre-dividers = 01 Start bit counter = 10 Delay counter and register additional information bit = 11" "0,1,2,3"
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bitfld.long 0x00 3. "test_receive_reg,Standard operating mode = TST receive_reg = 0 Test mode for receive register = TST receive_reg = 1 By writing to the address of the receive registers the content of test register 2 (bits (31:16) is transferred them. It is not possible.." "0,1"
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bitfld.long 0x00 2. "selection_tst_out,For testing the TST_OUT_PIN pin is assigned as follows: Internal (delayed by synchronization) DATA_RC_INT = 0 This signal is the signal that belongs to data strobe pulse" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "endat_receive4_0,Receive register 4 Receive register 4 contains position value 2 (Pos2) which is put together from the additional information 1 of Cycles 2 3 and 4"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
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hexmask.long.byte 0x00 16.--23. 1. "byte3,"
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hexmask.long.byte 0x00 8.--15. 1. "byte2,"
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hexmask.long.byte 0x00 0.--7. 1. "byte1,"
rgroup.long 0x34++0x03
line.long 0x00 "endat_receive4_1,Receive register 4"
hexmask.long.byte 0x00 8.--15. 1. "byte6,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte5,"
wgroup.long 0x38++0x03
line.long 0x00 "endat_sw_strobe,SW strobe"
hexmask.long 0x00 0.--31. 1. "sw_strobe,Writing this register will in each case cause the first H/L transition of the TCLK transmission clock signal"
rgroup.long 0x3C++0x03
line.long 0x00 "endat_id,Identification register The soft-macro specification (ID) is stored here"
hexmask.long 0x00 0.--31. 1. "id,"
tree.end
tree "ENDAT1_APP"
base ad:0xFF801740
group.long 0x00++0x03
line.long 0x00 "endat_send,Send register The send register contains data to be transmitted to the EnDat encoder"
bitfld.long 0x00 24.--29. "byte4,Mode bits M[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 16.--23. 1. "byte3,MRS code / Address / Port address A[7:0]"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,Parameters / Instructions D[15:0]"
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hexmask.long.byte 0x00 0.--7. 1. "byte1,Parameters / Instructions D[7:0]"
rgroup.long 0x04++0x03
line.long 0x00 "endat_receive1_0,Receive register 1 Depending on the transmitted type 2.1 mode command receive register 1 contains different data"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
newline
hexmask.long.byte 0x00 16.--23. 1. "byte3,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,"
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hexmask.long.byte 0x00 0.--7. 1. "byte1,"
rgroup.long 0x08++0x03
line.long 0x00 "endat_receive1_1,Receive register 1"
hexmask.long.byte 0x00 16.--23. 1. "byte7,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte6,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte5,"
rgroup.long 0x0C++0x03
line.long 0x00 "endat_receive2,Receive register 2 If a type 2.2 mode command was sent receive register 2 will contain the contents of additional information 2 and its CRC"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
newline
hexmask.long.byte 0x00 16.--23. 1. "byte3,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte1,"
rgroup.long 0x10++0x03
line.long 0x00 "endat_receive3,Receive register 3 If a type 2.2 mode command was sent receive register 3 will contain the contents of additional information 1 and its CRC"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
newline
hexmask.long.byte 0x00 16.--23. 1. "byte3,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte1,"
group.long 0x14++0x03
line.long 0x00 "endat_conf1,Configuration register 1"
bitfld.long 0x00 30.--31. "endat_ssi,These two bits set either the EnDat (0x2) or the SSI (0x1) transmission mode" "0,1,2,3"
newline
bitfld.long 0x00 29. "ic_reset,Setting of this bit has the effect that the entire interface component is reset to its initial state" "0,1"
newline
bitfld.long 0x00 26.--28. "f_sys,The system frequency actually used must be selected here" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24. "delay_comp,Delay compensation" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "cable_prop_time,The cable propagation time determined by the interface component is stored here"
newline
bitfld.long 0x00 15. "auto_reset,Autom" "0,1"
newline
bitfld.long 0x00 14. "reset_window,The set bit allows resetting of the status and error register only within a defined time period" "0,1"
newline
bitfld.long 0x00 8.--13. "data_word_len,Here the data word length is set binary with 6 bits for EnDat or SSI" "?,?,?,?,?,?,?,?,8: Data word length = 13 bits = 00,?,?,?,?,13: Data word length = 48 bits = 11 0000,?..."
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bitfld.long 0x00 4.--7. "f_tclk,Setting (4 bit) of transmission rate for EnDat and SSI from 100 kHz to 1 MHz (SSI) or 16 MHz (EnDat)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "endat_cont_clk_mode,This bit is used to select the EnDat continuous clock mode" "0,1"
newline
bitfld.long 0x00 1. "uncond_transfer,This bit defines the unconditional data transfer to receive registers 1 2 3 4 on completion of a data transmission process despite a flag being set in the status register" "0,1"
newline
bitfld.long 0x00 0. "hw_strobe," "0,1"
group.long 0x18++0x03
line.long 0x00 "endat_conf2,Configuration register 2"
hexmask.long.byte 0x00 24.--31. 1. "hw_strobe_delay,Here the application can enter a value for the HW strobe delay"
newline
bitfld.long 0x00 22. "rtm,Activates the recovery time measurement that is then performed after each EnDat transmission with the mode command 1-1 Encoder transmit position value and selection of memory area with MRS code 0x43 (selection of 2nd word of position value 2)" "0,1"
newline
bitfld.long 0x00 19.--21. "filter,The digital filter for the Data_RC data input can be adjusted in eight steps (3 bits) as shown in the table below" "0: Off Setting,1: 3 Setting,2: 4 Setting,3: 5 Setting,4: 6 Setting,5: 10 Setting,6: 20 Setting,7: 40 Setting 000 001 010 011"
newline
bitfld.long 0x00 16.--18. "t_st,This time is to be set in accordance with EnDat specification" "0: 0.5 * TCLK Setting,1: 0.5 us Setting,2: 1 us Setting,3: 1.5 us Setting,4: 2 us Setting,5: 4 us Setting,6: 8 us Setting,7: 10 us"
newline
hexmask.long.byte 0x00 8.--15. 1. "watchdog,256 different watchdog time values can be set"
newline
hexmask.long.byte 0x00 0.--7. 1. "timer_for_sampling_rate,256 different sampling rates can be set"
group.long 0x1C++0x03
line.long 0x00 "endat_conf3,Configuration register 3"
bitfld.long 0x00 15. "speed,(optional) This bit allows selection of the register width for velocity" "0,1"
newline
bitfld.long 0x00 8. "dw,This bit allows a double-word query to be selected with SSI transmission" "0,1"
newline
bitfld.long 0x00 3.--7. "singleturn_res,Here the number of steps per revolution is set to binary with 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 2. "gray_to_binary,In SSI transmission mode Gray code values can be converted here to binary code values" "0,1"
newline
bitfld.long 0x00 1. "format,Here the transmission format for SSI transmission is selected" "0,1"
newline
bitfld.long 0x00 0. "parity,Here the parity check for SSI transmission is selected" "0,1"
group.long 0x20++0x03
line.long 0x00 "endat_stat,Status register The status bits are created by the sequencing controller of the interface component as required"
bitfld.long 0x00 31. "ready,If the ready bit is set the status register is completely updated" "0,1"
newline
bitfld.long 0x00 30. "ready_for_strobe,This bit reports that data transmission has ended and that the EnDat protocol automation machine is ready for the next transmission" "0,1"
newline
bitfld.long 0x00 29. "speed_ready,(optional)" "0,1"
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bitfld.long 0x00 28. "rtm_stop,This bit indicates the end of the recovery time if conf2(22)=1 during EnDat transmission with mode command 1-1 Encoder transmit position value and selection of memory area with MRS code 0x43 (selection of 2nd word of position value 2)" "0,1"
newline
bitfld.long 0x00 27. "rtm_start,This bit indicates the beginning of the recovery time if conf2(22)=1 during EnDat transmission with mode command 1-1 Encoder transmit position value and selection of memory area with MRS code 0x43 (selection of 2nd word of position value 2)" "0,1"
newline
bitfld.long 0x00 23. "prop_time_measurement,(LZM)" "0,1"
newline
bitfld.long 0x00 22. "delay_comp,(LZK)" "0,1"
newline
bitfld.long 0x00 18. "f_type3,Type II error (transmission layer) triggers F type III" "0,1"
newline
bitfld.long 0x00 17. "watchdog,Reports triggering of the watchdog" "0,1"
newline
bitfld.long 0x00 16. "spike,Reports that a Spike was detected at the data input port" "0,1"
newline
bitfld.long 0x00 15. "wrn,Contains the WRN status bit as transmitted in the EnDat protocol" "0,1"
newline
bitfld.long 0x00 14. "rm,Contains the RM status bit as transmitted in the EnDat protocol" "0,1"
newline
bitfld.long 0x00 13. "busy,Contains the Busy status bit as transmitted in the EnDat protocol" "0,1"
newline
bitfld.long 0x00 12. "crc_zi2,During EnDat transmissions this bit indicates the result of the CRC checking of additional information (ZI2)" "0,1"
newline
bitfld.long 0x00 11. "crc_zi1,During EnDat transmissions this bit indicates the result of the CRC checking of additional information (ZI1)" "0,1"
newline
bitfld.long 0x00 10. "error2,Contains the /Error 2 status bit from the EnDat protocol (only with EnDat2.2 commands)" "0,1"
newline
bitfld.long 0x00 9. "receive3_reg,This status flag indicates that the data in Receive-Reg3 has been updated" "0,1"
newline
bitfld.long 0x00 8. "receive2_reg,This status flag indicates that the data in Receive-Reg 2 (3) has been updated" "0,1"
newline
bitfld.long 0x00 7. "ir7,This bit indicates the state of input pin /IR7" "0,1"
newline
bitfld.long 0x00 6. "ir6,This bit indicates an H/L edge at input pin /IR6" "0,1"
newline
bitfld.long 0x00 5. "mrs_adr,The occurrence of an addressing or acknowledgement error is shown here as described in the EnDat Interface specification" "0,1"
newline
bitfld.long 0x00 4. "f_type2,Shows type II error handling in accordance with the EnDat specification at Annex A2" "0,1"
newline
bitfld.long 0x00 3. "f_type1,Shows type I error handling in accordance with the EnDat specification at Annex A2" "0,1"
newline
bitfld.long 0x00 2. "crcpw_parity,This bit has two meanings" "0,1"
newline
bitfld.long 0x00 1. "error1,The status bit error1 from the EnDat protocol is entered here" "0,1"
newline
bitfld.long 0x00 0. "receive1_reg,This status flag indicates that the data in Receive-Reg 1 has been updated" "0,1"
group.long 0x24++0x03
line.long 0x00 "endat_int,Interrupt mask The interrupt mask register is for the masking of the status registers interrupt sources"
bitfld.long 0x00 31. "ready," "0,1"
newline
bitfld.long 0x00 29. "speed_ready," "0,1"
newline
bitfld.long 0x00 18. "f_type3," "0,1"
newline
bitfld.long 0x00 17. "watchdog," "0,1"
newline
bitfld.long 0x00 16. "spike," "0,1"
newline
bitfld.long 0x00 15. "wrn," "0,1"
newline
bitfld.long 0x00 14. "RM," "0,1"
newline
bitfld.long 0x00 13. "busy," "0,1"
newline
bitfld.long 0x00 12. "crc_zi2," "0,1"
newline
bitfld.long 0x00 11. "crc_zi1," "0,1"
newline
bitfld.long 0x00 10. "error2," "0,1"
newline
bitfld.long 0x00 9. "receive3_reg," "0,1"
newline
bitfld.long 0x00 8. "receive2_reg," "0,1"
newline
bitfld.long 0x00 7. "ir7," "0,1"
newline
bitfld.long 0x00 6. "ir6," "0,1"
newline
bitfld.long 0x00 5. "mrs_adr," "0,1"
newline
bitfld.long 0x00 4. "f_type2," "0,1"
newline
bitfld.long 0x00 3. "f_type1," "0,1"
newline
bitfld.long 0x00 2. "crcpw_parity," "0,1"
newline
bitfld.long 0x00 1. "error1," "0,1"
newline
bitfld.long 0x00 0. "receive1_reg," "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "endat_test1,Test register 1"
hexmask.long.tbyte 0x00 10.--31. 1. "ic_test_values,"
newline
bitfld.long 0x00 4.--9. "enDat_automation_engine," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1.--2. "status_zi,Allows testing of the IC-internal automation machine" "?,1: 01 IC sends clocks for one unit of additional,2: 10 IC sends clocks for two units of additional,?..."
newline
bitfld.long 0x00 0. "dl_high,For control of the EnDat automation machine" "0,1"
group.long 0x2C++0x03
line.long 0x00 "endat_test2,Test register 2"
hexmask.long.word 0x00 16.--31. 1. "ic_test_data,RTM value - Counter value of the recovery time measurement if conf2(22)=1"
newline
bitfld.long 0x00 14.--15. "sel_test_mux3,(For testing at IC manufacturing site internal resources can be read via test register 3) Write value test register" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "sel_test_mux2,(For testing at IC manufacturing site internal resources can be read via test register 4) Test_Mode_Divider =" "0: Selection of test multiplexer,?,2: Test value quotient (divider) = 00 Test value,?..."
newline
bitfld.long 0x00 11. "test_mode_divider,(For testing at IC manufacturing site internal resources can be read via test register 4) Standard operating mode = 0 Test mode active = 1" "0,1"
newline
bitfld.long 0x00 8.--10. "selection_add_info,The number of required additional information units (ZI) can also be selected manually(alternatively to implemented ZI automation resources) Automated resources active = 0 00 IC sends clocks for one unit of additional information" "?,1: 0 01 IC sends clocks for one unit of additional,2: 0 10 IC sends clocks for two units of..,?..."
newline
bitfld.long 0x00 7. "ic_test_mode,The IC can be switched to a special test mode allowing the testing of internal modules Standard application mode = 0 Special test mode = 1" "0,1"
newline
bitfld.long 0x00 4.--5. "sel_test_mux,(for testing at IC manufacturing site internal resources can be read) Standard operating mode = 00 Central pre-dividers = 01 Start bit counter = 10 Delay counter and register additional information bit = 11" "0,1,2,3"
newline
bitfld.long 0x00 3. "test_receive_reg,Standard operating mode = TST receive_reg = 0 Test mode for receive register = TST receive_reg = 1 By writing to the address of the receive registers the content of test register 2 (bits (31:16) is transferred them. It is not possible.." "0,1"
newline
bitfld.long 0x00 2. "selection_tst_out,For testing the TST_OUT_PIN pin is assigned as follows: Internal (delayed by synchronization) DATA_RC_INT = 0 This signal is the signal that belongs to data strobe pulse" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "endat_receive4_0,Receive register 4 Receive register 4 contains position value 2 (Pos2) which is put together from the additional information 1 of Cycles 2 3 and 4"
hexmask.long.byte 0x00 24.--31. 1. "byte4,"
newline
hexmask.long.byte 0x00 16.--23. 1. "byte3,"
newline
hexmask.long.byte 0x00 8.--15. 1. "byte2,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte1,"
rgroup.long 0x34++0x03
line.long 0x00 "endat_receive4_1,Receive register 4"
hexmask.long.byte 0x00 8.--15. 1. "byte6,"
newline
hexmask.long.byte 0x00 0.--7. 1. "byte5,"
wgroup.long 0x38++0x03
line.long 0x00 "endat_sw_strobe,SW strobe"
hexmask.long 0x00 0.--31. 1. "sw_strobe,Writing this register will in each case cause the first H/L transition of the TCLK transmission clock signal"
rgroup.long 0x3C++0x03
line.long 0x00 "endat_id,Identification register The soft-macro specification (ID) is stored here"
hexmask.long 0x00 0.--31. 1. "id,"
tree.end
tree "ETH"
base ad:0xFF480000
group.long 0x00++0x03
line.long 0x00 "eth_config,ETH config register"
bitfld.long 0x00 29. "phy_mode,PHY mode" "0: behave like an ethernet MAC sync to external,1: behave like an ethernet PHY generate txclk"
bitfld.long 0x00 28. "hd_suppress_loopback,Suppress loopback in half_duplex mode" "0: RX and TX work indepentently,1: don't start RX-process if txen is active"
newline
bitfld.long 0x00 27. "frequency,MII clock frequency" "0: 25MHz,1: 50MHz (use in"
bitfld.long 0x00 13. "rx_enable,Enable of receive state machine: When disabled receive state machine is reset" "0,1"
newline
bitfld.long 0x00 12. "rx_systime_sfd,Sample systime at SFD of received frame" "0: Sample systime_ns to eth_rx_systime_ns when..,1: Sample systime_ns to eth_rx_systime_ns at SFD"
bitfld.long 0x00 11. "rx_dma_mode,Receive DMA mode: Each received frame needs 2 DMA-transfers one for package data and one for rx_len/status" "0,1"
newline
bitfld.long 0x00 10. "rx_no_preamble,receive starts when rxdv gets active" "0,1"
bitfld.long 0x00 9. "rx_exact_preamble,Accept only packages with exact preamble rx_preamble_error IRQ will be generated independant on this setting" "0,1"
newline
bitfld.long 0x00 8. "rx_allow_jumbo_packets,Receive frames &gt 1522 bytes" "0,1"
bitfld.long 0x00 7. "rx_delay_inputs,Delay mii inputs (rx_d rx_dv rx_err crs col) by 1 clockcycle before sampling them" "0,1"
newline
bitfld.long 0x00 4.--6. "rx_sample_phase,clk-phase in which rxd is sampled: PHY mode (phy_mode=1): { | 0 4: sample at posedge tx_clk 1 5: sample at posedge tx_clk + 1cc 2 6: sample at posedge tx_clk + 2cc 3 7: sample at posedge tx_clk + 3cc} MAC mode (phy_mode=0): { | 0: sample.." "0: sample at posedge rx_clk + 1cc,1: sample at posedge rx_clk + 2cc,2: sample at posedge rx_clk + 3cc,3: sample at posedge rx_clk + 4cc,4: sample at negedge rx_clk + 3cc,5: sample at negedge rx_clk + 4cc,6: sample at negedge rx_clk + 1cc,7: sample at negedge rx_clk + 2cc}"
bitfld.long 0x00 0.--3. "rx_watermark_irq,Watermark for RX-FIFO that generates interrupt This number of DWords is available inside RX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "eth_tx_config,ETH config register"
bitfld.long 0x00 31. "half_duplex,Half Duplex Mode" "0: In full duplex mode transmission of a frame,1: In half duplex mode transmission of a frame"
bitfld.long 0x00 30. "tx_dma_mode,In tx_dma_mode tx_len comes from DMAC automatically" "0,1"
newline
bitfld.long 0x00 29. "tx_systime_sfd,Sample systime at SFD" "0: Sample systime_ns to eth_tx_systime_ns when..,1: Sample systime_ns to eth_tx_systime_ns at SFD"
bitfld.long 0x00 26.--28. "tx_abort_frame,Different abort mechanisms" "0: no abort,1: standard abort,2: abort with dribble nibble,3: no FCS mode,4: Fast Track Switching controlled abort,5: reserved,6: reserved,7: reserved"
newline
bitfld.long 0x00 21.--25. "tx_crs_low_cycles,txclk-cycles with mii_crs low before free carrier is detected (only used in half_duplex mode): Value range: [0 tx_min_ifg_cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "tx_min_ifg_cycles,minimum IFG in txclk-cycles In half_duplex mode reduce value by 2 to compensate cycles for sampling of mii_crs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11.--15. "tx_preamble_len,Length of TX-preamble in nibbles (incl. SFD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "tx_output_phase,clk-phase in which txd txen txer is changed at output PHY mode (phy_mode=1): { | 0 4: change output at negedge tx_clk 1 5: change output at negedge tx_clk + 1cc 2 6: change output at negedge tx_clk + 2cc 3 7: change output at negedge.." "0: change output at posedge tx_clk + 2cc,1: change output at posedge tx_clk + 3cc,2: change output at posedge tx_clk + 4cc,3: change output at posedge tx_clk + 5cc,4: change output at negedge tx_clk + 4cc,5: change output at negedge tx_clk + 5cc,6: change output at negedge tx_clk + 2cc,7: change output at negedge tx_clk + 3cc}"
newline
bitfld.long 0x00 4.--7. "tx_watermark_start,Watermark for TX-FIFO that starts transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "tx_watermark_irq,Watermark for TX-FIFO that generates IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x08++0x03
line.long 0x00 "eth_status,ETH status register"
bitfld.long 0x00 7.--11. "tx_fill,Fill-level of TX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "rx_fill,Fill-level of RX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x0C++0x03
line.long 0x00 "eth_tx_data,Data to TX-FIFO: returns 0xdeadbeef on read"
hexmask.long 0x00 0.--31. 1. "val,data to TX-FIFO"
rgroup.long 0x10++0x03
line.long 0x00 "eth_rx_data,Data from RX-FIFO"
hexmask.long 0x00 0.--31. 1. "val,data from RX-FIFO"
group.long 0x14++0x03
line.long 0x00 "eth_tx_len,Length of data inside transmitted frame (between SFD and FCS) Note: Set this value after previous frame is completely transmitted (irq-tx_frame_finished)"
hexmask.long.word 0x00 0.--10. 1. "val,To be transmitted data length (excluding SFD and excluding FCS)"
rgroup.long 0x18++0x03
line.long 0x00 "eth_rx_len_stat,Length and status information of lastly received frame"
bitfld.long 0x00 31. "rx_mii_rxerr,external rxerr signal was active in last frame" "0,1"
bitfld.long 0x00 30. "rx_crc_error,wrong RX FCS detected" "0,1"
newline
bitfld.long 0x00 29. "rx_dribble_nibble,frame finished at non-even nibble count last nibble was dropped" "0,1"
bitfld.long 0x00 28. "rx_jumbo_packet,rx_frame_len &gt 1522 detected: In case of eth_config-allow_jumbo_packets=1 this frame was received but rx_len will overflow at 2048" "0,1"
newline
bitfld.long 0x00 27. "rx_short_ifg,IFG shorter 960ns detected (preceeding this frame)" "0,1"
hexmask.long.word 0x00 0.--10. 1. "rx_len,Received data (excluding SFD and including FCS)"
rgroup.long 0x20++0x03
line.long 0x00 "eth_rx_systime_ns,Systime_ns sampled at start of received frame"
hexmask.long 0x00 0.--31. 1. "val,Sampled systime_ns"
rgroup.long 0x24++0x03
line.long 0x00 "eth_tx_systime_ns,Systime_ns sampled at start of transmitted frame"
hexmask.long 0x00 0.--31. 1. "val,Sampled systime_ns"
group.long 0x28++0x03
line.long 0x00 "eth_irq_raw,Raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 12. "tx_late_col,late colision detected in half_duplex mode started sending jam" "0,1"
bitfld.long 0x00 11. "tx_col,collision detected in half_duplex mode started sending jam" "0,1"
newline
bitfld.long 0x00 10. "rx_preamble_error,data &lt &gt 0x5 during preamble or wrong length of preamble" "0,1"
bitfld.long 0x00 9. "rx_short_dv,mii_rxdv becomes low before SFD" "0,1"
newline
bitfld.long 0x00 8. "rx_cpu_too_slow,next frame started before irq_raw_rx_frame_finished was cleared" "0,1"
bitfld.long 0x00 7. "rx_fifo_ovfl,RX-FIFO overflow" "0,1"
newline
bitfld.long 0x00 6. "rx_fifo_undr,RX-FIFO underrun (debug only can never happen in ASIC)" "0,1"
bitfld.long 0x00 5. "tx_fifo_ovfl,TX-FIFO overflow (debug only can never happen in ASIC)" "0,1"
newline
bitfld.long 0x00 4. "tx_fifo_undr,TX-FIFO underrun" "0,1"
bitfld.long 0x00 3. "rx_frame_finished,RX frame finished: Clearing this bit tells the module that the CPU has read rx_len_stat and the next frame can be received" "0,1"
newline
bitfld.long 0x00 2. "rx_data,RX Data is available" "0,1"
bitfld.long 0x00 1. "tx_frame_finished,TX frame finished: In tx_dma_mode this bit is handled automatically demask it to the CPU" "0,1"
newline
bitfld.long 0x00 0. "tx_fifo,TX-FIFO has free entries" "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "eth_irq_masked,Masked IRQ: Shows status of masked IRQs as connected to ARM/xPIC"
bitfld.long 0x00 12. "tx_late_col,late colision detected in half_duplex mode started sending jam" "0,1"
bitfld.long 0x00 11. "tx_col,collision detected in half_duplex mode started sending jam" "0,1"
newline
bitfld.long 0x00 10. "rx_preamble_error,data &lt &gt 0x5 during preamble or wrong length of preamble" "0,1"
bitfld.long 0x00 9. "rx_short_dv,mii_rxdv becomes low before SFD" "0,1"
newline
bitfld.long 0x00 8. "rx_cpu_too_slow,next frame started before irq_raw_rx_frame_finished was cleared" "0,1"
bitfld.long 0x00 7. "rx_fifo_ovfl,RX-FIFO overflow" "0,1"
newline
bitfld.long 0x00 6. "rx_fifo_undr,RX-FIFO underrun (debug only can never happen in ASIC)" "0,1"
bitfld.long 0x00 5. "tx_fifo_ovfl,TX-FIFO overflow (debug only can never happen in ASIC)" "0,1"
newline
bitfld.long 0x00 4. "tx_fifo_undr,TX-FIFO underrun" "0,1"
bitfld.long 0x00 3. "rx_frame_finished,RX frame finished" "0,1"
newline
bitfld.long 0x00 2. "rx_data,RX Data is available" "0,1"
bitfld.long 0x00 1. "tx_frame_finished,TX frame finished" "0,1"
newline
bitfld.long 0x00 0. "tx_fifo,TX-FIFO has free entries" "0,1"
group.long 0x30++0x03
line.long 0x00 "eth_irq_msk_set,IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 12. "tx_late_col,late colision detected in half_duplex mode started sending jam" "0,1"
bitfld.long 0x00 11. "tx_col,collision detected in half_duplex mode started sending jam" "0,1"
newline
bitfld.long 0x00 10. "rx_preamble_error,data &lt &gt 0x5 during preamble or wrong length of preamble" "0,1"
bitfld.long 0x00 9. "rx_short_dv,mii_rxdv becomes low before SFD" "0,1"
newline
bitfld.long 0x00 8. "rx_cpu_too_slow,next frame started before irq_raw_rx_frame_finished was cleared" "0,1"
bitfld.long 0x00 7. "rx_fifo_ovfl,RX-FIFO overflow" "0,1"
newline
bitfld.long 0x00 6. "rx_fifo_undr,RX-FIFO underrun (debug only can never happen in ASIC)" "0,1"
bitfld.long 0x00 5. "tx_fifo_ovfl,TX-FIFO overflow (debug only can never happen in ASIC)" "0,1"
newline
bitfld.long 0x00 4. "tx_fifo_undr,TX-FIFO underrun" "0,1"
bitfld.long 0x00 3. "rx_frame_finished,RX frame finished" "0,1"
newline
bitfld.long 0x00 2. "rx_data,RX Data is available" "0,1"
bitfld.long 0x00 1. "tx_frame_finished,TX frame finished" "0,1"
newline
bitfld.long 0x00 0. "tx_fifo,TX-FIFO has free entries" "0,1"
group.long 0x34++0x03
line.long 0x00 "eth_irq_msk_reset,IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 12. "tx_late_col,late colision detected in half_duplex mode started sending jam" "0,1"
bitfld.long 0x00 11. "tx_col,collision detected in half_duplex mode started sending jam" "0,1"
newline
bitfld.long 0x00 10. "rx_preamble_error,data &lt &gt 0x5 during preamble or wrong length of preamble" "0,1"
bitfld.long 0x00 9. "rx_short_dv,mii_rxdv becomes low before SFD" "0,1"
newline
bitfld.long 0x00 8. "rx_cpu_too_slow,next frame started before irq_raw_rx_frame_finished was cleared" "0,1"
bitfld.long 0x00 7. "rx_fifo_ovfl,RX-FIFO overflow" "0,1"
newline
bitfld.long 0x00 6. "rx_fifo_undr,RX-FIFO underrun (debug only can never happen in ASIC)" "0,1"
bitfld.long 0x00 5. "tx_fifo_ovfl,TX-FIFO overflow (debug only can never happen in ASIC)" "0,1"
newline
bitfld.long 0x00 4. "tx_fifo_undr,TX-FIFO underrun" "0,1"
bitfld.long 0x00 3. "rx_frame_finished,RX frame finished" "0,1"
newline
bitfld.long 0x00 2. "rx_data,RX Data is available" "0,1"
bitfld.long 0x00 1. "tx_frame_finished,TX frame finished" "0,1"
newline
bitfld.long 0x00 0. "tx_fifo,TX-FIFO has free entries" "0,1"
tree.end
tree "GLOBAL_BUF_MAN"
base ad:0xFF401380
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x00)++0x03
line.long 0x00 "global_read_buffer_$1,read: get read buffer number write reset buffer states"
bitfld.long 0x00 0.--1. "val,read: read buffer number[0 1 2] [3] = empty-no buffer" "0,1,2,3"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x20)++0x03
line.long 0x00 "global_write_buffer_$1,read: get write buffer number write release write buffer"
bitfld.long 0x00 0.--1. "val,read: write buffer number[0 1 2]" "0,1,2,3"
repeat.end
tree.end
tree "GPIO_APP"
base ad:0xFF801400
group.long 0x00++0x03
line.long 0x00 "gpio_app_cfg0,GPIO_APP pin 0 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,Run blink sequence only once (blink mode only)" "0,1"
bitfld.long 0x00 7.--11. "blink_len,Length of blink sequence minus 1 (blink mode only)" "0: use bit 0 of gpio_app_tc,1: use bits 0..1 of gpio_app_tc,2: use bits 0..2 of gpio_app_tc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: use bits 0..31 of gpio_app_tc"
newline
bitfld.long 0x00 5.--6. "count_ref,counter reference" "0: counter 0,1: counter 1,2: counter 2,3: sys_time (global system"
bitfld.long 0x00 4. "inv," "0,1"
newline
bitfld.long 0x00 0.--3. "mode,defines the gp input or output mode - depends on io_cfg Input modes" "0: read mode,1: capture continued at rising edge (allows,2: capture once at rising edge (reset gpio_app_irq,3: capture once at high level (reset gpio_app_irq,4: set to 0,5: set to 1,6: set to gpio_app_line[0],7: pwm mode direct threshold update (might cause,8: blink mode Multi pin modes,?,?,?,?,?,?,15: pwm2-mode with threshold update at counter=0"
group.long 0x04++0x03
line.long 0x00 "gpio_app_cfg1,GPIO_APP pin 1 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "gpio_app_cfg2,GPIO_APP pin 2 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "gpio_app_cfg3,GPIO_APP pin 3 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "gpio_app_cfg4,GPIO_APP pin 4 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "gpio_app_cfg5,GPIO_APP pin 5 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "gpio_app_cfg6,GPIO_APP pin 6 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "gpio_app_cfg7,GPIO_APP pin 7 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "gpio_app_tc0,GPIO_APP pin 0 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Threshold/Capture register: PWM mode (threshold): { | The counter threshold value equals the number of inactive clock cycles per period (cycles with pwm=0). Therefore it is interpreted differently in symmetrical and asymmetrical counter mode:.."
group.long 0x24++0x03
line.long 0x00 "gpio_app_tc1,GPIO_APP pin 1 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x28++0x03
line.long 0x00 "gpio_app_tc2,GPIO_APP pin 2 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x2C++0x03
line.long 0x00 "gpio_app_tc3,GPIO_APP pin 3 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x30++0x03
line.long 0x00 "gpio_app_tc4,GPIO_APP pin 4 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x34++0x03
line.long 0x00 "gpio_app_tc5,GPIO_APP pin 5 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x38++0x03
line.long 0x00 "gpio_app_tc6,GPIO_APP pin 6 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x3C++0x03
line.long 0x00 "gpio_app_tc7,GPIO_APP pin 7 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x40++0x03
line.long 0x00 "gpio_app_counter0_ctrl,GPIO_APP counter0 control register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 7.--9. "gpio_ref,gpio reference (0 - 7)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--6. "event_act,Define action of selected external event (dependent on sel_event gpio_ref)" "0: count every clock cycle ignore external events,1: count only external events (edge or level,2: enable watchdog mode of counter (external event,3: enable automatic run mode (external event sets"
newline
bitfld.long 0x00 4. "once," "0,1"
bitfld.long 0x00 3. "sel_event,select external event" "0: high level invert gpio in register gpio_app_cfg,1: pos"
newline
bitfld.long 0x00 2. "irq_en," "0,1"
bitfld.long 0x00 1. "sym_nasym," "0,1"
newline
bitfld.long 0x00 0. "run," "0,1"
group.long 0x44++0x03
line.long 0x00 "gpio_app_counter1_ctrl,GPIO_APP counter1 control register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 7.--9. "gpio_ref,analog to gpio_app_counter0_ctrl" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--6. "event_act,analog to gpio_app_counter0_ctrl" "0,1,2,3"
newline
bitfld.long 0x00 4. "once,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 3. "sel_event,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 2. "irq_en,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 1. "sym_nasym,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 0. "run,analog to gpio_app_counter0_ctrl" "0,1"
group.long 0x48++0x03
line.long 0x00 "gpio_app_counter2_ctrl,GPIO_APP counter2 control register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 7.--9. "gpio_ref,analog to gpio_app_counter0_ctrl" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--6. "event_act,analog to gpio_app_counter0_ctrl" "0,1,2,3"
newline
bitfld.long 0x00 4. "once,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 3. "sel_event,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 2. "irq_en,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 1. "sym_nasym,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 0. "run,analog to gpio_app_counter0_ctrl" "0,1"
group.long 0x4C++0x03
line.long 0x00 "gpio_app_counter0_max,GPIO_APP counter0 max value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc"
group.long 0x50++0x03
line.long 0x00 "gpio_app_counter1_max,GPIO_APP counter1 max value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc"
group.long 0x54++0x03
line.long 0x00 "gpio_app_counter2_max,GPIO_APP counter2 max value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc"
group.long 0x58++0x03
line.long 0x00 "gpio_app_counter0_cnt,GPIO_APP counter0 current value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,current counter value"
group.long 0x5C++0x03
line.long 0x00 "gpio_app_counter1_cnt,GPIO_APP counter1 current value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,current counter value"
group.long 0x60++0x03
line.long 0x00 "gpio_app_counter2_cnt,GPIO_APP counter2 current value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,current counter value"
group.long 0x64++0x03
line.long 0x00 "gpio_app_line,GPIO_APP line register This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long.byte 0x00 0.--7. 1. "val,gpio_app output values"
rgroup.long 0x68++0x03
line.long 0x00 "gpio_app_in,GPIO_APP latched inputs register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long.byte 0x00 0.--7. 1. "val,gpio_app input values"
group.long 0x6C++0x03
line.long 0x00 "gpio_app_irq_raw,GPIO_APP raw IRQ register: Read access shows the status of unmasked IRQs"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
rgroup.long 0x70++0x03
line.long 0x00 "gpio_app_irq_masked,GPIO_APP masked IRQ register: This register exists 2x for the different system busses (address areas) it is connected to"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
group.long 0x74++0x03
line.long 0x00 "gpio_app_irq_mask_set,GPIO_APP interrupt mask set: The interrupt mask register exists 2x for the different system busses (address areas) it is connected to"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
group.long 0x78++0x03
line.long 0x00 "gpio_app_irq_mask_rst,GPIO_APP interrupt mask reset: This reset mask serves to disable the interrupt requests for the corresponding interrupt sources"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
group.long 0x7C++0x03
line.long 0x00 "gpio_app_cnt_irq_raw,Counter raw IRQ register: Read access shows the status of unmasked IRQs"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
rgroup.long 0x80++0x03
line.long 0x00 "gpio_app_cnt_irq_masked,Counter masked IRQ register: Read access shows the status of masked IRQs (cnt_irq_raw AND cnt_irq_mask)"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
group.long 0x84++0x03
line.long 0x00 "gpio_app_cnt_irq_mask_set,Counter interrupt mask set: The interrupt mask register exists 2x for the different system busses (address areas) it is connected to"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
group.long 0x88++0x03
line.long 0x00 "gpio_app_cnt_irq_mask_rst,Counter interrupt mask reset: This reset mask serves to disable the interrupt requests for the corresponding interrupt sources"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
tree.end
tree "GPIO_XPIC_APP"
base ad:0xFF900200
group.long 0x00++0x03
line.long 0x00 "gpio_app_cfg0,GPIO_APP pin 0 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,Run blink sequence only once (blink mode only)" "0,1"
bitfld.long 0x00 7.--11. "blink_len,Length of blink sequence minus 1 (blink mode only)" "0: use bit 0 of gpio_app_tc,1: use bits 0..1 of gpio_app_tc,2: use bits 0..2 of gpio_app_tc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: use bits 0..31 of gpio_app_tc"
newline
bitfld.long 0x00 5.--6. "count_ref,counter reference" "0: counter 0,1: counter 1,2: counter 2,3: sys_time (global system"
bitfld.long 0x00 4. "inv," "0,1"
newline
bitfld.long 0x00 0.--3. "mode,defines the gp input or output mode - depends on io_cfg Input modes" "0: read mode,1: capture continued at rising edge (allows,2: capture once at rising edge (reset gpio_app_irq,3: capture once at high level (reset gpio_app_irq,4: set to 0,5: set to 1,6: set to gpio_app_line[0],7: pwm mode direct threshold update (might cause,8: blink mode Multi pin modes,?,?,?,?,?,?,15: pwm2-mode with threshold update at counter=0"
group.long 0x04++0x03
line.long 0x00 "gpio_app_cfg1,GPIO_APP pin 1 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "gpio_app_cfg2,GPIO_APP pin 2 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "gpio_app_cfg3,GPIO_APP pin 3 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "gpio_app_cfg4,GPIO_APP pin 4 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "gpio_app_cfg5,GPIO_APP pin 5 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "gpio_app_cfg6,GPIO_APP pin 6 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "gpio_app_cfg7,GPIO_APP pin 7 config register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 12. "blink_once,analog to gpio_app_cfg0" "0,1"
bitfld.long 0x00 7.--11. "blink_len,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--6. "count_ref,analog to gpio_app_cfg0" "0,1,2,3"
bitfld.long 0x00 4. "inv,analog to gpio_app_cfg0" "0,1"
newline
bitfld.long 0x00 0.--3. "mode,analog to gpio_app_cfg0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "gpio_app_tc0,GPIO_APP pin 0 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Threshold/Capture register: PWM mode (threshold): { | The counter threshold value equals the number of inactive clock cycles per period (cycles with pwm=0). Therefore it is interpreted differently in symmetrical and asymmetrical counter mode:.."
group.long 0x24++0x03
line.long 0x00 "gpio_app_tc1,GPIO_APP pin 1 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x28++0x03
line.long 0x00 "gpio_app_tc2,GPIO_APP pin 2 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x2C++0x03
line.long 0x00 "gpio_app_tc3,GPIO_APP pin 3 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x30++0x03
line.long 0x00 "gpio_app_tc4,GPIO_APP pin 4 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x34++0x03
line.long 0x00 "gpio_app_tc5,GPIO_APP pin 5 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x38++0x03
line.long 0x00 "gpio_app_tc6,GPIO_APP pin 6 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x3C++0x03
line.long 0x00 "gpio_app_tc7,GPIO_APP pin 7 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,analog to gpio_app_tc0"
group.long 0x40++0x03
line.long 0x00 "gpio_app_counter0_ctrl,GPIO_APP counter0 control register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 7.--9. "gpio_ref,gpio reference (0 - 7)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--6. "event_act,Define action of selected external event (dependent on sel_event gpio_ref)" "0: count every clock cycle ignore external events,1: count only external events (edge or level,2: enable watchdog mode of counter (external event,3: enable automatic run mode (external event sets"
newline
bitfld.long 0x00 4. "once," "0,1"
bitfld.long 0x00 3. "sel_event,select external event" "0: high level invert gpio in register gpio_app_cfg,1: pos"
newline
bitfld.long 0x00 2. "irq_en," "0,1"
bitfld.long 0x00 1. "sym_nasym," "0,1"
newline
bitfld.long 0x00 0. "run," "0,1"
group.long 0x44++0x03
line.long 0x00 "gpio_app_counter1_ctrl,GPIO_APP counter1 control register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 7.--9. "gpio_ref,analog to gpio_app_counter0_ctrl" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--6. "event_act,analog to gpio_app_counter0_ctrl" "0,1,2,3"
newline
bitfld.long 0x00 4. "once,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 3. "sel_event,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 2. "irq_en,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 1. "sym_nasym,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 0. "run,analog to gpio_app_counter0_ctrl" "0,1"
group.long 0x48++0x03
line.long 0x00 "gpio_app_counter2_ctrl,GPIO_APP counter2 control register: This register is accessible via address areas inlogic_app and xpic_app_system"
bitfld.long 0x00 7.--9. "gpio_ref,analog to gpio_app_counter0_ctrl" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--6. "event_act,analog to gpio_app_counter0_ctrl" "0,1,2,3"
newline
bitfld.long 0x00 4. "once,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 3. "sel_event,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 2. "irq_en,analog to gpio_app_counter0_ctrl" "0,1"
bitfld.long 0x00 1. "sym_nasym,analog to gpio_app_counter0_ctrl" "0,1"
newline
bitfld.long 0x00 0. "run,analog to gpio_app_counter0_ctrl" "0,1"
group.long 0x4C++0x03
line.long 0x00 "gpio_app_counter0_max,GPIO_APP counter0 max value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc"
group.long 0x50++0x03
line.long 0x00 "gpio_app_counter1_max,GPIO_APP counter1 max value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc"
group.long 0x54++0x03
line.long 0x00 "gpio_app_counter2_max,GPIO_APP counter2 max value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc"
group.long 0x58++0x03
line.long 0x00 "gpio_app_counter0_cnt,GPIO_APP counter0 current value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,current counter value"
group.long 0x5C++0x03
line.long 0x00 "gpio_app_counter1_cnt,GPIO_APP counter1 current value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,current counter value"
group.long 0x60++0x03
line.long 0x00 "gpio_app_counter2_cnt,GPIO_APP counter2 current value: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long 0x00 0.--31. 1. "val,current counter value"
group.long 0x64++0x03
line.long 0x00 "gpio_app_line,GPIO_APP line register This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long.byte 0x00 0.--7. 1. "val,gpio_app output values"
rgroup.long 0x68++0x03
line.long 0x00 "gpio_app_in,GPIO_APP latched inputs register: This register is accessible via address areas inlogic_app and xpic_app_system"
hexmask.long.byte 0x00 0.--7. 1. "val,gpio_app input values"
group.long 0x6C++0x03
line.long 0x00 "gpio_app_irq_raw,GPIO_APP raw IRQ register: Read access shows the status of unmasked IRQs"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
rgroup.long 0x70++0x03
line.long 0x00 "gpio_app_irq_masked,GPIO_APP masked IRQ register: This register exists 2x for the different system busses (address areas) it is connected to"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
group.long 0x74++0x03
line.long 0x00 "gpio_app_irq_mask_set,GPIO_APP interrupt mask set: The interrupt mask register exists 2x for the different system busses (address areas) it is connected to"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
group.long 0x78++0x03
line.long 0x00 "gpio_app_irq_mask_rst,GPIO_APP interrupt mask reset: This reset mask serves to disable the interrupt requests for the corresponding interrupt sources"
bitfld.long 0x00 7. "gpio_app7,Interrupt bit for GPIO_APP7" "0,1"
bitfld.long 0x00 6. "gpio_app6,Interrupt bit for GPIO_APP6" "0,1"
newline
bitfld.long 0x00 5. "gpio_app5,Interrupt bit for GPIO_APP5" "0,1"
bitfld.long 0x00 4. "gpio_app4,Interrupt bit for GPIO_APP4" "0,1"
newline
bitfld.long 0x00 3. "gpio_app3,Interrupt bit for GPIO_APP3" "0,1"
bitfld.long 0x00 2. "gpio_app2,Interrupt bit for GPIO_APP2" "0,1"
newline
bitfld.long 0x00 1. "gpio_app1,Interrupt bit for GPIO_APP1" "0,1"
bitfld.long 0x00 0. "gpio_app0,Interrupt bit for GPIO_APP0" "0,1"
group.long 0x7C++0x03
line.long 0x00 "gpio_app_cnt_irq_raw,Counter raw IRQ register: Read access shows the status of unmasked IRQs"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
rgroup.long 0x80++0x03
line.long 0x00 "gpio_app_cnt_irq_masked,Counter masked IRQ register: Read access shows the status of masked IRQs (cnt_irq_raw AND cnt_irq_mask)"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
group.long 0x84++0x03
line.long 0x00 "gpio_app_cnt_irq_mask_set,Counter interrupt mask set: The interrupt mask register exists 2x for the different system busses (address areas) it is connected to"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
group.long 0x88++0x03
line.long 0x00 "gpio_app_cnt_irq_mask_rst,Counter interrupt mask reset: This reset mask serves to disable the interrupt requests for the corresponding interrupt sources"
bitfld.long 0x00 2. "cnt2,Interrupt bit for counter2" "0,1"
bitfld.long 0x00 1. "cnt1,Interrupt bit for counter1" "0,1"
newline
bitfld.long 0x00 0. "cnt0,Interrupt bit for counter0" "0,1"
tree.end
tree "HASH"
base ad:0xFF080000
wgroup.long 0x00++0x03
line.long 0x00 "hash_din,Hash FIFO input: Unlike all other registers this address can be written with DWord(32 Bit) Word(16 Bit) or Byte acccss"
hexmask.long 0x00 0.--31. 1. "val,data bits"
group.long 0x04++0x03
line.long 0x00 "hash_cfg,Hash config register"
bitfld.long 0x00 5. "dma_burst_only,Generate DMAC burst signal only" "0,1"
bitfld.long 0x00 4. "dma_en,Enable DMAC control signals" "0,1"
bitfld.long 0x00 3. "reset,Reset of SHA engine: After writing '1' this bit will automatically be reset" "0: start calculation as soon as enough data in..,1: reset internal registers use this to start"
bitfld.long 0x00 0.--2. "mode,Hash core mode" "0: SHA1-160,1: SHA2-256,2: SHA2-384,3: SHA2-512,4: MD5,?..."
rgroup.long 0x08++0x03
line.long 0x00 "hash_stat,Hash status register"
hexmask.long.word 0x00 0.--8. 1. "fifo_fill,Fill level of FIFO in bytes (0..256)"
rgroup.long 0x0C++0x03
line.long 0x00 "hash_debug_info,Hash info register"
hexmask.long.byte 0x00 0.--6. 1. "sha_round,7bit current state counter of the SHA core"
group.long 0x10++0x03
line.long 0x00 "hash_irq_raw,Hash raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 2. "fifo_overflow,input buffer was overflown set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 1. "fifo_underrun,input buffer was underrun set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 0. "hash_ready,Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid" "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "hash_irq_masked,Hash masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 2. "fifo_overflow,input buffer was overflown set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 1. "fifo_underrun,input buffer was underrun set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 0. "hash_ready,Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid" "0,1"
group.long 0x18++0x03
line.long 0x00 "hash_irq_msk_set,Hash IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 2. "fifo_overflow,input buffer was overflown set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 1. "fifo_underrun,input buffer was underrun set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 0. "hash_ready,Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid" "0,1"
group.long 0x1C++0x03
line.long 0x00 "hash_irq_msk_reset,Hash IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 2. "fifo_overflow,input buffer was overflown set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 1. "fifo_underrun,input buffer was underrun set hash_cfg-reset=1 to reset this bit" "0,1"
bitfld.long 0x00 0. "hash_ready,Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "hash_dout0,Hash value0 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
rgroup.long 0x24++0x03
line.long 0x00 "hash_dout1,Hash value1 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
rgroup.long 0x28++0x03
line.long 0x00 "hash_dout2,Hash value2 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
rgroup.long 0x2C++0x03
line.long 0x00 "hash_dout3,Hash value3 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
rgroup.long 0x30++0x03
line.long 0x00 "hash_dout4,Hash value4 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
rgroup.long 0x34++0x03
line.long 0x00 "hash_dout5,Hash value5 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
rgroup.long 0x38++0x03
line.long 0x00 "hash_dout6,Hash value6 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
rgroup.long 0x3C++0x03
line.long 0x00 "hash_dout7,Hash value7 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
rgroup.long 0x40++0x03
line.long 0x00 "hash_dout8,Hash value8 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
rgroup.long 0x44++0x03
line.long 0x00 "hash_dout9,Hash value9 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
rgroup.long 0x48++0x03
line.long 0x00 "hash_dout10,Hash value10 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
rgroup.long 0x4C++0x03
line.long 0x00 "hash_dout11,Hash value11 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
rgroup.long 0x50++0x03
line.long 0x00 "hash_dout12,Hash value12 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
rgroup.long 0x54++0x03
line.long 0x00 "hash_dout13,Hash value13 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
rgroup.long 0x58++0x03
line.long 0x00 "hash_dout14,Hash value14 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
rgroup.long 0x5C++0x03
line.long 0x00 "hash_dout15,Hash value15 register"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
tree.end
tree "HIF_ASYNCMEM_CTRL"
base ad:0xFF401500
group.long 0x00++0x03
line.long 0x00 "extsram0_ctrl,Control Register for external bus interface and wait-states for chip-select 0 area"
bitfld.long 0x00 31. "ready_en,Ready Signal Enable" "0: Access timing is only controlled by Wait-State,1: Use external ready input to stretch Wait-State"
bitfld.long 0x00 30. "static_cs,Static chip-select signal generation" "0: No static chip-select signal generation,1: Static chip-select signal generation enabled"
newline
bitfld.long 0x00 29. "no_p_post_seq_rd,No Post-Pause insertion between sequential reads" "0: Post-Pause will be inserted after each read..,1: Disable Post-Pause between sequential reads"
bitfld.long 0x00 28. "no_p_pre_seq_rd,No Pre-Pause insertion between sequential reads" "0: Pre-Pause will be inserted after each read..,1: Disable Pre-Pause between sequential reads"
newline
bitfld.long 0x00 24.--25. "dwidth,Data bus width of ExtMem0 area" "0: 8bit memory device connected to this..,1: 16bit memory device connected to this,2: reserved,3: memory is disabled related chip-select signal"
bitfld.long 0x00 16.--17. "p_post,Post-Pause (0 - 3 cycles) of ExtMem0 area" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "p_pre,Pre-Pause (0 - 3 cycles) of ExtMem0 area" "0,1,2,3"
bitfld.long 0x00 0.--5. "ws,Wait-States (0 - 63 cycles) of ExtMem0 area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "extsram1_ctrl,Control Register for external bus interface and wait-states for chip-select 1 area"
bitfld.long 0x00 31. "ready_en,Ready Signal Enable" "0,1"
bitfld.long 0x00 30. "static_cs,Static chip-select signal generation" "0,1"
newline
bitfld.long 0x00 29. "no_p_post_seq_rd,No Post-Pause insertion between sequential reads" "0,1"
bitfld.long 0x00 28. "no_p_pre_seq_rd,No Pre-Pause insertion between sequential reads" "0,1"
newline
bitfld.long 0x00 24.--25. "dwidth,Data bus width of ExtMem1 area" "0,1,2,3"
bitfld.long 0x00 16.--17. "p_post,Post-Pause (0 - 3 cycles) of ExtMem1 area" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "p_pre,Pre-Pause (0 - 3 cycles) of ExtMem1 area" "0,1,2,3"
bitfld.long 0x00 0.--5. "ws,Wait-States (0 - 63 cycles) of ExtMem1 area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "extsram2_ctrl,Control Register for external bus interface and wait-states for chip-select 2 area"
bitfld.long 0x00 31. "ready_en,Ready Signal Enable" "0,1"
bitfld.long 0x00 30. "static_cs,Static chip-select signal generation" "0,1"
newline
bitfld.long 0x00 29. "no_p_post_seq_rd,No Post-Pause insertion between sequential reads" "0,1"
bitfld.long 0x00 28. "no_p_pre_seq_rd,No Pre-Pause insertion between sequential reads" "0,1"
newline
bitfld.long 0x00 24.--25. "dwidth,Data bus width of ExtMem2 area" "0,1,2,3"
bitfld.long 0x00 16.--17. "p_post,Post-Pause (0 - 3 cycles) of ExtMem2 area" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "p_pre,Pre-Pause (0 - 3 cycles) of ExtMem2 area" "0,1,2,3"
bitfld.long 0x00 0.--5. "ws,Wait-States (0 - 63 cycles) of ExtMem2 area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "extsram3_ctrl,Control Register for external bus interface and wait-states for ExtMem1 chip-select 3 area"
bitfld.long 0x00 31. "ready_en,Ready Signal Enable" "0,1"
bitfld.long 0x00 30. "static_cs,Static chip-select signal generation" "0,1"
newline
bitfld.long 0x00 29. "no_p_post_seq_rd,No Post-Pause insertion between sequential reads" "0,1"
bitfld.long 0x00 28. "no_p_pre_seq_rd,No Pre-Pause insertion between sequential reads" "0,1"
newline
bitfld.long 0x00 24.--25. "dwidth,Data bus width of ExtMem3 area" "0,1,2,3"
bitfld.long 0x00 16.--17. "p_post,Post-Pause (0 - 3 cycles) of ExtMem3 area" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "p_pre,Pre-Pause (0 - 3 cycles) of ExtMem3 area" "0,1,2,3"
bitfld.long 0x00 0.--5. "ws,Wait-States (0 - 63 cycles) of ExtMem3 area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "ext_cs0_apm_ctrl,Asynchronous Page Mode (APM) Control Register for ExtMem0 chip-select area"
bitfld.long 0x00 8.--10. "apm_cfg,APM configuration" "0: read bursts are disabled,1: 1 D-word (4 byte) address boundary for APM,2: 2 D-word (8 byte) address boundary for APM,3: 4 D-word (16 byte) address boundary for APM,4: 8 D-word (32 byte) address boundary for APM,5: 16 D-word (64 byte) address boundary for APM,6: 32 D-word (128 byte) address boundary for APM,?..."
bitfld.long 0x00 0.--3. "ws_apm,APM read burst wait-states (0 - 15 cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "ext_rdy_cfg,External Memory Ready Control Register"
bitfld.long 0x00 11. "rdy_to_dis,Ready Timeout Disable By default ready timeout is enabled" "0: Ready timeout is enabled,1: Ready timeout is disabled"
bitfld.long 0x00 8. "rdy_to_irq_en,Ready Timeout IRQ Enable" "0: No IRQ generation in case of ready timeout,1: generate an IRQ in case of ready timeout"
newline
bitfld.long 0x00 4.--5. "rdy_filter,Ready Input Filter" "0: Ready active state is detected after ready,1: Ready active state is detected after ready,2: Ready active state is detected after ready,3: Ready active state is detected after ready"
bitfld.long 0x00 0. "rdy_act_level,Ready Active Level" "0: Ready is active low / stall access while ready,1: Ready is active high / stall access while ready"
group.long 0x24++0x03
line.long 0x00 "ext_rdy_status,External Memory Ready Status Register"
bitfld.long 0x00 31. "rdy_to_err,Ready Timeout Error" "0,1"
bitfld.long 0x00 28.--29. "rdy_to_err_cs,Ready timeout error chip-select logging" "0,1,2,3"
newline
hexmask.long 0x00 0.--26. 1. "rdy_to_err_adr,Ready timeout error address logging"
tree.end
tree "HIF_IO_CTRL"
base ad:0xFF401480
group.long 0x00++0x03
line.long 0x00 "hif_io_cfg,IO Config Register: Selects of HIF pin multiplexing"
bitfld.long 0x00 25. "en_hif_wdg_sys_hif_d19,Obsolete for netX90 removed by regdef filter script" "0,1"
newline
bitfld.long 0x00 24. "en_hif_rdy_pio_mi,Enable HIF_RDY for PIO usage (or other netX MUX function) when the HIF is in memory-mode" "0,1"
newline
bitfld.long 0x00 8.--11. "sel_hif_a_width,Select HIF MI address width" "0: 11 2k HIF_A0..10 A0..A10 ext_a0..ext_a10,1: 12 4k HIF_A0..11 A0..A11 + ext_a11,2: 13 8k HIF_A0..12 A0..A12 + ext_a12,3: 14 16k HIF_A0..13 A0..A13 + ext_a13,4: 15 32k HIF_A0..14 A0..A14 + ext_a14,5: 16 64k HIF_A0..15 A0..A15 + ext_a15,6: 17 128k HIF_A0..16 A0..A16 + ext_a16,7: 18 256k HIF_A0..17 A0..A17 + ext_a17} Following,?..."
newline
bitfld.long 0x00 7. "en_hif_sdram_mi,Enable HIF IOs for SDRAM Memory Interface configuration" "0,1"
newline
bitfld.long 0x00 5.--6. "hif_mi_cfg,Global HIF IO Memory Interface usage configuration" "0: HIF IOs are used as 8 bit MI,1: HIF IOs are used as 16 bit MI HIF_D0..7 are,2: reserved,3: No MI usage"
newline
bitfld.long 0x00 4. "en_sdpm1,Enables the 2nd serial DPM for netX90" "0: 2nd serial DPM is disabled,1: 2nd serial DPM is enabled"
newline
bitfld.long 0x00 3. "sel_dpm_serial_spo,serial DPM mode SPI clock polarity selection (sel_hif_dpm and sel_dpm_serial must be set)" "0: Serial clock idle state is low,1: Serial clock idle state is high"
newline
bitfld.long 0x00 2. "sel_dpm_serial_sph,serial DPM mode SPI clock phase selection (sel_hif_dpm and sel_dpm_serial must be set)" "0: Serial data sampling on first serial clock edge,1: Serial data sampling on second serial clock.."
newline
bitfld.long 0x00 1. "sel_dpm_serial,serial (SPI) DPM mode selection (ignored if sel_hif_dpm not set)" "0,1"
newline
bitfld.long 0x00 0. "sel_hif_dpm,select DPM mode for HIF (serial or parallel) Note: For parallel DPM IO configuration use config registers in address area DPM" "0,1"
group.long 0x04++0x03
line.long 0x00 "hif_pio_cfg,HIF PIO Mode configuration register"
bitfld.long 0x00 31. "filter_irqs,Filtering of HIF PIO inputs for IRQ generation" "0,1"
newline
bitfld.long 0x00 26.--27. "irq_hif_dirq_cfg,HIF_DIRQ IRQ input configuration { | Mode Function 00 low level active IRQ 01 high level active IRQ 10 falling edge active IRQ 11 rising edge active IRQ } For IRQ usage this IO should be in PIO input mode (programmed in the 'hif_io_cfg'.." "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "irq_hif_a17_cfg,HIF_A17 IRQ input configuration For coding refer to irq_hif_dirq_cfg bit-field" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "irq_hif_a16_cfg,HIF_A16 IRQ input configuration For coding refer to irq_hif_dirq_cfg bit-field" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "irq_hif_d12_cfg,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ) IRQ input configuration For coding refer to irq_hif_dirq_cfg bit-field" "0,1,2,3"
newline
bitfld.long 0x00 3. "filter_en_in,HIF PIO Input sampling enable (EN_IN) filter" "0,1"
newline
bitfld.long 0x00 0.--1. "in_ctrl,HIF PIO Input sampling mode" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "hif_pio_out0,HIF PIO Output State Configuration Register 0"
bitfld.long 0x00 15. "hif_d15,PIO output drive level of HIF_D15 signal" "0,1"
newline
bitfld.long 0x00 14. "hif_d14,PIO output drive level of HIF_D14 signal" "0,1"
newline
bitfld.long 0x00 13. "hif_d13,PIO output drive level of HIF_D13 signal" "0,1"
newline
bitfld.long 0x00 12. "hif_d12,PIO output drive level of HIF_D12 signal" "0,1"
newline
bitfld.long 0x00 11. "hif_d11,PIO output drive level of HIF_D11 signal" "0,1"
newline
bitfld.long 0x00 10. "hif_d10,PIO output drive level of HIF_D10 signal" "0,1"
newline
bitfld.long 0x00 9. "hif_d9,PIO output drive level of HIF_D9 signal" "0,1"
newline
bitfld.long 0x00 8. "hif_d8,PIO output drive level of HIF_D8 signal" "0,1"
newline
bitfld.long 0x00 7. "hif_d7,PIO output drive level of HIF_D7 signal" "0,1"
newline
bitfld.long 0x00 6. "hif_d6,PIO output drive level of HIF_D6 signal" "0,1"
newline
bitfld.long 0x00 5. "hif_d5,PIO output drive level of HIF_D5 signal" "0,1"
newline
bitfld.long 0x00 4. "hif_d4,PIO output drive level of HIF_D4 signal" "0,1"
newline
bitfld.long 0x00 3. "hif_d3,PIO output drive level of HIF_D3 signal" "0,1"
newline
bitfld.long 0x00 2. "hif_d2,PIO output drive level of HIF_D2 signal" "0,1"
newline
bitfld.long 0x00 1. "hif_d1,PIO output drive level of HIF_D1 signal" "0,1"
newline
bitfld.long 0x00 0. "hif_d0,PIO output drive level of HIF_D0 signal" "0,1"
group.long 0x0C++0x03
line.long 0x00 "hif_pio_out1,HIF PIO Output State Configuration Register 1"
bitfld.long 0x00 31. "hif_sdclk,PIO output drive level of HIF_SDCLK signal" "0,1"
newline
bitfld.long 0x00 30. "hif_dirq,PIO output drive level of HIF_DIRQ signal" "0,1"
newline
bitfld.long 0x00 29. "hif_rdy,PIO output drive level of HIF_RDY signal" "0,1"
newline
bitfld.long 0x00 28. "hif_csn,PIO output drive level of HIF_CSN signal" "0,1"
newline
bitfld.long 0x00 27. "hif_wrn,PIO output drive level of HIF_WRN signal" "0,1"
newline
bitfld.long 0x00 26. "hif_rdn,PIO output drive level of HIF_RDN signal" "0,1"
newline
bitfld.long 0x00 25. "hif_bhen,PIO output drive level of HIF_BHEN signals" "0,1"
newline
bitfld.long 0x00 17. "hif_a17,PIO output drive level of HIF_A17 signal" "0,1"
newline
bitfld.long 0x00 16. "hif_a16,PIO output drive level of HIF_A16 signal" "0,1"
newline
bitfld.long 0x00 15. "hif_a15,PIO output drive level of HIF_A15 signal" "0,1"
newline
bitfld.long 0x00 14. "hif_a14,PIO output drive level of HIF_A14 signal" "0,1"
newline
bitfld.long 0x00 13. "hif_a13,PIO output drive level of HIF_A13 signal" "0,1"
newline
bitfld.long 0x00 12. "hif_a12,PIO output drive level of HIF_A12 signal" "0,1"
newline
bitfld.long 0x00 11. "hif_a11,PIO output drive level of HIF_A11 signal" "0,1"
newline
bitfld.long 0x00 10. "hif_a10,PIO output drive level of HIF_A10 signal" "0,1"
newline
bitfld.long 0x00 9. "hif_a9,PIO output drive level of HIF_A9 signal" "0,1"
newline
bitfld.long 0x00 8. "hif_a8,PIO output drive level of HIF_A8 signal" "0,1"
newline
bitfld.long 0x00 7. "hif_a7,PIO output drive level of HIF_A7 signal" "0,1"
newline
bitfld.long 0x00 6. "hif_a6,PIO output drive level of HIF_A6 signal" "0,1"
newline
bitfld.long 0x00 5. "hif_a5,PIO output drive level of HIF_A5 signal" "0,1"
newline
bitfld.long 0x00 4. "hif_a4,PIO output drive level of HIF_A4 signal" "0,1"
newline
bitfld.long 0x00 3. "hif_a3,PIO output drive level of HIF_A3 signal" "0,1"
newline
bitfld.long 0x00 2. "hif_a2,PIO output drive level of HIF_A2 signal" "0,1"
newline
bitfld.long 0x00 1. "hif_a1,PIO output drive level of HIF_A1 signal" "0,1"
newline
bitfld.long 0x00 0. "hif_a0,PIO output drive level of HIF_A0 signal" "0,1"
group.long 0x10++0x03
line.long 0x00 "hif_pio_oe0,HIF PIO Output Enable Configuration Register 0"
bitfld.long 0x00 15. "hif_d15,PIO output enable of HIF_D15 signal" "0,1"
newline
bitfld.long 0x00 14. "hif_d14,PIO output enable of HIF_D14 signal" "0,1"
newline
bitfld.long 0x00 13. "hif_d13,PIO output enable of HIF_D13 signal" "0,1"
newline
bitfld.long 0x00 12. "hif_d12,PIO output enable of HIF_D12 signal" "0,1"
newline
bitfld.long 0x00 11. "hif_d11,PIO output enable of HIF_D11 signal" "0,1"
newline
bitfld.long 0x00 10. "hif_d10,PIO output enable of HIF_D10 signal" "0,1"
newline
bitfld.long 0x00 9. "hif_d9,PIO output enable of HIF_D9 signal" "0,1"
newline
bitfld.long 0x00 8. "hif_d8,PIO output enable of HIF_D8 signal" "0,1"
newline
bitfld.long 0x00 7. "hif_d7,PIO output enable of HIF_D7 signal" "0,1"
newline
bitfld.long 0x00 6. "hif_d6,PIO output enable of HIF_D6 signal" "0,1"
newline
bitfld.long 0x00 5. "hif_d5,PIO output enable of HIF_D5 signal" "0,1"
newline
bitfld.long 0x00 4. "hif_d4,PIO output enable of HIF_D4 signal" "0,1"
newline
bitfld.long 0x00 3. "hif_d3,PIO output enable of HIF_D3 signal" "0,1"
newline
bitfld.long 0x00 2. "hif_d2,PIO output enable of HIF_D2 signal" "0,1"
newline
bitfld.long 0x00 1. "hif_d1,PIO output enable of HIF_D1 signal" "0,1"
newline
bitfld.long 0x00 0. "hif_d0,PIO output enable of HIF_D0 signal" "0,1"
group.long 0x14++0x03
line.long 0x00 "hif_pio_oe1,HIF PIO Output Enable Configuration Register 1"
bitfld.long 0x00 31. "hif_sdclk,PIO output enable of HIF_SDCLK signal" "0,1"
newline
bitfld.long 0x00 30. "hif_dirq,PIO output enable of HIF_DIRQ signal" "0,1"
newline
bitfld.long 0x00 29. "hif_rdy,PIO output enable of HIF_RDY signal" "0,1"
newline
bitfld.long 0x00 28. "hif_csn,PIO output enable of HIF_CSN signal" "0,1"
newline
bitfld.long 0x00 27. "hif_wrn,PIO output enable of HIF_WRN signal" "0,1"
newline
bitfld.long 0x00 26. "hif_rdn,PIO output enable of HIF_RDN signal" "0,1"
newline
bitfld.long 0x00 25. "hif_bhen,PIO output enable of HIF_BHEN signals" "0,1"
newline
bitfld.long 0x00 17. "hif_a17,PIO output enable of HIF_A17 signal" "0,1"
newline
bitfld.long 0x00 16. "hif_a16,PIO output enable of HIF_A16 signal" "0,1"
newline
bitfld.long 0x00 15. "hif_a15,PIO output enable of HIF_A15 signal" "0,1"
newline
bitfld.long 0x00 14. "hif_a14,PIO output enable of HIF_A14 signal" "0,1"
newline
bitfld.long 0x00 13. "hif_a13,PIO output enable of HIF_A13 signal" "0,1"
newline
bitfld.long 0x00 12. "hif_a12,PIO output enable of HIF_A12 signal" "0,1"
newline
bitfld.long 0x00 11. "hif_a11,PIO output enable of HIF_A11 signal" "0,1"
newline
bitfld.long 0x00 10. "hif_a10,PIO output enable of HIF_A10 signal" "0,1"
newline
bitfld.long 0x00 9. "hif_a9,PIO output enable of HIF_A9 signal" "0,1"
newline
bitfld.long 0x00 8. "hif_a8,PIO output enable of HIF_A8 signal" "0,1"
newline
bitfld.long 0x00 7. "hif_a7,PIO output enable of HIF_A7 signal" "0,1"
newline
bitfld.long 0x00 6. "hif_a6,PIO output enable of HIF_A6 signal" "0,1"
newline
bitfld.long 0x00 5. "hif_a5,PIO output enable of HIF_A5 signal" "0,1"
newline
bitfld.long 0x00 4. "hif_a4,PIO output enable of HIF_A4 signal" "0,1"
newline
bitfld.long 0x00 3. "hif_a3,PIO output enable of HIF_A3 signal" "0,1"
newline
bitfld.long 0x00 2. "hif_a2,PIO output enable of HIF_A2 signal" "0,1"
newline
bitfld.long 0x00 1. "hif_a1,PIO output enable of HIF_A1 signal" "0,1"
newline
bitfld.long 0x00 0. "hif_a0,PIO output enable of HIF_A0 signal" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "hif_pio_in0,HIF PIO Input State Register 0"
bitfld.long 0x00 15. "hif_d15,PIO input state of HIF_D15 signal" "0,1"
newline
bitfld.long 0x00 14. "hif_d14,PIO input state of HIF_D14 signal" "0,1"
newline
bitfld.long 0x00 13. "hif_d13,PIO input state of HIF_D13 signal" "0,1"
newline
bitfld.long 0x00 12. "hif_d12,PIO input state of HIF_D12 signal" "0,1"
newline
bitfld.long 0x00 11. "hif_d11,PIO input state of HIF_D11 signal" "0,1"
newline
bitfld.long 0x00 10. "hif_d10,PIO input state of HIF_D10 signal" "0,1"
newline
bitfld.long 0x00 9. "hif_d9,PIO input state of HIF_D9 signal" "0,1"
newline
bitfld.long 0x00 8. "hif_d8,PIO input state of HIF_D8 signal" "0,1"
newline
bitfld.long 0x00 7. "hif_d7,PIO input state of HIF_D7 signal" "0,1"
newline
bitfld.long 0x00 6. "hif_d6,PIO input state of HIF_D6 signal" "0,1"
newline
bitfld.long 0x00 5. "hif_d5,PIO input state of HIF_D5 signal" "0,1"
newline
bitfld.long 0x00 4. "hif_d4,PIO input state of HIF_D4 signal" "0,1"
newline
bitfld.long 0x00 3. "hif_d3,PIO input state of HIF_D3 signal" "0,1"
newline
bitfld.long 0x00 2. "hif_d2,PIO input state of HIF_D2 signal" "0,1"
newline
bitfld.long 0x00 1. "hif_d1,PIO input state of HIF_D1 signal" "0,1"
newline
bitfld.long 0x00 0. "hif_d0,PIO input state of HIF_D0 signal" "0,1"
rgroup.long 0x1C++0x03
line.long 0x00 "hif_pio_in1,HIF PIO Input State Register 1"
bitfld.long 0x00 31. "hif_sdclk,PIO input state of HIF_SDCLK signal" "0,1"
newline
bitfld.long 0x00 30. "hif_dirq,PIO input state of HIF_DIRQ signal" "0,1"
newline
bitfld.long 0x00 29. "hif_rdy,PIO input state of HIF_RDY signal" "0,1"
newline
bitfld.long 0x00 28. "hif_csn,PIO input state of HIF_CSN signal" "0,1"
newline
bitfld.long 0x00 27. "hif_wrn,PIO input state of HIF_WRN signal" "0,1"
newline
bitfld.long 0x00 26. "hif_rdn,PIO input state of HIF_RDN signal" "0,1"
newline
bitfld.long 0x00 25. "hif_bhen,PIO input state of HIF_BHEN signal" "0,1"
newline
bitfld.long 0x00 17. "hif_a17,PIO input state of HIF_A17 signal" "0,1"
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bitfld.long 0x00 16. "hif_a16,PIO input state of HIF_A16 signal" "0,1"
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bitfld.long 0x00 15. "hif_a15,PIO input state of HIF_A15 signal" "0,1"
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bitfld.long 0x00 14. "hif_a14,PIO input state of HIF_A14 signal" "0,1"
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bitfld.long 0x00 13. "hif_a13,PIO input state of HIF_A13 signal" "0,1"
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bitfld.long 0x00 12. "hif_a12,PIO input state of HIF_A12 signal" "0,1"
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bitfld.long 0x00 11. "hif_a11,PIO input state of HIF_A11 signal" "0,1"
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bitfld.long 0x00 10. "hif_a10,PIO input state of HIF_A10 signal" "0,1"
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bitfld.long 0x00 9. "hif_a9,PIO input state of HIF_A9 signal" "0,1"
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bitfld.long 0x00 8. "hif_a8,PIO input state of HIF_A8 signal" "0,1"
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bitfld.long 0x00 7. "hif_a7,PIO input state of HIF_A7 signal" "0,1"
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bitfld.long 0x00 6. "hif_a6,PIO input state of HIF_A6 signal" "0,1"
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bitfld.long 0x00 5. "hif_a5,PIO input state of HIF_A5 signal" "0,1"
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bitfld.long 0x00 4. "hif_a4,PIO input state of HIF_A4 signal" "0,1"
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bitfld.long 0x00 3. "hif_a3,PIO input state of HIF_A3 signal" "0,1"
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bitfld.long 0x00 2. "hif_a2,PIO input state of HIF_A2 signal" "0,1"
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bitfld.long 0x00 1. "hif_a1,PIO input state of HIF_A1 signal" "0,1"
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bitfld.long 0x00 0. "hif_a0,PIO input state of HIF_A0 signal" "0,1"
rgroup.long 0x24++0x03
line.long 0x00 "hif_pio_irq_raw,HIF PIO Raw (before masking) IRQ Status Register"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
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bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
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bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
group.long 0x28++0x03
line.long 0x00 "hif_pio_irq_arm_mask_set,HIF PIO Interrupt Mask Register for netX internal ARM"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
newline
bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
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bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "hif_pio_irq_arm_mask_reset,HIF PIO Interrupt Mask Reset Register for netX internal ARM"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
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bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
newline
bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "hif_pio_irq_arm_masked,HIF PIO Masked Interrupt Status Register for netX internal ARM"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
newline
bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
newline
bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
group.long 0x34++0x03
line.long 0x00 "hif_pio_irq_xpic_mask_set,HIF PIO Interrupt Mask Register for netX internal xPIC"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
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bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
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bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
group.long 0x38++0x03
line.long 0x00 "hif_pio_irq_xpic_mask_reset,HIF PIO Interrupt Mask Reset Register for netX internal xPIC"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
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bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
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bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
rgroup.long 0x3C++0x03
line.long 0x00 "hif_pio_irq_xpic_masked,HIF PIO Masked Interrupt Status Register for netX internal xPIC"
bitfld.long 0x00 3. "irq_hif_dirq,HIF_DIRQ IRQ" "0,1"
newline
bitfld.long 0x00 2. "irq_hif_a17,HIF_A17 IRQ" "0,1"
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bitfld.long 0x00 1. "irq_hif_a16,HIF_A16 IRQ" "0,1"
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bitfld.long 0x00 0. "irq_hif_d12,HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)" "0,1"
tree.end
tree "HIF_SDRAM_CTRL"
base ad:0xFF401540
group.long 0x00++0x03
line.long 0x00 "sdram_general_ctrl,Control Register for external SDRAM access"
bitfld.long 0x00 31. "refresh_status,Refresh status flag" "0,1"
bitfld.long 0x00 30. "sdram_ready,SDRAM ready" "0,1"
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bitfld.long 0x00 24.--25. "refresh_mode,Refresh request generation mode" "0: fix interval,1: collect up to 8 refreshes (default),2: collect up to 16 refreshes,3: collect up to 2047 refreshes"
bitfld.long 0x00 19. "ctrl_en,Global SDRAM controller enable" "0,1"
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bitfld.long 0x00 18. "extclk_en,external SDRAM clock enable" "0: SDRAM clock disabled (default),1: SDRAM clock enabled"
bitfld.long 0x00 17. "sdram_pwdn,SDRAM power down If this bit is set the controller will move SDRAM to power down self refresh mode (no data loss) and stop the external SDRAM clock" "0,1"
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bitfld.long 0x00 16. "dbus16,SDRAM data bus width" "0: SDRAM data bus is 8 bit wide (default),1: SDRAM data bus is 16 bit wide"
bitfld.long 0x00 8.--10. "columns,Number of SDRAM device columns and address lines" "0: 256 columns address lines A0..A7 (default),1: 512 columns address lines A0..A8,2: 1k columns address lines A0..A9,3: 2k columns address lines A0..A9 A11,4: 4k columns address lines A0..A9 A11 A12 All,?..."
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bitfld.long 0x00 4.--5. "rows,Number of SDRAM device rows and address lines" "0: 2k rows address lines A0..A10 (default),1: 4k rows address lines A0..A11,2: 8k rows address lines A0..A12,?..."
bitfld.long 0x00 0.--1. "banks,Number of SDRAM device banks and address lines" "0: 2 banks address (BA0),1: 4 banks address lines (BA1 BA0)(default) All,?..."
group.long 0x04++0x03
line.long 0x00 "sdram_timing_ctrl,Control Register for external SDRAM access"
bitfld.long 0x00 28. "bypass_neg_delay,Bypass data sample clock phase shift" "0: use phase shifted (negative delayed) SDRAM,1: bypass phase shift logic for SDRAM data.."
bitfld.long 0x00 24.--26. "data_sample_phase,Data sample clock phase shift" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "mem_sdclk_phase,MEM_SDCLK phase shift" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--17. "t_REFI,Average periodic refresh interval (3.90 us * 2^t_REFI 00 : 3.90 us 01 : 7.80 us (default) 10 : 15.60 us 11 : 31.20 us Note: Typically refresh of SDRAM devices is specified by a certain number of refreshes that must be performed within a certain.." "0: 3.90 us,1: 7.80 us (default),2: 15.60 us,3: 31.20 us"
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bitfld.long 0x00 12.--15. "t_RFC,REFRESH to next command time (clk = tRFC + 4)" "0: 4 clks,1: 5 clks and so on,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 19 clks (default)"
bitfld.long 0x00 8.--10. "t_RAS,ACTIVE to PRECHARGE command time (clk = t_RAS + 3)" "0: 3 clks,1: 4 clks and so on,?,?,?,?,?,7: 10 clks (default)"
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bitfld.long 0x00 6.--7. "t_RP,Precharge command period time (PRECHARGE to next command)" "0: 1 clk,1: 2 clks,2: 3 clks (default),3: reserved"
bitfld.long 0x00 4.--5. "t_WR,Write recovery time (last write data to PRECHARGE)" "0: 1 clk,1: 2 clks,2: 3 clks (default),3: reserved"
newline
bitfld.long 0x00 0.--1. "t_RCD,ACTIVE to READ or WRITE time (RAS to CAS clk = t_RCD) This value will be also taken as t_RRD (ACTIVE bank A to ACTIVE bank B time)" "0: 1 clk,1: 2 clks,2: 3 clks (default),3: reserved"
group.long 0x08++0x03
line.long 0x00 "sdram_mr,Mode Register for SDRAM device"
hexmask.long.word 0x00 0.--13. 1. "MR,SDRAM Mode Register"
tree.end
tree "HIFMEM_PRIORITY_CTRL"
base ad:0xFF401580
group.long 0x00++0x03
line.long 0x00 "extmem_prio_timslot_ctrl,Memory interface master timeslot priority control register"
bitfld.long 0x00 16.--18. "ts_length_shared_mi,0..7: the timeslot of hifmem-master 4 is on external memory interface 64*2^ts_length_shared_mi systen clock cycles" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "ts_length_arm_app_i,0..7: the timeslot of hifmem-master 3 is on external memory interface 64*2^ts_length_arm_app_i systen clock cycles" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "ts_length_arm_app_d,0..7: the timeslot of hifmem-master 2 is on external memory interface 64*2^ts_length_arm_app_d systen clock cycles" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "ts_length_arm_com_i,0..7: the timeslot of hifmem-master 1 is on external memory interface 64*2^ts_length_arm_com_i systen clock cycles" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "ts_length_arm_com_d,0..7: the timeslot of hifmem-master 0 is on external memory interface 64*2^ts_length_arm_com_d systen clock cycles" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "extmem_prio_accesstime_ctrl,Control Register for master channel accesses per timeslot on external meory interface"
bitfld.long 0x00 24.--29. "ts_accessrate_shared_mi,0..63: hifmem-master 4 is alowed to request ((ts_accessrate_shared_mi*ts_length_shared_mi)/64) + 1 accesses on external memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "ts_accessrate_arm_app_i,0..63: hifmem-master 3 is alowed to request ((ts_accessrate_arm_app_i*ts_length_arm_app_i)/64) + 1 accesses on external memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 12.--17. "ts_accessrate_arm_app_d,0..63: hifmem-master 2 is alowed to request ((ts_accessrate_arm_app_d*ts_length_arm_app_d)/64) + 1 accesses on external memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--11. "ts_accessrate_arm_com_i,0..63: hifmem-master 1 is alowed to request ((ts_accessrate_arm_com_i*ts_length_arm_com_i)/64) + 1 accesses on external memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "ts_accessrate_arm_com_d,0..63: hifmem-master 0 is alowed to request ((ts_accessrate_arm_com_d*ts_length_arm_com_d)/64) + 1 accesses on external memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "I2C_APP"
base ad:0xFF801080
group.long 0x00++0x03
line.long 0x00 "i2c_mcr,I2C master control register"
bitfld.long 0x00 18. "en_timeout,Enable I2C command timeout detection" "0,1"
bitfld.long 0x00 17. "rst_i2c,Reset the I2C bus-state-detection logic" "0,1"
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bitfld.long 0x00 16. "pio_mode,If this bit is set SCL and SDA can be controlled directly by register i2c_pio (e.g. to access devices being incompatible with I2C)" "0,1"
hexmask.long.byte 0x00 4.--10. 1. "sadr,7-bit slave address sent after (r)START: For 10-bit addressing the first byte (10-bit start '11110' address bits[9:8] must be programmed here. The second start byte (lower slave address bits) must be on top of the master FIFO (i2c_mdr). This.."
newline
bitfld.long 0x00 1.--3. "mode,I2C-speed-mode: If this device is used as a slave only the mode should be set to the data rate generated by the fastest master on the I2C-bus for appropriate input filtering and spike suppression" "0: Fast/Standard mode 50 kbit/s,1: Fast/Standard mode 100 kbit/s,2: Fast/Standard mode 200 kbit/s,3: Fast/Standard mode 400 kbit/s,4: High-speed mode 800 kbit/s,5: High-speed mode 1.2 Mbit/s,6: High-speed mode 1.7 Mbit/s,7: High-speed mode 3.4 Mbit/s)"
bitfld.long 0x00 0. "en_i2c,Global I2C controller enable" "0: Disable I2C controller Disabling the I2C module,1: Enable I2C controller"
group.long 0x04++0x03
line.long 0x00 "i2c_scr,I2C slave control register"
bitfld.long 0x00 20. "autoreset_ac_start,Auto reset ac_start (ac_start must be set again after any (r)START)" "0: ac_start will not be reset automatically (netX,1: Reset ac_start after this slave acknowledged a"
bitfld.long 0x00 18. "ac_gcall,General call acknowledge" "0: Do not generate an acknowledge after a general,1: Generate an acknowledge after a general call"
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bitfld.long 0x00 17. "ac_start,Enable start sequence acknowledge: If the received address matches the sid-bits the start-byte (2 bytes if sid10 is set) will be acknowledged" "0: Do not generate an acknowledge after the start,1: Generate an acknowledge after the start.."
bitfld.long 0x00 16. "ac_srx,Enable slave-receive-data acknowledge" "0: Do not acknowledge receive bytes,1: Acknowledge receive bytes If the slave FIFO is"
newline
bitfld.long 0x00 10. "sid10,10-bit slave device ID/address" "0: Wait for 7-bit slave address after (r)START,1: Wait for 10-bit slave address after (r)START"
hexmask.long.word 0x00 0.--9. 1. "sid,Slave device ID/address: External masters can address this device (this I2C module in slave mode) by the ID/address programmed here"
group.long 0x08++0x03
line.long 0x00 "i2c_cmd,I2C master command register"
hexmask.long.byte 0x00 20.--27. 1. "acpollmax,Number of tries (acpollmax+1 i.e. 1 to 256) for start sequence acknowledge polling: For 7-bit addressing acknowledge polling START and the first byte containing the slave address (i2c_mcr.sadr) will be repeated up to acpollmax+1 times until a.."
hexmask.long.word 0x00 8.--17. 1. "tsize,Transfer tsize+1 bytes (1...1024): If no acknowledge is generated by the slave (receiver) write transfers will be terminated and IRQ cmd_err will be generated"
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bitfld.long 0x00 1.--3. "cmd,I2C sequence command: All commands will generate IRQ cmd_ok or IRQ cmd_err" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "nwr,Transfer direction (not-write/read)" "0: cmd will be executed as,1: cmd will be executed as read Master"
group.long 0x0C++0x03
line.long 0x00 "i2c_mdr,I2C master data register (master FIFO): There is only one FIFO for both receive and transmit master data with a depth of 16 bytes"
hexmask.long.byte 0x00 0.--7. 1. "mdata,I2C master transmit or receive data: Write data will be removed from the FIFO after the receiving slave has generated the corresponding acknowledge"
group.long 0x10++0x03
line.long 0x00 "i2c_sdr,I2C slave data register (slave FIFO): There is only one FIFO for both receive and transmit slave data with a depth of 16 bytes"
hexmask.long.byte 0x00 0.--7. 1. "sdata,I2C slave transmit or receive data: The software must handle i2c_scr.ac_start correctly to avoid FIFO errors after (r)START"
group.long 0x14++0x03
line.long 0x00 "i2c_mfifo_cr,I2C master FIFO control register"
bitfld.long 0x00 8. "mfifo_clr,Clear master data FIFO write only bit" "0,1"
bitfld.long 0x00 0.--3. "mfifo_wm,Master FIFO watermark for the generation of IRQ mfifo_req: If the master is the transmitter (enabled and i2c_cmd.nwr is 0) IRQ mfifo_req is generated if mfifo_level&lt mfifo_wm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "i2c_sfifo_cr,I2C slave FIFO control register"
bitfld.long 0x00 8. "sfifo_clr,Clear slave data FIFO write only bit" "0,1"
bitfld.long 0x00 0.--3. "sfifo_wm,Slave FIFO watermark for the generation of IRQ sfifo_req: If the slave is the transmitter (start sequence with set read bit was acknowledged by this slave) IRQ sfifo_req is generated if sfifo_level&lt sfifo_wm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "i2c_sr,I2C status register"
bitfld.long 0x00 31. "sda_state,SDA signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit" "0,1"
bitfld.long 0x00 30. "scl_state,SCL signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit" "0,1"
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bitfld.long 0x00 28. "timeout,I2C command timeout detection (for I2C master)" "0,1"
bitfld.long 0x00 27. "sid10_aced,10-bit slave address acknowledge state" "0: There was no 10-bit slave address or it was not,1: A 10-bit slave address was broadcasted and a"
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bitfld.long 0x00 26. "gcall_aced,General call acknowledge state" "0: No general call start-byte or general call,1: The slave side of the i2c module received and"
bitfld.long 0x00 25. "nwr_aced,Transfer direction (nwr-bit) of the last acknowledged start-byte (or 2-byte start sequence for 10-bit addressing)" "0: The last acknowledged start-byte defined a..,1: The last acknowledged start-byte defined a read"
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bitfld.long 0x00 24. "last_ac,Last acknowledge detected on bus" "0: SDA was high at the last acknowledge i.e,1: SDA was low at the last acknowledge i.e"
bitfld.long 0x00 23. "slave_access,Slave access state" "0: No slave access to this device,1: A master addressed this slave device"
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bitfld.long 0x00 22. "started,START condition detection" "0: The bus is idle (STOP was detected not started),1: (r)START was detected on the bus"
bitfld.long 0x00 21. "nwr,Transfer direction detected after last (r)START" "0: The last start-byte defined a write transfer,1: The last start-byte defined a read transfer"
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bitfld.long 0x00 20. "bus_master,Bus arbitration state" "0: Master lost I2C bus arbitration bus is busy by,1: Master gains I2C bus arbitration or bus is idle"
bitfld.long 0x00 19. "sfifo_err_undr,Slave FIFO underrun error occurred" "0,1"
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bitfld.long 0x00 18. "sfifo_err_ovfl,Slave FIFO overflow error occurred" "0,1"
bitfld.long 0x00 17. "sfifo_full,Slave FIFO is full (1 if full) This is a read-only status bit" "0,1"
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bitfld.long 0x00 16. "sfifo_empty,Slave FIFO is empty (1 if empty) This is a read-only status bit" "0,1"
bitfld.long 0x00 10.--14. "sfifo_level,Slave FIFO level (0..16) This is a read-only status bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 9. "mfifo_err_undr,Master FIFO underrun error occurred" "0,1"
bitfld.long 0x00 8. "mfifo_err_ovfl,Master FIFO overflow error occurred" "0,1"
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bitfld.long 0x00 7. "mfifo_full,Master FIFO is full (1 if full) This is a read-only status bit" "0,1"
bitfld.long 0x00 6. "mfifo_empty,Master FIFO is empty (1 if empty) This is a read-only status bit" "0,1"
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bitfld.long 0x00 0.--4. "mfifo_level,Master FIFO level (0..16) This is a read-only status bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20++0x03
line.long 0x00 "i2c_irqmsk,I2C interrupt mask set or clear register: These bits have AND-mask character"
bitfld.long 0x00 6. "sreq,Slave request interrupt mask" "0,1"
bitfld.long 0x00 5. "sfifo_req,Slave FIFO action request interrupt mask" "0,1"
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bitfld.long 0x00 4. "mfifo_req,Master FIFO action request interrupt mask" "0,1"
bitfld.long 0x00 3. "bus_busy,External I2C-bus is busy interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "fifo_err,FIFO error interrupt mask" "0,1"
bitfld.long 0x00 1. "cmd_err,Command error interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "cmd_ok,Command OK interrupt mask" "0,1"
group.long 0x24++0x03
line.long 0x00 "i2c_irqsr,I2C interrupt state register (raw interrupt before masking): Writing '1' will clear the corresponding IRQ"
bitfld.long 0x00 6. "sreq,Unmasked slave request interrupt state: Purpose: Set up slave FIFO" "0: Slave is not requested,1: External master was running START-sequence and"
bitfld.long 0x00 5. "sfifo_req,Unmasked slave FIFO action request interrupt state: Purpose: Slave FIFO should be updated" "0: Slave FIFO state not critical,1: Slave FIFO request"
newline
bitfld.long 0x00 4. "mfifo_req,Unmasked master FIFO action request interrupt state: Purpose: Master FIFO should be updated" "0: Master FIFO state not critical,1: Master FIFO request"
bitfld.long 0x00 3. "bus_busy,Unmasked external I2C-bus is busy interrupt state: Purpose: Detect I2C-bus arbitration loss" "0: Bus is idle or no transfer is requested by this,1: Master did not gain the requested bus access"
newline
bitfld.long 0x00 2. "fifo_err,Unmasked FIFO error interrupt state: Purpose: Detect FIFO errors/transfer failures" "0: FIFOs ok,1: FIFO error occurred"
bitfld.long 0x00 1. "cmd_err,Unmasked command error interrupt state: Purpose: Check last command termination" "0: Command not finished no command or command,1: Last command finished erroneously"
newline
bitfld.long 0x00 0. "cmd_ok,Unmasked command OK interrupt state: Purpose: Check last command termination" "0: Command not finished no command or command,1: Last command finished successfully"
rgroup.long 0x28++0x03
line.long 0x00 "i2c_irqmsked,I2C masked interrupt state register: If one of these bits is set the I2C IRQ will be set to the interrupt controller"
bitfld.long 0x00 6. "sreq,Masked slave request interrupt state" "0,1"
bitfld.long 0x00 5. "sfifo_req,Masked slave FIFO action request interrupt state" "0,1"
newline
bitfld.long 0x00 4. "mfifo_req,Masked master FIFO action request interrupt state" "0,1"
bitfld.long 0x00 3. "bus_busy,Masked external I2C-bus is busy interrupt state" "0,1"
newline
bitfld.long 0x00 2. "fifo_err,Masked FIFO error interrupt state" "0,1"
bitfld.long 0x00 1. "cmd_err,Masked command error interrupt state" "0,1"
newline
bitfld.long 0x00 0. "cmd_ok,Masked command OK interrupt state" "0,1"
group.long 0x2C++0x03
line.long 0x00 "i2c_dmacr,I2C DMA control register: Required settings for the DMA controller: - DMA transfer size to/from I2C module: Byte - DMA burst length to/from I2C module: 4 DMA burst requests will be generated if the corresponding FIFO contains more than 4 bytes.."
bitfld.long 0x00 3. "sdmab_en,Enable DMA burst requests for I2C slave data" "0,1"
bitfld.long 0x00 2. "sdmas_en,Enable DMA single requests for I2C slave data" "0,1"
newline
bitfld.long 0x00 1. "mdmab_en,Enable DMA burst requests for I2C master data" "0,1"
bitfld.long 0x00 0. "mdmas_en,Enable DMA single requests for I2C master data" "0,1"
group.long 0x30++0x03
line.long 0x00 "i2c_pio,PIO mode register: This register can directly control the I2C signals SCL and SDA if pio_mode is enabled in register i2c_mcr"
bitfld.long 0x00 6. "sda_in_ro,SDA input state (read-only)" "0,1"
bitfld.long 0x00 5. "sda_oe,SDA output enable" "0: Do not drive SDA switch pad to high-z,1: Drive SDA switch pad to programmed.."
newline
bitfld.long 0x00 4. "sda_out,Driving level of SDA (1: high 0: low) if output is enabled (sda_oe is set)" "0,1"
bitfld.long 0x00 2. "scl_in_ro,SCL input state (read-only)" "0,1"
newline
bitfld.long 0x00 1. "scl_oe,SCL output enable" "0: Do not drive SCL switch pad to high-z,1: Drive SCL switch pad to programmed.."
bitfld.long 0x00 0. "scl_out,Driving level of SCL (1: high 0: low) if output is enabled (scl_oe is set)" "0,1"
tree.end
tree "I2C_XPIC_APP"
base ad:0xFF900340
group.long 0x00++0x03
line.long 0x00 "i2c_mcr,I2C master control register"
bitfld.long 0x00 18. "en_timeout,Enable I2C command timeout detection" "0,1"
bitfld.long 0x00 17. "rst_i2c,Reset the I2C bus-state-detection logic" "0,1"
newline
bitfld.long 0x00 16. "pio_mode,If this bit is set SCL and SDA can be controlled directly by register i2c_pio (e.g. to access devices being incompatible with I2C)" "0,1"
hexmask.long.byte 0x00 4.--10. 1. "sadr,7-bit slave address sent after (r)START: For 10-bit addressing the first byte (10-bit start '11110' address bits[9:8] must be programmed here. The second start byte (lower slave address bits) must be on top of the master FIFO (i2c_mdr). This.."
newline
bitfld.long 0x00 1.--3. "mode,I2C-speed-mode: If this device is used as a slave only the mode should be set to the data rate generated by the fastest master on the I2C-bus for appropriate input filtering and spike suppression" "0: Fast/Standard mode 50 kbit/s,1: Fast/Standard mode 100 kbit/s,2: Fast/Standard mode 200 kbit/s,3: Fast/Standard mode 400 kbit/s,4: High-speed mode 800 kbit/s,5: High-speed mode 1.2 Mbit/s,6: High-speed mode 1.7 Mbit/s,7: High-speed mode 3.4 Mbit/s)"
bitfld.long 0x00 0. "en_i2c,Global I2C controller enable" "0: Disable I2C controller Disabling the I2C module,1: Enable I2C controller"
group.long 0x04++0x03
line.long 0x00 "i2c_scr,I2C slave control register"
bitfld.long 0x00 20. "autoreset_ac_start,Auto reset ac_start (ac_start must be set again after any (r)START)" "0: ac_start will not be reset automatically (netX,1: Reset ac_start after this slave acknowledged a"
bitfld.long 0x00 18. "ac_gcall,General call acknowledge" "0: Do not generate an acknowledge after a general,1: Generate an acknowledge after a general call"
newline
bitfld.long 0x00 17. "ac_start,Enable start sequence acknowledge: If the received address matches the sid-bits the start-byte (2 bytes if sid10 is set) will be acknowledged" "0: Do not generate an acknowledge after the start,1: Generate an acknowledge after the start.."
bitfld.long 0x00 16. "ac_srx,Enable slave-receive-data acknowledge" "0: Do not acknowledge receive bytes,1: Acknowledge receive bytes If the slave FIFO is"
newline
bitfld.long 0x00 10. "sid10,10-bit slave device ID/address" "0: Wait for 7-bit slave address after (r)START,1: Wait for 10-bit slave address after (r)START"
hexmask.long.word 0x00 0.--9. 1. "sid,Slave device ID/address: External masters can address this device (this I2C module in slave mode) by the ID/address programmed here"
group.long 0x08++0x03
line.long 0x00 "i2c_cmd,I2C master command register"
hexmask.long.byte 0x00 20.--27. 1. "acpollmax,Number of tries (acpollmax+1 i.e. 1 to 256) for start sequence acknowledge polling: For 7-bit addressing acknowledge polling START and the first byte containing the slave address (i2c_mcr.sadr) will be repeated up to acpollmax+1 times until a.."
hexmask.long.word 0x00 8.--17. 1. "tsize,Transfer tsize+1 bytes (1...1024): If no acknowledge is generated by the slave (receiver) write transfers will be terminated and IRQ cmd_err will be generated"
newline
bitfld.long 0x00 1.--3. "cmd,I2C sequence command: All commands will generate IRQ cmd_ok or IRQ cmd_err" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "nwr,Transfer direction (not-write/read)" "0: cmd will be executed as,1: cmd will be executed as read Master"
group.long 0x0C++0x03
line.long 0x00 "i2c_mdr,I2C master data register (master FIFO): There is only one FIFO for both receive and transmit master data with a depth of 16 bytes"
hexmask.long.byte 0x00 0.--7. 1. "mdata,I2C master transmit or receive data: Write data will be removed from the FIFO after the receiving slave has generated the corresponding acknowledge"
group.long 0x10++0x03
line.long 0x00 "i2c_sdr,I2C slave data register (slave FIFO): There is only one FIFO for both receive and transmit slave data with a depth of 16 bytes"
hexmask.long.byte 0x00 0.--7. 1. "sdata,I2C slave transmit or receive data: The software must handle i2c_scr.ac_start correctly to avoid FIFO errors after (r)START"
group.long 0x14++0x03
line.long 0x00 "i2c_mfifo_cr,I2C master FIFO control register"
bitfld.long 0x00 8. "mfifo_clr,Clear master data FIFO write only bit" "0,1"
bitfld.long 0x00 0.--3. "mfifo_wm,Master FIFO watermark for the generation of IRQ mfifo_req: If the master is the transmitter (enabled and i2c_cmd.nwr is 0) IRQ mfifo_req is generated if mfifo_level&lt mfifo_wm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "i2c_sfifo_cr,I2C slave FIFO control register"
bitfld.long 0x00 8. "sfifo_clr,Clear slave data FIFO write only bit" "0,1"
bitfld.long 0x00 0.--3. "sfifo_wm,Slave FIFO watermark for the generation of IRQ sfifo_req: If the slave is the transmitter (start sequence with set read bit was acknowledged by this slave) IRQ sfifo_req is generated if sfifo_level&lt sfifo_wm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "i2c_sr,I2C status register"
bitfld.long 0x00 31. "sda_state,SDA signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit" "0,1"
bitfld.long 0x00 30. "scl_state,SCL signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit" "0,1"
newline
bitfld.long 0x00 28. "timeout,I2C command timeout detection (for I2C master)" "0,1"
bitfld.long 0x00 27. "sid10_aced,10-bit slave address acknowledge state" "0: There was no 10-bit slave address or it was not,1: A 10-bit slave address was broadcasted and a"
newline
bitfld.long 0x00 26. "gcall_aced,General call acknowledge state" "0: No general call start-byte or general call,1: The slave side of the i2c module received and"
bitfld.long 0x00 25. "nwr_aced,Transfer direction (nwr-bit) of the last acknowledged start-byte (or 2-byte start sequence for 10-bit addressing)" "0: The last acknowledged start-byte defined a..,1: The last acknowledged start-byte defined a read"
newline
bitfld.long 0x00 24. "last_ac,Last acknowledge detected on bus" "0: SDA was high at the last acknowledge i.e,1: SDA was low at the last acknowledge i.e"
bitfld.long 0x00 23. "slave_access,Slave access state" "0: No slave access to this device,1: A master addressed this slave device"
newline
bitfld.long 0x00 22. "started,START condition detection" "0: The bus is idle (STOP was detected not started),1: (r)START was detected on the bus"
bitfld.long 0x00 21. "nwr,Transfer direction detected after last (r)START" "0: The last start-byte defined a write transfer,1: The last start-byte defined a read transfer"
newline
bitfld.long 0x00 20. "bus_master,Bus arbitration state" "0: Master lost I2C bus arbitration bus is busy by,1: Master gains I2C bus arbitration or bus is idle"
bitfld.long 0x00 19. "sfifo_err_undr,Slave FIFO underrun error occurred" "0,1"
newline
bitfld.long 0x00 18. "sfifo_err_ovfl,Slave FIFO overflow error occurred" "0,1"
bitfld.long 0x00 17. "sfifo_full,Slave FIFO is full (1 if full) This is a read-only status bit" "0,1"
newline
bitfld.long 0x00 16. "sfifo_empty,Slave FIFO is empty (1 if empty) This is a read-only status bit" "0,1"
bitfld.long 0x00 10.--14. "sfifo_level,Slave FIFO level (0..16) This is a read-only status bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 9. "mfifo_err_undr,Master FIFO underrun error occurred" "0,1"
bitfld.long 0x00 8. "mfifo_err_ovfl,Master FIFO overflow error occurred" "0,1"
newline
bitfld.long 0x00 7. "mfifo_full,Master FIFO is full (1 if full) This is a read-only status bit" "0,1"
bitfld.long 0x00 6. "mfifo_empty,Master FIFO is empty (1 if empty) This is a read-only status bit" "0,1"
newline
bitfld.long 0x00 0.--4. "mfifo_level,Master FIFO level (0..16) This is a read-only status bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20++0x03
line.long 0x00 "i2c_irqmsk,I2C interrupt mask set or clear register: These bits have AND-mask character"
bitfld.long 0x00 6. "sreq,Slave request interrupt mask" "0,1"
bitfld.long 0x00 5. "sfifo_req,Slave FIFO action request interrupt mask" "0,1"
newline
bitfld.long 0x00 4. "mfifo_req,Master FIFO action request interrupt mask" "0,1"
bitfld.long 0x00 3. "bus_busy,External I2C-bus is busy interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "fifo_err,FIFO error interrupt mask" "0,1"
bitfld.long 0x00 1. "cmd_err,Command error interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "cmd_ok,Command OK interrupt mask" "0,1"
group.long 0x24++0x03
line.long 0x00 "i2c_irqsr,I2C interrupt state register (raw interrupt before masking): Writing '1' will clear the corresponding IRQ"
bitfld.long 0x00 6. "sreq,Unmasked slave request interrupt state: Purpose: Set up slave FIFO" "0: Slave is not requested,1: External master was running START-sequence and"
bitfld.long 0x00 5. "sfifo_req,Unmasked slave FIFO action request interrupt state: Purpose: Slave FIFO should be updated" "0: Slave FIFO state not critical,1: Slave FIFO request"
newline
bitfld.long 0x00 4. "mfifo_req,Unmasked master FIFO action request interrupt state: Purpose: Master FIFO should be updated" "0: Master FIFO state not critical,1: Master FIFO request"
bitfld.long 0x00 3. "bus_busy,Unmasked external I2C-bus is busy interrupt state: Purpose: Detect I2C-bus arbitration loss" "0: Bus is idle or no transfer is requested by this,1: Master did not gain the requested bus access"
newline
bitfld.long 0x00 2. "fifo_err,Unmasked FIFO error interrupt state: Purpose: Detect FIFO errors/transfer failures" "0: FIFOs ok,1: FIFO error occurred"
bitfld.long 0x00 1. "cmd_err,Unmasked command error interrupt state: Purpose: Check last command termination" "0: Command not finished no command or command,1: Last command finished erroneously"
newline
bitfld.long 0x00 0. "cmd_ok,Unmasked command OK interrupt state: Purpose: Check last command termination" "0: Command not finished no command or command,1: Last command finished successfully"
rgroup.long 0x28++0x03
line.long 0x00 "i2c_irqmsked,I2C masked interrupt state register: If one of these bits is set the I2C IRQ will be set to the interrupt controller"
bitfld.long 0x00 6. "sreq,Masked slave request interrupt state" "0,1"
bitfld.long 0x00 5. "sfifo_req,Masked slave FIFO action request interrupt state" "0,1"
newline
bitfld.long 0x00 4. "mfifo_req,Masked master FIFO action request interrupt state" "0,1"
bitfld.long 0x00 3. "bus_busy,Masked external I2C-bus is busy interrupt state" "0,1"
newline
bitfld.long 0x00 2. "fifo_err,Masked FIFO error interrupt state" "0,1"
bitfld.long 0x00 1. "cmd_err,Masked command error interrupt state" "0,1"
newline
bitfld.long 0x00 0. "cmd_ok,Masked command OK interrupt state" "0,1"
group.long 0x2C++0x03
line.long 0x00 "i2c_dmacr,I2C DMA control register: Required settings for the DMA controller: - DMA transfer size to/from I2C module: Byte - DMA burst length to/from I2C module: 4 DMA burst requests will be generated if the corresponding FIFO contains more than 4 bytes.."
bitfld.long 0x00 3. "sdmab_en,Enable DMA burst requests for I2C slave data" "0,1"
bitfld.long 0x00 2. "sdmas_en,Enable DMA single requests for I2C slave data" "0,1"
newline
bitfld.long 0x00 1. "mdmab_en,Enable DMA burst requests for I2C master data" "0,1"
bitfld.long 0x00 0. "mdmas_en,Enable DMA single requests for I2C master data" "0,1"
group.long 0x30++0x03
line.long 0x00 "i2c_pio,PIO mode register: This register can directly control the I2C signals SCL and SDA if pio_mode is enabled in register i2c_mcr"
bitfld.long 0x00 6. "sda_in_ro,SDA input state (read-only)" "0,1"
bitfld.long 0x00 5. "sda_oe,SDA output enable" "0: Do not drive SDA switch pad to high-z,1: Drive SDA switch pad to programmed.."
newline
bitfld.long 0x00 4. "sda_out,Driving level of SDA (1: high 0: low) if output is enabled (sda_oe is set)" "0,1"
bitfld.long 0x00 2. "scl_in_ro,SCL input state (read-only)" "0,1"
newline
bitfld.long 0x00 1. "scl_oe,SCL output enable" "0: Do not drive SCL switch pad to high-z,1: Drive SCL switch pad to programmed.."
bitfld.long 0x00 0. "scl_out,Driving level of SCL (1: high 0: low) if output is enabled (scl_oe is set)" "0,1"
tree.end
tree "IDPM_COM"
base ad:0xFF001B00
group.long 0x00++0x03
line.long 0x00 "idpm_cfg0x0,DPM IO Control Register 0"
bitfld.long 0x00 4.--5. "endian,Endianess of 32 bit (DWord) address alignment (B0: least significant byte B3: most significant byte): { | | | | | coding Address A+3 A+2 A+1 A+0 00 little endian B3 B2 B1 B0 01 16 bit big endian B2 B3 B0 B1 10 32 bit big endian B0 B1 B2 B3 11.." "0,1,2,3"
newline
bitfld.long 0x00 0. "enable,Global IDPM enable bit" "0,1"
group.long 0x10++0x03
line.long 0x00 "idpm_addr_cfg,DPM External Address Configuration Register"
bitfld.long 0x00 4.--5. "cfg_win_addr_cfg,Location of the DPM Configuration Window (Window 0)" "0: Low Configuration Window,1: High Configuration Window,2: reserved,3: Configuration Window is disabled for external"
rgroup.long 0x1C++0x03
line.long 0x00 "idpm_status,DPM Status Register"
bitfld.long 0x00 0. "unlocked,DPM is locked during netX power up and boot phase" "0,1"
group.long 0x38++0x03
line.long 0x00 "idpm_tunnel_cfg,Register description is too long please enter short descripton"
bitfld.long 0x00 31. "wp_cfg_win,Write-protect tunnel configuration inside the configuration window 0" "0: The two tunnel configuration registers,1: The tunnel configuration registers"
newline
hexmask.long.word 0x00 6.--14. 1. "base,DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space"
newline
bitfld.long 0x00 3. "tunnel_all,Enable/disable the ITBAddr configuration register at tunnel offset 0x3C" "0: Only 15 DWords are tunneled to the internal,1: All 16 DWords are tunneled to the internal"
newline
bitfld.long 0x00 2. "enable,Enable/disable Access Tunnel function" "0,1"
newline
bitfld.long 0x00 1. "wp_itbaddr,ITBAddr is write-protected from host" "0: The ITBAddr is mirrored to offset 0x3C of the,1: ITBAddr (Internal netX 32 bit Tunnel Target.."
newline
bitfld.long 0x00 0. "wp_data,Access Tunnel function is write-protected for data access (DWords 0 to 14 (15 for 'tunnel_all') of DATunnel)" "0: Write access is forwarded through the tunnel,1: Write access to DWords 0 to 14 (15 for"
group.long 0x3C++0x03
line.long 0x00 "idpm_itbaddr,DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register"
hexmask.long 0x00 6.--31. 1. "base,Internal netX Tunnel Target Base Address (ITBAddr) divided by 64"
newline
bitfld.long 0x00 2.--5. "map,Mapping part of ITBAddr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "wp_itbaddr_ro,ITBAddr is write-protected from host" "0,1"
newline
bitfld.long 0x00 0. "wp_data_ro,Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel)" "0,1"
group.long 0x40++0x03
line.long 0x00 "idpm_win1_end,DPM Window 1 End Address Configuration Register"
hexmask.long.word 0x00 7.--15. 1. "win_end,Window 1 End Address divided by 128"
group.long 0x44++0x03
line.long 0x00 "idpm_win1_map,DPM Window 1 Address Map Configuration Register"
hexmask.long.byte 0x00 7.--14. 1. "win_map,Window 1 Address Mapping"
newline
bitfld.long 0x00 5. "wp_cfg_win,Write-protect window configuration inside the configuration window 0" "0: All 8 window configuration registers,1: All 8 window configuration registers"
newline
bitfld.long 0x00 2.--3. "win_map_alt,Window 1 Alternative Address Mapping Configuration" "0: Alternative Address Mapping disabled,1: Alternative Address Mapping enabled,2: Alternative Address Mapping enabled,3: reserved If Alternative Address Mapping is"
group.long 0x48++0x03
line.long 0x00 "idpm_win2_end,DPM Window 2 End Address Configuration Register"
hexmask.long.word 0x00 7.--15. 1. "win_end,Window 2 End Address divided by 128"
group.long 0x4C++0x03
line.long 0x00 "idpm_win2_map,DPM Window 2 Address Map Configuration Register"
hexmask.long.byte 0x00 7.--14. 1. "win_map,Window address mapping"
newline
bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
group.long 0x50++0x03
line.long 0x00 "idpm_win3_end,DPM Window 3 End Address Configuration Register"
hexmask.long.word 0x00 7.--15. 1. "win_end,Window 3 End Address divided by 128"
group.long 0x54++0x03
line.long 0x00 "idpm_win3_map,DPM Window 3 Address Map Configuration Register"
hexmask.long.byte 0x00 7.--14. 1. "win_map,Window map address"
newline
bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "idpm_win4_end,DPM Window 4 End Address Configuration Register"
hexmask.long.word 0x00 7.--15. 1. "win_end,Window 4 End Address divided by 128"
group.long 0x5C++0x03
line.long 0x00 "idpm_win4_map,DPM Window 4 Address Map Configuration Register"
hexmask.long.byte 0x00 7.--14. 1. "win_map,Window map address"
newline
bitfld.long 0x00 2.--3. "win_map_alt,Window Alternative Address Mapping Configuration" "0,1,2,3"
rgroup.long 0x80++0x03
line.long 0x00 "idpm_irq_raw,DPM Raw (before masking) IRQ Status Register"
bitfld.long 0x00 2. "firmware,raw combined handshake-cell and SYS_STA firmware interrupt" "0,1"
newline
bitfld.long 0x00 0. "dpm_sw,raw software IRQ for IRQ targets interrupt" "0,1"
group.long 0x84++0x03
line.long 0x00 "idpm_irq_host_mask_set,DPM Interrupt Mask Register for IDPM host interrupt"
bitfld.long 0x00 2. "firmware,set combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt" "0,1"
newline
bitfld.long 0x00 0. "dpm_sw,set software IRQ for IRQ targets interrupt mask for IDPM host interrupt" "0,1"
group.long 0x88++0x03
line.long 0x00 "idpm_irq_host_mask_reset,DPM Interrupt Mask Reset Register for IDPM host interrupt"
bitfld.long 0x00 2. "firmware,reset combined handshake-cell and SYS_STA firmware interrupt mask for IDPM host interrupt" "0,1"
newline
bitfld.long 0x00 0. "dpm_sw,reset software IRQ for IRQ targets interrupt mask for IDPM host interrupt" "0,1"
rgroup.long 0x8C++0x03
line.long 0x00 "idpm_irq_host_masked,DPM Masked Interrupt Status Register for IDPM host interrupt"
bitfld.long 0x00 2. "firmware,masked combined handshake-cell and SYS_STA firmware interrupt state for IDPM host interrupt" "0,1"
newline
bitfld.long 0x00 0. "dpm_sw,masked software IRQ for IRQ targets interrupt state for IDPM host interrupt" "0,1"
group.long 0xC0++0x03
line.long 0x00 "idpm_sw_irq,DPM Register for Software Interrupt Generation to Host and netX Interrupt Targets"
bitfld.long 0x00 8. "reset_host,Reset 'dpm_sw' IRQ for host (always 0 when read)" "0,1"
newline
bitfld.long 0x00 0. "set_host,Set 'dpm_sw' IRQ for host (current 'dpm_sw' status for host when read)" "0,1"
group.long 0xD8++0x03
line.long 0x00 "idpm_sys_sta,DPM System Status Information Register"
hexmask.long.byte 0x00 8.--15. 1. "NETX_STA_CODE_ro,Bit field for Hilscher firmware compatibility (read only)"
newline
bitfld.long 0x00 4.--7. "HOST_STATE,Bit field for Hilscher firmware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "NETX_STATE_ro,Bit field for Hilscher firmware compatibility" "0,1,2,3"
newline
bitfld.long 0x00 1. "RUN_ro,Output state of netX RUN LED IO" "0,1"
newline
bitfld.long 0x00 0. "RDY_ro,Output state of netX RDY LED IO" "0,1"
group.long 0xDC++0x03
line.long 0x00 "idpm_reset_request,DPM Reset Request Register"
hexmask.long.byte 0x00 0.--7. 1. "reset_key,Reset key sequence register"
group.long 0xE0++0x03
line.long 0x00 "idpm_firmware_irq_raw,1st netx50 compatible DPM Interrupt Status Register (related to 'dpm_firmware_irq_mask'-register)"
bitfld.long 0x00 31. "INT_REQ,Interrupt Request for IRQs handled in this register" "0: No Interrupts to host requested by IRQ sources,1: IRQ sources handled in this register request a"
newline
bitfld.long 0x00 30. "res_MEM_LCK_ro,reserved for Memory Lock IRQ flag (not available in this netX version)" "0,1"
newline
bitfld.long 0x00 29. "res_WDG_NETX_ro,reserved for netX supervision Watchdog Timeout IRQ flag (not available in this netX version)" "0,1"
newline
bitfld.long 0x00 28. "res_RDY_TIMEOUT_ro,reserved DPM_RDY timeout error does not exist for IDPM" "0,1"
newline
bitfld.long 0x00 26. "SYS_STA,System Status Change IRQ flag" "0,1"
newline
bitfld.long 0x00 25. "res_TMR_ro,reserved for Timer IRQ flag (not available in this netX version)" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "IRQ_VECTOR,Interrupt Vector according to status flags generated by enabled IRQ sources"
newline
bitfld.long 0x00 15. "HS_EVENT15,Handshake Event 15 IRQ status flag" "0,1"
newline
bitfld.long 0x00 14. "HS_EVENT14,Handshake Event 14 IRQ status flag" "0,1"
newline
bitfld.long 0x00 13. "HS_EVENT13,Handshake Event 13 IRQ status flag" "0,1"
newline
bitfld.long 0x00 12. "HS_EVENT12,Handshake Event 12 IRQ status flag" "0,1"
newline
bitfld.long 0x00 11. "HS_EVENT11,Handshake Event 11 IRQ status flag" "0,1"
newline
bitfld.long 0x00 10. "HS_EVENT10,Handshake Event 10 IRQ status flag" "0,1"
newline
bitfld.long 0x00 9. "HS_EVENT9,Handshake Event 9 IRQ status flag" "0,1"
newline
bitfld.long 0x00 8. "HS_EVENT8,Handshake Event 8 IRQ status flag" "0,1"
newline
bitfld.long 0x00 7. "HS_EVENT7,Handshake Event 7 IRQ status flag" "0,1"
newline
bitfld.long 0x00 6. "HS_EVENT6,Handshake Event 6 IRQ status flag" "0,1"
newline
bitfld.long 0x00 5. "HS_EVENT5,Handshake Event 5 IRQ status flag" "0,1"
newline
bitfld.long 0x00 4. "HS_EVENT4,Handshake Event 4 IRQ status flag" "0,1"
newline
bitfld.long 0x00 3. "HS_EVENT3,Handshake Event 3 IRQ status flag" "0,1"
newline
bitfld.long 0x00 2. "HS_EVENT2,Handshake Event 2 IRQ status flag" "0,1"
newline
bitfld.long 0x00 1. "HS_EVENT1,Handshake Event 1 IRQ status flag" "0,1"
newline
bitfld.long 0x00 0. "HS_EVENT0,Handshake Event 0 IRQ status flag" "0,1"
group.long 0xF0++0x03
line.long 0x00 "idpm_firmware_irq_mask,DPM Handshake Interrupt Enable Register"
bitfld.long 0x00 31. "INT_EN,Interrupt Enable for IRQs handled in this register" "0: No Interrupts to host ARM or xPIC are generated,1: Enabled IRQ sources handled in this register"
newline
bitfld.long 0x00 30. "res_MEM_LCK_ro,reserved for Memory Lock IRQ (not available in this netX version)" "0,1"
newline
bitfld.long 0x00 29. "res_WDG_NETX_ro,reserved for netX supervision Watchdog Timeout IRQ (not available in this netX version)" "0,1"
newline
bitfld.long 0x00 28. "res_RDY_TIMEOUT_ro,reserved DPM_RDY timeout error does not exist for IDPM" "0,1"
newline
bitfld.long 0x00 26. "SYS_STA,System Status Change IRQ Enable" "0,1"
newline
bitfld.long 0x00 25. "res_TMR_ro,reserved for Timer IRQ (not available in this netX version)" "0,1"
newline
bitfld.long 0x00 15. "HS_EVENT15,Handshake Event 15 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 14. "HS_EVENT14,Handshake Event 14 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 13. "HS_EVENT13,Handshake Event 13 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 12. "HS_EVENT12,Handshake Event 12 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 11. "HS_EVENT11,Handshake Event 11 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 10. "HS_EVENT10,Handshake Event 10 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 9. "HS_EVENT9,Handshake Event 9 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 8. "HS_EVENT8,Handshake Event 8 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 7. "HS_EVENT7,Handshake Event 7 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 6. "HS_EVENT6,Handshake Event 6 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 5. "HS_EVENT5,Handshake Event 5 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 4. "HS_EVENT4,Handshake Event 4 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 3. "HS_EVENT3,Handshake Event 3 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 2. "HS_EVENT2,Handshake Event 2 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 1. "HS_EVENT1,Handshake Event 1 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
newline
bitfld.long 0x00 0. "HS_EVENT0,Handshake Event 0 IRQ Enable (also netX-controllable by HANDSHAKE_CTRL netX50 comp.)" "0,1"
rgroup.long 0xFC++0x03
line.long 0x00 "idpm_netx_version,DPM netX Version Register"
hexmask.long 0x00 0.--31. 1. "netx_version,netX version from version register"
tree.end
tree "IFLASH_CFG2"
base ad:0xFF401400
group.long 0x00++0x03
line.long 0x00 "buffer_read_ahead_instructions,read ahead on instruction channel of flash controller max read ahead = buffer lines - 1"
hexmask.long 0x00 0.--31. 1. "val,read ahead on instruction channel of flash controller"
group.long 0x04++0x03
line.long 0x00 "buffer_read_ahead_data,read ahead on data channel of flash controller max read ahead = buffer lines - 1"
hexmask.long 0x00 0.--31. 1. "val,read ahead on data channel of flash controller"
group.long 0x08++0x03
line.long 0x00 "iflash_signals_cfg,no Register description"
bitfld.long 0x00 6. "se,flash clock" "0,1"
bitfld.long 0x00 5. "prog,defines program cycle" "0,1"
bitfld.long 0x00 4. "nvstr,defines non-volatile store cycle" "0,1"
bitfld.long 0x00 3. "mas1,defines mass erase cycle" "0,1"
bitfld.long 0x00 2. "erase,defines erase cycle" "0,1"
bitfld.long 0x00 1. "ye,y address enable" "0,1"
bitfld.long 0x00 0. "xe,x address enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "iflash_mode_cfg,no Register description"
bitfld.long 0x00 0.--2. "iflash_mode,3'b000 READ_MODE / 3'b001 PROGRAM_MODE / 3'b010 ERASE_MODE / 3'b011 MASS_ERASE_MODE / 3'b100 MANUAL_MODE" "0,1,2,3,4,5,6,7"
rgroup.long 0x10++0x03
line.long 0x00 "iflash_access,read only for the ready bit write 1 to start access flash action depends on iflash_mode_cfg"
bitfld.long 0x00 0. "run,write 1 to start accesss poll until set to 0 for finsh" "0,1"
group.long 0x14++0x03
line.long 0x00 "iflash_yadr,Y address of flash controller not all bits are used see: implementation size of flash"
bitfld.long 0x00 0.--4. "val,Y address of flash controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "iflash_xadr,X address of flash controller not all bits are used see: implementation size of flash"
hexmask.long.word 0x00 0.--9. 1. "val,X address of flash controller"
group.long 0x1C++0x03
line.long 0x00 "iflash_din0,data[31:0] of din flash controller"
hexmask.long 0x00 0.--31. 1. "val,data[31:0] of din flash controller"
group.long 0x20++0x03
line.long 0x00 "iflash_din1,data[63:32] of din flash controller"
hexmask.long 0x00 0.--31. 1. "val,data[63:32] of din flash controller"
group.long 0x24++0x03
line.long 0x00 "iflash_din2,data[95:64] of din flash controller"
hexmask.long 0x00 0.--31. 1. "val,data[95:64] of din flash controller"
group.long 0x28++0x03
line.long 0x00 "iflash_din3,data[127:96] of din flash controller"
hexmask.long 0x00 0.--31. 1. "val,data[127:96] of din flash controller"
group.long 0x2C++0x03
line.long 0x00 "iflash_din4,in manual mode for din data[143:128] of din flash controller"
hexmask.long.word 0x00 0.--15. 1. "val,data[143:128] of din flash controller"
group.long 0x30++0x03
line.long 0x00 "iflash_reset,reset flash controller"
bitfld.long 0x00 0. "reset," "0,1"
group.long 0x34++0x03
line.long 0x00 "iflash_red_cfg0,enable redundancy page XADR[9:3]"
hexmask.long.byte 0x00 1.--7. 1. "adr0,XADR to compare"
bitfld.long 0x00 0. "n_enb," "0,1"
group.long 0x38++0x03
line.long 0x00 "iflash_red_cfg1,enable redundancy page XADR[9:3]"
hexmask.long.byte 0x00 1.--7. 1. "adr1,XADR to compare"
bitfld.long 0x00 0. "n_enb," "0,1"
group.long 0x3C++0x03
line.long 0x00 "iflash_ifren_cfg,no Register description"
bitfld.long 0x00 1. "ifren1,information 1 block enable for read only" "0,1"
bitfld.long 0x00 0. "ifren,information block enable" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "iflash_din4_ecc,in manual mode for ecc calculation of din3..0"
hexmask.long.word 0x00 0.--15. 1. "val,ecc of din3..0 flash controller"
group.long 0x44++0x03
line.long 0x00 "iflash_special_cfg,no Register description"
bitfld.long 0x00 1. "slm,sleep mode" "0,1"
bitfld.long 0x00 0. "tmr,test mode" "0,1"
group.long 0x48++0x03
line.long 0x00 "iflash_protection_info,no Register description"
bitfld.long 0x00 3. "read_up,protect infopage 0 upper 4k page for read" "0,1"
bitfld.long 0x00 2. "read_dw,protect infopage 0 lower 4k page for read" "0,1"
bitfld.long 0x00 1. "write_up,protect infopage 0 upper 4k page for write" "0,1"
bitfld.long 0x00 0. "write_dw,protect infopage 0 lower 4k page for write" "0,1"
group.long 0x4C++0x03
line.long 0x00 "iflash_write_protection_main,no Register description"
hexmask.long 0x00 0.--31. 1. "val,protect flash main memory each bit protect 16k (16k x 32 = 512 kByte) xadr[9:5]"
tree.end
tree "IO_LINK_IRQ"
base ad:0xFF900480
group.long 0x00++0x03
line.long 0x00 "io_link_irq_raw,IO-Link raw interrupts: Read access shows status of unmasked IRQs"
bitfld.long 0x00 30. "xlink7_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 29. "xlink7_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 28. "xlink7_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 26. "xlink6_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 25. "xlink6_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 24. "xlink6_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 22. "xlink5_shift_en,shift_en interrupt" "0,1"
newline
bitfld.long 0x00 21. "xlink5_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 20. "xlink5_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 18. "xlink4_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 17. "xlink4_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 16. "xlink4_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 14. "xlink3_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 13. "xlink3_rx_next,rx_next interrupt" "0,1"
newline
bitfld.long 0x00 12. "xlink3_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 10. "xlink2_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 9. "xlink2_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 8. "xlink2_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 6. "xlink1_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 5. "xlink1_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 4. "xlink1_tx_next,tx_next interrupt" "0,1"
newline
bitfld.long 0x00 2. "xlink0_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 1. "xlink0_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 0. "xlink0_tx_next,tx_next interrupt" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "io_link_irq_masked,IO-Link Masked IRQ register Shows status of masked IRQs (as connected to ARM/xPIC)"
bitfld.long 0x00 30. "xlink7_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 29. "xlink7_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 28. "xlink7_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 26. "xlink6_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 25. "xlink6_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 24. "xlink6_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 22. "xlink5_shift_en,shift_en interrupt" "0,1"
newline
bitfld.long 0x00 21. "xlink5_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 20. "xlink5_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 18. "xlink4_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 17. "xlink4_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 16. "xlink4_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 14. "xlink3_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 13. "xlink3_rx_next,rx_next interrupt" "0,1"
newline
bitfld.long 0x00 12. "xlink3_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 10. "xlink2_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 9. "xlink2_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 8. "xlink2_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 6. "xlink1_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 5. "xlink1_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 4. "xlink1_tx_next,tx_next interrupt" "0,1"
newline
bitfld.long 0x00 2. "xlink0_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 1. "xlink0_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 0. "xlink0_tx_next,tx_next interrupt" "0,1"
group.long 0x08++0x03
line.long 0x00 "io_link_irq_msk_set,IO-Link interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 30. "xlink7_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 29. "xlink7_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 28. "xlink7_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 26. "xlink6_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 25. "xlink6_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 24. "xlink6_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 22. "xlink5_shift_en,shift_en interrupt" "0,1"
newline
bitfld.long 0x00 21. "xlink5_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 20. "xlink5_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 18. "xlink4_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 17. "xlink4_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 16. "xlink4_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 14. "xlink3_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 13. "xlink3_rx_next,rx_next interrupt" "0,1"
newline
bitfld.long 0x00 12. "xlink3_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 10. "xlink2_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 9. "xlink2_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 8. "xlink2_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 6. "xlink1_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 5. "xlink1_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 4. "xlink1_tx_next,tx_next interrupt" "0,1"
newline
bitfld.long 0x00 2. "xlink0_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 1. "xlink0_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 0. "xlink0_tx_next,tx_next interrupt" "0,1"
group.long 0x0C++0x03
line.long 0x00 "io_link_irq_msk_reset,IO-Link interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
bitfld.long 0x00 30. "xlink7_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 29. "xlink7_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 28. "xlink7_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 26. "xlink6_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 25. "xlink6_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 24. "xlink6_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 22. "xlink5_shift_en,shift_en interrupt" "0,1"
newline
bitfld.long 0x00 21. "xlink5_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 20. "xlink5_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 18. "xlink4_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 17. "xlink4_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 16. "xlink4_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 14. "xlink3_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 13. "xlink3_rx_next,rx_next interrupt" "0,1"
newline
bitfld.long 0x00 12. "xlink3_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 10. "xlink2_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 9. "xlink2_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 8. "xlink2_tx_next,tx_next interrupt" "0,1"
bitfld.long 0x00 6. "xlink1_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 5. "xlink1_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 4. "xlink1_tx_next,tx_next interrupt" "0,1"
newline
bitfld.long 0x00 2. "xlink0_shift_en,shift_en interrupt" "0,1"
bitfld.long 0x00 1. "xlink0_rx_next,rx_next interrupt" "0,1"
bitfld.long 0x00 0. "xlink0_tx_next,tx_next interrupt" "0,1"
tree.end
tree "MCP_APP"
base ad:0xFF801620
group.long 0x00++0x03
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
group.long 0x04++0x03
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
group.long 0x08++0x03
line.long 0x00 "hs_irq_set_mask,read: mask value"
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
group.long 0x0C++0x03
line.long 0x00 "hs_irq_reset_mask,read: mask value"
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
group.long 0x10++0x03
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
tree.end
tree "MCP_XPIC_APP"
base ad:0xFF9001A0
group.long 0x00++0x03
line.long 0x00 "hs_irq_set_raw,read: hs_iq_reg value write: hs_iq_reg set bit(s)"
hexmask.long 0x00 0.--31. 1. "hs_irq_set_bits,IRQs for Inter-CPU-Communication"
group.long 0x04++0x03
line.long 0x00 "hs_irq_reset_raw,read: hs_iq_reg value write: hs_iq_reg reset bit(s)"
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_bits,IRQs for Inter-CPU-Communication"
group.long 0x08++0x03
line.long 0x00 "hs_irq_set_mask,read: mask value"
hexmask.long 0x00 0.--31. 1. "hs_irq_set_mask,IRQs for Inter-CPU-Communication"
group.long 0x0C++0x03
line.long 0x00 "hs_irq_reset_mask,read: mask value"
hexmask.long 0x00 0.--31. 1. "hs_irq_reset_mask,reset IRQs for Inter-CPU-Communication"
group.long 0x10++0x03
line.long 0x00 "hs_irq_masked,read: hs_iq_reg masked value"
hexmask.long 0x00 0.--31. 1. "hs_irq_masked,mask IRQs for Inter-CPU-Communication"
tree.end
tree "MIIMU"
base ad:0xFF401700
group.long 0x00++0x03
line.long 0x00 "miimu,MDIO FSM interface controlling for netX external PHY"
hexmask.long.word 0x00 16.--31. 1. "data,Data to or from PHY register"
bitfld.long 0x00 11.--15. "phyaddr,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6.--10. "regaddr,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "rta,Read Turn Around field" "0: one bit,1: two bits"
bitfld.long 0x00 3. "mdc_period,MDC period" "0: 400ns,1: 800ns"
newline
bitfld.long 0x00 2. "opmode,Operation mode" "0: read,1: write"
bitfld.long 0x00 1. "preamble,Send preamble" "0,1"
bitfld.long 0x00 0. "snrdy,Start not ready" "0,1"
group.long 0x04++0x03
line.long 0x00 "miimu_sw,MDIO software interface controlling for netX internal PHY"
bitfld.long 0x00 8. "loopback,MDIO-data-out to data-in loopback for test purpose" "0: no loopback MDIO-data-in comes from internal..,1: loopback MDIO-data-in comes from current"
bitfld.long 0x00 7. "mdi_ro,current MDI value" "0,1"
bitfld.long 0x00 6. "mdoe,MDOE value for software mode" "0,1"
bitfld.long 0x00 5. "mdo,MDO value for software mode" "0,1"
bitfld.long 0x00 4. "mdc,MDC value for software mode" "0,1"
newline
bitfld.long 0x00 0. "enable,Enables software mode: MDC MDO and MDOE are set by software" "0,1"
tree.end
tree "MLED_CTRL_APP"
base ad:0xFF801100
group.long 0x00++0x03
line.long 0x00 "mled_ctrl_app_cfg,Global configuration register"
hexmask.long.word 0x00 11.--19. 1. "blink_counter_max,Maximum value the blink counter will count to"
hexmask.long.word 0x00 1.--10. 1. "prescale_counter_max,Maximum value the prescale counter will count to"
bitfld.long 0x00 0. "enable,Writing a '1' to this bit will enable the MLED_CTRL_APP module" "0,1"
group.long 0x04++0x03
line.long 0x00 "mled_ctrl_app_output_sel0,Output 0 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x08++0x03
line.long 0x00 "mled_ctrl_app_output_sel1,Output 0 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x0C++0x03
line.long 0x00 "mled_ctrl_app_output_sel2,Output 1 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x10++0x03
line.long 0x00 "mled_ctrl_app_output_sel3,Output 1 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x14++0x03
line.long 0x00 "mled_ctrl_app_output_sel4,Output 2 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x18++0x03
line.long 0x00 "mled_ctrl_app_output_sel5,Output 2 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x1C++0x03
line.long 0x00 "mled_ctrl_app_output_sel6,Output 3 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x20++0x03
line.long 0x00 "mled_ctrl_app_output_sel7,Output 3 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x24++0x03
line.long 0x00 "mled_ctrl_app_output_sel8,Output 4 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x28++0x03
line.long 0x00 "mled_ctrl_app_output_sel9,Output 4 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x2C++0x03
line.long 0x00 "mled_ctrl_app_output_sel10,Output 5 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x30++0x03
line.long 0x00 "mled_ctrl_app_output_sel11,Output 5 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x34++0x03
line.long 0x00 "mled_ctrl_app_output_sel12,Output 6 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x38++0x03
line.long 0x00 "mled_ctrl_app_output_sel13,Output 6 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x3C++0x03
line.long 0x00 "mled_ctrl_app_output_sel14,Output 7 phase 0 (high-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x40++0x03
line.long 0x00 "mled_ctrl_app_output_sel15,Output 7 phase 1 (low-side LED) configuration"
bitfld.long 0x00 1.--2. "sel,Selection of the signal connected to this output" "0,1,2,3"
bitfld.long 0x00 0. "inv,Invert input signal" "0,1"
group.long 0x44++0x03
line.long 0x00 "mled_ctrl_app_output_on_time0,Output 0 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x48++0x03
line.long 0x00 "mled_ctrl_app_output_on_time1,Output 0 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x4C++0x03
line.long 0x00 "mled_ctrl_app_output_on_time2,Output 1 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x50++0x03
line.long 0x00 "mled_ctrl_app_output_on_time3,Output 1 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x54++0x03
line.long 0x00 "mled_ctrl_app_output_on_time4,Output 2 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x58++0x03
line.long 0x00 "mled_ctrl_app_output_on_time5,Output 2 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x5C++0x03
line.long 0x00 "mled_ctrl_app_output_on_time6,Output 3 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x60++0x03
line.long 0x00 "mled_ctrl_app_output_on_time7,Output 3 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x64++0x03
line.long 0x00 "mled_ctrl_app_output_on_time8,Output 4 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x68++0x03
line.long 0x00 "mled_ctrl_app_output_on_time9,Output 4 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x6C++0x03
line.long 0x00 "mled_ctrl_app_output_on_time10,Output 5 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x70++0x03
line.long 0x00 "mled_ctrl_app_output_on_time11,Output 5 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x74++0x03
line.long 0x00 "mled_ctrl_app_output_on_time12,Output 6 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x78++0x03
line.long 0x00 "mled_ctrl_app_output_on_time13,Output 6 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x7C++0x03
line.long 0x00 "mled_ctrl_app_output_on_time14,Output 7 phase 0 (high-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x80++0x03
line.long 0x00 "mled_ctrl_app_output_on_time15,Output 7 phase 1 (low-side LED) switch-on time"
hexmask.long.byte 0x00 0.--7. 1. "val,Switch-on time of this LED"
group.long 0x84++0x03
line.long 0x00 "mled_ctrl_app_line0,Line register"
hexmask.long.word 0x00 0.--15. 1. "val,MLED output values 15..0 when line mode is selected in the corresponding 'sel' register"
tree.end
tree "MMIO_CTRL"
base ad:0xFF401300
group.long 0x00++0x03
line.long 0x00 "mmio0_cfg,Register description is too long please enter short descripton"
bitfld.long 0x00 18. "status_in_ro,current input status of mmio0 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio0 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio0 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio0 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "mmio1_cfg,Multiplexmatrix Configuration Register for MMIO1 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio1 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio1 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio1 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio1 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "mmio2_cfg,Multiplexmatrix Configuration Register for MMIO2 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio2 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio2 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio2 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio2 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "mmio3_cfg,Multiplexmatrix Configuration Register for MMIO3 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio3 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio3 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio3 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio3 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "mmio4_cfg,Multiplexmatrix Configuration Register for MMIO4 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio4 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio4 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio4 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio4 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "mmio5_cfg,Multiplexmatrix Configuration Register for MMIO5 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio5 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio5 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio5 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio5 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18++0x03
line.long 0x00 "mmio6_cfg,Multiplexmatrix Configuration Register for MMIO6 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio6 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio6 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio6 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio6 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1C++0x03
line.long 0x00 "mmio7_cfg,Multiplexmatrix Configuration Register for MMIO7 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio7 could also be read from 'mmio_in_line_status' register" "0,1"
bitfld.long 0x00 17. "pio_out,PIO mode output drive level of mmio7 could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cfg register'" "0,1"
bitfld.long 0x00 16. "pio_oe,PIO mode output enable of mmio7 could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio7 signal selection (default: PIO mode access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20++0x03
line.long 0x00 "mmio8_cfg,Multiplexmatrix Configuration Register for MMIO8 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio8 port HIF_D8" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio8 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x03
line.long 0x00 "mmio9_cfg,Multiplexmatrix Configuration Register for MMIO9 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio9 port HIF_D9" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio9 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x28++0x03
line.long 0x00 "mmio10_cfg,Multiplexmatrix Configuration Register for MMIO10 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio10 port HIF_D10" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio10 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2C++0x03
line.long 0x00 "mmio11_cfg,Multiplexmatrix Configuration Register for MMIO11 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio11 port HIF_D11" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio11 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x30++0x03
line.long 0x00 "mmio12_cfg,Multiplexmatrix Configuration Register for MMIO12 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio12 port HIF_D12" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio12 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x34++0x03
line.long 0x00 "mmio13_cfg,Multiplexmatrix Configuration Register for MMIO13 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio13 port HIF_D13" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio13 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "mmio14_cfg,Multiplexmatrix Configuration Register for MMIO14 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio14 port HIF_D14" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio14 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3C++0x03
line.long 0x00 "mmio15_cfg,Multiplexmatrix Configuration Register for MMIO15 ------------------------------- Some bits of this register is protected by the netX access-key mechanism changing this register is only possible by the following sequence: 1.: read out.."
bitfld.long 0x00 18. "status_in_ro,current input status of mmio15 port HIF_D15" "0,1"
bitfld.long 0x00 10. "mmio_in_inv," "0,1"
bitfld.long 0x00 9. "mmio_out_inv," "0,1"
bitfld.long 0x00 0.--5. "mmio_sel,mmio15 signal selection and multiplex function enable (access-key-protected)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x40++0x03
line.long 0x00 "mmio_pio_out_line_cfg0,MMIO PIO line output level register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,MMIO output state if related MMIO is in PIO mode"
group.long 0x44++0x03
line.long 0x00 "mmio_pio_out_line_set_cfg0,MMIO PIO line output level set register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,Write '1's to set the related MMIO output to high level (when it is in PIO mode and output is enabled)"
group.long 0x48++0x03
line.long 0x00 "mmio_pio_out_line_reset_cfg0,MMIO PIO line output level reset register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,Write '1's to set the related MMIO output to low level (when it is in PIO mode and output is enabled)"
group.long 0x4C++0x03
line.long 0x00 "mmio_pio_oe_line_cfg0,MMIO PIO line output enable register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,MMIO output enable if related MMIO is in PIO mode"
group.long 0x50++0x03
line.long 0x00 "mmio_pio_oe_line_set_cfg0,MMIO PIO line output enable set register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,Write '1's to activate the related MMIO output enable (when it is in PIO mode)"
group.long 0x54++0x03
line.long 0x00 "mmio_pio_oe_line_reset_cfg0,MMIO PIO line output enable reset register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,Write '1's to clear the related MMIO output enable (when it is in PIO mode)"
rgroup.long 0x58++0x03
line.long 0x00 "mmio_in_line_status0,MMIO input line register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,sampled MMIO input state"
rgroup.long 0x5C++0x03
line.long 0x00 "mmio_is_pio_status0,MMIO mode line register of MMIO 0 to 15"
hexmask.long.word 0x00 0.--15. 1. "line,Bit 0 shows status of MMIO0 Bit 1 shows status of MMIO1"
tree.end
tree "MTGY"
base ad:0xFF082000
group.long 0x00++0x03
line.long 0x00 "mtgy_cmd,MWMM command register"
bitfld.long 0x00 27.--31. "src_addr_x,Source address X specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22.--26. "src_addr_e,Source Address E specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17.--21. "dest_addr,Destination Address / Source Address A specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 12.--16. "src_addr,Source Address specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--11. "op,The operation code of the core" "0: MontMult (Montgomery Multiplication Step),1: MontR (Montgomery Parameter R),2: MontR2 (Montgomery Parameter R2 ),3: MontExp (Montgomery Exponentiation Step),4: ModAdd (Modular Addition),5: ModSub (Modular Subtraction),6: CopyH2V (Copy from horizontal to vertical RAM,7: CopyV2V (Copy from vertical to vertical RAM,8: CopyH2H (Copy from horizontal to horizontal RAM,9: CopyV2H (Copy from vertical to horizontal RAM,10: MontMult1 (Montgomery Multiplication Step with,?..."
bitfld.long 0x00 4.--7. "precision,Precision of executed operations" "0: 192 bit,1: 224 bit,2: 256 bit,3: 320 bit,4: 384 bit,5: 512 bit,6: 768 bit,7: 1024 bit,8: 1536 bit,9: 2048 bit,10: 3072 bit,11: 4096 bit,12: reserved,?..."
bitfld.long 0x00 2. "f_sel,Finite Field Selection signal" "0: GF(2^m),1: GF(p) or"
bitfld.long 0x00 1. "abort,Abort Signal of the MWMM Core" "0,1"
newline
bitfld.long 0x00 0. "start,Start Signal of the MWMM Core" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "mtgy_stat,MWMM status register"
bitfld.long 0x00 0. "done,Done signal from the MWMM core" "0,1"
group.long 0x08++0x03
line.long 0x00 "mtgy_irq_raw,MWMM raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 0. "done,Done signal from the MWMM core" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "mtgy_irq_masked,MWMM masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 0. "done,Done signal from the MWMM core" "0,1"
group.long 0x10++0x03
line.long 0x00 "mtgy_irq_msk_set,MWMM IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 0. "done,Done signal from the MWMM core" "0,1"
group.long 0x14++0x03
line.long 0x00 "mtgy_irq_msk_reset,MWMM IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 0. "done,Done signal from the MWMM core" "0,1"
group.long 0x1000++0x03
line.long 0x00 "mtgy_op_tc0,MWMM TC register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1004++0x03
line.long 0x00 "mtgy_op_tc1,MWMM TC register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1008++0x03
line.long 0x00 "mtgy_op_tc2,MWMM TC register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x100C++0x03
line.long 0x00 "mtgy_op_tc3,MWMM TC register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1010++0x03
line.long 0x00 "mtgy_op_tc4,MWMM TC register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1014++0x03
line.long 0x00 "mtgy_op_tc5,MWMM TC register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1018++0x03
line.long 0x00 "mtgy_op_tc6,MWMM TC register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x101C++0x03
line.long 0x00 "mtgy_op_tc7,MWMM TC register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1020++0x03
line.long 0x00 "mtgy_op_tc8,MWMM TC register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1024++0x03
line.long 0x00 "mtgy_op_tc9,MWMM TC register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1028++0x03
line.long 0x00 "mtgy_op_tc10,MWMM TC register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x102C++0x03
line.long 0x00 "mtgy_op_tc11,MWMM TC register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1030++0x03
line.long 0x00 "mtgy_op_tc12,MWMM TC register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1034++0x03
line.long 0x00 "mtgy_op_tc13,MWMM TC register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1038++0x03
line.long 0x00 "mtgy_op_tc14,MWMM TC register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x103C++0x03
line.long 0x00 "mtgy_op_tc15,MWMM TC register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1040++0x03
line.long 0x00 "mtgy_op_tc16,MWMM TC register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1044++0x03
line.long 0x00 "mtgy_op_tc17,MWMM TC register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1048++0x03
line.long 0x00 "mtgy_op_tc18,MWMM TC register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x104C++0x03
line.long 0x00 "mtgy_op_tc19,MWMM TC register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1050++0x03
line.long 0x00 "mtgy_op_tc20,MWMM TC register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1054++0x03
line.long 0x00 "mtgy_op_tc21,MWMM TC register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1058++0x03
line.long 0x00 "mtgy_op_tc22,MWMM TC register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x105C++0x03
line.long 0x00 "mtgy_op_tc23,MWMM TC register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1060++0x03
line.long 0x00 "mtgy_op_tc24,MWMM TC register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1064++0x03
line.long 0x00 "mtgy_op_tc25,MWMM TC register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1068++0x03
line.long 0x00 "mtgy_op_tc26,MWMM TC register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x106C++0x03
line.long 0x00 "mtgy_op_tc27,MWMM TC register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1070++0x03
line.long 0x00 "mtgy_op_tc28,MWMM TC register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1074++0x03
line.long 0x00 "mtgy_op_tc29,MWMM TC register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1078++0x03
line.long 0x00 "mtgy_op_tc30,MWMM TC register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x107C++0x03
line.long 0x00 "mtgy_op_tc31,MWMM TC register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1080++0x03
line.long 0x00 "mtgy_op_tc32,MWMM TC register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1084++0x03
line.long 0x00 "mtgy_op_tc33,MWMM TC register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1088++0x03
line.long 0x00 "mtgy_op_tc34,MWMM TC register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x108C++0x03
line.long 0x00 "mtgy_op_tc35,MWMM TC register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1090++0x03
line.long 0x00 "mtgy_op_tc36,MWMM TC register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1094++0x03
line.long 0x00 "mtgy_op_tc37,MWMM TC register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1098++0x03
line.long 0x00 "mtgy_op_tc38,MWMM TC register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x109C++0x03
line.long 0x00 "mtgy_op_tc39,MWMM TC register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x10A0++0x03
line.long 0x00 "mtgy_op_tc40,MWMM TC register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x10A4++0x03
line.long 0x00 "mtgy_op_tc41,MWMM TC register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x10A8++0x03
line.long 0x00 "mtgy_op_tc42,MWMM TC register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x10AC++0x03
line.long 0x00 "mtgy_op_tc43,MWMM TC register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x10B0++0x03
line.long 0x00 "mtgy_op_tc44,MWMM TC register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x10B4++0x03
line.long 0x00 "mtgy_op_tc45,MWMM TC register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x10B8++0x03
line.long 0x00 "mtgy_op_tc46,MWMM TC register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x10BC++0x03
line.long 0x00 "mtgy_op_tc47,MWMM TC register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x10C0++0x03
line.long 0x00 "mtgy_op_tc48,MWMM TC register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x10C4++0x03
line.long 0x00 "mtgy_op_tc49,MWMM TC register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x10C8++0x03
line.long 0x00 "mtgy_op_tc50,MWMM TC register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x10CC++0x03
line.long 0x00 "mtgy_op_tc51,MWMM TC register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x10D0++0x03
line.long 0x00 "mtgy_op_tc52,MWMM TC register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x10D4++0x03
line.long 0x00 "mtgy_op_tc53,MWMM TC register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x10D8++0x03
line.long 0x00 "mtgy_op_tc54,MWMM TC register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x10DC++0x03
line.long 0x00 "mtgy_op_tc55,MWMM TC register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x10E0++0x03
line.long 0x00 "mtgy_op_tc56,MWMM TC register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x10E4++0x03
line.long 0x00 "mtgy_op_tc57,MWMM TC register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x10E8++0x03
line.long 0x00 "mtgy_op_tc58,MWMM TC register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x10EC++0x03
line.long 0x00 "mtgy_op_tc59,MWMM TC register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x10F0++0x03
line.long 0x00 "mtgy_op_tc60,MWMM TC register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x10F4++0x03
line.long 0x00 "mtgy_op_tc61,MWMM TC register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x10F8++0x03
line.long 0x00 "mtgy_op_tc62,MWMM TC register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x10FC++0x03
line.long 0x00 "mtgy_op_tc63,MWMM TC register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1100++0x03
line.long 0x00 "mtgy_op_tc64,MWMM TC register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1104++0x03
line.long 0x00 "mtgy_op_tc65,MWMM TC register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1108++0x03
line.long 0x00 "mtgy_op_tc66,MWMM TC register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x110C++0x03
line.long 0x00 "mtgy_op_tc67,MWMM TC register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1110++0x03
line.long 0x00 "mtgy_op_tc68,MWMM TC register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1114++0x03
line.long 0x00 "mtgy_op_tc69,MWMM TC register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1118++0x03
line.long 0x00 "mtgy_op_tc70,MWMM TC register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x111C++0x03
line.long 0x00 "mtgy_op_tc71,MWMM TC register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1120++0x03
line.long 0x00 "mtgy_op_tc72,MWMM TC register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1124++0x03
line.long 0x00 "mtgy_op_tc73,MWMM TC register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1128++0x03
line.long 0x00 "mtgy_op_tc74,MWMM TC register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x112C++0x03
line.long 0x00 "mtgy_op_tc75,MWMM TC register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1130++0x03
line.long 0x00 "mtgy_op_tc76,MWMM TC register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1134++0x03
line.long 0x00 "mtgy_op_tc77,MWMM TC register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1138++0x03
line.long 0x00 "mtgy_op_tc78,MWMM TC register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x113C++0x03
line.long 0x00 "mtgy_op_tc79,MWMM TC register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1140++0x03
line.long 0x00 "mtgy_op_tc80,MWMM TC register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1144++0x03
line.long 0x00 "mtgy_op_tc81,MWMM TC register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1148++0x03
line.long 0x00 "mtgy_op_tc82,MWMM TC register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x114C++0x03
line.long 0x00 "mtgy_op_tc83,MWMM TC register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1150++0x03
line.long 0x00 "mtgy_op_tc84,MWMM TC register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1154++0x03
line.long 0x00 "mtgy_op_tc85,MWMM TC register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1158++0x03
line.long 0x00 "mtgy_op_tc86,MWMM TC register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x115C++0x03
line.long 0x00 "mtgy_op_tc87,MWMM TC register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1160++0x03
line.long 0x00 "mtgy_op_tc88,MWMM TC register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1164++0x03
line.long 0x00 "mtgy_op_tc89,MWMM TC register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1168++0x03
line.long 0x00 "mtgy_op_tc90,MWMM TC register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x116C++0x03
line.long 0x00 "mtgy_op_tc91,MWMM TC register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1170++0x03
line.long 0x00 "mtgy_op_tc92,MWMM TC register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1174++0x03
line.long 0x00 "mtgy_op_tc93,MWMM TC register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1178++0x03
line.long 0x00 "mtgy_op_tc94,MWMM TC register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x117C++0x03
line.long 0x00 "mtgy_op_tc95,MWMM TC register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1180++0x03
line.long 0x00 "mtgy_op_tc96,MWMM TC register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1184++0x03
line.long 0x00 "mtgy_op_tc97,MWMM TC register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1188++0x03
line.long 0x00 "mtgy_op_tc98,MWMM TC register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x118C++0x03
line.long 0x00 "mtgy_op_tc99,MWMM TC register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1190++0x03
line.long 0x00 "mtgy_op_tc100,MWMM TC register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1194++0x03
line.long 0x00 "mtgy_op_tc101,MWMM TC register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1198++0x03
line.long 0x00 "mtgy_op_tc102,MWMM TC register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x119C++0x03
line.long 0x00 "mtgy_op_tc103,MWMM TC register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x11A0++0x03
line.long 0x00 "mtgy_op_tc104,MWMM TC register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x11A4++0x03
line.long 0x00 "mtgy_op_tc105,MWMM TC register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x11A8++0x03
line.long 0x00 "mtgy_op_tc106,MWMM TC register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x11AC++0x03
line.long 0x00 "mtgy_op_tc107,MWMM TC register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x11B0++0x03
line.long 0x00 "mtgy_op_tc108,MWMM TC register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x11B4++0x03
line.long 0x00 "mtgy_op_tc109,MWMM TC register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x11B8++0x03
line.long 0x00 "mtgy_op_tc110,MWMM TC register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x11BC++0x03
line.long 0x00 "mtgy_op_tc111,MWMM TC register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x11C0++0x03
line.long 0x00 "mtgy_op_tc112,MWMM TC register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x11C4++0x03
line.long 0x00 "mtgy_op_tc113,MWMM TC register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x11C8++0x03
line.long 0x00 "mtgy_op_tc114,MWMM TC register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x11CC++0x03
line.long 0x00 "mtgy_op_tc115,MWMM TC register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x11D0++0x03
line.long 0x00 "mtgy_op_tc116,MWMM TC register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x11D4++0x03
line.long 0x00 "mtgy_op_tc117,MWMM TC register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x11D8++0x03
line.long 0x00 "mtgy_op_tc118,MWMM TC register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x11DC++0x03
line.long 0x00 "mtgy_op_tc119,MWMM TC register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x11E0++0x03
line.long 0x00 "mtgy_op_tc120,MWMM TC register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x11E4++0x03
line.long 0x00 "mtgy_op_tc121,MWMM TC register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x11E8++0x03
line.long 0x00 "mtgy_op_tc122,MWMM TC register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x11EC++0x03
line.long 0x00 "mtgy_op_tc123,MWMM TC register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x11F0++0x03
line.long 0x00 "mtgy_op_tc124,MWMM TC register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x11F4++0x03
line.long 0x00 "mtgy_op_tc125,MWMM TC register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x11F8++0x03
line.long 0x00 "mtgy_op_tc126,MWMM TC register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x11FC++0x03
line.long 0x00 "mtgy_op_tc127,MWMM TC register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
group.long 0x1200++0x03
line.long 0x00 "mtgy_op_ts0,MWMM TS register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1204++0x03
line.long 0x00 "mtgy_op_ts1,MWMM TS register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1208++0x03
line.long 0x00 "mtgy_op_ts2,MWMM TS register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x120C++0x03
line.long 0x00 "mtgy_op_ts3,MWMM TS register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1210++0x03
line.long 0x00 "mtgy_op_ts4,MWMM TS register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1214++0x03
line.long 0x00 "mtgy_op_ts5,MWMM TS register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1218++0x03
line.long 0x00 "mtgy_op_ts6,MWMM TS register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x121C++0x03
line.long 0x00 "mtgy_op_ts7,MWMM TS register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1220++0x03
line.long 0x00 "mtgy_op_ts8,MWMM TS register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1224++0x03
line.long 0x00 "mtgy_op_ts9,MWMM TS register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1228++0x03
line.long 0x00 "mtgy_op_ts10,MWMM TS register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x122C++0x03
line.long 0x00 "mtgy_op_ts11,MWMM TS register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1230++0x03
line.long 0x00 "mtgy_op_ts12,MWMM TS register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1234++0x03
line.long 0x00 "mtgy_op_ts13,MWMM TS register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1238++0x03
line.long 0x00 "mtgy_op_ts14,MWMM TS register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x123C++0x03
line.long 0x00 "mtgy_op_ts15,MWMM TS register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1240++0x03
line.long 0x00 "mtgy_op_ts16,MWMM TS register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1244++0x03
line.long 0x00 "mtgy_op_ts17,MWMM TS register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1248++0x03
line.long 0x00 "mtgy_op_ts18,MWMM TS register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x124C++0x03
line.long 0x00 "mtgy_op_ts19,MWMM TS register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1250++0x03
line.long 0x00 "mtgy_op_ts20,MWMM TS register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1254++0x03
line.long 0x00 "mtgy_op_ts21,MWMM TS register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1258++0x03
line.long 0x00 "mtgy_op_ts22,MWMM TS register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x125C++0x03
line.long 0x00 "mtgy_op_ts23,MWMM TS register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1260++0x03
line.long 0x00 "mtgy_op_ts24,MWMM TS register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1264++0x03
line.long 0x00 "mtgy_op_ts25,MWMM TS register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1268++0x03
line.long 0x00 "mtgy_op_ts26,MWMM TS register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x126C++0x03
line.long 0x00 "mtgy_op_ts27,MWMM TS register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1270++0x03
line.long 0x00 "mtgy_op_ts28,MWMM TS register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1274++0x03
line.long 0x00 "mtgy_op_ts29,MWMM TS register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1278++0x03
line.long 0x00 "mtgy_op_ts30,MWMM TS register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x127C++0x03
line.long 0x00 "mtgy_op_ts31,MWMM TS register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1280++0x03
line.long 0x00 "mtgy_op_ts32,MWMM TS register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1284++0x03
line.long 0x00 "mtgy_op_ts33,MWMM TS register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1288++0x03
line.long 0x00 "mtgy_op_ts34,MWMM TS register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x128C++0x03
line.long 0x00 "mtgy_op_ts35,MWMM TS register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1290++0x03
line.long 0x00 "mtgy_op_ts36,MWMM TS register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1294++0x03
line.long 0x00 "mtgy_op_ts37,MWMM TS register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1298++0x03
line.long 0x00 "mtgy_op_ts38,MWMM TS register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x129C++0x03
line.long 0x00 "mtgy_op_ts39,MWMM TS register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x12A0++0x03
line.long 0x00 "mtgy_op_ts40,MWMM TS register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x12A4++0x03
line.long 0x00 "mtgy_op_ts41,MWMM TS register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x12A8++0x03
line.long 0x00 "mtgy_op_ts42,MWMM TS register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x12AC++0x03
line.long 0x00 "mtgy_op_ts43,MWMM TS register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x12B0++0x03
line.long 0x00 "mtgy_op_ts44,MWMM TS register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x12B4++0x03
line.long 0x00 "mtgy_op_ts45,MWMM TS register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x12B8++0x03
line.long 0x00 "mtgy_op_ts46,MWMM TS register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x12BC++0x03
line.long 0x00 "mtgy_op_ts47,MWMM TS register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x12C0++0x03
line.long 0x00 "mtgy_op_ts48,MWMM TS register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x12C4++0x03
line.long 0x00 "mtgy_op_ts49,MWMM TS register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x12C8++0x03
line.long 0x00 "mtgy_op_ts50,MWMM TS register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x12CC++0x03
line.long 0x00 "mtgy_op_ts51,MWMM TS register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x12D0++0x03
line.long 0x00 "mtgy_op_ts52,MWMM TS register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x12D4++0x03
line.long 0x00 "mtgy_op_ts53,MWMM TS register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x12D8++0x03
line.long 0x00 "mtgy_op_ts54,MWMM TS register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x12DC++0x03
line.long 0x00 "mtgy_op_ts55,MWMM TS register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x12E0++0x03
line.long 0x00 "mtgy_op_ts56,MWMM TS register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x12E4++0x03
line.long 0x00 "mtgy_op_ts57,MWMM TS register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x12E8++0x03
line.long 0x00 "mtgy_op_ts58,MWMM TS register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x12EC++0x03
line.long 0x00 "mtgy_op_ts59,MWMM TS register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x12F0++0x03
line.long 0x00 "mtgy_op_ts60,MWMM TS register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x12F4++0x03
line.long 0x00 "mtgy_op_ts61,MWMM TS register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x12F8++0x03
line.long 0x00 "mtgy_op_ts62,MWMM TS register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x12FC++0x03
line.long 0x00 "mtgy_op_ts63,MWMM TS register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1300++0x03
line.long 0x00 "mtgy_op_ts64,MWMM TS register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1304++0x03
line.long 0x00 "mtgy_op_ts65,MWMM TS register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1308++0x03
line.long 0x00 "mtgy_op_ts66,MWMM TS register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x130C++0x03
line.long 0x00 "mtgy_op_ts67,MWMM TS register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1310++0x03
line.long 0x00 "mtgy_op_ts68,MWMM TS register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1314++0x03
line.long 0x00 "mtgy_op_ts69,MWMM TS register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1318++0x03
line.long 0x00 "mtgy_op_ts70,MWMM TS register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x131C++0x03
line.long 0x00 "mtgy_op_ts71,MWMM TS register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1320++0x03
line.long 0x00 "mtgy_op_ts72,MWMM TS register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1324++0x03
line.long 0x00 "mtgy_op_ts73,MWMM TS register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1328++0x03
line.long 0x00 "mtgy_op_ts74,MWMM TS register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x132C++0x03
line.long 0x00 "mtgy_op_ts75,MWMM TS register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1330++0x03
line.long 0x00 "mtgy_op_ts76,MWMM TS register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1334++0x03
line.long 0x00 "mtgy_op_ts77,MWMM TS register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1338++0x03
line.long 0x00 "mtgy_op_ts78,MWMM TS register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x133C++0x03
line.long 0x00 "mtgy_op_ts79,MWMM TS register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1340++0x03
line.long 0x00 "mtgy_op_ts80,MWMM TS register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1344++0x03
line.long 0x00 "mtgy_op_ts81,MWMM TS register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1348++0x03
line.long 0x00 "mtgy_op_ts82,MWMM TS register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x134C++0x03
line.long 0x00 "mtgy_op_ts83,MWMM TS register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1350++0x03
line.long 0x00 "mtgy_op_ts84,MWMM TS register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1354++0x03
line.long 0x00 "mtgy_op_ts85,MWMM TS register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1358++0x03
line.long 0x00 "mtgy_op_ts86,MWMM TS register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x135C++0x03
line.long 0x00 "mtgy_op_ts87,MWMM TS register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1360++0x03
line.long 0x00 "mtgy_op_ts88,MWMM TS register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1364++0x03
line.long 0x00 "mtgy_op_ts89,MWMM TS register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1368++0x03
line.long 0x00 "mtgy_op_ts90,MWMM TS register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x136C++0x03
line.long 0x00 "mtgy_op_ts91,MWMM TS register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1370++0x03
line.long 0x00 "mtgy_op_ts92,MWMM TS register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1374++0x03
line.long 0x00 "mtgy_op_ts93,MWMM TS register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1378++0x03
line.long 0x00 "mtgy_op_ts94,MWMM TS register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x137C++0x03
line.long 0x00 "mtgy_op_ts95,MWMM TS register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1380++0x03
line.long 0x00 "mtgy_op_ts96,MWMM TS register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1384++0x03
line.long 0x00 "mtgy_op_ts97,MWMM TS register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1388++0x03
line.long 0x00 "mtgy_op_ts98,MWMM TS register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x138C++0x03
line.long 0x00 "mtgy_op_ts99,MWMM TS register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1390++0x03
line.long 0x00 "mtgy_op_ts100,MWMM TS register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1394++0x03
line.long 0x00 "mtgy_op_ts101,MWMM TS register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1398++0x03
line.long 0x00 "mtgy_op_ts102,MWMM TS register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x139C++0x03
line.long 0x00 "mtgy_op_ts103,MWMM TS register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x13A0++0x03
line.long 0x00 "mtgy_op_ts104,MWMM TS register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x13A4++0x03
line.long 0x00 "mtgy_op_ts105,MWMM TS register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x13A8++0x03
line.long 0x00 "mtgy_op_ts106,MWMM TS register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x13AC++0x03
line.long 0x00 "mtgy_op_ts107,MWMM TS register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x13B0++0x03
line.long 0x00 "mtgy_op_ts108,MWMM TS register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x13B4++0x03
line.long 0x00 "mtgy_op_ts109,MWMM TS register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x13B8++0x03
line.long 0x00 "mtgy_op_ts110,MWMM TS register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x13BC++0x03
line.long 0x00 "mtgy_op_ts111,MWMM TS register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x13C0++0x03
line.long 0x00 "mtgy_op_ts112,MWMM TS register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x13C4++0x03
line.long 0x00 "mtgy_op_ts113,MWMM TS register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x13C8++0x03
line.long 0x00 "mtgy_op_ts114,MWMM TS register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x13CC++0x03
line.long 0x00 "mtgy_op_ts115,MWMM TS register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x13D0++0x03
line.long 0x00 "mtgy_op_ts116,MWMM TS register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x13D4++0x03
line.long 0x00 "mtgy_op_ts117,MWMM TS register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x13D8++0x03
line.long 0x00 "mtgy_op_ts118,MWMM TS register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x13DC++0x03
line.long 0x00 "mtgy_op_ts119,MWMM TS register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x13E0++0x03
line.long 0x00 "mtgy_op_ts120,MWMM TS register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x13E4++0x03
line.long 0x00 "mtgy_op_ts121,MWMM TS register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x13E8++0x03
line.long 0x00 "mtgy_op_ts122,MWMM TS register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x13EC++0x03
line.long 0x00 "mtgy_op_ts123,MWMM TS register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x13F0++0x03
line.long 0x00 "mtgy_op_ts124,MWMM TS register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x13F4++0x03
line.long 0x00 "mtgy_op_ts125,MWMM TS register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x13F8++0x03
line.long 0x00 "mtgy_op_ts126,MWMM TS register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x13FC++0x03
line.long 0x00 "mtgy_op_ts127,MWMM TS register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
group.long 0x1400++0x03
line.long 0x00 "mtgy_op_p0,MWMM operand P register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1404++0x03
line.long 0x00 "mtgy_op_p1,MWMM operand P register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1408++0x03
line.long 0x00 "mtgy_op_p2,MWMM operand P register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x140C++0x03
line.long 0x00 "mtgy_op_p3,MWMM operand P register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1410++0x03
line.long 0x00 "mtgy_op_p4,MWMM operand P register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1414++0x03
line.long 0x00 "mtgy_op_p5,MWMM operand P register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1418++0x03
line.long 0x00 "mtgy_op_p6,MWMM operand P register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x141C++0x03
line.long 0x00 "mtgy_op_p7,MWMM operand P register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1420++0x03
line.long 0x00 "mtgy_op_p8,MWMM operand P register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1424++0x03
line.long 0x00 "mtgy_op_p9,MWMM operand P register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1428++0x03
line.long 0x00 "mtgy_op_p10,MWMM operand P register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x142C++0x03
line.long 0x00 "mtgy_op_p11,MWMM operand P register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1430++0x03
line.long 0x00 "mtgy_op_p12,MWMM operand P register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1434++0x03
line.long 0x00 "mtgy_op_p13,MWMM operand P register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1438++0x03
line.long 0x00 "mtgy_op_p14,MWMM operand P register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x143C++0x03
line.long 0x00 "mtgy_op_p15,MWMM operand P register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1440++0x03
line.long 0x00 "mtgy_op_p16,MWMM operand P register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1444++0x03
line.long 0x00 "mtgy_op_p17,MWMM operand P register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1448++0x03
line.long 0x00 "mtgy_op_p18,MWMM operand P register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x144C++0x03
line.long 0x00 "mtgy_op_p19,MWMM operand P register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1450++0x03
line.long 0x00 "mtgy_op_p20,MWMM operand P register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1454++0x03
line.long 0x00 "mtgy_op_p21,MWMM operand P register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1458++0x03
line.long 0x00 "mtgy_op_p22,MWMM operand P register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x145C++0x03
line.long 0x00 "mtgy_op_p23,MWMM operand P register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1460++0x03
line.long 0x00 "mtgy_op_p24,MWMM operand P register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1464++0x03
line.long 0x00 "mtgy_op_p25,MWMM operand P register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1468++0x03
line.long 0x00 "mtgy_op_p26,MWMM operand P register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x146C++0x03
line.long 0x00 "mtgy_op_p27,MWMM operand P register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1470++0x03
line.long 0x00 "mtgy_op_p28,MWMM operand P register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1474++0x03
line.long 0x00 "mtgy_op_p29,MWMM operand P register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1478++0x03
line.long 0x00 "mtgy_op_p30,MWMM operand P register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x147C++0x03
line.long 0x00 "mtgy_op_p31,MWMM operand P register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1480++0x03
line.long 0x00 "mtgy_op_p32,MWMM operand P register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1484++0x03
line.long 0x00 "mtgy_op_p33,MWMM operand P register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1488++0x03
line.long 0x00 "mtgy_op_p34,MWMM operand P register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x148C++0x03
line.long 0x00 "mtgy_op_p35,MWMM operand P register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1490++0x03
line.long 0x00 "mtgy_op_p36,MWMM operand P register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1494++0x03
line.long 0x00 "mtgy_op_p37,MWMM operand P register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1498++0x03
line.long 0x00 "mtgy_op_p38,MWMM operand P register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x149C++0x03
line.long 0x00 "mtgy_op_p39,MWMM operand P register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x14A0++0x03
line.long 0x00 "mtgy_op_p40,MWMM operand P register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x14A4++0x03
line.long 0x00 "mtgy_op_p41,MWMM operand P register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x14A8++0x03
line.long 0x00 "mtgy_op_p42,MWMM operand P register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x14AC++0x03
line.long 0x00 "mtgy_op_p43,MWMM operand P register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x14B0++0x03
line.long 0x00 "mtgy_op_p44,MWMM operand P register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x14B4++0x03
line.long 0x00 "mtgy_op_p45,MWMM operand P register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x14B8++0x03
line.long 0x00 "mtgy_op_p46,MWMM operand P register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x14BC++0x03
line.long 0x00 "mtgy_op_p47,MWMM operand P register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x14C0++0x03
line.long 0x00 "mtgy_op_p48,MWMM operand P register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x14C4++0x03
line.long 0x00 "mtgy_op_p49,MWMM operand P register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x14C8++0x03
line.long 0x00 "mtgy_op_p50,MWMM operand P register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x14CC++0x03
line.long 0x00 "mtgy_op_p51,MWMM operand P register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x14D0++0x03
line.long 0x00 "mtgy_op_p52,MWMM operand P register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x14D4++0x03
line.long 0x00 "mtgy_op_p53,MWMM operand P register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x14D8++0x03
line.long 0x00 "mtgy_op_p54,MWMM operand P register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x14DC++0x03
line.long 0x00 "mtgy_op_p55,MWMM operand P register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x14E0++0x03
line.long 0x00 "mtgy_op_p56,MWMM operand P register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x14E4++0x03
line.long 0x00 "mtgy_op_p57,MWMM operand P register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x14E8++0x03
line.long 0x00 "mtgy_op_p58,MWMM operand P register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x14EC++0x03
line.long 0x00 "mtgy_op_p59,MWMM operand P register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x14F0++0x03
line.long 0x00 "mtgy_op_p60,MWMM operand P register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x14F4++0x03
line.long 0x00 "mtgy_op_p61,MWMM operand P register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x14F8++0x03
line.long 0x00 "mtgy_op_p62,MWMM operand P register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x14FC++0x03
line.long 0x00 "mtgy_op_p63,MWMM operand P register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1500++0x03
line.long 0x00 "mtgy_op_p64,MWMM operand P register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1504++0x03
line.long 0x00 "mtgy_op_p65,MWMM operand P register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1508++0x03
line.long 0x00 "mtgy_op_p66,MWMM operand P register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x150C++0x03
line.long 0x00 "mtgy_op_p67,MWMM operand P register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1510++0x03
line.long 0x00 "mtgy_op_p68,MWMM operand P register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1514++0x03
line.long 0x00 "mtgy_op_p69,MWMM operand P register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1518++0x03
line.long 0x00 "mtgy_op_p70,MWMM operand P register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x151C++0x03
line.long 0x00 "mtgy_op_p71,MWMM operand P register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1520++0x03
line.long 0x00 "mtgy_op_p72,MWMM operand P register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1524++0x03
line.long 0x00 "mtgy_op_p73,MWMM operand P register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1528++0x03
line.long 0x00 "mtgy_op_p74,MWMM operand P register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x152C++0x03
line.long 0x00 "mtgy_op_p75,MWMM operand P register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1530++0x03
line.long 0x00 "mtgy_op_p76,MWMM operand P register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1534++0x03
line.long 0x00 "mtgy_op_p77,MWMM operand P register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1538++0x03
line.long 0x00 "mtgy_op_p78,MWMM operand P register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x153C++0x03
line.long 0x00 "mtgy_op_p79,MWMM operand P register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1540++0x03
line.long 0x00 "mtgy_op_p80,MWMM operand P register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1544++0x03
line.long 0x00 "mtgy_op_p81,MWMM operand P register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1548++0x03
line.long 0x00 "mtgy_op_p82,MWMM operand P register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x154C++0x03
line.long 0x00 "mtgy_op_p83,MWMM operand P register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1550++0x03
line.long 0x00 "mtgy_op_p84,MWMM operand P register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1554++0x03
line.long 0x00 "mtgy_op_p85,MWMM operand P register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1558++0x03
line.long 0x00 "mtgy_op_p86,MWMM operand P register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x155C++0x03
line.long 0x00 "mtgy_op_p87,MWMM operand P register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1560++0x03
line.long 0x00 "mtgy_op_p88,MWMM operand P register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1564++0x03
line.long 0x00 "mtgy_op_p89,MWMM operand P register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1568++0x03
line.long 0x00 "mtgy_op_p90,MWMM operand P register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x156C++0x03
line.long 0x00 "mtgy_op_p91,MWMM operand P register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1570++0x03
line.long 0x00 "mtgy_op_p92,MWMM operand P register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1574++0x03
line.long 0x00 "mtgy_op_p93,MWMM operand P register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1578++0x03
line.long 0x00 "mtgy_op_p94,MWMM operand P register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x157C++0x03
line.long 0x00 "mtgy_op_p95,MWMM operand P register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1580++0x03
line.long 0x00 "mtgy_op_p96,MWMM operand P register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1584++0x03
line.long 0x00 "mtgy_op_p97,MWMM operand P register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1588++0x03
line.long 0x00 "mtgy_op_p98,MWMM operand P register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x158C++0x03
line.long 0x00 "mtgy_op_p99,MWMM operand P register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1590++0x03
line.long 0x00 "mtgy_op_p100,MWMM operand P register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1594++0x03
line.long 0x00 "mtgy_op_p101,MWMM operand P register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1598++0x03
line.long 0x00 "mtgy_op_p102,MWMM operand P register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x159C++0x03
line.long 0x00 "mtgy_op_p103,MWMM operand P register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x15A0++0x03
line.long 0x00 "mtgy_op_p104,MWMM operand P register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x15A4++0x03
line.long 0x00 "mtgy_op_p105,MWMM operand P register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x15A8++0x03
line.long 0x00 "mtgy_op_p106,MWMM operand P register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x15AC++0x03
line.long 0x00 "mtgy_op_p107,MWMM operand P register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x15B0++0x03
line.long 0x00 "mtgy_op_p108,MWMM operand P register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x15B4++0x03
line.long 0x00 "mtgy_op_p109,MWMM operand P register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x15B8++0x03
line.long 0x00 "mtgy_op_p110,MWMM operand P register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x15BC++0x03
line.long 0x00 "mtgy_op_p111,MWMM operand P register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x15C0++0x03
line.long 0x00 "mtgy_op_p112,MWMM operand P register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x15C4++0x03
line.long 0x00 "mtgy_op_p113,MWMM operand P register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x15C8++0x03
line.long 0x00 "mtgy_op_p114,MWMM operand P register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x15CC++0x03
line.long 0x00 "mtgy_op_p115,MWMM operand P register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x15D0++0x03
line.long 0x00 "mtgy_op_p116,MWMM operand P register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x15D4++0x03
line.long 0x00 "mtgy_op_p117,MWMM operand P register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x15D8++0x03
line.long 0x00 "mtgy_op_p118,MWMM operand P register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x15DC++0x03
line.long 0x00 "mtgy_op_p119,MWMM operand P register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x15E0++0x03
line.long 0x00 "mtgy_op_p120,MWMM operand P register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x15E4++0x03
line.long 0x00 "mtgy_op_p121,MWMM operand P register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x15E8++0x03
line.long 0x00 "mtgy_op_p122,MWMM operand P register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x15EC++0x03
line.long 0x00 "mtgy_op_p123,MWMM operand P register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x15F0++0x03
line.long 0x00 "mtgy_op_p124,MWMM operand P register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x15F4++0x03
line.long 0x00 "mtgy_op_p125,MWMM operand P register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x15F8++0x03
line.long 0x00 "mtgy_op_p126,MWMM operand P register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x15FC++0x03
line.long 0x00 "mtgy_op_p127,MWMM operand P register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
group.long 0x1600++0x03
line.long 0x00 "mtgy_op_b0,MWMM operand B register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1604++0x03
line.long 0x00 "mtgy_op_b1,MWMM operand B register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1608++0x03
line.long 0x00 "mtgy_op_b2,MWMM operand B register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x160C++0x03
line.long 0x00 "mtgy_op_b3,MWMM operand B register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1610++0x03
line.long 0x00 "mtgy_op_b4,MWMM operand B register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1614++0x03
line.long 0x00 "mtgy_op_b5,MWMM operand B register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1618++0x03
line.long 0x00 "mtgy_op_b6,MWMM operand B register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x161C++0x03
line.long 0x00 "mtgy_op_b7,MWMM operand B register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1620++0x03
line.long 0x00 "mtgy_op_b8,MWMM operand B register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1624++0x03
line.long 0x00 "mtgy_op_b9,MWMM operand B register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1628++0x03
line.long 0x00 "mtgy_op_b10,MWMM operand B register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x162C++0x03
line.long 0x00 "mtgy_op_b11,MWMM operand B register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1630++0x03
line.long 0x00 "mtgy_op_b12,MWMM operand B register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1634++0x03
line.long 0x00 "mtgy_op_b13,MWMM operand B register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1638++0x03
line.long 0x00 "mtgy_op_b14,MWMM operand B register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x163C++0x03
line.long 0x00 "mtgy_op_b15,MWMM operand B register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1640++0x03
line.long 0x00 "mtgy_op_b16,MWMM operand B register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1644++0x03
line.long 0x00 "mtgy_op_b17,MWMM operand B register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1648++0x03
line.long 0x00 "mtgy_op_b18,MWMM operand B register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x164C++0x03
line.long 0x00 "mtgy_op_b19,MWMM operand B register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1650++0x03
line.long 0x00 "mtgy_op_b20,MWMM operand B register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1654++0x03
line.long 0x00 "mtgy_op_b21,MWMM operand B register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1658++0x03
line.long 0x00 "mtgy_op_b22,MWMM operand B register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x165C++0x03
line.long 0x00 "mtgy_op_b23,MWMM operand B register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1660++0x03
line.long 0x00 "mtgy_op_b24,MWMM operand B register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1664++0x03
line.long 0x00 "mtgy_op_b25,MWMM operand B register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1668++0x03
line.long 0x00 "mtgy_op_b26,MWMM operand B register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x166C++0x03
line.long 0x00 "mtgy_op_b27,MWMM operand B register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1670++0x03
line.long 0x00 "mtgy_op_b28,MWMM operand B register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1674++0x03
line.long 0x00 "mtgy_op_b29,MWMM operand B register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1678++0x03
line.long 0x00 "mtgy_op_b30,MWMM operand B register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x167C++0x03
line.long 0x00 "mtgy_op_b31,MWMM operand B register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1680++0x03
line.long 0x00 "mtgy_op_b32,MWMM operand B register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1684++0x03
line.long 0x00 "mtgy_op_b33,MWMM operand B register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1688++0x03
line.long 0x00 "mtgy_op_b34,MWMM operand B register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x168C++0x03
line.long 0x00 "mtgy_op_b35,MWMM operand B register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1690++0x03
line.long 0x00 "mtgy_op_b36,MWMM operand B register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1694++0x03
line.long 0x00 "mtgy_op_b37,MWMM operand B register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1698++0x03
line.long 0x00 "mtgy_op_b38,MWMM operand B register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x169C++0x03
line.long 0x00 "mtgy_op_b39,MWMM operand B register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x16A0++0x03
line.long 0x00 "mtgy_op_b40,MWMM operand B register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x16A4++0x03
line.long 0x00 "mtgy_op_b41,MWMM operand B register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x16A8++0x03
line.long 0x00 "mtgy_op_b42,MWMM operand B register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x16AC++0x03
line.long 0x00 "mtgy_op_b43,MWMM operand B register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x16B0++0x03
line.long 0x00 "mtgy_op_b44,MWMM operand B register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x16B4++0x03
line.long 0x00 "mtgy_op_b45,MWMM operand B register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x16B8++0x03
line.long 0x00 "mtgy_op_b46,MWMM operand B register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x16BC++0x03
line.long 0x00 "mtgy_op_b47,MWMM operand B register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x16C0++0x03
line.long 0x00 "mtgy_op_b48,MWMM operand B register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x16C4++0x03
line.long 0x00 "mtgy_op_b49,MWMM operand B register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x16C8++0x03
line.long 0x00 "mtgy_op_b50,MWMM operand B register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x16CC++0x03
line.long 0x00 "mtgy_op_b51,MWMM operand B register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x16D0++0x03
line.long 0x00 "mtgy_op_b52,MWMM operand B register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x16D4++0x03
line.long 0x00 "mtgy_op_b53,MWMM operand B register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x16D8++0x03
line.long 0x00 "mtgy_op_b54,MWMM operand B register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x16DC++0x03
line.long 0x00 "mtgy_op_b55,MWMM operand B register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x16E0++0x03
line.long 0x00 "mtgy_op_b56,MWMM operand B register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x16E4++0x03
line.long 0x00 "mtgy_op_b57,MWMM operand B register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x16E8++0x03
line.long 0x00 "mtgy_op_b58,MWMM operand B register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x16EC++0x03
line.long 0x00 "mtgy_op_b59,MWMM operand B register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x16F0++0x03
line.long 0x00 "mtgy_op_b60,MWMM operand B register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x16F4++0x03
line.long 0x00 "mtgy_op_b61,MWMM operand B register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x16F8++0x03
line.long 0x00 "mtgy_op_b62,MWMM operand B register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x16FC++0x03
line.long 0x00 "mtgy_op_b63,MWMM operand B register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1700++0x03
line.long 0x00 "mtgy_op_b64,MWMM operand B register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1704++0x03
line.long 0x00 "mtgy_op_b65,MWMM operand B register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1708++0x03
line.long 0x00 "mtgy_op_b66,MWMM operand B register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x170C++0x03
line.long 0x00 "mtgy_op_b67,MWMM operand B register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1710++0x03
line.long 0x00 "mtgy_op_b68,MWMM operand B register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1714++0x03
line.long 0x00 "mtgy_op_b69,MWMM operand B register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1718++0x03
line.long 0x00 "mtgy_op_b70,MWMM operand B register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x171C++0x03
line.long 0x00 "mtgy_op_b71,MWMM operand B register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1720++0x03
line.long 0x00 "mtgy_op_b72,MWMM operand B register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1724++0x03
line.long 0x00 "mtgy_op_b73,MWMM operand B register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1728++0x03
line.long 0x00 "mtgy_op_b74,MWMM operand B register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x172C++0x03
line.long 0x00 "mtgy_op_b75,MWMM operand B register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1730++0x03
line.long 0x00 "mtgy_op_b76,MWMM operand B register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1734++0x03
line.long 0x00 "mtgy_op_b77,MWMM operand B register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1738++0x03
line.long 0x00 "mtgy_op_b78,MWMM operand B register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x173C++0x03
line.long 0x00 "mtgy_op_b79,MWMM operand B register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1740++0x03
line.long 0x00 "mtgy_op_b80,MWMM operand B register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1744++0x03
line.long 0x00 "mtgy_op_b81,MWMM operand B register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1748++0x03
line.long 0x00 "mtgy_op_b82,MWMM operand B register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x174C++0x03
line.long 0x00 "mtgy_op_b83,MWMM operand B register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1750++0x03
line.long 0x00 "mtgy_op_b84,MWMM operand B register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1754++0x03
line.long 0x00 "mtgy_op_b85,MWMM operand B register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1758++0x03
line.long 0x00 "mtgy_op_b86,MWMM operand B register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x175C++0x03
line.long 0x00 "mtgy_op_b87,MWMM operand B register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1760++0x03
line.long 0x00 "mtgy_op_b88,MWMM operand B register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1764++0x03
line.long 0x00 "mtgy_op_b89,MWMM operand B register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1768++0x03
line.long 0x00 "mtgy_op_b90,MWMM operand B register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x176C++0x03
line.long 0x00 "mtgy_op_b91,MWMM operand B register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1770++0x03
line.long 0x00 "mtgy_op_b92,MWMM operand B register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1774++0x03
line.long 0x00 "mtgy_op_b93,MWMM operand B register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1778++0x03
line.long 0x00 "mtgy_op_b94,MWMM operand B register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x177C++0x03
line.long 0x00 "mtgy_op_b95,MWMM operand B register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1780++0x03
line.long 0x00 "mtgy_op_b96,MWMM operand B register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1784++0x03
line.long 0x00 "mtgy_op_b97,MWMM operand B register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1788++0x03
line.long 0x00 "mtgy_op_b98,MWMM operand B register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x178C++0x03
line.long 0x00 "mtgy_op_b99,MWMM operand B register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1790++0x03
line.long 0x00 "mtgy_op_b100,MWMM operand B register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1794++0x03
line.long 0x00 "mtgy_op_b101,MWMM operand B register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1798++0x03
line.long 0x00 "mtgy_op_b102,MWMM operand B register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x179C++0x03
line.long 0x00 "mtgy_op_b103,MWMM operand B register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x17A0++0x03
line.long 0x00 "mtgy_op_b104,MWMM operand B register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x17A4++0x03
line.long 0x00 "mtgy_op_b105,MWMM operand B register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x17A8++0x03
line.long 0x00 "mtgy_op_b106,MWMM operand B register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x17AC++0x03
line.long 0x00 "mtgy_op_b107,MWMM operand B register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x17B0++0x03
line.long 0x00 "mtgy_op_b108,MWMM operand B register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x17B4++0x03
line.long 0x00 "mtgy_op_b109,MWMM operand B register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x17B8++0x03
line.long 0x00 "mtgy_op_b110,MWMM operand B register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x17BC++0x03
line.long 0x00 "mtgy_op_b111,MWMM operand B register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x17C0++0x03
line.long 0x00 "mtgy_op_b112,MWMM operand B register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x17C4++0x03
line.long 0x00 "mtgy_op_b113,MWMM operand B register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x17C8++0x03
line.long 0x00 "mtgy_op_b114,MWMM operand B register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x17CC++0x03
line.long 0x00 "mtgy_op_b115,MWMM operand B register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x17D0++0x03
line.long 0x00 "mtgy_op_b116,MWMM operand B register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x17D4++0x03
line.long 0x00 "mtgy_op_b117,MWMM operand B register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x17D8++0x03
line.long 0x00 "mtgy_op_b118,MWMM operand B register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x17DC++0x03
line.long 0x00 "mtgy_op_b119,MWMM operand B register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x17E0++0x03
line.long 0x00 "mtgy_op_b120,MWMM operand B register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x17E4++0x03
line.long 0x00 "mtgy_op_b121,MWMM operand B register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x17E8++0x03
line.long 0x00 "mtgy_op_b122,MWMM operand B register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x17EC++0x03
line.long 0x00 "mtgy_op_b123,MWMM operand B register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x17F0++0x03
line.long 0x00 "mtgy_op_b124,MWMM operand B register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x17F4++0x03
line.long 0x00 "mtgy_op_b125,MWMM operand B register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x17F8++0x03
line.long 0x00 "mtgy_op_b126,MWMM operand B register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x17FC++0x03
line.long 0x00 "mtgy_op_b127,MWMM operand B register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
group.long 0x1800++0x03
line.long 0x00 "mtgy_op_a0,MWMM operand A register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1804++0x03
line.long 0x00 "mtgy_op_a1,MWMM operand A register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1808++0x03
line.long 0x00 "mtgy_op_a2,MWMM operand A register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x180C++0x03
line.long 0x00 "mtgy_op_a3,MWMM operand A register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1810++0x03
line.long 0x00 "mtgy_op_a4,MWMM operand A register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1814++0x03
line.long 0x00 "mtgy_op_a5,MWMM operand A register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1818++0x03
line.long 0x00 "mtgy_op_a6,MWMM operand A register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x181C++0x03
line.long 0x00 "mtgy_op_a7,MWMM operand A register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1820++0x03
line.long 0x00 "mtgy_op_a8,MWMM operand A register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1824++0x03
line.long 0x00 "mtgy_op_a9,MWMM operand A register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1828++0x03
line.long 0x00 "mtgy_op_a10,MWMM operand A register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x182C++0x03
line.long 0x00 "mtgy_op_a11,MWMM operand A register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1830++0x03
line.long 0x00 "mtgy_op_a12,MWMM operand A register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1834++0x03
line.long 0x00 "mtgy_op_a13,MWMM operand A register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1838++0x03
line.long 0x00 "mtgy_op_a14,MWMM operand A register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x183C++0x03
line.long 0x00 "mtgy_op_a15,MWMM operand A register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1840++0x03
line.long 0x00 "mtgy_op_a16,MWMM operand A register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1844++0x03
line.long 0x00 "mtgy_op_a17,MWMM operand A register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1848++0x03
line.long 0x00 "mtgy_op_a18,MWMM operand A register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x184C++0x03
line.long 0x00 "mtgy_op_a19,MWMM operand A register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1850++0x03
line.long 0x00 "mtgy_op_a20,MWMM operand A register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1854++0x03
line.long 0x00 "mtgy_op_a21,MWMM operand A register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1858++0x03
line.long 0x00 "mtgy_op_a22,MWMM operand A register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x185C++0x03
line.long 0x00 "mtgy_op_a23,MWMM operand A register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1860++0x03
line.long 0x00 "mtgy_op_a24,MWMM operand A register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1864++0x03
line.long 0x00 "mtgy_op_a25,MWMM operand A register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1868++0x03
line.long 0x00 "mtgy_op_a26,MWMM operand A register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x186C++0x03
line.long 0x00 "mtgy_op_a27,MWMM operand A register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1870++0x03
line.long 0x00 "mtgy_op_a28,MWMM operand A register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1874++0x03
line.long 0x00 "mtgy_op_a29,MWMM operand A register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1878++0x03
line.long 0x00 "mtgy_op_a30,MWMM operand A register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x187C++0x03
line.long 0x00 "mtgy_op_a31,MWMM operand A register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1880++0x03
line.long 0x00 "mtgy_op_a32,MWMM operand A register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1884++0x03
line.long 0x00 "mtgy_op_a33,MWMM operand A register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1888++0x03
line.long 0x00 "mtgy_op_a34,MWMM operand A register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x188C++0x03
line.long 0x00 "mtgy_op_a35,MWMM operand A register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1890++0x03
line.long 0x00 "mtgy_op_a36,MWMM operand A register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1894++0x03
line.long 0x00 "mtgy_op_a37,MWMM operand A register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1898++0x03
line.long 0x00 "mtgy_op_a38,MWMM operand A register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x189C++0x03
line.long 0x00 "mtgy_op_a39,MWMM operand A register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x18A0++0x03
line.long 0x00 "mtgy_op_a40,MWMM operand A register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x18A4++0x03
line.long 0x00 "mtgy_op_a41,MWMM operand A register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x18A8++0x03
line.long 0x00 "mtgy_op_a42,MWMM operand A register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x18AC++0x03
line.long 0x00 "mtgy_op_a43,MWMM operand A register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x18B0++0x03
line.long 0x00 "mtgy_op_a44,MWMM operand A register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x18B4++0x03
line.long 0x00 "mtgy_op_a45,MWMM operand A register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x18B8++0x03
line.long 0x00 "mtgy_op_a46,MWMM operand A register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x18BC++0x03
line.long 0x00 "mtgy_op_a47,MWMM operand A register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x18C0++0x03
line.long 0x00 "mtgy_op_a48,MWMM operand A register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x18C4++0x03
line.long 0x00 "mtgy_op_a49,MWMM operand A register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x18C8++0x03
line.long 0x00 "mtgy_op_a50,MWMM operand A register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x18CC++0x03
line.long 0x00 "mtgy_op_a51,MWMM operand A register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x18D0++0x03
line.long 0x00 "mtgy_op_a52,MWMM operand A register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x18D4++0x03
line.long 0x00 "mtgy_op_a53,MWMM operand A register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x18D8++0x03
line.long 0x00 "mtgy_op_a54,MWMM operand A register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x18DC++0x03
line.long 0x00 "mtgy_op_a55,MWMM operand A register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x18E0++0x03
line.long 0x00 "mtgy_op_a56,MWMM operand A register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x18E4++0x03
line.long 0x00 "mtgy_op_a57,MWMM operand A register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x18E8++0x03
line.long 0x00 "mtgy_op_a58,MWMM operand A register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x18EC++0x03
line.long 0x00 "mtgy_op_a59,MWMM operand A register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x18F0++0x03
line.long 0x00 "mtgy_op_a60,MWMM operand A register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x18F4++0x03
line.long 0x00 "mtgy_op_a61,MWMM operand A register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x18F8++0x03
line.long 0x00 "mtgy_op_a62,MWMM operand A register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x18FC++0x03
line.long 0x00 "mtgy_op_a63,MWMM operand A register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1900++0x03
line.long 0x00 "mtgy_op_a64,MWMM operand A register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1904++0x03
line.long 0x00 "mtgy_op_a65,MWMM operand A register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1908++0x03
line.long 0x00 "mtgy_op_a66,MWMM operand A register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x190C++0x03
line.long 0x00 "mtgy_op_a67,MWMM operand A register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1910++0x03
line.long 0x00 "mtgy_op_a68,MWMM operand A register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1914++0x03
line.long 0x00 "mtgy_op_a69,MWMM operand A register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1918++0x03
line.long 0x00 "mtgy_op_a70,MWMM operand A register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x191C++0x03
line.long 0x00 "mtgy_op_a71,MWMM operand A register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1920++0x03
line.long 0x00 "mtgy_op_a72,MWMM operand A register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1924++0x03
line.long 0x00 "mtgy_op_a73,MWMM operand A register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1928++0x03
line.long 0x00 "mtgy_op_a74,MWMM operand A register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x192C++0x03
line.long 0x00 "mtgy_op_a75,MWMM operand A register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1930++0x03
line.long 0x00 "mtgy_op_a76,MWMM operand A register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1934++0x03
line.long 0x00 "mtgy_op_a77,MWMM operand A register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1938++0x03
line.long 0x00 "mtgy_op_a78,MWMM operand A register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x193C++0x03
line.long 0x00 "mtgy_op_a79,MWMM operand A register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1940++0x03
line.long 0x00 "mtgy_op_a80,MWMM operand A register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1944++0x03
line.long 0x00 "mtgy_op_a81,MWMM operand A register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1948++0x03
line.long 0x00 "mtgy_op_a82,MWMM operand A register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x194C++0x03
line.long 0x00 "mtgy_op_a83,MWMM operand A register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1950++0x03
line.long 0x00 "mtgy_op_a84,MWMM operand A register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1954++0x03
line.long 0x00 "mtgy_op_a85,MWMM operand A register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1958++0x03
line.long 0x00 "mtgy_op_a86,MWMM operand A register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x195C++0x03
line.long 0x00 "mtgy_op_a87,MWMM operand A register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1960++0x03
line.long 0x00 "mtgy_op_a88,MWMM operand A register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1964++0x03
line.long 0x00 "mtgy_op_a89,MWMM operand A register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1968++0x03
line.long 0x00 "mtgy_op_a90,MWMM operand A register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x196C++0x03
line.long 0x00 "mtgy_op_a91,MWMM operand A register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1970++0x03
line.long 0x00 "mtgy_op_a92,MWMM operand A register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1974++0x03
line.long 0x00 "mtgy_op_a93,MWMM operand A register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1978++0x03
line.long 0x00 "mtgy_op_a94,MWMM operand A register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x197C++0x03
line.long 0x00 "mtgy_op_a95,MWMM operand A register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1980++0x03
line.long 0x00 "mtgy_op_a96,MWMM operand A register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1984++0x03
line.long 0x00 "mtgy_op_a97,MWMM operand A register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1988++0x03
line.long 0x00 "mtgy_op_a98,MWMM operand A register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x198C++0x03
line.long 0x00 "mtgy_op_a99,MWMM operand A register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1990++0x03
line.long 0x00 "mtgy_op_a100,MWMM operand A register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1994++0x03
line.long 0x00 "mtgy_op_a101,MWMM operand A register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1998++0x03
line.long 0x00 "mtgy_op_a102,MWMM operand A register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x199C++0x03
line.long 0x00 "mtgy_op_a103,MWMM operand A register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x19A0++0x03
line.long 0x00 "mtgy_op_a104,MWMM operand A register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x19A4++0x03
line.long 0x00 "mtgy_op_a105,MWMM operand A register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x19A8++0x03
line.long 0x00 "mtgy_op_a106,MWMM operand A register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x19AC++0x03
line.long 0x00 "mtgy_op_a107,MWMM operand A register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x19B0++0x03
line.long 0x00 "mtgy_op_a108,MWMM operand A register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x19B4++0x03
line.long 0x00 "mtgy_op_a109,MWMM operand A register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x19B8++0x03
line.long 0x00 "mtgy_op_a110,MWMM operand A register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x19BC++0x03
line.long 0x00 "mtgy_op_a111,MWMM operand A register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x19C0++0x03
line.long 0x00 "mtgy_op_a112,MWMM operand A register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x19C4++0x03
line.long 0x00 "mtgy_op_a113,MWMM operand A register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x19C8++0x03
line.long 0x00 "mtgy_op_a114,MWMM operand A register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x19CC++0x03
line.long 0x00 "mtgy_op_a115,MWMM operand A register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x19D0++0x03
line.long 0x00 "mtgy_op_a116,MWMM operand A register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x19D4++0x03
line.long 0x00 "mtgy_op_a117,MWMM operand A register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x19D8++0x03
line.long 0x00 "mtgy_op_a118,MWMM operand A register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x19DC++0x03
line.long 0x00 "mtgy_op_a119,MWMM operand A register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x19E0++0x03
line.long 0x00 "mtgy_op_a120,MWMM operand A register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x19E4++0x03
line.long 0x00 "mtgy_op_a121,MWMM operand A register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x19E8++0x03
line.long 0x00 "mtgy_op_a122,MWMM operand A register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x19EC++0x03
line.long 0x00 "mtgy_op_a123,MWMM operand A register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x19F0++0x03
line.long 0x00 "mtgy_op_a124,MWMM operand A register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x19F4++0x03
line.long 0x00 "mtgy_op_a125,MWMM operand A register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x19F8++0x03
line.long 0x00 "mtgy_op_a126,MWMM operand A register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x19FC++0x03
line.long 0x00 "mtgy_op_a127,MWMM operand A register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
group.long 0x1A00++0x03
line.long 0x00 "mtgy_op_e0,MWMM operand E register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1A04++0x03
line.long 0x00 "mtgy_op_e1,MWMM operand E register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1A08++0x03
line.long 0x00 "mtgy_op_e2,MWMM operand E register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x1A0C++0x03
line.long 0x00 "mtgy_op_e3,MWMM operand E register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1A10++0x03
line.long 0x00 "mtgy_op_e4,MWMM operand E register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1A14++0x03
line.long 0x00 "mtgy_op_e5,MWMM operand E register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1A18++0x03
line.long 0x00 "mtgy_op_e6,MWMM operand E register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x1A1C++0x03
line.long 0x00 "mtgy_op_e7,MWMM operand E register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1A20++0x03
line.long 0x00 "mtgy_op_e8,MWMM operand E register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1A24++0x03
line.long 0x00 "mtgy_op_e9,MWMM operand E register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1A28++0x03
line.long 0x00 "mtgy_op_e10,MWMM operand E register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x1A2C++0x03
line.long 0x00 "mtgy_op_e11,MWMM operand E register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1A30++0x03
line.long 0x00 "mtgy_op_e12,MWMM operand E register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1A34++0x03
line.long 0x00 "mtgy_op_e13,MWMM operand E register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1A38++0x03
line.long 0x00 "mtgy_op_e14,MWMM operand E register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x1A3C++0x03
line.long 0x00 "mtgy_op_e15,MWMM operand E register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1A40++0x03
line.long 0x00 "mtgy_op_e16,MWMM operand E register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1A44++0x03
line.long 0x00 "mtgy_op_e17,MWMM operand E register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1A48++0x03
line.long 0x00 "mtgy_op_e18,MWMM operand E register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x1A4C++0x03
line.long 0x00 "mtgy_op_e19,MWMM operand E register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1A50++0x03
line.long 0x00 "mtgy_op_e20,MWMM operand E register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1A54++0x03
line.long 0x00 "mtgy_op_e21,MWMM operand E register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1A58++0x03
line.long 0x00 "mtgy_op_e22,MWMM operand E register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x1A5C++0x03
line.long 0x00 "mtgy_op_e23,MWMM operand E register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1A60++0x03
line.long 0x00 "mtgy_op_e24,MWMM operand E register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1A64++0x03
line.long 0x00 "mtgy_op_e25,MWMM operand E register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1A68++0x03
line.long 0x00 "mtgy_op_e26,MWMM operand E register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x1A6C++0x03
line.long 0x00 "mtgy_op_e27,MWMM operand E register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1A70++0x03
line.long 0x00 "mtgy_op_e28,MWMM operand E register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1A74++0x03
line.long 0x00 "mtgy_op_e29,MWMM operand E register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1A78++0x03
line.long 0x00 "mtgy_op_e30,MWMM operand E register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x1A7C++0x03
line.long 0x00 "mtgy_op_e31,MWMM operand E register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1A80++0x03
line.long 0x00 "mtgy_op_e32,MWMM operand E register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1A84++0x03
line.long 0x00 "mtgy_op_e33,MWMM operand E register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1A88++0x03
line.long 0x00 "mtgy_op_e34,MWMM operand E register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x1A8C++0x03
line.long 0x00 "mtgy_op_e35,MWMM operand E register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1A90++0x03
line.long 0x00 "mtgy_op_e36,MWMM operand E register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1A94++0x03
line.long 0x00 "mtgy_op_e37,MWMM operand E register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1A98++0x03
line.long 0x00 "mtgy_op_e38,MWMM operand E register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x1A9C++0x03
line.long 0x00 "mtgy_op_e39,MWMM operand E register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x1AA0++0x03
line.long 0x00 "mtgy_op_e40,MWMM operand E register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x1AA4++0x03
line.long 0x00 "mtgy_op_e41,MWMM operand E register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x1AA8++0x03
line.long 0x00 "mtgy_op_e42,MWMM operand E register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x1AAC++0x03
line.long 0x00 "mtgy_op_e43,MWMM operand E register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x1AB0++0x03
line.long 0x00 "mtgy_op_e44,MWMM operand E register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x1AB4++0x03
line.long 0x00 "mtgy_op_e45,MWMM operand E register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x1AB8++0x03
line.long 0x00 "mtgy_op_e46,MWMM operand E register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x1ABC++0x03
line.long 0x00 "mtgy_op_e47,MWMM operand E register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x1AC0++0x03
line.long 0x00 "mtgy_op_e48,MWMM operand E register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x1AC4++0x03
line.long 0x00 "mtgy_op_e49,MWMM operand E register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x1AC8++0x03
line.long 0x00 "mtgy_op_e50,MWMM operand E register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x1ACC++0x03
line.long 0x00 "mtgy_op_e51,MWMM operand E register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x1AD0++0x03
line.long 0x00 "mtgy_op_e52,MWMM operand E register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x1AD4++0x03
line.long 0x00 "mtgy_op_e53,MWMM operand E register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x1AD8++0x03
line.long 0x00 "mtgy_op_e54,MWMM operand E register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x1ADC++0x03
line.long 0x00 "mtgy_op_e55,MWMM operand E register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x1AE0++0x03
line.long 0x00 "mtgy_op_e56,MWMM operand E register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x1AE4++0x03
line.long 0x00 "mtgy_op_e57,MWMM operand E register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x1AE8++0x03
line.long 0x00 "mtgy_op_e58,MWMM operand E register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x1AEC++0x03
line.long 0x00 "mtgy_op_e59,MWMM operand E register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x1AF0++0x03
line.long 0x00 "mtgy_op_e60,MWMM operand E register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x1AF4++0x03
line.long 0x00 "mtgy_op_e61,MWMM operand E register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x1AF8++0x03
line.long 0x00 "mtgy_op_e62,MWMM operand E register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x1AFC++0x03
line.long 0x00 "mtgy_op_e63,MWMM operand E register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1B00++0x03
line.long 0x00 "mtgy_op_e64,MWMM operand E register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1B04++0x03
line.long 0x00 "mtgy_op_e65,MWMM operand E register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1B08++0x03
line.long 0x00 "mtgy_op_e66,MWMM operand E register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x1B0C++0x03
line.long 0x00 "mtgy_op_e67,MWMM operand E register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1B10++0x03
line.long 0x00 "mtgy_op_e68,MWMM operand E register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1B14++0x03
line.long 0x00 "mtgy_op_e69,MWMM operand E register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1B18++0x03
line.long 0x00 "mtgy_op_e70,MWMM operand E register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x1B1C++0x03
line.long 0x00 "mtgy_op_e71,MWMM operand E register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1B20++0x03
line.long 0x00 "mtgy_op_e72,MWMM operand E register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1B24++0x03
line.long 0x00 "mtgy_op_e73,MWMM operand E register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1B28++0x03
line.long 0x00 "mtgy_op_e74,MWMM operand E register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x1B2C++0x03
line.long 0x00 "mtgy_op_e75,MWMM operand E register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1B30++0x03
line.long 0x00 "mtgy_op_e76,MWMM operand E register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1B34++0x03
line.long 0x00 "mtgy_op_e77,MWMM operand E register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1B38++0x03
line.long 0x00 "mtgy_op_e78,MWMM operand E register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x1B3C++0x03
line.long 0x00 "mtgy_op_e79,MWMM operand E register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1B40++0x03
line.long 0x00 "mtgy_op_e80,MWMM operand E register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1B44++0x03
line.long 0x00 "mtgy_op_e81,MWMM operand E register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1B48++0x03
line.long 0x00 "mtgy_op_e82,MWMM operand E register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x1B4C++0x03
line.long 0x00 "mtgy_op_e83,MWMM operand E register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1B50++0x03
line.long 0x00 "mtgy_op_e84,MWMM operand E register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1B54++0x03
line.long 0x00 "mtgy_op_e85,MWMM operand E register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1B58++0x03
line.long 0x00 "mtgy_op_e86,MWMM operand E register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x1B5C++0x03
line.long 0x00 "mtgy_op_e87,MWMM operand E register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1B60++0x03
line.long 0x00 "mtgy_op_e88,MWMM operand E register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1B64++0x03
line.long 0x00 "mtgy_op_e89,MWMM operand E register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1B68++0x03
line.long 0x00 "mtgy_op_e90,MWMM operand E register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x1B6C++0x03
line.long 0x00 "mtgy_op_e91,MWMM operand E register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1B70++0x03
line.long 0x00 "mtgy_op_e92,MWMM operand E register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1B74++0x03
line.long 0x00 "mtgy_op_e93,MWMM operand E register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1B78++0x03
line.long 0x00 "mtgy_op_e94,MWMM operand E register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x1B7C++0x03
line.long 0x00 "mtgy_op_e95,MWMM operand E register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1B80++0x03
line.long 0x00 "mtgy_op_e96,MWMM operand E register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1B84++0x03
line.long 0x00 "mtgy_op_e97,MWMM operand E register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1B88++0x03
line.long 0x00 "mtgy_op_e98,MWMM operand E register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x1B8C++0x03
line.long 0x00 "mtgy_op_e99,MWMM operand E register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1B90++0x03
line.long 0x00 "mtgy_op_e100,MWMM operand E register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1B94++0x03
line.long 0x00 "mtgy_op_e101,MWMM operand E register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1B98++0x03
line.long 0x00 "mtgy_op_e102,MWMM operand E register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x1B9C++0x03
line.long 0x00 "mtgy_op_e103,MWMM operand E register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x1BA0++0x03
line.long 0x00 "mtgy_op_e104,MWMM operand E register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x1BA4++0x03
line.long 0x00 "mtgy_op_e105,MWMM operand E register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x1BA8++0x03
line.long 0x00 "mtgy_op_e106,MWMM operand E register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x1BAC++0x03
line.long 0x00 "mtgy_op_e107,MWMM operand E register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x1BB0++0x03
line.long 0x00 "mtgy_op_e108,MWMM operand E register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x1BB4++0x03
line.long 0x00 "mtgy_op_e109,MWMM operand E register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x1BB8++0x03
line.long 0x00 "mtgy_op_e110,MWMM operand E register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x1BBC++0x03
line.long 0x00 "mtgy_op_e111,MWMM operand E register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x1BC0++0x03
line.long 0x00 "mtgy_op_e112,MWMM operand E register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x1BC4++0x03
line.long 0x00 "mtgy_op_e113,MWMM operand E register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x1BC8++0x03
line.long 0x00 "mtgy_op_e114,MWMM operand E register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x1BCC++0x03
line.long 0x00 "mtgy_op_e115,MWMM operand E register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x1BD0++0x03
line.long 0x00 "mtgy_op_e116,MWMM operand E register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x1BD4++0x03
line.long 0x00 "mtgy_op_e117,MWMM operand E register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x1BD8++0x03
line.long 0x00 "mtgy_op_e118,MWMM operand E register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x1BDC++0x03
line.long 0x00 "mtgy_op_e119,MWMM operand E register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x1BE0++0x03
line.long 0x00 "mtgy_op_e120,MWMM operand E register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x1BE4++0x03
line.long 0x00 "mtgy_op_e121,MWMM operand E register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x1BE8++0x03
line.long 0x00 "mtgy_op_e122,MWMM operand E register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x1BEC++0x03
line.long 0x00 "mtgy_op_e123,MWMM operand E register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x1BF0++0x03
line.long 0x00 "mtgy_op_e124,MWMM operand E register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x1BF4++0x03
line.long 0x00 "mtgy_op_e125,MWMM operand E register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x1BF8++0x03
line.long 0x00 "mtgy_op_e126,MWMM operand E register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x1BFC++0x03
line.long 0x00 "mtgy_op_e127,MWMM operand E register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
group.long 0x1C00++0x03
line.long 0x00 "mtgy_op_x0,MWMM operand X register 0"
hexmask.long 0x00 0.--31. 1. "val,data bits 31..0"
group.long 0x1C04++0x03
line.long 0x00 "mtgy_op_x1,MWMM operand X register 1"
hexmask.long 0x00 0.--31. 1. "val,data bits 63..32"
group.long 0x1C08++0x03
line.long 0x00 "mtgy_op_x2,MWMM operand X register 2"
hexmask.long 0x00 0.--31. 1. "val,data bits 95..64"
group.long 0x1C0C++0x03
line.long 0x00 "mtgy_op_x3,MWMM operand X register 3"
hexmask.long 0x00 0.--31. 1. "val,data bits 127..96"
group.long 0x1C10++0x03
line.long 0x00 "mtgy_op_x4,MWMM operand X register 4"
hexmask.long 0x00 0.--31. 1. "val,data bits 159..128"
group.long 0x1C14++0x03
line.long 0x00 "mtgy_op_x5,MWMM operand X register 5"
hexmask.long 0x00 0.--31. 1. "val,data bits 191..160"
group.long 0x1C18++0x03
line.long 0x00 "mtgy_op_x6,MWMM operand X register 6"
hexmask.long 0x00 0.--31. 1. "val,data bits 223..192"
group.long 0x1C1C++0x03
line.long 0x00 "mtgy_op_x7,MWMM operand X register 7"
hexmask.long 0x00 0.--31. 1. "val,data bits 255..224"
group.long 0x1C20++0x03
line.long 0x00 "mtgy_op_x8,MWMM operand X register 8"
hexmask.long 0x00 0.--31. 1. "val,data bits 287..256"
group.long 0x1C24++0x03
line.long 0x00 "mtgy_op_x9,MWMM operand X register 9"
hexmask.long 0x00 0.--31. 1. "val,data bits 319..288"
group.long 0x1C28++0x03
line.long 0x00 "mtgy_op_x10,MWMM operand X register 10"
hexmask.long 0x00 0.--31. 1. "val,data bits 351..320"
group.long 0x1C2C++0x03
line.long 0x00 "mtgy_op_x11,MWMM operand X register 11"
hexmask.long 0x00 0.--31. 1. "val,data bits 383..352"
group.long 0x1C30++0x03
line.long 0x00 "mtgy_op_x12,MWMM operand X register 12"
hexmask.long 0x00 0.--31. 1. "val,data bits 415..384"
group.long 0x1C34++0x03
line.long 0x00 "mtgy_op_x13,MWMM operand X register 13"
hexmask.long 0x00 0.--31. 1. "val,data bits 447..416"
group.long 0x1C38++0x03
line.long 0x00 "mtgy_op_x14,MWMM operand X register 14"
hexmask.long 0x00 0.--31. 1. "val,data bits 479..448"
group.long 0x1C3C++0x03
line.long 0x00 "mtgy_op_x15,MWMM operand X register 15"
hexmask.long 0x00 0.--31. 1. "val,data bits 511..480"
group.long 0x1C40++0x03
line.long 0x00 "mtgy_op_x16,MWMM operand X register 16"
hexmask.long 0x00 0.--31. 1. "val,data bits 543..512"
group.long 0x1C44++0x03
line.long 0x00 "mtgy_op_x17,MWMM operand X register 17"
hexmask.long 0x00 0.--31. 1. "val,data bits 575..544"
group.long 0x1C48++0x03
line.long 0x00 "mtgy_op_x18,MWMM operand X register 18"
hexmask.long 0x00 0.--31. 1. "val,data bits 607..576"
group.long 0x1C4C++0x03
line.long 0x00 "mtgy_op_x19,MWMM operand X register 19"
hexmask.long 0x00 0.--31. 1. "val,data bits 639..608"
group.long 0x1C50++0x03
line.long 0x00 "mtgy_op_x20,MWMM operand X register 20"
hexmask.long 0x00 0.--31. 1. "val,data bits 671..640"
group.long 0x1C54++0x03
line.long 0x00 "mtgy_op_x21,MWMM operand X register 21"
hexmask.long 0x00 0.--31. 1. "val,data bits 703..672"
group.long 0x1C58++0x03
line.long 0x00 "mtgy_op_x22,MWMM operand X register 22"
hexmask.long 0x00 0.--31. 1. "val,data bits 735..704"
group.long 0x1C5C++0x03
line.long 0x00 "mtgy_op_x23,MWMM operand X register 23"
hexmask.long 0x00 0.--31. 1. "val,data bits 767..736"
group.long 0x1C60++0x03
line.long 0x00 "mtgy_op_x24,MWMM operand X register 24"
hexmask.long 0x00 0.--31. 1. "val,data bits 799..768"
group.long 0x1C64++0x03
line.long 0x00 "mtgy_op_x25,MWMM operand X register 25"
hexmask.long 0x00 0.--31. 1. "val,data bits 831..800"
group.long 0x1C68++0x03
line.long 0x00 "mtgy_op_x26,MWMM operand X register 26"
hexmask.long 0x00 0.--31. 1. "val,data bits 863..832"
group.long 0x1C6C++0x03
line.long 0x00 "mtgy_op_x27,MWMM operand X register 27"
hexmask.long 0x00 0.--31. 1. "val,data bits 895..864"
group.long 0x1C70++0x03
line.long 0x00 "mtgy_op_x28,MWMM operand X register 28"
hexmask.long 0x00 0.--31. 1. "val,data bits 927..896"
group.long 0x1C74++0x03
line.long 0x00 "mtgy_op_x29,MWMM operand X register 29"
hexmask.long 0x00 0.--31. 1. "val,data bits 959..928"
group.long 0x1C78++0x03
line.long 0x00 "mtgy_op_x30,MWMM operand X register 30"
hexmask.long 0x00 0.--31. 1. "val,data bits 991..960"
group.long 0x1C7C++0x03
line.long 0x00 "mtgy_op_x31,MWMM operand X register 31"
hexmask.long 0x00 0.--31. 1. "val,data bits 1023..992"
group.long 0x1C80++0x03
line.long 0x00 "mtgy_op_x32,MWMM operand X register 32"
hexmask.long 0x00 0.--31. 1. "val,data bits 1055..1024"
group.long 0x1C84++0x03
line.long 0x00 "mtgy_op_x33,MWMM operand X register 33"
hexmask.long 0x00 0.--31. 1. "val,data bits 1087..1056"
group.long 0x1C88++0x03
line.long 0x00 "mtgy_op_x34,MWMM operand X register 34"
hexmask.long 0x00 0.--31. 1. "val,data bits 1119..1088"
group.long 0x1C8C++0x03
line.long 0x00 "mtgy_op_x35,MWMM operand X register 35"
hexmask.long 0x00 0.--31. 1. "val,data bits 1151..1120"
group.long 0x1C90++0x03
line.long 0x00 "mtgy_op_x36,MWMM operand X register 36"
hexmask.long 0x00 0.--31. 1. "val,data bits 1183..1152"
group.long 0x1C94++0x03
line.long 0x00 "mtgy_op_x37,MWMM operand X register 37"
hexmask.long 0x00 0.--31. 1. "val,data bits 1215..1184"
group.long 0x1C98++0x03
line.long 0x00 "mtgy_op_x38,MWMM operand X register 38"
hexmask.long 0x00 0.--31. 1. "val,data bits 1247..1216"
group.long 0x1C9C++0x03
line.long 0x00 "mtgy_op_x39,MWMM operand X register 39"
hexmask.long 0x00 0.--31. 1. "val,data bits 1279..1248"
group.long 0x1CA0++0x03
line.long 0x00 "mtgy_op_x40,MWMM operand X register 40"
hexmask.long 0x00 0.--31. 1. "val,data bits 1311..1280"
group.long 0x1CA4++0x03
line.long 0x00 "mtgy_op_x41,MWMM operand X register 41"
hexmask.long 0x00 0.--31. 1. "val,data bits 1343..1312"
group.long 0x1CA8++0x03
line.long 0x00 "mtgy_op_x42,MWMM operand X register 42"
hexmask.long 0x00 0.--31. 1. "val,data bits 1375..1344"
group.long 0x1CAC++0x03
line.long 0x00 "mtgy_op_x43,MWMM operand X register 43"
hexmask.long 0x00 0.--31. 1. "val,data bits 1407..1376"
group.long 0x1CB0++0x03
line.long 0x00 "mtgy_op_x44,MWMM operand X register 44"
hexmask.long 0x00 0.--31. 1. "val,data bits 1439..1408"
group.long 0x1CB4++0x03
line.long 0x00 "mtgy_op_x45,MWMM operand X register 45"
hexmask.long 0x00 0.--31. 1. "val,data bits 1471..1440"
group.long 0x1CB8++0x03
line.long 0x00 "mtgy_op_x46,MWMM operand X register 46"
hexmask.long 0x00 0.--31. 1. "val,data bits 1503..1472"
group.long 0x1CBC++0x03
line.long 0x00 "mtgy_op_x47,MWMM operand X register 47"
hexmask.long 0x00 0.--31. 1. "val,data bits 1535..1504"
group.long 0x1CC0++0x03
line.long 0x00 "mtgy_op_x48,MWMM operand X register 48"
hexmask.long 0x00 0.--31. 1. "val,data bits 1567..1536"
group.long 0x1CC4++0x03
line.long 0x00 "mtgy_op_x49,MWMM operand X register 49"
hexmask.long 0x00 0.--31. 1. "val,data bits 1599..1568"
group.long 0x1CC8++0x03
line.long 0x00 "mtgy_op_x50,MWMM operand X register 50"
hexmask.long 0x00 0.--31. 1. "val,data bits 1631..1600"
group.long 0x1CCC++0x03
line.long 0x00 "mtgy_op_x51,MWMM operand X register 51"
hexmask.long 0x00 0.--31. 1. "val,data bits 1663..1632"
group.long 0x1CD0++0x03
line.long 0x00 "mtgy_op_x52,MWMM operand X register 52"
hexmask.long 0x00 0.--31. 1. "val,data bits 1695..1664"
group.long 0x1CD4++0x03
line.long 0x00 "mtgy_op_x53,MWMM operand X register 53"
hexmask.long 0x00 0.--31. 1. "val,data bits 1727..1696"
group.long 0x1CD8++0x03
line.long 0x00 "mtgy_op_x54,MWMM operand X register 54"
hexmask.long 0x00 0.--31. 1. "val,data bits 1759..1728"
group.long 0x1CDC++0x03
line.long 0x00 "mtgy_op_x55,MWMM operand X register 55"
hexmask.long 0x00 0.--31. 1. "val,data bits 1791..1760"
group.long 0x1CE0++0x03
line.long 0x00 "mtgy_op_x56,MWMM operand X register 56"
hexmask.long 0x00 0.--31. 1. "val,data bits 1823..1792"
group.long 0x1CE4++0x03
line.long 0x00 "mtgy_op_x57,MWMM operand X register 57"
hexmask.long 0x00 0.--31. 1. "val,data bits 1855..1824"
group.long 0x1CE8++0x03
line.long 0x00 "mtgy_op_x58,MWMM operand X register 58"
hexmask.long 0x00 0.--31. 1. "val,data bits 1887..1856"
group.long 0x1CEC++0x03
line.long 0x00 "mtgy_op_x59,MWMM operand X register 59"
hexmask.long 0x00 0.--31. 1. "val,data bits 1919..1888"
group.long 0x1CF0++0x03
line.long 0x00 "mtgy_op_x60,MWMM operand X register 60"
hexmask.long 0x00 0.--31. 1. "val,data bits 1951..1920"
group.long 0x1CF4++0x03
line.long 0x00 "mtgy_op_x61,MWMM operand X register 61"
hexmask.long 0x00 0.--31. 1. "val,data bits 1983..1952"
group.long 0x1CF8++0x03
line.long 0x00 "mtgy_op_x62,MWMM operand X register 62"
hexmask.long 0x00 0.--31. 1. "val,data bits 2015..1984"
group.long 0x1CFC++0x03
line.long 0x00 "mtgy_op_x63,MWMM operand X register 63"
hexmask.long 0x00 0.--31. 1. "val,data bits 2047..2016"
group.long 0x1D00++0x03
line.long 0x00 "mtgy_op_x64,MWMM operand X register 64"
hexmask.long 0x00 0.--31. 1. "val,data bits 2079..2048"
group.long 0x1D04++0x03
line.long 0x00 "mtgy_op_x65,MWMM operand X register 65"
hexmask.long 0x00 0.--31. 1. "val,data bits 2111..2080"
group.long 0x1D08++0x03
line.long 0x00 "mtgy_op_x66,MWMM operand X register 66"
hexmask.long 0x00 0.--31. 1. "val,data bits 2143..2112"
group.long 0x1D0C++0x03
line.long 0x00 "mtgy_op_x67,MWMM operand X register 67"
hexmask.long 0x00 0.--31. 1. "val,data bits 2175..2144"
group.long 0x1D10++0x03
line.long 0x00 "mtgy_op_x68,MWMM operand X register 68"
hexmask.long 0x00 0.--31. 1. "val,data bits 2207..2176"
group.long 0x1D14++0x03
line.long 0x00 "mtgy_op_x69,MWMM operand X register 69"
hexmask.long 0x00 0.--31. 1. "val,data bits 2239..2208"
group.long 0x1D18++0x03
line.long 0x00 "mtgy_op_x70,MWMM operand X register 70"
hexmask.long 0x00 0.--31. 1. "val,data bits 2271..2240"
group.long 0x1D1C++0x03
line.long 0x00 "mtgy_op_x71,MWMM operand X register 71"
hexmask.long 0x00 0.--31. 1. "val,data bits 2303..2272"
group.long 0x1D20++0x03
line.long 0x00 "mtgy_op_x72,MWMM operand X register 72"
hexmask.long 0x00 0.--31. 1. "val,data bits 2335..2304"
group.long 0x1D24++0x03
line.long 0x00 "mtgy_op_x73,MWMM operand X register 73"
hexmask.long 0x00 0.--31. 1. "val,data bits 2367..2336"
group.long 0x1D28++0x03
line.long 0x00 "mtgy_op_x74,MWMM operand X register 74"
hexmask.long 0x00 0.--31. 1. "val,data bits 2399..2368"
group.long 0x1D2C++0x03
line.long 0x00 "mtgy_op_x75,MWMM operand X register 75"
hexmask.long 0x00 0.--31. 1. "val,data bits 2431..2400"
group.long 0x1D30++0x03
line.long 0x00 "mtgy_op_x76,MWMM operand X register 76"
hexmask.long 0x00 0.--31. 1. "val,data bits 2463..2432"
group.long 0x1D34++0x03
line.long 0x00 "mtgy_op_x77,MWMM operand X register 77"
hexmask.long 0x00 0.--31. 1. "val,data bits 2495..2464"
group.long 0x1D38++0x03
line.long 0x00 "mtgy_op_x78,MWMM operand X register 78"
hexmask.long 0x00 0.--31. 1. "val,data bits 2527..2496"
group.long 0x1D3C++0x03
line.long 0x00 "mtgy_op_x79,MWMM operand X register 79"
hexmask.long 0x00 0.--31. 1. "val,data bits 2559..2528"
group.long 0x1D40++0x03
line.long 0x00 "mtgy_op_x80,MWMM operand X register 80"
hexmask.long 0x00 0.--31. 1. "val,data bits 2591..2560"
group.long 0x1D44++0x03
line.long 0x00 "mtgy_op_x81,MWMM operand X register 81"
hexmask.long 0x00 0.--31. 1. "val,data bits 2623..2592"
group.long 0x1D48++0x03
line.long 0x00 "mtgy_op_x82,MWMM operand X register 82"
hexmask.long 0x00 0.--31. 1. "val,data bits 2655..2624"
group.long 0x1D4C++0x03
line.long 0x00 "mtgy_op_x83,MWMM operand X register 83"
hexmask.long 0x00 0.--31. 1. "val,data bits 2687..2656"
group.long 0x1D50++0x03
line.long 0x00 "mtgy_op_x84,MWMM operand X register 84"
hexmask.long 0x00 0.--31. 1. "val,data bits 2719..2688"
group.long 0x1D54++0x03
line.long 0x00 "mtgy_op_x85,MWMM operand X register 85"
hexmask.long 0x00 0.--31. 1. "val,data bits 2751..2720"
group.long 0x1D58++0x03
line.long 0x00 "mtgy_op_x86,MWMM operand X register 86"
hexmask.long 0x00 0.--31. 1. "val,data bits 2783..2752"
group.long 0x1D5C++0x03
line.long 0x00 "mtgy_op_x87,MWMM operand X register 87"
hexmask.long 0x00 0.--31. 1. "val,data bits 2815..2784"
group.long 0x1D60++0x03
line.long 0x00 "mtgy_op_x88,MWMM operand X register 88"
hexmask.long 0x00 0.--31. 1. "val,data bits 2847..2816"
group.long 0x1D64++0x03
line.long 0x00 "mtgy_op_x89,MWMM operand X register 89"
hexmask.long 0x00 0.--31. 1. "val,data bits 2879..2848"
group.long 0x1D68++0x03
line.long 0x00 "mtgy_op_x90,MWMM operand X register 90"
hexmask.long 0x00 0.--31. 1. "val,data bits 2911..2880"
group.long 0x1D6C++0x03
line.long 0x00 "mtgy_op_x91,MWMM operand X register 91"
hexmask.long 0x00 0.--31. 1. "val,data bits 2943..2912"
group.long 0x1D70++0x03
line.long 0x00 "mtgy_op_x92,MWMM operand X register 92"
hexmask.long 0x00 0.--31. 1. "val,data bits 2975..2944"
group.long 0x1D74++0x03
line.long 0x00 "mtgy_op_x93,MWMM operand X register 93"
hexmask.long 0x00 0.--31. 1. "val,data bits 3007..2976"
group.long 0x1D78++0x03
line.long 0x00 "mtgy_op_x94,MWMM operand X register 94"
hexmask.long 0x00 0.--31. 1. "val,data bits 3039..3008"
group.long 0x1D7C++0x03
line.long 0x00 "mtgy_op_x95,MWMM operand X register 95"
hexmask.long 0x00 0.--31. 1. "val,data bits 3071..3040"
group.long 0x1D80++0x03
line.long 0x00 "mtgy_op_x96,MWMM operand X register 96"
hexmask.long 0x00 0.--31. 1. "val,data bits 3103..3072"
group.long 0x1D84++0x03
line.long 0x00 "mtgy_op_x97,MWMM operand X register 97"
hexmask.long 0x00 0.--31. 1. "val,data bits 3135..3104"
group.long 0x1D88++0x03
line.long 0x00 "mtgy_op_x98,MWMM operand X register 98"
hexmask.long 0x00 0.--31. 1. "val,data bits 3167..3136"
group.long 0x1D8C++0x03
line.long 0x00 "mtgy_op_x99,MWMM operand X register 99"
hexmask.long 0x00 0.--31. 1. "val,data bits 3199..3168"
group.long 0x1D90++0x03
line.long 0x00 "mtgy_op_x100,MWMM operand X register 100"
hexmask.long 0x00 0.--31. 1. "val,data bits 3231..3200"
group.long 0x1D94++0x03
line.long 0x00 "mtgy_op_x101,MWMM operand X register 101"
hexmask.long 0x00 0.--31. 1. "val,data bits 3263..3232"
group.long 0x1D98++0x03
line.long 0x00 "mtgy_op_x102,MWMM operand X register 102"
hexmask.long 0x00 0.--31. 1. "val,data bits 3295..3264"
group.long 0x1D9C++0x03
line.long 0x00 "mtgy_op_x103,MWMM operand X register 103"
hexmask.long 0x00 0.--31. 1. "val,data bits 3327..3296"
group.long 0x1DA0++0x03
line.long 0x00 "mtgy_op_x104,MWMM operand X register 104"
hexmask.long 0x00 0.--31. 1. "val,data bits 3359..3328"
group.long 0x1DA4++0x03
line.long 0x00 "mtgy_op_x105,MWMM operand X register 105"
hexmask.long 0x00 0.--31. 1. "val,data bits 3391..3360"
group.long 0x1DA8++0x03
line.long 0x00 "mtgy_op_x106,MWMM operand X register 106"
hexmask.long 0x00 0.--31. 1. "val,data bits 3423..3392"
group.long 0x1DAC++0x03
line.long 0x00 "mtgy_op_x107,MWMM operand X register 107"
hexmask.long 0x00 0.--31. 1. "val,data bits 3455..3424"
group.long 0x1DB0++0x03
line.long 0x00 "mtgy_op_x108,MWMM operand X register 108"
hexmask.long 0x00 0.--31. 1. "val,data bits 3487..3456"
group.long 0x1DB4++0x03
line.long 0x00 "mtgy_op_x109,MWMM operand X register 109"
hexmask.long 0x00 0.--31. 1. "val,data bits 3519..3488"
group.long 0x1DB8++0x03
line.long 0x00 "mtgy_op_x110,MWMM operand X register 110"
hexmask.long 0x00 0.--31. 1. "val,data bits 3551..3520"
group.long 0x1DBC++0x03
line.long 0x00 "mtgy_op_x111,MWMM operand X register 111"
hexmask.long 0x00 0.--31. 1. "val,data bits 3583..3552"
group.long 0x1DC0++0x03
line.long 0x00 "mtgy_op_x112,MWMM operand X register 112"
hexmask.long 0x00 0.--31. 1. "val,data bits 3615..3584"
group.long 0x1DC4++0x03
line.long 0x00 "mtgy_op_x113,MWMM operand X register 113"
hexmask.long 0x00 0.--31. 1. "val,data bits 3647..3616"
group.long 0x1DC8++0x03
line.long 0x00 "mtgy_op_x114,MWMM operand X register 114"
hexmask.long 0x00 0.--31. 1. "val,data bits 3679..3648"
group.long 0x1DCC++0x03
line.long 0x00 "mtgy_op_x115,MWMM operand X register 115"
hexmask.long 0x00 0.--31. 1. "val,data bits 3711..3680"
group.long 0x1DD0++0x03
line.long 0x00 "mtgy_op_x116,MWMM operand X register 116"
hexmask.long 0x00 0.--31. 1. "val,data bits 3743..3712"
group.long 0x1DD4++0x03
line.long 0x00 "mtgy_op_x117,MWMM operand X register 117"
hexmask.long 0x00 0.--31. 1. "val,data bits 3775..3744"
group.long 0x1DD8++0x03
line.long 0x00 "mtgy_op_x118,MWMM operand X register 118"
hexmask.long 0x00 0.--31. 1. "val,data bits 3807..3776"
group.long 0x1DDC++0x03
line.long 0x00 "mtgy_op_x119,MWMM operand X register 119"
hexmask.long 0x00 0.--31. 1. "val,data bits 3839..3808"
group.long 0x1DE0++0x03
line.long 0x00 "mtgy_op_x120,MWMM operand X register 120"
hexmask.long 0x00 0.--31. 1. "val,data bits 3871..3840"
group.long 0x1DE4++0x03
line.long 0x00 "mtgy_op_x121,MWMM operand X register 121"
hexmask.long 0x00 0.--31. 1. "val,data bits 3903..3872"
group.long 0x1DE8++0x03
line.long 0x00 "mtgy_op_x122,MWMM operand X register 122"
hexmask.long 0x00 0.--31. 1. "val,data bits 3935..3904"
group.long 0x1DEC++0x03
line.long 0x00 "mtgy_op_x123,MWMM operand X register 123"
hexmask.long 0x00 0.--31. 1. "val,data bits 3967..3936"
group.long 0x1DF0++0x03
line.long 0x00 "mtgy_op_x124,MWMM operand X register 124"
hexmask.long 0x00 0.--31. 1. "val,data bits 3999..3968"
group.long 0x1DF4++0x03
line.long 0x00 "mtgy_op_x125,MWMM operand X register 125"
hexmask.long 0x00 0.--31. 1. "val,data bits 4031..4000"
group.long 0x1DF8++0x03
line.long 0x00 "mtgy_op_x126,MWMM operand X register 126"
hexmask.long 0x00 0.--31. 1. "val,data bits 4063..4032"
group.long 0x1DFC++0x03
line.long 0x00 "mtgy_op_x127,MWMM operand X register 127"
hexmask.long 0x00 0.--31. 1. "val,data bits 4095..4064"
tree.end
tree "NFIFO"
base ad:0xFF400000
group.long 0x00++0x03
line.long 0x00 "nfifo_config,NFIFO config register 'base_config' is a pointer to start of NFIFO configuration area in memory"
hexmask.long 0x00 2.--31. 1. "base_config,Pointer to base_config"
group.long 0x0C++0x03
line.long 0x00 "nfifo_irq_raw,Raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "nfifo_irq_arm_app_masked,Masked IRQ of ARM_APP: Shows status of masked IRQs as connected to application ARM Cortex M4"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
group.long 0x14++0x03
line.long 0x00 "nfifo_irq_arm_app_msk_set,ARM_APP Cortex M4 IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources to the ARM_APP processor"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
group.long 0x18++0x03
line.long 0x00 "nfifo_irq_arm_app_msk_reset,ARM_APP Cortex M4 IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "nfifo_irq_xpic_app_masked,Masked IRQ of xPIC_APP: Shows status of masked IRQs as connected to xPIC_APP"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "nfifo_irq_xpic_app_msk_set,xPIC_APP IRQ mask set: The xPIC_APP IRQ mask enables interrupt requests for corresponding interrupt sources to the xPIC_APP processor"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
group.long 0x30++0x03
line.long 0x00 "nfifo_irq_xpic_app_msk_reset,xPIC_APP IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 13. "observe9,access to FIFO as defined in observe9" "0,1"
bitfld.long 0x00 12. "observe8,access to FIFO as defined in observe8" "0,1"
bitfld.long 0x00 11. "observe7,access to FIFO as defined in observe7" "0,1"
bitfld.long 0x00 10. "observe6,access to FIFO as defined in observe6" "0,1"
bitfld.long 0x00 9. "observe5,access to FIFO as defined in observe5" "0,1"
bitfld.long 0x00 8. "observe4,access to FIFO as defined in observe4" "0,1"
bitfld.long 0x00 7. "observe3,access to FIFO as defined in observe3" "0,1"
newline
bitfld.long 0x00 6. "observe2,access to FIFO as defined in observe2" "0,1"
bitfld.long 0x00 5. "observe1,access to FIFO as defined in observe1" "0,1"
bitfld.long 0x00 4. "observe0,access to FIFO as defined in observe0" "0,1"
bitfld.long 0x00 3. "fifo_active,any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)" "0,1"
bitfld.long 0x00 2. "write,any write access happened to any FIFO" "0,1"
bitfld.long 0x00 1. "read,any read access happened to any FIFO" "0,1"
bitfld.long 0x00 0. "ahbl_error,AHBL returned HRESP=1 (abort)" "0,1"
group.long 0x58++0x03
line.long 0x00 "nfifo_irq_observe0,FIFO OBSERVE0: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x5C++0x03
line.long 0x00 "nfifo_irq_observe1,FIFO OBSERVE1: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x60++0x03
line.long 0x00 "nfifo_irq_observe2,FIFO OBSERVE2: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x64++0x03
line.long 0x00 "nfifo_irq_observe3,FIFO OBSERVE3: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x68++0x03
line.long 0x00 "nfifo_irq_observe4,FIFO OBSERVE4: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x6C++0x03
line.long 0x00 "nfifo_irq_observe5,FIFO OBSERVE5: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x70++0x03
line.long 0x00 "nfifo_irq_observe6,FIFO OBSERVE6: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x74++0x03
line.long 0x00 "nfifo_irq_observe7,FIFO OBSERVE7: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x78++0x03
line.long 0x00 "nfifo_irq_observe8,FIFO OBSERVE8: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x7C++0x03
line.long 0x00 "nfifo_irq_observe9,FIFO OBSERVE9: This register configures the observation unit that allows to observe one FIFO for special events"
bitfld.long 0x00 22. "full,Activate IRQ in case of FIFO gets full" "0,1"
bitfld.long 0x00 21. "fmw,Activate IRQ in case of Full-Minus-Watermark is set" "0,1"
bitfld.long 0x00 20. "ovfl,Activate IRQ in case of FIFO overflow" "0,1"
bitfld.long 0x00 19. "write,Activate IRQ in case of any write access" "0,1"
bitfld.long 0x00 18. "empty,Activate IRQ in case of FIFO gets empty" "0,1"
bitfld.long 0x00 17. "emw,Activate IRQ in case of Empty-Minus-Watermark is set" "0,1"
bitfld.long 0x00 16. "undr,Activate IRQ in case of FIFO underrun" "0,1"
newline
bitfld.long 0x00 15. "read,Activate IRQ in case of any read access" "0,1"
hexmask.long.word 0x00 0.--9. 1. "fifonr,Number of FIFO to be observed"
group.long 0x80++0x03
line.long 0x00 "nfifo_fifo_start,Start of NFIFO FIFO access addresses: The following DW-addresses are associated with FIFOs: Read accesses to an address in this area are reading from the appropriate FIFO write accesses to an address in this area are writing to the.."
group.long 0xFFC++0x03
line.long 0x00 "nfifo_fifo_end,End of NFIFO FIFO access addresses"
tree.end
tree "PAD_CTRL"
base ad:0xFF401000
group.long 0x00++0x03
line.long 0x00 "pad_ctrl_rdy_n,Pad configuration register of port RDY_N (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x04++0x03
line.long 0x00 "pad_ctrl_run_n,Pad configuration register of port RUN_N (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x08++0x03
line.long 0x00 "pad_ctrl_mled0,Pad configuration register of port MLED0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x0C++0x03
line.long 0x00 "pad_ctrl_mled1,Pad configuration register of port MLED1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x10++0x03
line.long 0x00 "pad_ctrl_mled2,Pad configuration register of port MLED2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x14++0x03
line.long 0x00 "pad_ctrl_mled3,Pad configuration register of port MLED3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x18++0x03
line.long 0x00 "pad_ctrl_com_io0,Pad configuration register of port COM_IO0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x1C++0x03
line.long 0x00 "pad_ctrl_com_io1,Pad configuration register of port COM_IO1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x20++0x03
line.long 0x00 "pad_ctrl_com_io2,Pad configuration register of port COM_IO2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x24++0x03
line.long 0x00 "pad_ctrl_com_io3,Pad configuration register of port COM_IO3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x28++0x03
line.long 0x00 "pad_ctrl_mii0_rxclk,Pad configuration register of port MII0_RXCLK (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "pad_ctrl_mii0_rxd0,Pad configuration register of port MII0_RXD0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x30++0x03
line.long 0x00 "pad_ctrl_mii0_rxd1,Pad configuration register of port MII0_RXD1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x34++0x03
line.long 0x00 "pad_ctrl_mii0_rxd2,Pad configuration register of port MII0_RXD2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x38++0x03
line.long 0x00 "pad_ctrl_mii0_rxd3,Pad configuration register of port MII0_RXD3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x3C++0x03
line.long 0x00 "pad_ctrl_mii0_rxdv,Pad configuration register of port MII0_RXDV (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x40++0x03
line.long 0x00 "pad_ctrl_mii0_rxer,Pad configuration register of port MII0_RXER (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x44++0x03
line.long 0x00 "pad_ctrl_mii0_txclk,Pad configuration register of port MII0_TXCLK (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x48++0x03
line.long 0x00 "pad_ctrl_mii0_txd0,Pad configuration register of port MII0_TXD0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x4C++0x03
line.long 0x00 "pad_ctrl_mii0_txd1,Pad configuration register of port MII0_TXD1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x50++0x03
line.long 0x00 "pad_ctrl_mii0_txd2,Pad configuration register of port MII0_TXD2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x54++0x03
line.long 0x00 "pad_ctrl_mii0_txd3,Pad configuration register of port MII0_TXD3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x58++0x03
line.long 0x00 "pad_ctrl_mii0_txen,Pad configuration register of port MII0_TXEN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x5C++0x03
line.long 0x00 "pad_ctrl_mii0_col,Pad configuration register of port MII0_COL (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x60++0x03
line.long 0x00 "pad_ctrl_mii0_crs,Pad configuration register of port MII0_CRS (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x64++0x03
line.long 0x00 "pad_ctrl_phy0_led_link_in,Pad configuration register of port PHY0_LED_LINK_IN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x68++0x03
line.long 0x00 "pad_ctrl_mii1_rxclk,Pad configuration register of port MII1_RXCLK (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x6C++0x03
line.long 0x00 "pad_ctrl_mii1_rxd0,Pad configuration register of port MII1_RXD0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
group.long 0x70++0x03
line.long 0x00 "pad_ctrl_mii1_rxd1,Pad configuration register of port MII1_RXD1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x74++0x03
line.long 0x00 "pad_ctrl_mii1_rxd2,Pad configuration register of port MII1_RXD2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x78++0x03
line.long 0x00 "pad_ctrl_mii1_rxd3,Pad configuration register of port MII1_RXD3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
group.long 0x7C++0x03
line.long 0x00 "pad_ctrl_mii1_rxdv,Pad configuration register of port MII1_RXDV (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x80++0x03
line.long 0x00 "pad_ctrl_mii1_rxer,Pad configuration register of port MII1_RXER (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0x84++0x03
line.long 0x00 "pad_ctrl_mii1_txclk,Pad configuration register of port MII1_TXCLK (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x88++0x03
line.long 0x00 "pad_ctrl_mii1_txd0,Pad configuration register of port MII1_TXD0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x8C++0x03
line.long 0x00 "pad_ctrl_mii1_txd1,Pad configuration register of port MII1_TXD1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x90++0x03
line.long 0x00 "pad_ctrl_mii1_txd2,Pad configuration register of port MII1_TXD2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x94++0x03
line.long 0x00 "pad_ctrl_mii1_txd3,Pad configuration register of port MII1_TXD3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad disabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x98++0x03
line.long 0x00 "pad_ctrl_mii1_txen,Pad configuration register of port MII1_TXEN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x9C++0x03
line.long 0x00 "pad_ctrl_mii1_col,Pad configuration register of port MII1_COL (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xA0++0x03
line.long 0x00 "pad_ctrl_mii1_crs,Pad configuration register of port MII1_CRS (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xA4++0x03
line.long 0x00 "pad_ctrl_phy1_led_link_in,Pad configuration register of port PHY1_LED_LINK_IN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
group.long 0xA8++0x03
line.long 0x00 "pad_ctrl_mii_mdc,Pad configuration register of port MII_MDC (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xAC++0x03
line.long 0x00 "pad_ctrl_mii_mdio,Pad configuration register of port MII_MDIO (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xB0++0x03
line.long 0x00 "pad_ctrl_rst_out_n,Pad configuration register of port RST_OUT_N (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xB4++0x03
line.long 0x00 "pad_ctrl_clk25out,Pad configuration register of port CLK25OUT (asic_ctrl_access_key protected)"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xB8++0x03
line.long 0x00 "pad_ctrl_mmio0,Pad configuration register of port MMIO0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xBC++0x03
line.long 0x00 "pad_ctrl_mmio1,Pad configuration register of port MMIO1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xC0++0x03
line.long 0x00 "pad_ctrl_mmio2,Pad configuration register of port MMIO2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xC4++0x03
line.long 0x00 "pad_ctrl_mmio3,Pad configuration register of port MMIO3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xC8++0x03
line.long 0x00 "pad_ctrl_mmio4,Pad configuration register of port MMIO4 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (shared analog function disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xCC++0x03
line.long 0x00 "pad_ctrl_mmio5,Pad configuration register of port MMIO5 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (shared analog function disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xD0++0x03
line.long 0x00 "pad_ctrl_mmio6,Pad configuration register of port MMIO6 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (shared analog function disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xD4++0x03
line.long 0x00 "pad_ctrl_mmio7,Pad configuration register of port MMIO7 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (shared analog function disabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-down pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xD8++0x03
line.long 0x00 "pad_ctrl_sqi_clk,Pad configuration register of port SQI_CLK (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xDC++0x03
line.long 0x00 "pad_ctrl_sqi_cs0n,Pad configuration register of port SQI_CS0N (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xE0++0x03
line.long 0x00 "pad_ctrl_sqi_mosi,Pad configuration register of port SQI_MOSI (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xE4++0x03
line.long 0x00 "pad_ctrl_sqi_miso,Pad configuration register of port SQI_MISO (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xE8++0x03
line.long 0x00 "pad_ctrl_sqi_sio2,Pad configuration register of port SQI_SIO2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xEC++0x03
line.long 0x00 "pad_ctrl_sqi_sio3,Pad configuration register of port SQI_SIO3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xF0++0x03
line.long 0x00 "pad_ctrl_hif_a0,Pad configuration register of port HIF_A0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xF4++0x03
line.long 0x00 "pad_ctrl_hif_a1,Pad configuration register of port HIF_A1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xF8++0x03
line.long 0x00 "pad_ctrl_hif_a2,Pad configuration register of port HIF_A2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0xFC++0x03
line.long 0x00 "pad_ctrl_hif_a3,Pad configuration register of port HIF_A3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x100++0x03
line.long 0x00 "pad_ctrl_hif_a4,Pad configuration register of port HIF_A4 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x104++0x03
line.long 0x00 "pad_ctrl_hif_a5,Pad configuration register of port HIF_A5 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x108++0x03
line.long 0x00 "pad_ctrl_hif_a6,Pad configuration register of port HIF_A6 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x10C++0x03
line.long 0x00 "pad_ctrl_hif_a7,Pad configuration register of port HIF_A7 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x110++0x03
line.long 0x00 "pad_ctrl_hif_a8,Pad configuration register of port HIF_A8 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x114++0x03
line.long 0x00 "pad_ctrl_hif_a9,Pad configuration register of port HIF_A9 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x118++0x03
line.long 0x00 "pad_ctrl_hif_a10,Pad configuration register of port HIF_A10 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x11C++0x03
line.long 0x00 "pad_ctrl_hif_a11,Pad configuration register of port HIF_A11 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x120++0x03
line.long 0x00 "pad_ctrl_hif_a12,Pad configuration register of port HIF_A12 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x124++0x03
line.long 0x00 "pad_ctrl_hif_a13,Pad configuration register of port HIF_A13 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x128++0x03
line.long 0x00 "pad_ctrl_hif_a14,Pad configuration register of port HIF_A14 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x12C++0x03
line.long 0x00 "pad_ctrl_hif_a15,Pad configuration register of port HIF_A15 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x130++0x03
line.long 0x00 "pad_ctrl_hif_a16,Pad configuration register of port HIF_A16 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x134++0x03
line.long 0x00 "pad_ctrl_hif_a17,Pad configuration register of port HIF_A17 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x138++0x03
line.long 0x00 "pad_ctrl_hif_d0,Pad configuration register of port HIF_D0 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x13C++0x03
line.long 0x00 "pad_ctrl_hif_d1,Pad configuration register of port HIF_D1 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x140++0x03
line.long 0x00 "pad_ctrl_hif_d2,Pad configuration register of port HIF_D2 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x144++0x03
line.long 0x00 "pad_ctrl_hif_d3,Pad configuration register of port HIF_D3 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x148++0x03
line.long 0x00 "pad_ctrl_hif_d4,Pad configuration register of port HIF_D4 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x14C++0x03
line.long 0x00 "pad_ctrl_hif_d5,Pad configuration register of port HIF_D5 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x150++0x03
line.long 0x00 "pad_ctrl_hif_d6,Pad configuration register of port HIF_D6 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x154++0x03
line.long 0x00 "pad_ctrl_hif_d7,Pad configuration register of port HIF_D7 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x158++0x03
line.long 0x00 "pad_ctrl_hif_d8,Pad configuration register of port HIF_D8 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x15C++0x03
line.long 0x00 "pad_ctrl_hif_d9,Pad configuration register of port HIF_D9 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x160++0x03
line.long 0x00 "pad_ctrl_hif_d10,Pad configuration register of port HIF_D10 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x164++0x03
line.long 0x00 "pad_ctrl_hif_d11,Pad configuration register of port HIF_D11 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x168++0x03
line.long 0x00 "pad_ctrl_hif_d12,Pad configuration register of port HIF_D12 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x16C++0x03
line.long 0x00 "pad_ctrl_hif_d13,Pad configuration register of port HIF_D13 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x170++0x03
line.long 0x00 "pad_ctrl_hif_d14,Pad configuration register of port HIF_D14 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x174++0x03
line.long 0x00 "pad_ctrl_hif_d15,Pad configuration register of port HIF_D15 (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x178++0x03
line.long 0x00 "pad_ctrl_hif_bhen,Pad configuration register of port HIF_BHEN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x17C++0x03
line.long 0x00 "pad_ctrl_hif_csn,Pad configuration register of port HIF_CSN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x180++0x03
line.long 0x00 "pad_ctrl_hif_rdn,Pad configuration register of port HIF_RDN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x184++0x03
line.long 0x00 "pad_ctrl_hif_wrn,Pad configuration register of port HIF_WRN (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x188++0x03
line.long 0x00 "pad_ctrl_hif_rdy,Pad configuration register of port HIF_RDY (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x18C++0x03
line.long 0x00 "pad_ctrl_hif_dirq,Pad configuration register of port HIF_DIRQ (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
group.long 0x190++0x03
line.long 0x00 "pad_ctrl_hif_sdclk,Pad configuration register of port HIF_SDCLK (asic_ctrl_access_key protected)"
bitfld.long 0x00 6. "ie,input enable (enabled by default)" "0,1"
bitfld.long 0x00 4. "pe,pull enable (pull-up pad enabled by default)" "0,1"
bitfld.long 0x00 0. "ds,driving strength (low by default)" "0,1"
tree.end
tree "PIO_APP"
base ad:0xFF801AC0
rgroup.long 0x00++0x03
line.long 0x00 "pio_in,PIO input line status register"
hexmask.long.byte 0x00 0.--7. 1. "val,PIO input states (LSB: PIO0)"
group.long 0x04++0x03
line.long 0x00 "pio_out,PIO output drive level line register"
hexmask.long.byte 0x00 0.--7. 1. "val,PIO output drive levels (LSB: PIO0)"
group.long 0x08++0x03
line.long 0x00 "pio_oe,PIO output enable line register"
hexmask.long.byte 0x00 0.--7. 1. "val,PIO output enables (LSB: PIO0)"
tree.end
tree "RANDOM"
base ad:0xFF0800C0
group.long 0x00++0x03
line.long 0x00 "random_init,Random initialization value: Write a value depending on Chip ID to this register to generate a random sequence different for each netX"
hexmask.long 0x00 0.--31. 1. "val,random init value"
rgroup.long 0x04++0x03
line.long 0x00 "random_random,Random value: This random value sequence is derived from many random events inside netX chip"
hexmask.long 0x00 0.--31. 1. "val,random value"
tree.end
tree "SAMPLE_AT_PORN_STAT"
base ad:0xFF401680
rgroup.long 0x00++0x03
line.long 0x00 "sample_at_porn_stat_in0,Status of inputs sampled at power-on-reset (PORn) register 0"
bitfld.long 0x00 31. "hif_a15,Input status of pin 'hif_a15' sampled at power-on-reset" "0,1"
bitfld.long 0x00 30. "hif_a14,Input status of pin 'hif_a14' sampled at power-on-reset" "0,1"
bitfld.long 0x00 29. "hif_a13,Input status of pin 'hif_a13' sampled at power-on-reset" "0,1"
bitfld.long 0x00 28. "hif_a12,Input status of pin 'hif_a12' sampled at power-on-reset" "0,1"
bitfld.long 0x00 27. "hif_a11,Input status of pin 'hif_a11' sampled at power-on-reset" "0,1"
bitfld.long 0x00 26. "hif_a10,Input status of pin 'hif_a10' sampled at power-on-reset" "0,1"
bitfld.long 0x00 25. "hif_a9,Input status of pin 'hif_a9' sampled at power-on-reset" "0,1"
bitfld.long 0x00 24. "hif_a8,Input status of pin 'hif_a8' sampled at power-on-reset" "0,1"
bitfld.long 0x00 23. "hif_a7,Input status of pin 'hif_a7' sampled at power-on-reset" "0,1"
bitfld.long 0x00 22. "hif_a6,Input status of pin 'hif_a6' sampled at power-on-reset" "0,1"
newline
bitfld.long 0x00 21. "hif_a5,Input status of pin 'hif_a5' sampled at power-on-reset" "0,1"
bitfld.long 0x00 20. "hif_a4,Input status of pin 'hif_a4' sampled at power-on-reset" "0,1"
bitfld.long 0x00 19. "hif_a3,Input status of pin 'hif_a3' sampled at power-on-reset" "0,1"
bitfld.long 0x00 18. "hif_a2,Input status of pin 'hif_a2' sampled at power-on-reset" "0,1"
bitfld.long 0x00 17. "hif_a1,Input status of pin 'hif_a1' sampled at power-on-reset" "0,1"
bitfld.long 0x00 16. "hif_a0,Input status of pin 'hif_a0' sampled at power-on-reset" "0,1"
bitfld.long 0x00 15. "hif_d15,Input status of pin 'hif_d15' sampled at power-on-reset" "0,1"
bitfld.long 0x00 14. "hif_d14,Input status of pin 'hif_d14' sampled at power-on-reset" "0,1"
bitfld.long 0x00 13. "hif_d13,Input status of pin 'hif_d13' sampled at power-on-reset" "0,1"
bitfld.long 0x00 12. "hif_d12,Input status of pin 'hif_d12' sampled at power-on-reset" "0,1"
newline
bitfld.long 0x00 11. "hif_d11,Input status of pin 'hif_d11' sampled at power-on-reset" "0,1"
bitfld.long 0x00 10. "hif_d10,Input status of pin 'hif_d10' sampled at power-on-reset" "0,1"
bitfld.long 0x00 9. "hif_d9,Input status of pin 'hif_d9' sampled at power-on-reset" "0,1"
bitfld.long 0x00 8. "hif_d8,Input status of pin 'hif_d8' sampled at power-on-reset" "0,1"
bitfld.long 0x00 7. "hif_d7,Input status of pin 'hif_d7' sampled at power-on-reset" "0,1"
bitfld.long 0x00 6. "hif_d6,Input status of pin 'hif_d6' sampled at power-on-reset" "0,1"
bitfld.long 0x00 5. "hif_d5,Input status of pin 'hif_d5' sampled at power-on-reset" "0,1"
bitfld.long 0x00 4. "hif_d4,Input status of pin 'hif_d4' sampled at power-on-reset" "0,1"
bitfld.long 0x00 3. "hif_d3,Input status of pin 'hif_d3' sampled at power-on-reset" "0,1"
bitfld.long 0x00 2. "hif_d2,Input status of pin 'hif_d2' sampled at power-on-reset" "0,1"
newline
bitfld.long 0x00 1. "hif_d1,Input status of pin 'hif_d1' sampled at power-on-reset" "0,1"
bitfld.long 0x00 0. "hif_d0,Input status of pin 'hif_d0' sampled at power-on-reset" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "sample_at_porn_stat_in1,Status of inputs sampled at power-on-reset (PORn) register 1"
bitfld.long 0x00 16. "sqi_sio3,Input status of pin 'sqi_sio3' sampled at power-on-reset" "0,1"
bitfld.long 0x00 15. "sqi_sio2,Input status of pin 'sqi_sio2' sampled at power-on-reset" "0,1"
bitfld.long 0x00 14. "sqi_miso,Input status of pin 'sqi_miso' sampled at power-on-reset" "0,1"
bitfld.long 0x00 13. "sqi_mosi,Input status of pin 'sqi_mosi' sampled at power-on-reset" "0,1"
bitfld.long 0x00 12. "sqi_cs0n,Input status of pin 'sqi_cs0n' sampled at power-on-reset" "0,1"
bitfld.long 0x00 11. "sqi_clk,Input status of pin 'sqi_clk' sampled at power-on-reset" "0,1"
bitfld.long 0x00 10. "run_n,Input status of pin 'run_n' sampled at power-on-reset" "0,1"
bitfld.long 0x00 9. "rdy_n,Input status of pin 'rdy_n' sampled at power-on-reset" "0,1"
bitfld.long 0x00 8. "hif_sdclk,Input status of pin 'hif_sdclk' sampled at power-on-reset" "0,1"
bitfld.long 0x00 7. "hif_dirq,Input status of pin 'hif_dirq' sampled at power-on-reset" "0,1"
newline
bitfld.long 0x00 6. "hif_rdy,Input status of pin 'hif_rdy' sampled at power-on-reset" "0,1"
bitfld.long 0x00 5. "hif_csn,Input status of pin 'hif_csn' sampled at power-on-reset" "0,1"
bitfld.long 0x00 4. "hif_wrn,Input status of pin 'hif_wrn' sampled at power-on-reset" "0,1"
bitfld.long 0x00 3. "hif_rdn,Input status of pin 'hif_rdn' sampled at power-on-reset" "0,1"
bitfld.long 0x00 2. "hif_bhen,Input status of pin 'hif_bhen' sampled at power-on-reset" "0,1"
bitfld.long 0x00 1. "hif_a17,Input status of pin 'hif_a17' sampled at power-on-reset" "0,1"
bitfld.long 0x00 0. "hif_a16,Input status of pin 'hif_a16' sampled at power-on-reset" "0,1"
tree.end
tree "SPI_XPIC_APP"
base ad:0xFF900380
group.long 0x00++0x03
line.long 0x00 "spi_cr0,SPI control register 0 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "netx100_comp,Use netx100/500-compatible SPI mode" "0: start transfer after writing data,1: start transfer after setting CR_write or.."
newline
bitfld.long 0x00 28. "slave_sig_early,Generate MISO in slave mode 1 SCK clock edge earlier than defined in the SPI specification" "0,1"
newline
bitfld.long 0x00 27. "filter_in,Receive data is sampled every 10ns (100MHz system clock)" "0,1"
newline
bitfld.long 0x00 24.--25. "format,Frame format" "0,1,2,3"
newline
hexmask.long.word 0x00 8.--19. 1. "sck_muladd,Serial clock rate multiply add value for master SCK generation"
newline
bitfld.long 0x00 7. "SPH,Serial clock phase (netx500: CR_ncpha)" "0: sample data at first clock edge data is,1: sample data at second clock edge data is"
newline
bitfld.long 0x00 6. "SPO,Serial clock polarity (netx500: CR_cpol)" "0: idle,1: idle"
newline
bitfld.long 0x00 0.--3. "datasize,DSS: data size select (transfer size = datasize + 1 bits): { | 0000...0010: reserved 0011: 4 bit 0100: 5 bit ... 0111: 8 bit ... 1111: 16 bit } Note: 16 bit TX-data-loss bug of netX50/netX5 is fixed since netX10" "?,?,?,3: 4 bit,4: 5 bit,?,?,7: 8 bit,?,?,?,?,?,?,?,15: 16 bit } Note: 16"
group.long 0x04++0x03
line.long 0x00 "spi_cr1,SPI control register 1 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 28. "rx_fifo_clr,Writing 1 to this bit will clear the receive FIFOs" "0,1"
newline
bitfld.long 0x00 24.--27. "rx_fifo_wm,Receive FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20. "tx_fifo_clr,Writing 1 to this bit will clear the transmit FIFOs" "0,1"
newline
bitfld.long 0x00 16.--19. "tx_fifo_wm,Transmit FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "fss_static,SPI static chip-select: { | 0: SPI chip-select will be toggled automatically before and after each transferred word according to fss and datasize. 1: SPI chip-select will be set statically according to the fss bits. }" "0: SPI chip-select will be toggled automatically,1: SPI chip-select will be set statically.."
newline
bitfld.long 0x00 8.--10. "fss,Frame or slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "SOD,Slave mode output disable (to connect multiple slaves to one master)" "0: MISO can be driven in slave mode,1: MISO is not driven in slave mode"
newline
bitfld.long 0x00 2. "MS,Mode select" "0: Module is configured as master,1: Module is configured as slave"
newline
bitfld.long 0x00 1. "SSE,SPI enable" "0: Module disabled,1: Module enabled"
newline
bitfld.long 0x00 0. "LBM,Loop back mode" "0: Internal loop back disabled,1: Internal loop back enabled spi_cr0.filter_in"
group.long 0x08++0x03
line.long 0x00 "spi_dr,SPI data register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
hexmask.long.tbyte 0x00 0.--16. 1. "data,Transmit data: Only lowest bits according to spi_cr0.datasize will be sent"
rgroup.long 0x0C++0x03
line.long 0x00 "spi_sr,SPI status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "rx_fifo_err_undr,Receive FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 30. "rx_fifo_err_ovfl,Receive FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 24.--28. "rx_fifo_level,Receive FIFO level (number of received words to read out are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 23. "tx_fifo_err_undr,Transmit FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 22. "tx_fifo_err_ovfl,Transmit FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 16.--20. "tx_fifo_level,Transmit FIFO level (number of words to transmit are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BSY,Device busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)" "0,1"
newline
bitfld.long 0x00 3. "RFF,Receive FIFO is full (1 if full)" "0,1"
newline
bitfld.long 0x00 2. "RNE,Receive FIFO is not empty (0 if empty)" "0,1"
newline
bitfld.long 0x00 1. "TNF,Transmit FIFO is not full (0 if full)" "0,1"
newline
bitfld.long 0x00 0. "TFE,Transmit FIFO is empty (1 if empty)" "0,1"
group.long 0x14++0x03
line.long 0x00 "spi_imsc,SPI Interrupt Mask Set and Clear register: Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeim,Transmit FIFO empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfim,Receive FIFO full interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneim,Receive FIFO not empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "RORIM,Receive FIFO overrun interrupt mask" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "spi_ris,SPI interrupt state before masking register (raw interrupt) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeris,Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0: transmit FIFO is not empty,1: transmit FIFO is empty"
newline
bitfld.long 0x00 5. "rxfris,Unmasked receive FIFO full interrupt state (for netx100/500 compliance)" "0: receive FIFO is not full,1: receive FIFO is full"
newline
bitfld.long 0x00 4. "rxneris,Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0: receive FIFO is empty,1: receive FIFO is not empty"
newline
bitfld.long 0x00 3. "TXRIS,Unmasked transmit FIFO interrupt state" "0: transmit FIFO equals or is higher than,1: transmit FIFO level is below spi_cr1.tx_fifo_wm"
newline
bitfld.long 0x00 2. "RXRIS,Unmasked receive FIFO interrupt state" "0: receive FIFO is equals or is below,1: receive FIFO is higher than spi_cr1.rx_fifo_wm"
newline
bitfld.long 0x00 1. "RTRIS,Unmasked receive timeout interrupt state Timeout period are 32 SPI clock periods depending on adr_spi_cr0.sck_muladd" "0: receive FIFO is empty or read during the last,1: receive FIFO is not empty and not read out in"
newline
bitfld.long 0x00 0. "RORRIS,Unmasked receive FIFO overrun interrupt state" "0: no receive FIFO overrun error occurred,1: receive FIFO overrun error occurred"
rgroup.long 0x1C++0x03
line.long 0x00 "spi_mis,SPI interrupt status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txemis,Masked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfmis,Masked receive FIFO full interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxnemis,Masked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXMIS,Masked transmit FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 2. "RXMIS,Masked receive FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 1. "RTMIS,Masked receive timeout interrupt state" "0,1"
newline
bitfld.long 0x00 0. "RORMIS,Masked receive FIFO overrun interrupt state" "0,1"
group.long 0x20++0x03
line.long 0x00 "spi_icr,SPI interrupt clear register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeic,Clear transmit FIFO empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfic,Clear receive FIFO full interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneic,Clear receive FIFO not empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIC,PL022 extension: clear transmit FIFO interrupt" "0,1"
newline
bitfld.long 0x00 2. "RXIC,PL022 extension: clear receive FIFO interrupt" "0,1"
newline
bitfld.long 0x00 1. "RTIC,Clear receive FIFO overrun interrupt" "0,1"
newline
bitfld.long 0x00 0. "RORIC,Clear receive FIFO overrun interrupt Writing '1' here will clear the receive FIFO" "0,1"
group.long 0x28++0x03
line.long 0x00 "spi_dmacr,SPI DMA control register"
bitfld.long 0x00 1. "TXDMAE,Enable DMA for SPI transmit data" "0,1"
newline
bitfld.long 0x00 0. "RXDMAE,Enable DMA for SPI receive data" "0,1"
group.long 0x30++0x03
line.long 0x00 "spi_data_register,netx100/500 compliant SPI data register (DR) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 17. "dr_valid1,Obsolete always 0" "0,1"
newline
bitfld.long 0x00 16. "dr_valid0,Valid bit for data_byte_0 This bit shows if data_byte_0 is valid and must be set during a FIFO write access" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "data_byte_1,Obsolete don't use"
newline
hexmask.long.byte 0x00 0.--7. 1. "data_byte_0,Data byte 0"
rgroup.long 0x34++0x03
line.long 0x00 "spi_status_register,netx100/500 compliant SPI status register (SR): Shows the actual status of the SPI interface"
bitfld.long 0x00 25. "SR_selected,External master has access to SPI interface" "0,1"
newline
bitfld.long 0x00 24. "SR_out_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 23. "SR_out_empty,Output FIFO is empty in slave mode (equals spi_ris.txeris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "SR_out_fw,netX is writing data too fast into output FIFO" "0,1"
newline
bitfld.long 0x00 21. "SR_out_fuel,Adjustable fill value of output FIFO reached (equals spi_ris.TXRIS in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "SR_in_full,Input FIFO is full (equals spi_ris.rxfris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "SR_in_recdata,Valid data bytes in input FIFO (equals spi_ris.rxneris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "SR_in_fuel,Adjustable fill value of input FIFO reached (equals spi_ris.RXRIS in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "SR_out_fuel_val,Output FIFO fill value (number of bytes)"
newline
hexmask.long.word 0x00 0.--8. 1. "SR_in_fuel_val,Input FIFO fill value (number of bytes)"
group.long 0x38++0x03
line.long 0x00 "spi_control_register,netx100/500 compliant SPI control register (CR)"
bitfld.long 0x00 31. "CR_en," "0,1"
newline
bitfld.long 0x00 30. "CR_ms," "0,1"
newline
bitfld.long 0x00 29. "CR_cpol," "0,1"
newline
bitfld.long 0x00 28. "CR_ncpha,SPI clock phase mode (Note: meaning of this bit is inverted to functionality of bit spi_cr0.SPH): { | 0: change data on secondary SCK edge data is active on primary SCK edge 1: change data on primary SCK edge data is active on secondary SCK.." "0: change data on secondary SCK edge data is..,1: change data on primary SCK edge data is active"
newline
bitfld.long 0x00 25.--27. "CR_burst,netx100/netx500 only obsolete in later versions: burst length = 2^CR_burst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22.--24. "CR_burstdelay,netx100/netx500 only obsolete in later versions: delay between transmission of 2 data bytes (0 to 7 SCK cycles)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "CR_clr_outfifo,Clear output FIFO" "0,1"
newline
bitfld.long 0x00 20. "CR_clr_infifo,Clear input FIFO" "0,1"
newline
bitfld.long 0x00 11. "CS_mode," "0,1"
newline
bitfld.long 0x00 8.--10. "CR_ss,External slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "CR_write,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 6. "CR_read,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 1.--4. "CR_speed,Clock divider for SPI clock (2 - 2^16) If SPI clock rate is changed using spi_cr0.sck_muladd this value will not be updated and may be incorrect There are 16 different SPI clocks frequencies to choose" "0: 0.025 MHz (Note,1: 0.05 MHz,2: 0.1 MHz,3: 0.2 MHz,4: 0.5 MHz,5: 1 MHz,6: 1.25 MHz,7: 2 MHz,8: 2.5 MHz,9: 3.3333 MHz,10: 5 MHz,11: 10 MHz,12: 12.5 MHz,13: 16.6666 MHz,14: 25 MHz,15: 50 MHz"
newline
bitfld.long 0x00 0. "CR_softreset,write only: no function in netx100/netx500 later versions: clears IRQs and FIFOs" "0,1"
group.long 0x3C++0x03
line.long 0x00 "spi_interrupt_control_register,netx100/500 compliant SPI interrupt control register (IR) In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16 fill values are fixed to 4"
bitfld.long 0x00 24. "IR_out_full_en,IRQ enable for irq_spi(6) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 23. "IR_out_empty_en,IRQ enable for irq_spi(5) (equals spi_imsc.rxeim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "IR_out_fw_en,IRQ enable for irq_spi(4) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 21. "IR_out_fuel_en,IRQ enable for irq_spi(3) (equals spi_imsc.TXIM in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "IR_in_full_en,IRQ enable for irq_spi(2) (equals spi_imsc.txfim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "IR_in_recdata_en,IRQ enable for irq_spi(1) (equals spi_imsc.txneim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "IR_in_fuel_en,IRQ enable for irq_spi(0) (equals spi_imsc.RXIM in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "IR_out_fuel,Adjustable watermark level of output FIFO"
newline
hexmask.long.word 0x00 0.--8. 1. "IR_in_fuel,Adjustable watermark level of input FIFO"
tree.end
tree "SPI0_APP"
base ad:0xFF801A00
group.long 0x00++0x03
line.long 0x00 "spi_cr0,SPI control register 0 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "netx100_comp,Use netx100/500-compatible SPI mode" "0: start transfer after writing data,1: start transfer after setting CR_write or.."
newline
bitfld.long 0x00 28. "slave_sig_early,Generate MISO in slave mode 1 SCK clock edge earlier than defined in the SPI specification" "0,1"
newline
bitfld.long 0x00 27. "filter_in,Receive data is sampled every 10ns (100MHz system clock)" "0,1"
newline
bitfld.long 0x00 24.--25. "format,Frame format" "0,1,2,3"
newline
hexmask.long.word 0x00 8.--19. 1. "sck_muladd,Serial clock rate multiply add value for master SCK generation"
newline
bitfld.long 0x00 7. "SPH,Serial clock phase (netx500: CR_ncpha)" "0: sample data at first clock edge data is,1: sample data at second clock edge data is"
newline
bitfld.long 0x00 6. "SPO,Serial clock polarity (netx500: CR_cpol)" "0: idle,1: idle"
newline
bitfld.long 0x00 0.--3. "datasize,DSS: data size select (transfer size = datasize + 1 bits): { | 0000...0010: reserved 0011: 4 bit 0100: 5 bit ... 0111: 8 bit ... 1111: 16 bit } Note: 16 bit TX-data-loss bug of netX50/netX5 is fixed since netX10" "?,?,?,3: 4 bit,4: 5 bit,?,?,7: 8 bit,?,?,?,?,?,?,?,15: 16 bit } Note: 16"
group.long 0x04++0x03
line.long 0x00 "spi_cr1,SPI control register 1 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 28. "rx_fifo_clr,Writing 1 to this bit will clear the receive FIFOs" "0,1"
newline
bitfld.long 0x00 24.--27. "rx_fifo_wm,Receive FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20. "tx_fifo_clr,Writing 1 to this bit will clear the transmit FIFOs" "0,1"
newline
bitfld.long 0x00 16.--19. "tx_fifo_wm,Transmit FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "fss_static,SPI static chip-select: { | 0: SPI chip-select will be toggled automatically before and after each transferred word according to fss and datasize. 1: SPI chip-select will be set statically according to the fss bits. }" "0: SPI chip-select will be toggled automatically,1: SPI chip-select will be set statically.."
newline
bitfld.long 0x00 8.--10. "fss,Frame or slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "SOD,Slave mode output disable (to connect multiple slaves to one master)" "0: MISO can be driven in slave mode,1: MISO is not driven in slave mode"
newline
bitfld.long 0x00 2. "MS,Mode select" "0: Module is configured as master,1: Module is configured as slave"
newline
bitfld.long 0x00 1. "SSE,SPI enable" "0: Module disabled,1: Module enabled"
newline
bitfld.long 0x00 0. "LBM,Loop back mode" "0: Internal loop back disabled,1: Internal loop back enabled spi_cr0.filter_in"
group.long 0x08++0x03
line.long 0x00 "spi_dr,SPI data register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
hexmask.long.tbyte 0x00 0.--16. 1. "data,Transmit data: Only lowest bits according to spi_cr0.datasize will be sent"
rgroup.long 0x0C++0x03
line.long 0x00 "spi_sr,SPI status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "rx_fifo_err_undr,Receive FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 30. "rx_fifo_err_ovfl,Receive FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 24.--28. "rx_fifo_level,Receive FIFO level (number of received words to read out are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 23. "tx_fifo_err_undr,Transmit FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 22. "tx_fifo_err_ovfl,Transmit FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 16.--20. "tx_fifo_level,Transmit FIFO level (number of words to transmit are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BSY,Device busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)" "0,1"
newline
bitfld.long 0x00 3. "RFF,Receive FIFO is full (1 if full)" "0,1"
newline
bitfld.long 0x00 2. "RNE,Receive FIFO is not empty (0 if empty)" "0,1"
newline
bitfld.long 0x00 1. "TNF,Transmit FIFO is not full (0 if full)" "0,1"
newline
bitfld.long 0x00 0. "TFE,Transmit FIFO is empty (1 if empty)" "0,1"
group.long 0x14++0x03
line.long 0x00 "spi_imsc,SPI Interrupt Mask Set and Clear register: Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeim,Transmit FIFO empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfim,Receive FIFO full interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneim,Receive FIFO not empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "RORIM,Receive FIFO overrun interrupt mask" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "spi_ris,SPI interrupt state before masking register (raw interrupt) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeris,Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0: transmit FIFO is not empty,1: transmit FIFO is empty"
newline
bitfld.long 0x00 5. "rxfris,Unmasked receive FIFO full interrupt state (for netx100/500 compliance)" "0: receive FIFO is not full,1: receive FIFO is full"
newline
bitfld.long 0x00 4. "rxneris,Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0: receive FIFO is empty,1: receive FIFO is not empty"
newline
bitfld.long 0x00 3. "TXRIS,Unmasked transmit FIFO interrupt state" "0: transmit FIFO equals or is higher than,1: transmit FIFO level is below spi_cr1.tx_fifo_wm"
newline
bitfld.long 0x00 2. "RXRIS,Unmasked receive FIFO interrupt state" "0: receive FIFO is equals or is below,1: receive FIFO is higher than spi_cr1.rx_fifo_wm"
newline
bitfld.long 0x00 1. "RTRIS,Unmasked receive timeout interrupt state Timeout period are 32 SPI clock periods depending on adr_spi_cr0.sck_muladd" "0: receive FIFO is empty or read during the last,1: receive FIFO is not empty and not read out in"
newline
bitfld.long 0x00 0. "RORRIS,Unmasked receive FIFO overrun interrupt state" "0: no receive FIFO overrun error occurred,1: receive FIFO overrun error occurred"
rgroup.long 0x1C++0x03
line.long 0x00 "spi_mis,SPI interrupt status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txemis,Masked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfmis,Masked receive FIFO full interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxnemis,Masked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXMIS,Masked transmit FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 2. "RXMIS,Masked receive FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 1. "RTMIS,Masked receive timeout interrupt state" "0,1"
newline
bitfld.long 0x00 0. "RORMIS,Masked receive FIFO overrun interrupt state" "0,1"
group.long 0x20++0x03
line.long 0x00 "spi_icr,SPI interrupt clear register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeic,Clear transmit FIFO empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfic,Clear receive FIFO full interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneic,Clear receive FIFO not empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIC,PL022 extension: clear transmit FIFO interrupt" "0,1"
newline
bitfld.long 0x00 2. "RXIC,PL022 extension: clear receive FIFO interrupt" "0,1"
newline
bitfld.long 0x00 1. "RTIC,Clear receive FIFO overrun interrupt" "0,1"
newline
bitfld.long 0x00 0. "RORIC,Clear receive FIFO overrun interrupt Writing '1' here will clear the receive FIFO" "0,1"
group.long 0x28++0x03
line.long 0x00 "spi_dmacr,SPI DMA control register"
bitfld.long 0x00 1. "TXDMAE,Enable DMA for SPI transmit data" "0,1"
newline
bitfld.long 0x00 0. "RXDMAE,Enable DMA for SPI receive data" "0,1"
group.long 0x30++0x03
line.long 0x00 "spi_data_register,netx100/500 compliant SPI data register (DR) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 17. "dr_valid1,Obsolete always 0" "0,1"
newline
bitfld.long 0x00 16. "dr_valid0,Valid bit for data_byte_0 This bit shows if data_byte_0 is valid and must be set during a FIFO write access" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "data_byte_1,Obsolete don't use"
newline
hexmask.long.byte 0x00 0.--7. 1. "data_byte_0,Data byte 0"
rgroup.long 0x34++0x03
line.long 0x00 "spi_status_register,netx100/500 compliant SPI status register (SR): Shows the actual status of the SPI interface"
bitfld.long 0x00 25. "SR_selected,External master has access to SPI interface" "0,1"
newline
bitfld.long 0x00 24. "SR_out_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 23. "SR_out_empty,Output FIFO is empty in slave mode (equals spi_ris.txeris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "SR_out_fw,netX is writing data too fast into output FIFO" "0,1"
newline
bitfld.long 0x00 21. "SR_out_fuel,Adjustable fill value of output FIFO reached (equals spi_ris.TXRIS in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "SR_in_full,Input FIFO is full (equals spi_ris.rxfris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "SR_in_recdata,Valid data bytes in input FIFO (equals spi_ris.rxneris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "SR_in_fuel,Adjustable fill value of input FIFO reached (equals spi_ris.RXRIS in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "SR_out_fuel_val,Output FIFO fill value (number of bytes)"
newline
hexmask.long.word 0x00 0.--8. 1. "SR_in_fuel_val,Input FIFO fill value (number of bytes)"
group.long 0x38++0x03
line.long 0x00 "spi_control_register,netx100/500 compliant SPI control register (CR)"
bitfld.long 0x00 31. "CR_en," "0,1"
newline
bitfld.long 0x00 30. "CR_ms," "0,1"
newline
bitfld.long 0x00 29. "CR_cpol," "0,1"
newline
bitfld.long 0x00 28. "CR_ncpha,SPI clock phase mode (Note: meaning of this bit is inverted to functionality of bit spi_cr0.SPH): { | 0: change data on secondary SCK edge data is active on primary SCK edge 1: change data on primary SCK edge data is active on secondary SCK.." "0: change data on secondary SCK edge data is..,1: change data on primary SCK edge data is active"
newline
bitfld.long 0x00 25.--27. "CR_burst,netx100/netx500 only obsolete in later versions: burst length = 2^CR_burst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22.--24. "CR_burstdelay,netx100/netx500 only obsolete in later versions: delay between transmission of 2 data bytes (0 to 7 SCK cycles)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "CR_clr_outfifo,Clear output FIFO" "0,1"
newline
bitfld.long 0x00 20. "CR_clr_infifo,Clear input FIFO" "0,1"
newline
bitfld.long 0x00 11. "CS_mode," "0,1"
newline
bitfld.long 0x00 8.--10. "CR_ss,External slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "CR_write,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 6. "CR_read,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 1.--4. "CR_speed,Clock divider for SPI clock (2 - 2^16) If SPI clock rate is changed using spi_cr0.sck_muladd this value will not be updated and may be incorrect There are 16 different SPI clocks frequencies to choose" "0: 0.025 MHz (Note,1: 0.05 MHz,2: 0.1 MHz,3: 0.2 MHz,4: 0.5 MHz,5: 1 MHz,6: 1.25 MHz,7: 2 MHz,8: 2.5 MHz,9: 3.3333 MHz,10: 5 MHz,11: 10 MHz,12: 12.5 MHz,13: 16.6666 MHz,14: 25 MHz,15: 50 MHz"
newline
bitfld.long 0x00 0. "CR_softreset,write only: no function in netx100/netx500 later versions: clears IRQs and FIFOs" "0,1"
group.long 0x3C++0x03
line.long 0x00 "spi_interrupt_control_register,netx100/500 compliant SPI interrupt control register (IR) In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16 fill values are fixed to 4"
bitfld.long 0x00 24. "IR_out_full_en,IRQ enable for irq_spi(6) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 23. "IR_out_empty_en,IRQ enable for irq_spi(5) (equals spi_imsc.rxeim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "IR_out_fw_en,IRQ enable for irq_spi(4) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 21. "IR_out_fuel_en,IRQ enable for irq_spi(3) (equals spi_imsc.TXIM in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "IR_in_full_en,IRQ enable for irq_spi(2) (equals spi_imsc.txfim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "IR_in_recdata_en,IRQ enable for irq_spi(1) (equals spi_imsc.txneim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "IR_in_fuel_en,IRQ enable for irq_spi(0) (equals spi_imsc.RXIM in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "IR_out_fuel,Adjustable watermark level of output FIFO"
newline
hexmask.long.word 0x00 0.--8. 1. "IR_in_fuel,Adjustable watermark level of input FIFO"
tree.end
tree "SPI1_APP"
base ad:0xFF801A40
group.long 0x00++0x03
line.long 0x00 "spi_cr0,SPI control register 0 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "netx100_comp,Use netx100/500-compatible SPI mode" "0: start transfer after writing data,1: start transfer after setting CR_write or.."
newline
bitfld.long 0x00 28. "slave_sig_early,Generate MISO in slave mode 1 SCK clock edge earlier than defined in the SPI specification" "0,1"
newline
bitfld.long 0x00 27. "filter_in,Receive data is sampled every 10ns (100MHz system clock)" "0,1"
newline
bitfld.long 0x00 24.--25. "format,Frame format" "0,1,2,3"
newline
hexmask.long.word 0x00 8.--19. 1. "sck_muladd,Serial clock rate multiply add value for master SCK generation"
newline
bitfld.long 0x00 7. "SPH,Serial clock phase (netx500: CR_ncpha)" "0: sample data at first clock edge data is,1: sample data at second clock edge data is"
newline
bitfld.long 0x00 6. "SPO,Serial clock polarity (netx500: CR_cpol)" "0: idle,1: idle"
newline
bitfld.long 0x00 0.--3. "datasize,DSS: data size select (transfer size = datasize + 1 bits): { | 0000...0010: reserved 0011: 4 bit 0100: 5 bit ... 0111: 8 bit ... 1111: 16 bit } Note: 16 bit TX-data-loss bug of netX50/netX5 is fixed since netX10" "?,?,?,3: 4 bit,4: 5 bit,?,?,7: 8 bit,?,?,?,?,?,?,?,15: 16 bit } Note: 16"
group.long 0x04++0x03
line.long 0x00 "spi_cr1,SPI control register 1 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 28. "rx_fifo_clr,Writing 1 to this bit will clear the receive FIFOs" "0,1"
newline
bitfld.long 0x00 24.--27. "rx_fifo_wm,Receive FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20. "tx_fifo_clr,Writing 1 to this bit will clear the transmit FIFOs" "0,1"
newline
bitfld.long 0x00 16.--19. "tx_fifo_wm,Transmit FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "fss_static,SPI static chip-select: { | 0: SPI chip-select will be toggled automatically before and after each transferred word according to fss and datasize. 1: SPI chip-select will be set statically according to the fss bits. }" "0: SPI chip-select will be toggled automatically,1: SPI chip-select will be set statically.."
newline
bitfld.long 0x00 8.--10. "fss,Frame or slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "SOD,Slave mode output disable (to connect multiple slaves to one master)" "0: MISO can be driven in slave mode,1: MISO is not driven in slave mode"
newline
bitfld.long 0x00 2. "MS,Mode select" "0: Module is configured as master,1: Module is configured as slave"
newline
bitfld.long 0x00 1. "SSE,SPI enable" "0: Module disabled,1: Module enabled"
newline
bitfld.long 0x00 0. "LBM,Loop back mode" "0: Internal loop back disabled,1: Internal loop back enabled spi_cr0.filter_in"
group.long 0x08++0x03
line.long 0x00 "spi_dr,SPI data register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
hexmask.long.tbyte 0x00 0.--16. 1. "data,Transmit data: Only lowest bits according to spi_cr0.datasize will be sent"
rgroup.long 0x0C++0x03
line.long 0x00 "spi_sr,SPI status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "rx_fifo_err_undr,Receive FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 30. "rx_fifo_err_ovfl,Receive FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 24.--28. "rx_fifo_level,Receive FIFO level (number of received words to read out are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 23. "tx_fifo_err_undr,Transmit FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 22. "tx_fifo_err_ovfl,Transmit FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 16.--20. "tx_fifo_level,Transmit FIFO level (number of words to transmit are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BSY,Device busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)" "0,1"
newline
bitfld.long 0x00 3. "RFF,Receive FIFO is full (1 if full)" "0,1"
newline
bitfld.long 0x00 2. "RNE,Receive FIFO is not empty (0 if empty)" "0,1"
newline
bitfld.long 0x00 1. "TNF,Transmit FIFO is not full (0 if full)" "0,1"
newline
bitfld.long 0x00 0. "TFE,Transmit FIFO is empty (1 if empty)" "0,1"
group.long 0x14++0x03
line.long 0x00 "spi_imsc,SPI Interrupt Mask Set and Clear register: Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeim,Transmit FIFO empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfim,Receive FIFO full interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneim,Receive FIFO not empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "RORIM,Receive FIFO overrun interrupt mask" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "spi_ris,SPI interrupt state before masking register (raw interrupt) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeris,Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0: transmit FIFO is not empty,1: transmit FIFO is empty"
newline
bitfld.long 0x00 5. "rxfris,Unmasked receive FIFO full interrupt state (for netx100/500 compliance)" "0: receive FIFO is not full,1: receive FIFO is full"
newline
bitfld.long 0x00 4. "rxneris,Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0: receive FIFO is empty,1: receive FIFO is not empty"
newline
bitfld.long 0x00 3. "TXRIS,Unmasked transmit FIFO interrupt state" "0: transmit FIFO equals or is higher than,1: transmit FIFO level is below spi_cr1.tx_fifo_wm"
newline
bitfld.long 0x00 2. "RXRIS,Unmasked receive FIFO interrupt state" "0: receive FIFO is equals or is below,1: receive FIFO is higher than spi_cr1.rx_fifo_wm"
newline
bitfld.long 0x00 1. "RTRIS,Unmasked receive timeout interrupt state Timeout period are 32 SPI clock periods depending on adr_spi_cr0.sck_muladd" "0: receive FIFO is empty or read during the last,1: receive FIFO is not empty and not read out in"
newline
bitfld.long 0x00 0. "RORRIS,Unmasked receive FIFO overrun interrupt state" "0: no receive FIFO overrun error occurred,1: receive FIFO overrun error occurred"
rgroup.long 0x1C++0x03
line.long 0x00 "spi_mis,SPI interrupt status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txemis,Masked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfmis,Masked receive FIFO full interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxnemis,Masked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXMIS,Masked transmit FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 2. "RXMIS,Masked receive FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 1. "RTMIS,Masked receive timeout interrupt state" "0,1"
newline
bitfld.long 0x00 0. "RORMIS,Masked receive FIFO overrun interrupt state" "0,1"
group.long 0x20++0x03
line.long 0x00 "spi_icr,SPI interrupt clear register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeic,Clear transmit FIFO empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfic,Clear receive FIFO full interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneic,Clear receive FIFO not empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIC,PL022 extension: clear transmit FIFO interrupt" "0,1"
newline
bitfld.long 0x00 2. "RXIC,PL022 extension: clear receive FIFO interrupt" "0,1"
newline
bitfld.long 0x00 1. "RTIC,Clear receive FIFO overrun interrupt" "0,1"
newline
bitfld.long 0x00 0. "RORIC,Clear receive FIFO overrun interrupt Writing '1' here will clear the receive FIFO" "0,1"
group.long 0x28++0x03
line.long 0x00 "spi_dmacr,SPI DMA control register"
bitfld.long 0x00 1. "TXDMAE,Enable DMA for SPI transmit data" "0,1"
newline
bitfld.long 0x00 0. "RXDMAE,Enable DMA for SPI receive data" "0,1"
group.long 0x30++0x03
line.long 0x00 "spi_data_register,netx100/500 compliant SPI data register (DR) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 17. "dr_valid1,Obsolete always 0" "0,1"
newline
bitfld.long 0x00 16. "dr_valid0,Valid bit for data_byte_0 This bit shows if data_byte_0 is valid and must be set during a FIFO write access" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "data_byte_1,Obsolete don't use"
newline
hexmask.long.byte 0x00 0.--7. 1. "data_byte_0,Data byte 0"
rgroup.long 0x34++0x03
line.long 0x00 "spi_status_register,netx100/500 compliant SPI status register (SR): Shows the actual status of the SPI interface"
bitfld.long 0x00 25. "SR_selected,External master has access to SPI interface" "0,1"
newline
bitfld.long 0x00 24. "SR_out_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 23. "SR_out_empty,Output FIFO is empty in slave mode (equals spi_ris.txeris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "SR_out_fw,netX is writing data too fast into output FIFO" "0,1"
newline
bitfld.long 0x00 21. "SR_out_fuel,Adjustable fill value of output FIFO reached (equals spi_ris.TXRIS in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "SR_in_full,Input FIFO is full (equals spi_ris.rxfris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "SR_in_recdata,Valid data bytes in input FIFO (equals spi_ris.rxneris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "SR_in_fuel,Adjustable fill value of input FIFO reached (equals spi_ris.RXRIS in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "SR_out_fuel_val,Output FIFO fill value (number of bytes)"
newline
hexmask.long.word 0x00 0.--8. 1. "SR_in_fuel_val,Input FIFO fill value (number of bytes)"
group.long 0x38++0x03
line.long 0x00 "spi_control_register,netx100/500 compliant SPI control register (CR)"
bitfld.long 0x00 31. "CR_en," "0,1"
newline
bitfld.long 0x00 30. "CR_ms," "0,1"
newline
bitfld.long 0x00 29. "CR_cpol," "0,1"
newline
bitfld.long 0x00 28. "CR_ncpha,SPI clock phase mode (Note: meaning of this bit is inverted to functionality of bit spi_cr0.SPH): { | 0: change data on secondary SCK edge data is active on primary SCK edge 1: change data on primary SCK edge data is active on secondary SCK.." "0: change data on secondary SCK edge data is..,1: change data on primary SCK edge data is active"
newline
bitfld.long 0x00 25.--27. "CR_burst,netx100/netx500 only obsolete in later versions: burst length = 2^CR_burst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22.--24. "CR_burstdelay,netx100/netx500 only obsolete in later versions: delay between transmission of 2 data bytes (0 to 7 SCK cycles)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "CR_clr_outfifo,Clear output FIFO" "0,1"
newline
bitfld.long 0x00 20. "CR_clr_infifo,Clear input FIFO" "0,1"
newline
bitfld.long 0x00 11. "CS_mode," "0,1"
newline
bitfld.long 0x00 8.--10. "CR_ss,External slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "CR_write,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 6. "CR_read,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 1.--4. "CR_speed,Clock divider for SPI clock (2 - 2^16) If SPI clock rate is changed using spi_cr0.sck_muladd this value will not be updated and may be incorrect There are 16 different SPI clocks frequencies to choose" "0: 0.025 MHz (Note,1: 0.05 MHz,2: 0.1 MHz,3: 0.2 MHz,4: 0.5 MHz,5: 1 MHz,6: 1.25 MHz,7: 2 MHz,8: 2.5 MHz,9: 3.3333 MHz,10: 5 MHz,11: 10 MHz,12: 12.5 MHz,13: 16.6666 MHz,14: 25 MHz,15: 50 MHz"
newline
bitfld.long 0x00 0. "CR_softreset,write only: no function in netx100/netx500 later versions: clears IRQs and FIFOs" "0,1"
group.long 0x3C++0x03
line.long 0x00 "spi_interrupt_control_register,netx100/500 compliant SPI interrupt control register (IR) In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16 fill values are fixed to 4"
bitfld.long 0x00 24. "IR_out_full_en,IRQ enable for irq_spi(6) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 23. "IR_out_empty_en,IRQ enable for irq_spi(5) (equals spi_imsc.rxeim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "IR_out_fw_en,IRQ enable for irq_spi(4) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 21. "IR_out_fuel_en,IRQ enable for irq_spi(3) (equals spi_imsc.TXIM in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "IR_in_full_en,IRQ enable for irq_spi(2) (equals spi_imsc.txfim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "IR_in_recdata_en,IRQ enable for irq_spi(1) (equals spi_imsc.txneim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "IR_in_fuel_en,IRQ enable for irq_spi(0) (equals spi_imsc.RXIM in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "IR_out_fuel,Adjustable watermark level of output FIFO"
newline
hexmask.long.word 0x00 0.--8. 1. "IR_in_fuel,Adjustable watermark level of input FIFO"
tree.end
tree "SPI2_APP"
base ad:0xFF801A80
group.long 0x00++0x03
line.long 0x00 "spi_cr0,SPI control register 0 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "netx100_comp,Use netx100/500-compatible SPI mode" "0: start transfer after writing data,1: start transfer after setting CR_write or.."
newline
bitfld.long 0x00 28. "slave_sig_early,Generate MISO in slave mode 1 SCK clock edge earlier than defined in the SPI specification" "0,1"
newline
bitfld.long 0x00 27. "filter_in,Receive data is sampled every 10ns (100MHz system clock)" "0,1"
newline
bitfld.long 0x00 24.--25. "format,Frame format" "0,1,2,3"
newline
hexmask.long.word 0x00 8.--19. 1. "sck_muladd,Serial clock rate multiply add value for master SCK generation"
newline
bitfld.long 0x00 7. "SPH,Serial clock phase (netx500: CR_ncpha)" "0: sample data at first clock edge data is,1: sample data at second clock edge data is"
newline
bitfld.long 0x00 6. "SPO,Serial clock polarity (netx500: CR_cpol)" "0: idle,1: idle"
newline
bitfld.long 0x00 0.--3. "datasize,DSS: data size select (transfer size = datasize + 1 bits): { | 0000...0010: reserved 0011: 4 bit 0100: 5 bit ... 0111: 8 bit ... 1111: 16 bit } Note: 16 bit TX-data-loss bug of netX50/netX5 is fixed since netX10" "?,?,?,3: 4 bit,4: 5 bit,?,?,7: 8 bit,?,?,?,?,?,?,?,15: 16 bit } Note: 16"
group.long 0x04++0x03
line.long 0x00 "spi_cr1,SPI control register 1 Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 28. "rx_fifo_clr,Writing 1 to this bit will clear the receive FIFOs" "0,1"
newline
bitfld.long 0x00 24.--27. "rx_fifo_wm,Receive FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20. "tx_fifo_clr,Writing 1 to this bit will clear the transmit FIFOs" "0,1"
newline
bitfld.long 0x00 16.--19. "tx_fifo_wm,Transmit FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "fss_static,SPI static chip-select: { | 0: SPI chip-select will be toggled automatically before and after each transferred word according to fss and datasize. 1: SPI chip-select will be set statically according to the fss bits. }" "0: SPI chip-select will be toggled automatically,1: SPI chip-select will be set statically.."
newline
bitfld.long 0x00 8.--10. "fss,Frame or slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "SOD,Slave mode output disable (to connect multiple slaves to one master)" "0: MISO can be driven in slave mode,1: MISO is not driven in slave mode"
newline
bitfld.long 0x00 2. "MS,Mode select" "0: Module is configured as master,1: Module is configured as slave"
newline
bitfld.long 0x00 1. "SSE,SPI enable" "0: Module disabled,1: Module enabled"
newline
bitfld.long 0x00 0. "LBM,Loop back mode" "0: Internal loop back disabled,1: Internal loop back enabled spi_cr0.filter_in"
group.long 0x08++0x03
line.long 0x00 "spi_dr,SPI data register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
hexmask.long.tbyte 0x00 0.--16. 1. "data,Transmit data: Only lowest bits according to spi_cr0.datasize will be sent"
rgroup.long 0x0C++0x03
line.long 0x00 "spi_sr,SPI status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 31. "rx_fifo_err_undr,Receive FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 30. "rx_fifo_err_ovfl,Receive FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 24.--28. "rx_fifo_level,Receive FIFO level (number of received words to read out are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 23. "tx_fifo_err_undr,Transmit FIFO underrun error occurred data is lost" "0,1"
newline
bitfld.long 0x00 22. "tx_fifo_err_ovfl,Transmit FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 16.--20. "tx_fifo_level,Transmit FIFO level (number of words to transmit are left in FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BSY,Device busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)" "0,1"
newline
bitfld.long 0x00 3. "RFF,Receive FIFO is full (1 if full)" "0,1"
newline
bitfld.long 0x00 2. "RNE,Receive FIFO is not empty (0 if empty)" "0,1"
newline
bitfld.long 0x00 1. "TNF,Transmit FIFO is not full (0 if full)" "0,1"
newline
bitfld.long 0x00 0. "TFE,Transmit FIFO is empty (1 if empty)" "0,1"
group.long 0x14++0x03
line.long 0x00 "spi_imsc,SPI Interrupt Mask Set and Clear register: Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeim,Transmit FIFO empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfim,Receive FIFO full interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneim,Receive FIFO not empty interrupt mask (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "RORIM,Receive FIFO overrun interrupt mask" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "spi_ris,SPI interrupt state before masking register (raw interrupt) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeris,Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0: transmit FIFO is not empty,1: transmit FIFO is empty"
newline
bitfld.long 0x00 5. "rxfris,Unmasked receive FIFO full interrupt state (for netx100/500 compliance)" "0: receive FIFO is not full,1: receive FIFO is full"
newline
bitfld.long 0x00 4. "rxneris,Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0: receive FIFO is empty,1: receive FIFO is not empty"
newline
bitfld.long 0x00 3. "TXRIS,Unmasked transmit FIFO interrupt state" "0: transmit FIFO equals or is higher than,1: transmit FIFO level is below spi_cr1.tx_fifo_wm"
newline
bitfld.long 0x00 2. "RXRIS,Unmasked receive FIFO interrupt state" "0: receive FIFO is equals or is below,1: receive FIFO is higher than spi_cr1.rx_fifo_wm"
newline
bitfld.long 0x00 1. "RTRIS,Unmasked receive timeout interrupt state Timeout period are 32 SPI clock periods depending on adr_spi_cr0.sck_muladd" "0: receive FIFO is empty or read during the last,1: receive FIFO is not empty and not read out in"
newline
bitfld.long 0x00 0. "RORRIS,Unmasked receive FIFO overrun interrupt state" "0: no receive FIFO overrun error occurred,1: receive FIFO overrun error occurred"
rgroup.long 0x1C++0x03
line.long 0x00 "spi_mis,SPI interrupt status register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txemis,Masked transmit FIFO empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfmis,Masked receive FIFO full interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxnemis,Masked receive FIFO not empty interrupt state (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXMIS,Masked transmit FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 2. "RXMIS,Masked receive FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 1. "RTMIS,Masked receive timeout interrupt state" "0,1"
newline
bitfld.long 0x00 0. "RORMIS,Masked receive FIFO overrun interrupt state" "0,1"
group.long 0x20++0x03
line.long 0x00 "spi_icr,SPI interrupt clear register Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 6. "txeic,Clear transmit FIFO empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 5. "rxfic,Clear receive FIFO full interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 4. "rxneic,Clear receive FIFO not empty interrupt (for netx100/500 compliance)" "0,1"
newline
bitfld.long 0x00 3. "TXIC,PL022 extension: clear transmit FIFO interrupt" "0,1"
newline
bitfld.long 0x00 2. "RXIC,PL022 extension: clear receive FIFO interrupt" "0,1"
newline
bitfld.long 0x00 1. "RTIC,Clear receive FIFO overrun interrupt" "0,1"
newline
bitfld.long 0x00 0. "RORIC,Clear receive FIFO overrun interrupt Writing '1' here will clear the receive FIFO" "0,1"
group.long 0x28++0x03
line.long 0x00 "spi_dmacr,SPI DMA control register"
bitfld.long 0x00 1. "TXDMAE,Enable DMA for SPI transmit data" "0,1"
newline
bitfld.long 0x00 0. "RXDMAE,Enable DMA for SPI receive data" "0,1"
group.long 0x30++0x03
line.long 0x00 "spi_data_register,netx100/500 compliant SPI data register (DR) Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500"
bitfld.long 0x00 17. "dr_valid1,Obsolete always 0" "0,1"
newline
bitfld.long 0x00 16. "dr_valid0,Valid bit for data_byte_0 This bit shows if data_byte_0 is valid and must be set during a FIFO write access" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "data_byte_1,Obsolete don't use"
newline
hexmask.long.byte 0x00 0.--7. 1. "data_byte_0,Data byte 0"
rgroup.long 0x34++0x03
line.long 0x00 "spi_status_register,netx100/500 compliant SPI status register (SR): Shows the actual status of the SPI interface"
bitfld.long 0x00 25. "SR_selected,External master has access to SPI interface" "0,1"
newline
bitfld.long 0x00 24. "SR_out_full,Output FIFO is full" "0,1"
newline
bitfld.long 0x00 23. "SR_out_empty,Output FIFO is empty in slave mode (equals spi_ris.txeris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "SR_out_fw,netX is writing data too fast into output FIFO" "0,1"
newline
bitfld.long 0x00 21. "SR_out_fuel,Adjustable fill value of output FIFO reached (equals spi_ris.TXRIS in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "SR_in_full,Input FIFO is full (equals spi_ris.rxfris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "SR_in_recdata,Valid data bytes in input FIFO (equals spi_ris.rxneris in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "SR_in_fuel,Adjustable fill value of input FIFO reached (equals spi_ris.RXRIS in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "SR_out_fuel_val,Output FIFO fill value (number of bytes)"
newline
hexmask.long.word 0x00 0.--8. 1. "SR_in_fuel_val,Input FIFO fill value (number of bytes)"
group.long 0x38++0x03
line.long 0x00 "spi_control_register,netx100/500 compliant SPI control register (CR)"
bitfld.long 0x00 31. "CR_en," "0,1"
newline
bitfld.long 0x00 30. "CR_ms," "0,1"
newline
bitfld.long 0x00 29. "CR_cpol," "0,1"
newline
bitfld.long 0x00 28. "CR_ncpha,SPI clock phase mode (Note: meaning of this bit is inverted to functionality of bit spi_cr0.SPH): { | 0: change data on secondary SCK edge data is active on primary SCK edge 1: change data on primary SCK edge data is active on secondary SCK.." "0: change data on secondary SCK edge data is..,1: change data on primary SCK edge data is active"
newline
bitfld.long 0x00 25.--27. "CR_burst,netx100/netx500 only obsolete in later versions: burst length = 2^CR_burst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22.--24. "CR_burstdelay,netx100/netx500 only obsolete in later versions: delay between transmission of 2 data bytes (0 to 7 SCK cycles)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "CR_clr_outfifo,Clear output FIFO" "0,1"
newline
bitfld.long 0x00 20. "CR_clr_infifo,Clear input FIFO" "0,1"
newline
bitfld.long 0x00 11. "CS_mode," "0,1"
newline
bitfld.long 0x00 8.--10. "CR_ss,External slave select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "CR_write,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 6. "CR_read,netx100/netx500 only in later versions always" "0,1"
newline
bitfld.long 0x00 1.--4. "CR_speed,Clock divider for SPI clock (2 - 2^16) If SPI clock rate is changed using spi_cr0.sck_muladd this value will not be updated and may be incorrect There are 16 different SPI clocks frequencies to choose" "0: 0.025 MHz (Note,1: 0.05 MHz,2: 0.1 MHz,3: 0.2 MHz,4: 0.5 MHz,5: 1 MHz,6: 1.25 MHz,7: 2 MHz,8: 2.5 MHz,9: 3.3333 MHz,10: 5 MHz,11: 10 MHz,12: 12.5 MHz,13: 16.6666 MHz,14: 25 MHz,15: 50 MHz"
newline
bitfld.long 0x00 0. "CR_softreset,write only: no function in netx100/netx500 later versions: clears IRQs and FIFOs" "0,1"
group.long 0x3C++0x03
line.long 0x00 "spi_interrupt_control_register,netx100/500 compliant SPI interrupt control register (IR) In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16 fill values are fixed to 4"
bitfld.long 0x00 24. "IR_out_full_en,IRQ enable for irq_spi(6) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 23. "IR_out_empty_en,IRQ enable for irq_spi(5) (equals spi_imsc.rxeim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 22. "IR_out_fw_en,IRQ enable for irq_spi(4) netx100/netx500 only always 0 in later versions" "0,1"
newline
bitfld.long 0x00 21. "IR_out_fuel_en,IRQ enable for irq_spi(3) (equals spi_imsc.TXIM in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 20. "IR_in_full_en,IRQ enable for irq_spi(2) (equals spi_imsc.txfim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 19. "IR_in_recdata_en,IRQ enable for irq_spi(1) (equals spi_imsc.txneim in netx50 and later versions)" "0,1"
newline
bitfld.long 0x00 18. "IR_in_fuel_en,IRQ enable for irq_spi(0) (equals spi_imsc.RXIM in netx50 and later versions)" "0,1"
newline
hexmask.long.word 0x00 9.--17. 1. "IR_out_fuel,Adjustable watermark level of output FIFO"
newline
hexmask.long.word 0x00 0.--8. 1. "IR_in_fuel,Adjustable watermark level of input FIFO"
tree.end
tree "SQI"
base ad:0xFF401640
group.long 0x00++0x03
line.long 0x00 "sqi_cr0,SQI control register 0 This register is compatible with the netX50 and netX10 SPI module but some additional settings are possible"
bitfld.long 0x00 27. "filter_in,Input filtering Receive data is sampled every 10 ns (100 MHz system clock)" "0,1"
bitfld.long 0x00 22.--23. "sio_cfg,SQI IO configuration Default: All additional SQI-IOs (SIO2+3) are in PIO input mode" "0: only SIO2+3 are controllable as PIOs (2-bit SPI,1: all SQI IOs are used for transfers (4-bit..,2: reserved,3: all SQI IOs are controllable as PIOs"
newline
hexmask.long.word 0x00 8.--19. 1. "sck_muladd,Serial clock rate multiply add value for sck generation sck-frequency: f_sck = (sck_muladd * 100)/4096 [MHz]"
bitfld.long 0x00 7. "sck_phase,Serial clock phase" "0: Sample data at first clock edge data is,1: Sample data at second clock edge data is"
newline
bitfld.long 0x00 6. "sck_pol,Serial clock polarity" "0: idle,1: idle"
bitfld.long 0x00 0.--3. "datasize,Data size select for standard Motorola SPI mode This bit field is unused in 2-bit and 4-bit SPI modes (i.e. data size fixed to 8 bit)" "?,?,?,3: 4 bit,4: 5 bit,?,?,7: 8 bit,?,?,?,?,?,?,?,15: 16 bit }"
group.long 0x04++0x03
line.long 0x00 "sqi_cr1,SQI control register 1 This register is compatible with the netX50 and netX10 SPI module but some additional settings are possible"
bitfld.long 0x00 28. "rx_fifo_clr,Receive FIFO clear Writing 1 to this bit will clear the receive FIFO" "0,1"
bitfld.long 0x00 24.--27. "rx_fifo_wm,Receive FIFO watermark for IRQ generation If the receive FIFO watermark IRQ is enabled (bit 'RXIM' is set in register 'sqi_irq_mask') transfers will stop when the receive FIFO runs full" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20. "tx_fifo_clr,Transmit FIFO clear Writing 1 to this bit will clear the transmit FIFO" "0,1"
bitfld.long 0x00 16.--19. "tx_fifo_wm,Transmit FIFO watermark for IRQ generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "spi_trans_ctrl,Transfer control for standard Motorola SPI (default: disabled) This bit is used only for standard Motorola SPI (bits 'mode' of register 'sqi_tcr') in full-duplex and half-duplex mode" "0,1"
bitfld.long 0x00 11. "fss_static,SQI static chip select" "0: Chip select will be generated automatically at,1: Chip select will be set statically according to"
newline
bitfld.long 0x00 8.--10. "fss,Frame slave select Up to 3 devices can be assigned directly" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "sqi_en,SQI enable" "0: Interface disabled,1: Interface enabled"
group.long 0x08++0x03
line.long 0x00 "sqi_dr,SQI data register (DR) Read access: Received data word is delivered from receive FIFO"
hexmask.long 0x00 0.--31. 1. "data,Transmit data The data must be right-aligned during writing"
rgroup.long 0x0C++0x03
line.long 0x00 "sqi_sr,Read-only SQI status register Shows the current status of the SQI interface"
bitfld.long 0x00 31. "rx_fifo_err_undr,Receive FIFO underrun error has occurred unexpected data has been" "0,1"
bitfld.long 0x00 30. "rx_fifo_err_ovfl,Receive FIFO overflow error occurred data is lost" "0,1"
newline
bitfld.long 0x00 24.--28. "rx_fifo_level,Receive FIFO level (number of received words to be read from the FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "tx_fifo_err_undr,Transmit FIFO underrun error has occurred unexpected data has been sent" "0,1"
newline
bitfld.long 0x00 22. "tx_fifo_err_ovfl,Transmit FIFO overflow error occurred data is lost" "0,1"
bitfld.long 0x00 16.--20. "tx_fifo_level,Transmit FIFO level (number of words to be transmitted are left in the FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "sqirom_disabled_err,Access to the disabled SQIROM area has occurred" "0,1"
bitfld.long 0x00 14. "sqirom_write_err,Write access to the read-only SQIROM area has occurred" "0,1"
newline
bitfld.long 0x00 13. "sqirom_timeout_err,Timeout during a read of the SQIROM area has occurred" "0,1"
bitfld.long 0x00 4. "busy,Device is busy 1 if data is currently transmitted/received or the transmit FIFO is not empty" "0,1"
newline
bitfld.long 0x00 3. "rx_fifo_full,Receive FIFO is full (1 if full)" "0,1"
bitfld.long 0x00 2. "rx_fifo_not_empty,Receive FIFO is not empty (0 if empty)" "0,1"
newline
bitfld.long 0x00 1. "tx_fifo_not_full,Transmit FIFO is not full (0 if full)" "0,1"
bitfld.long 0x00 0. "tx_fifo_empty,Transmit FIFO is empty (1 if empty)" "0,1"
group.long 0x10++0x03
line.long 0x00 "sqi_tcr,SQI transfer control This register must not be changed during a transfer (bit 'busy' of register 'sqi_sr' is '1') to avoid corrupted transfers causing damage to the hardware"
bitfld.long 0x00 29. "ms_byte_first,Most significant byte first 2- and 4-bit mode: Writing 1 to this bit will use most significant byte first in DWords (big endian)" "0,1"
bitfld.long 0x00 28. "ms_bit_first,Most significant bit first 2- and 4-bit mode: Writing 1 to this bit will transfer most significant bit first (default)" "0,1"
newline
bitfld.long 0x00 26.--27. "duplex,Transfer type selection Default is '11' for standard SPI compatibility" "0: dummy Generates 'transfer_size' + 1 serial..,1: half-duplex receive Receives 'transfer_size'..,2: half-duplex transmit Transmits..,3: full-duplex Standard Motorola SPI mode only"
bitfld.long 0x00 24.--25. "mode,SPI/SQI mode selection" "0: Standard Motorola SPI mode,1: 2-bit SPI mode,2: 4-bit SPI mode,3: reserved"
newline
bitfld.long 0x00 23. "start_transfer,Transfer start signal Writing a 1 starts the transfer of transfer_size bytes or dummy cycles" "0,1"
bitfld.long 0x00 22. "tx_oe,Output driver enable in dummy or standard SPI receive-only mode Writing a 1 enables the output drivers of the data pins in the dummy mode" "0,1"
newline
bitfld.long 0x00 21. "tx_out,Output level in dummy or standard SPI receive-only mode This bit selects the output level when the output driver is enabled in the dummy mode" "0,1"
abitfld.long 0x00 0.--18. "transfer_size,Number of bytes within the current SQI transaction Program (number of bytes - 1) or (number of dummy clock cycles - 1)" "0x00000=0: one byte/dummy cycle,0x7FFFF=524287: 512k bytes/dummy cycles } This.."
group.long 0x14++0x03
line.long 0x00 "sqi_irq_mask,SQI interrupt mask register: IRQ mask is an AND-mask: Only raw interrupts with mask bit set can generate a module IRQ to CPU"
bitfld.long 0x00 8. "sqirom_error,SQIROM error interrupt mask" "0,1"
bitfld.long 0x00 7. "trans_end,Transfer end interrupt mask" "0,1"
newline
bitfld.long 0x00 6. "txeim,Transmit FIFO empty interrupt mask (for compatibility with netx100/500)" "0,1"
bitfld.long 0x00 5. "rxfim,Receive FIFO full interrupt mask (for compatibility with netx100/500)" "0,1"
newline
bitfld.long 0x00 4. "rxneim,Receive FIFO not empty interrupt mask (for compatibility with netx100/500)" "0,1"
bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask" "0,1"
newline
bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask" "0,1"
bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask" "0,1"
newline
bitfld.long 0x00 0. "RORIM,Receive FIFO overrun interrupt mask" "0,1"
group.long 0x18++0x03
line.long 0x00 "sqi_irq_raw,SQI interrupt state before masking register (raw interrupt)"
bitfld.long 0x00 8. "sqirom_error,Unmasked SQIROM error interrupt state" "0: no SQIROM error detected,1: SQIROM access error detected"
bitfld.long 0x00 7. "trans_end,Unmasked transfer end interrupt state (related to bit 'busy' of register 'sqi_sr')" "0: transfer not finished,1: transfer finished"
newline
bitfld.long 0x00 6. "txeris,Unmasked transmit FIFO empty interrupt state (for compatibility with netx100/500)" "0: transmit FIFO is not empty,1: transmit FIFO is empty"
bitfld.long 0x00 5. "rxfris,Unmasked receive FIFO full interrupt state (for compatibility with netx100/500)" "0: receive FIFO is not full,1: receive FIFO is full"
newline
bitfld.long 0x00 4. "rxneris,Unmasked receive FIFO not empty interrupt state (for compatibility with netx100/500)" "0: receive FIFO is empty,1: receive FIFO is not empty"
bitfld.long 0x00 3. "TXRIS,Unmasked transmit FIFO interrupt state" "0: transmit FIFO is equal or higher than,1: transmit FIFO level is below sqi_cr1.tx_fifo_wm"
newline
bitfld.long 0x00 2. "RXRIS,Unmasked receive FIFO interrupt state" "0: receive FIFO is equal or below..,1: receive FIFO is higher than sqi_cr1.rx_fifo_wm"
bitfld.long 0x00 1. "RTRIS,Unmasked receive timeout interrupt state Timeout period is 32 serial clock periods (depending on adr_sqi_cr0.sck_muladd)" "0: receive FIFO is empty or read during the last,1: receive FIFO is not empty and has not been read"
newline
bitfld.long 0x00 0. "RORRIS,Unmasked receive FIFO overrun interrupt state" "0: no receive FIFO overrun error occurred,1: receive FIFO overrun error occurred"
rgroup.long 0x1C++0x03
line.long 0x00 "sqi_irq_masked,SQI masked interrupt status register For detailed IRQ behavior and function see register 'sqi_irq_raw'"
bitfld.long 0x00 8. "sqirom_error,Masked SQIROM error interrupt state" "0,1"
bitfld.long 0x00 7. "trans_end,Masked transfer end interrupt state" "0,1"
newline
bitfld.long 0x00 6. "txemis,Masked transmit FIFO empty interrupt state (for compatibility with netx100/500)" "0,1"
bitfld.long 0x00 5. "rxfmis,Masked receive FIFO full interrupt state (for compatibility with netx100/500)" "0,1"
newline
bitfld.long 0x00 4. "rxnemis,Masked receive FIFO not empty interrupt state (for compatibility with netx100/500)" "0,1"
bitfld.long 0x00 3. "TXMIS,Masked transmit FIFO interrupt state" "0,1"
newline
bitfld.long 0x00 2. "RXMIS,Masked receive FIFO interrupt state" "0,1"
bitfld.long 0x00 1. "RTMIS,Masked receive timeout interrupt state" "0,1"
newline
bitfld.long 0x00 0. "RORMIS,Masked receive FIFO overrun interrupt state" "0,1"
group.long 0x20++0x03
line.long 0x00 "sqi_irq_clear,SQI interrupt clear register (for compatibility with netX10/50 SPI module)"
bitfld.long 0x00 8. "sqirom_error,Clear SQIROM error interrupt" "0,1"
bitfld.long 0x00 7. "trans_end,Clear transfer end interrupt" "0,1"
newline
bitfld.long 0x00 6. "txeic,Clear transmit FIFO empty interrupt (for compatibility with netx100/500)" "0,1"
bitfld.long 0x00 5. "rxfic,Clear receive FIFO full interrupt (for compatibility with netx100/500)" "0,1"
newline
bitfld.long 0x00 4. "rxneic,Clear receive FIFO not empty interrupt (for compatibility with netx100/500)" "0,1"
bitfld.long 0x00 3. "TXIC,Clear transmit FIFO interrupt" "0,1"
newline
bitfld.long 0x00 2. "RXIC,Clear receive FIFO interrupt" "0,1"
bitfld.long 0x00 1. "RTIC,Clear receive timeout interrupt" "0,1"
newline
bitfld.long 0x00 0. "RORIC,Clear receive FIFO overrun interrupt" "0,1"
group.long 0x24++0x03
line.long 0x00 "sqi_dmacr,SQI DMA control register This module generates normal transfer requests only (i.e. no last requests will be issued)"
bitfld.long 0x00 1. "tx_dma_en,Enable DMA for SQI-transmit data A request will be generated if TX-FIFO is not full and sqi_cr1.sqi_en (module enable) is set" "0,1"
bitfld.long 0x00 0. "rx_dma_en,Enable DMA for SQI-receive data A request will be generated if RX-FIFO is not empty and sqi_cr1.sqi_en (module enable) is set" "0,1"
group.long 0x28++0x03
line.long 0x00 "sqi_pio_out,SQI PIO output level control register Bits 'sio_cfg' of register 'sqi_cr0' control the IO PIO mode"
bitfld.long 0x00 7. "sio3,SIO3 output state" "0,1"
bitfld.long 0x00 6. "sio2,SIO2 output state" "0,1"
newline
bitfld.long 0x00 5. "miso,MISO/SIO1 output state" "0,1"
bitfld.long 0x00 4. "mosi,MOSI/SIO0 output state" "0,1"
newline
bitfld.long 0x00 1.--3. "csn,Chip select/FSS output state {CS2 CS1 CS0}" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "sclk,Serial SPI clock output state" "0,1"
group.long 0x30++0x03
line.long 0x00 "sqi_pio_oe,SQI PIO output enable control register Bits 'sio_cfg' of register 'sqi_cr0' control the IO PIO mode"
bitfld.long 0x00 7. "sio3,SIO3 output enable" "0,1"
bitfld.long 0x00 6. "sio2,SIO2 output enable" "0,1"
newline
bitfld.long 0x00 5. "miso,MISO/SIO1 output enable" "0,1"
bitfld.long 0x00 4. "mosi,MOSI/SIO0 output enable" "0,1"
newline
bitfld.long 0x00 1.--3. "csn,Chip select/FSS output enable {CS2 CS1 CS0}" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "sclk,Serial SPI clock output enable" "0,1"
rgroup.long 0x34++0x03
line.long 0x00 "sqi_pio_in,SQI PIO input status register Bits 'sio_cfg' of register 'sqi_cr0' control the IO PIO mode"
bitfld.long 0x00 7. "sio3,SIO3 input state" "0,1"
bitfld.long 0x00 6. "sio2,SIO2 input state" "0,1"
newline
bitfld.long 0x00 5. "miso,MISO/SIO1 input state" "0,1"
bitfld.long 0x00 4. "mosi,MOSI/SIO0 input state" "0,1"
newline
bitfld.long 0x00 1.--3. "csn,Chip select/FSS input state {CS2 CS1 CS0}" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "sclk,Serial SPI clock input state" "0,1"
group.long 0x38++0x03
line.long 0x00 "sqi_sqirom_cfg,SQIROM mode configuration This mode supports the 'eXecute in Place' (XiP) feature of SQI flash chips"
hexmask.long.byte 0x00 24.--31. 1. "clk_div_val,clk400 will be divided by (clk_div_val+3) for sqirom_clk generation"
bitfld.long 0x00 20.--21. "t_csh,Min" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "dummy_cycles,Selects the number of dummy cycles before data will be sampled from the SQI chip" "0: 0 cycles,1: 1 cycle,2: 2 cycles (default),?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles }"
hexmask.long.byte 0x00 8.--15. 1. "cmd_byte,This byte is transferred to the SQI chip as the command sequence"
newline
bitfld.long 0x00 4.--6. "addr_bits,The number of address bits of the access address considered to generate the address for the SQI chip" "0: 20 bits (1-MByte/8-MBit device) (default),1: 21 bits (2-MByte/16-MBit device),2: 22 bits (4-MByte/32-MBit device),3: 23 bits (8-MByte/64-MBit device),4: 24 bits (16-MByte/128-MBit device),5: 25 bits (32-MByte/256-MBit device),6: 26 bits (64-MByte/512-MBit device),7: reserved }"
bitfld.long 0x00 2.--3. "addr_nibbles,The number of nibbles to be transferred as the address to the SQI chip" "0: 5 nibbles,1: 6 nibbles (default),2: 7 nibbles,3: 8 nibbles"
newline
bitfld.long 0x00 1. "addr_before_cmd,Address before command When set to '1' the address nibbles will be transferred before the command byte" "0,1"
bitfld.long 0x00 0. "enable,Enables the SQIROM mode of the SQI module" "0,1"
tree.end
tree "SYSTIME_APP"
base ad:0xFF801600
group.long 0x00++0x03
line.long 0x00 "systime_s,Upper SYSTIME register: To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
hexmask.long 0x00 0.--31. 1. "systime_s,systime high value is incremented if systime_ns reaches systime_border Sample systime_ns at read access to systime_s"
group.long 0x04++0x03
line.long 0x00 "systime_ns,Lower SYSTIME register: To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
hexmask.long 0x00 0.--31. 1. "systime_ns,Systime low: Sample systime_ns at read access to systime_s"
group.long 0x08++0x03
line.long 0x00 "systime_border,SYSTIME border register"
hexmask.long 0x00 0.--31. 1. "systime_border,Systime border for lower systime: systime_ns counts from 0 to this value (inlcuded) i.e"
group.long 0x0C++0x03
line.long 0x00 "systime_count_value,SYSTIME count register"
hexmask.long 0x00 0.--31. 1. "systime_count_value,Each clock cycle (systime_count_value &gt &gt 28) will be added to systime (rate multiplier for IEEE1588)"
tree.end
tree "SYSTIME_LT_APP"
base ad:0xFF801540
rgroup.long 0x00++0x03
line.long 0x00 "intlogic_lt_systime_com_ns,systime_com_ns last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_ns last latched value"
rgroup.long 0x04++0x03
line.long 0x00 "intlogic_lt_systime_com_s,systime_com_s last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_s last latched value"
rgroup.long 0x08++0x03
line.long 0x00 "intlogic_lt_systime_com_uc_ns,systime_com_uc_ns last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_uc_ns last latched value"
rgroup.long 0x0C++0x03
line.long 0x00 "intlogic_lt_systime_com_uc_s,systime_com_uc_s last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_uc_s last latched value"
rgroup.long 0x10++0x03
line.long 0x00 "intlogic_lt_systime_app_ns,systime_app_ns last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_app_ns last latched value"
rgroup.long 0x14++0x03
line.long 0x00 "intlogic_lt_systime_app_s,systime_app_s last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_app_s last latched value"
wgroup.long 0x18++0x03
line.long 0x00 "intlogic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
bitfld.long 0x00 5. "systime_app_s,no field descpription" "0,1"
bitfld.long 0x00 4. "systime_app_ns,no field descpription" "0,1"
bitfld.long 0x00 3. "systime_com_uc_s,no field descpription" "0,1"
bitfld.long 0x00 2. "systime_com_uc_ns,no field descpription" "0,1"
bitfld.long 0x00 1. "systime_com_s,no field descpription" "0,1"
bitfld.long 0x00 0. "systime_com_ns,no field descpription" "0,1"
tree.end
tree "SYSTIME_LT_XPIC_APP"
base ad:0xFF9001C0
rgroup.long 0x00++0x03
line.long 0x00 "intlogic_lt_systime_com_ns,systime_com_ns last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_ns last latched value"
rgroup.long 0x04++0x03
line.long 0x00 "intlogic_lt_systime_com_s,systime_com_s last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_s last latched value"
rgroup.long 0x08++0x03
line.long 0x00 "intlogic_lt_systime_com_uc_ns,systime_com_uc_ns last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_uc_ns last latched value"
rgroup.long 0x0C++0x03
line.long 0x00 "intlogic_lt_systime_com_uc_s,systime_com_uc_s last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_com_uc_s last latched value"
rgroup.long 0x10++0x03
line.long 0x00 "intlogic_lt_systime_app_ns,systime_app_ns last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_app_ns last latched value"
rgroup.long 0x14++0x03
line.long 0x00 "intlogic_lt_systime_app_s,systime_app_s last latched value"
hexmask.long 0x00 0.--31. 1. "val,systime_app_s last latched value"
wgroup.long 0x18++0x03
line.long 0x00 "intlogic_lt_systimes_latch,latch systimes by writing 1'b1 to the assigned bit"
bitfld.long 0x00 5. "systime_app_s,no field descpription" "0,1"
bitfld.long 0x00 4. "systime_app_ns,no field descpription" "0,1"
bitfld.long 0x00 3. "systime_com_uc_s,no field descpription" "0,1"
bitfld.long 0x00 2. "systime_com_uc_ns,no field descpription" "0,1"
bitfld.long 0x00 1. "systime_com_s,no field descpription" "0,1"
bitfld.long 0x00 0. "systime_com_ns,no field descpription" "0,1"
tree.end
tree "TIMER_APP"
base ad:0xFF801580
group.long 0x00++0x03
line.long 0x00 "timer_config_timer0,ARM TIMER Config register0"
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
group.long 0x04++0x03
line.long 0x00 "timer_config_timer1,ARM TIMER Config register1"
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
group.long 0x08++0x03
line.long 0x00 "timer_config_timer2,ARM TIMER Config register2"
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
group.long ($2+0x0C)++0x03
line.long 0x00 "timer_preload_timer$1,ARM TIMER Timer $1"
hexmask.long 0x00 0.--31. 1. "val,preload value"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
group.long ($2+0x18)++0x03
line.long 0x00 "timer_timer$1,ARM TIMER Timer $1"
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
repeat.end
rgroup.long 0x24++0x03
line.long 0x00 "timer_systime_s,ARM_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
rgroup.long 0x28++0x03
line.long 0x00 "timer_systime_ns,ARM_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
group.long 0x2C++0x03
line.long 0x00 "timer_compare_systime_s_value,SYSTIME sec compare value"
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
group.long 0x30++0x03
line.long 0x00 "timer_irq_raw,ARM_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
rgroup.long 0x34++0x03
line.long 0x00 "timer_irq_masked,ARM_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to ARM/xPIC)"
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
group.long 0x38++0x03
line.long 0x00 "timer_irq_msk_set,ARM_TIMER interrupt mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
group.long 0x3C++0x03
line.long 0x00 "timer_irq_msk_reset,ARM_TIMER interrupt mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
group.long 0x40++0x03
line.long 0x00 "timer_systime_config,Select systime for arm_timer_systime_(ns)s functions"
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
tree.end
tree "TIMER_XPIC_APP"
base ad:0xFF900100
group.long 0x00++0x03
line.long 0x00 "timer_config_timer0,ARM TIMER Config register0"
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
bitfld.long 0x00 0.--1. "mode,Timer0" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
group.long 0x04++0x03
line.long 0x00 "timer_config_timer1,ARM TIMER Config register1"
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
bitfld.long 0x00 0.--1. "mode,Timer1" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
group.long 0x08++0x03
line.long 0x00 "timer_config_timer2,ARM TIMER Config register2"
bitfld.long 0x00 2.--3. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
bitfld.long 0x00 0.--1. "mode,Timer2" "0: Timer stops at 0,1: Timer is preload with value from preload,2: Timer (value) compare with systime (once),3: reserved"
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
group.long ($2+0x0C)++0x03
line.long 0x00 "timer_preload_timer$1,ARM TIMER Timer $1"
hexmask.long 0x00 0.--31. 1. "val,preload value"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
group.long ($2+0x18)++0x03
line.long 0x00 "timer_timer$1,ARM TIMER Timer $1"
hexmask.long 0x00 0.--31. 1. "val,actual value of timer / systime compare value"
repeat.end
rgroup.long 0x24++0x03
line.long 0x00 "timer_systime_s,ARM_TIMER upper SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
hexmask.long 0x00 0.--31. 1. "val,Systime high: Sample systime_ns at read access to systime_s"
rgroup.long 0x28++0x03
line.long 0x00 "timer_systime_ns,ARM_TIMER lower SYSTIME register To allow consistent values of systime_s and systime_ns lower bits of systime is latched to systime_ns when systime_s is"
hexmask.long 0x00 0.--31. 1. "val,Systime low: Sample systime_ns at read access to systime_s"
group.long 0x2C++0x03
line.long 0x00 "timer_compare_systime_s_value,SYSTIME sec compare value"
hexmask.long 0x00 0.--31. 1. "val,Compare value with systime_s (seconds): Systime_s_compare_irq is set if systime_s matches"
group.long 0x30++0x03
line.long 0x00 "timer_irq_raw,ARM_TIMER Raw IRQ register: Read access shows status of unmasked IRQs"
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
rgroup.long 0x34++0x03
line.long 0x00 "timer_irq_masked,ARM_TIMER Masked IRQ register: Shows status of masked IRQs (as connected to ARM/xPIC)"
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
group.long 0x38++0x03
line.long 0x00 "timer_irq_msk_set,ARM_TIMER interrupt mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
group.long 0x3C++0x03
line.long 0x00 "timer_irq_msk_reset,ARM_TIMER interrupt mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
bitfld.long 0x00 3. "systime_s_irq,Systime sec Interrupt" "0,1"
bitfld.long 0x00 2. "timer2_irq,Timer 2 Interrupt" "0,1"
bitfld.long 0x00 1. "timer1_irq,Timer 1 Interrupt" "0,1"
bitfld.long 0x00 0. "timer0_irq,Timer 0 Interrupt" "0,1"
group.long 0x40++0x03
line.long 0x00 "timer_systime_config,Select systime for arm_timer_systime_(ns)s functions"
bitfld.long 0x00 0.--1. "systime_config,systime for timer (2'b00.. systime_com 2'b01.. systime_com_uc 2'b10.. systime_app)" "0,1,2,3"
tree.end
tree "TRIGGER_IRQ_APP"
base ad:0xFF801660
group.long 0x00++0x03
line.long 0x00 "trigger_irq_cfg,Trigger IRQ configuration register"
bitfld.long 0x00 0.--1. "xc_trigger_out_polarity,Polarity of xc_trigger_out signals for edge detection" "0: Use pos-edge on xc_trigger_out signals to,1: Use neg-edge on xc_trigger_out signals to,?..."
group.long 0x04++0x03
line.long 0x00 "trigger_irq_raw,Trigger raw IRQ: Read access shows status of unmasked IRQs"
bitfld.long 0x00 0.--1. "xc_trigger_out_edge,Edge detected on xc_trigger_out" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "trigger_irq_masked,Trigger masked IRQ: Shows status of masked IRQs"
bitfld.long 0x00 0.--1. "xc_trigger_out_edge,Edge detected on xc_trigger_out" "0,1,2,3"
group.long 0x0C++0x03
line.long 0x00 "trigger_irq_msk_set,Trigger IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 0.--1. "xc_trigger_out_edge,Edge detected on xc_trigger_out" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "trigger_irq_msk_reset,Trigger IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit"
bitfld.long 0x00 0.--1. "xc_trigger_out_edge,Edge detected on xc_trigger_out" "0,1,2,3"
tree.end
tree "UART_APP"
base ad:0xFF801040
group.long 0x00++0x03
line.long 0x00 "uartdr,data read or written from the interface"
bitfld.long 0x00 10. "BE,Break Error read only mirrored from uartrsr to handle in DMA-read-out data" "0,1"
bitfld.long 0x00 9. "PE,Parity Error read only mirrored from uartrsr to handle in DMA-read-out data" "0,1"
bitfld.long 0x00 8. "FE,Framing Error read only mirrored from uartrsr to handle in DMA-read-out data" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DATA,data read or written from the interface"
group.long 0x04++0x03
line.long 0x00 "uartrsr,receive status register (read) / Error Clear Register (write)"
bitfld.long 0x00 3. "OE,Overrun Error" "0,1"
bitfld.long 0x00 2. "BE,Break Error" "0,1"
bitfld.long 0x00 1. "PE,Parity Error" "0,1"
bitfld.long 0x00 0. "FE,Framing Error" "0,1"
group.long 0x08++0x03
line.long 0x00 "uartlcr_h,Line control Register high byte"
bitfld.long 0x00 5.--6. "WLEN,Word Length 00 5 bits 01 6 bits 10 7 bits 11 8 bits" "0,1,2,3"
bitfld.long 0x00 4. "FEN,FIFO Enable" "0,1"
bitfld.long 0x00 3. "STP2,2 Stop Bits Select" "0,1"
bitfld.long 0x00 2. "EPS,Even Parity Select" "0,1"
bitfld.long 0x00 1. "PEN,Parity Enalble" "0,1"
bitfld.long 0x00 0. "BRK,Send Break" "0,1"
group.long 0x0C++0x03
line.long 0x00 "uartlcr_m,Line control Register middle byte"
hexmask.long.byte 0x00 0.--7. 1. "BAUDDIVMS,bauddiv : Baud Divisor Most Significant Byte use higher byte of bauddiv = (system clk / (16 * baud rate)) - 1 if not alternative settings by register uartcr_2 are done"
group.long 0x10++0x03
line.long 0x00 "uartlcr_l,Line control Register low byte"
hexmask.long.byte 0x00 0.--7. 1. "BAUDDIVLS,Baud Divisor Least Significant Byte use lower byte of bauddiv = (system clk / (16 * baud rate)) - 1 if not alternative settings by register uartcr_2 are done"
group.long 0x14++0x03
line.long 0x00 "uartcr,uart control Register"
bitfld.long 0x00 8. "TX_RX_LOOP,internal loop (TX -&gt RX) (test purpose only)" "0,1"
bitfld.long 0x00 7. "LBE,Loop Back Enable for IrDA mode" "0,1"
bitfld.long 0x00 6. "RTIE,Receive Timeout Interrupt Enable" "0,1"
bitfld.long 0x00 5. "TIE,Transmit Interrupt Enable" "0,1"
bitfld.long 0x00 4. "RIE,Receive Interrupt Enable" "0,1"
bitfld.long 0x00 3. "MSIE,Modem Status Interrupt Enable" "0,1"
bitfld.long 0x00 2. "SIRLP,IrDA SIR Low Power Mode" "0,1"
newline
bitfld.long 0x00 1. "SIREN,SIR Enable" "0,1"
bitfld.long 0x00 0. "uartEN,uart Enable" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "uartfr,uart Flag Register"
bitfld.long 0x00 7. "TXFE,Transmit FIFO Empty" "0,1"
bitfld.long 0x00 6. "RXFF,Receive FIFO Full" "0,1"
bitfld.long 0x00 5. "TXFF,Transmit FIFO Full" "0,1"
bitfld.long 0x00 4. "RXFE,Receive FIFO Empty" "0,1"
bitfld.long 0x00 3. "BUSY,uart BUSY" "0,1"
bitfld.long 0x00 2. "DCD,Data Carrier Detect" "0,1"
bitfld.long 0x00 1. "DSR,Data Set Ready" "0,1"
newline
bitfld.long 0x00 0. "CTS,Clear To Send" "0,1"
group.long 0x1C++0x03
line.long 0x00 "uartiir,Interrupt Identification (read) / interrupt clear (write)"
bitfld.long 0x00 3. "RTIS,Receive Timeout Interrupt Status" "0,1"
bitfld.long 0x00 2. "TIS,Transmit Interrupt Status" "0,1"
bitfld.long 0x00 1. "RIS,Receive Interrupt Status" "0,1"
bitfld.long 0x00 0. "MIS,Modem Interrupt Status" "0,1"
group.long 0x20++0x03
line.long 0x00 "uartilpr,IrDA Low Power Counter Register"
hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,IrDA Low Power Divisor"
group.long 0x24++0x03
line.long 0x00 "uartrts,RTS Control Register"
bitfld.long 0x00 7. "STICK,stick parity" "0,1"
bitfld.long 0x00 6. "CTS_pol,nUARTCTS polarity" "0,1"
bitfld.long 0x00 5. "CTS_ctr,nUARTCTS control" "0,1"
bitfld.long 0x00 4. "RTS_pol,RTS polarity" "0,1"
bitfld.long 0x00 3. "MOD2,mode1/mode2" "0,1"
bitfld.long 0x00 2. "COUNT,count base" "0: time in bauds,1: system clocks"
bitfld.long 0x00 1. "RTS,if AUTO=0: controlled by this bit" "0,1"
newline
bitfld.long 0x00 0. "AUTO,automatic or controlled by the next bit (RTS)" "0,1"
group.long 0x28++0x03
line.long 0x00 "uartforerun,RTS forerun cycles"
hexmask.long.byte 0x00 0.--7. 1. "FORERUN,number of forerun cycles in system clocks or bauds"
group.long 0x2C++0x03
line.long 0x00 "uarttrail,RTS trail cycles"
hexmask.long.byte 0x00 0.--7. 1. "TRAIL,number of trail cycles in system clocks or bauds"
group.long 0x30++0x03
line.long 0x00 "uartdrvout,Drive Output"
bitfld.long 0x00 1. "DRVRTS,enable driver for RTS" "0,1"
bitfld.long 0x00 0. "DRVTX,enable driver for TX" "0,1"
group.long 0x34++0x03
line.long 0x00 "uartcr_2,Control Register 2"
bitfld.long 0x00 0. "Baud_Rate_Mode,If this bit is set the baud rate is generated more exactly by the following formula: value = ( (Baud Rate * 16) / System Frequency ) * 2^16" "0,1"
group.long 0x38++0x03
line.long 0x00 "uartrxiflsel,RX FIFO trigger level and RX-DMA enable"
bitfld.long 0x00 5. "RXDMA,Enable DMA-requests for RX-fifo-data" "0,1"
bitfld.long 0x00 0.--4. "RXIFLSEL,Choose a number between 1 and 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "uarttxiflsel,TX FIFO trigger level and TX-DMA enable"
bitfld.long 0x00 5. "TXDMA,Enable DMA-requests for TX-fifo-data" "0,1"
bitfld.long 0x00 0.--4. "TXIFLSEL,Choose a number between 1 and 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "UART_XPIC_APP"
base ad:0xFF900300
group.long 0x00++0x03
line.long 0x00 "uartdr,data read or written from the interface"
bitfld.long 0x00 10. "BE,Break Error read only mirrored from uartrsr to handle in DMA-read-out data" "0,1"
bitfld.long 0x00 9. "PE,Parity Error read only mirrored from uartrsr to handle in DMA-read-out data" "0,1"
bitfld.long 0x00 8. "FE,Framing Error read only mirrored from uartrsr to handle in DMA-read-out data" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DATA,data read or written from the interface"
group.long 0x04++0x03
line.long 0x00 "uartrsr,receive status register (read) / Error Clear Register (write)"
bitfld.long 0x00 3. "OE,Overrun Error" "0,1"
bitfld.long 0x00 2. "BE,Break Error" "0,1"
bitfld.long 0x00 1. "PE,Parity Error" "0,1"
bitfld.long 0x00 0. "FE,Framing Error" "0,1"
group.long 0x08++0x03
line.long 0x00 "uartlcr_h,Line control Register high byte"
bitfld.long 0x00 5.--6. "WLEN,Word Length 00 5 bits 01 6 bits 10 7 bits 11 8 bits" "0,1,2,3"
bitfld.long 0x00 4. "FEN,FIFO Enable" "0,1"
bitfld.long 0x00 3. "STP2,2 Stop Bits Select" "0,1"
bitfld.long 0x00 2. "EPS,Even Parity Select" "0,1"
bitfld.long 0x00 1. "PEN,Parity Enalble" "0,1"
bitfld.long 0x00 0. "BRK,Send Break" "0,1"
group.long 0x0C++0x03
line.long 0x00 "uartlcr_m,Line control Register middle byte"
hexmask.long.byte 0x00 0.--7. 1. "BAUDDIVMS,bauddiv : Baud Divisor Most Significant Byte use higher byte of bauddiv = (system clk / (16 * baud rate)) - 1 if not alternative settings by register uartcr_2 are done"
group.long 0x10++0x03
line.long 0x00 "uartlcr_l,Line control Register low byte"
hexmask.long.byte 0x00 0.--7. 1. "BAUDDIVLS,Baud Divisor Least Significant Byte use lower byte of bauddiv = (system clk / (16 * baud rate)) - 1 if not alternative settings by register uartcr_2 are done"
group.long 0x14++0x03
line.long 0x00 "uartcr,uart control Register"
bitfld.long 0x00 8. "TX_RX_LOOP,internal loop (TX -&gt RX) (test purpose only)" "0,1"
bitfld.long 0x00 7. "LBE,Loop Back Enable for IrDA mode" "0,1"
bitfld.long 0x00 6. "RTIE,Receive Timeout Interrupt Enable" "0,1"
bitfld.long 0x00 5. "TIE,Transmit Interrupt Enable" "0,1"
bitfld.long 0x00 4. "RIE,Receive Interrupt Enable" "0,1"
bitfld.long 0x00 3. "MSIE,Modem Status Interrupt Enable" "0,1"
bitfld.long 0x00 2. "SIRLP,IrDA SIR Low Power Mode" "0,1"
newline
bitfld.long 0x00 1. "SIREN,SIR Enable" "0,1"
bitfld.long 0x00 0. "uartEN,uart Enable" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "uartfr,uart Flag Register"
bitfld.long 0x00 7. "TXFE,Transmit FIFO Empty" "0,1"
bitfld.long 0x00 6. "RXFF,Receive FIFO Full" "0,1"
bitfld.long 0x00 5. "TXFF,Transmit FIFO Full" "0,1"
bitfld.long 0x00 4. "RXFE,Receive FIFO Empty" "0,1"
bitfld.long 0x00 3. "BUSY,uart BUSY" "0,1"
bitfld.long 0x00 2. "DCD,Data Carrier Detect" "0,1"
bitfld.long 0x00 1. "DSR,Data Set Ready" "0,1"
newline
bitfld.long 0x00 0. "CTS,Clear To Send" "0,1"
group.long 0x1C++0x03
line.long 0x00 "uartiir,Interrupt Identification (read) / interrupt clear (write)"
bitfld.long 0x00 3. "RTIS,Receive Timeout Interrupt Status" "0,1"
bitfld.long 0x00 2. "TIS,Transmit Interrupt Status" "0,1"
bitfld.long 0x00 1. "RIS,Receive Interrupt Status" "0,1"
bitfld.long 0x00 0. "MIS,Modem Interrupt Status" "0,1"
group.long 0x20++0x03
line.long 0x00 "uartilpr,IrDA Low Power Counter Register"
hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,IrDA Low Power Divisor"
group.long 0x24++0x03
line.long 0x00 "uartrts,RTS Control Register"
bitfld.long 0x00 7. "STICK,stick parity" "0,1"
bitfld.long 0x00 6. "CTS_pol,nUARTCTS polarity" "0,1"
bitfld.long 0x00 5. "CTS_ctr,nUARTCTS control" "0,1"
bitfld.long 0x00 4. "RTS_pol,RTS polarity" "0,1"
bitfld.long 0x00 3. "MOD2,mode1/mode2" "0,1"
bitfld.long 0x00 2. "COUNT,count base" "0: time in bauds,1: system clocks"
bitfld.long 0x00 1. "RTS,if AUTO=0: controlled by this bit" "0,1"
newline
bitfld.long 0x00 0. "AUTO,automatic or controlled by the next bit (RTS)" "0,1"
group.long 0x28++0x03
line.long 0x00 "uartforerun,RTS forerun cycles"
hexmask.long.byte 0x00 0.--7. 1. "FORERUN,number of forerun cycles in system clocks or bauds"
group.long 0x2C++0x03
line.long 0x00 "uarttrail,RTS trail cycles"
hexmask.long.byte 0x00 0.--7. 1. "TRAIL,number of trail cycles in system clocks or bauds"
group.long 0x30++0x03
line.long 0x00 "uartdrvout,Drive Output"
bitfld.long 0x00 1. "DRVRTS,enable driver for RTS" "0,1"
bitfld.long 0x00 0. "DRVTX,enable driver for TX" "0,1"
group.long 0x34++0x03
line.long 0x00 "uartcr_2,Control Register 2"
bitfld.long 0x00 0. "Baud_Rate_Mode,If this bit is set the baud rate is generated more exactly by the following formula: value = ( (Baud Rate * 16) / System Frequency ) * 2^16" "0,1"
group.long 0x38++0x03
line.long 0x00 "uartrxiflsel,RX FIFO trigger level and RX-DMA enable"
bitfld.long 0x00 5. "RXDMA,Enable DMA-requests for RX-fifo-data" "0,1"
bitfld.long 0x00 0.--4. "RXIFLSEL,Choose a number between 1 and 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "uarttxiflsel,TX FIFO trigger level and TX-DMA enable"
bitfld.long 0x00 5. "TXDMA,Enable DMA-requests for TX-fifo-data" "0,1"
bitfld.long 0x00 0.--4. "TXIFLSEL,Choose a number between 1 and 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "VIC_XPIC_APP"
base ad:0xFF900000
group.long 0x00++0x03
line.long 0x00 "xpic_vic_config,XPIC VIC Configuration register"
bitfld.long 0x00 1. "table,use far or near Table" "0: Base Pointer Addr for IRQ Jmp Table + (n*4),1: Base Pointer Addr for IRQ Jmp Table + (n*16) 4"
bitfld.long 0x00 0. "enable,global enable of xPIC VIC (0: disable/ 1: enable)" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "xpic_vic_raw_intr0,XPIC VIC Raw0 interrupt status register see netx4000_irq doc"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
rgroup.long 0x08++0x03
line.long 0x00 "xpic_vic_raw_intr1,XPIC VIC Raw1 interrupt status register see netx4000_irq doc"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
rgroup.long 0x0C++0x03
line.long 0x00 "xpic_vic_raw_intr2,XPIC VIC Raw2 interrupt status register see netx4000_irq doc"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x10++0x03
line.long 0x00 "xpic_vic_softint0_set,XPIC VIC Software0 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x14++0x03
line.long 0x00 "xpic_vic_softint1_set,XPIC VIC Software1 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x18++0x03
line.long 0x00 "xpic_vic_softint2_set,XPIC VIC Software2 interrupt set register: Read status or set IRQ by writing '1' to the appropriate bit"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x1C++0x03
line.long 0x00 "xpic_vic_softint0_reset,XPIC VIC Software0 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x20++0x03
line.long 0x00 "xpic_vic_softint1_reset,XPIC VIC Software1 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x24++0x03
line.long 0x00 "xpic_vic_softint2_reset,XPIC VIC Software2 interrupt reset register: Read status or reset IRQ by writing '1' to the appropriate bit"
hexmask.long 0x00 0.--31. 1. "irqs,see netx doc"
group.long 0x28++0x03
line.long 0x00 "xpic_vic_fiq_addr,XPIC VIC FIQ Vector address 0 register"
hexmask.long 0x00 0.--31. 1. "val,FIQ handler address"
group.long 0x2C++0x03
line.long 0x00 "xpic_vic_irq_addr,XPIC VIC normal IRQ address register"
hexmask.long 0x00 0.--31. 1. "val,IRQ handler address"
rgroup.long 0x30++0x03
line.long 0x00 "xpic_vic_vector_addr,XPIC VIC IRQ Vector address"
hexmask.long 0x00 0.--31. 1. "val,IRQ vector address read access get actuel highest prior IRQ read access get adr_xpic_vic_table_base_addr + IRQ Number * (4/16)"
group.long 0x34++0x03
line.long 0x00 "xpic_vic_table_base_addr,XPIC VIC IRQ TABLE ADDRESS BASE POINTER"
hexmask.long 0x00 0.--31. 1. "val,IRQ Table base address the Base Pointer Addr for IRQ Jmp Table"
group.long 0x38++0x03
line.long 0x00 "xpic_vic_fiq_vect_config,no Register description"
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
bitfld.long 0x00 30. "select_fiq_default," "0,1"
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
group.long 0x3C++0x03
line.long 0x00 "xpic_vic_vect_config0,highest priority"
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
repeat 14. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
group.long ($2+0x40)++0x03
line.long 0x00 "xpic_vic_vect_config$1,no Register description"
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "int_source,INT_SOURCE 0-95"
repeat.end
group.long 0x78++0x03
line.long 0x00 "xpic_vic_vect_config15,XPIC default interrupt vector all interrupt sources (wired-OR) select with default interrupt vector register lowest priority"
bitfld.long 0x00 31. "enable,vector interrupt enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "xpic_vic_default0,XPIC default interrupt vector select0"
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
group.long 0x80++0x03
line.long 0x00 "xpic_vic_default1,XPIC default interrupt vector select1"
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
group.long 0x84++0x03
line.long 0x00 "xpic_vic_default2,XPIC default interrupt vector select1"
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
group.long 0x88++0x03
line.long 0x00 "xpic_vic_fiq_default0,XPIC default interrupt vector select0 for fiq"
hexmask.long 0x00 0.--31. 1. "val,select int0 - int31 (wired-OR) 1-selected 0-not selected"
group.long 0x8C++0x03
line.long 0x00 "xpic_vic_fiq_default1,XPIC default interrupt vector select1 for fiq"
hexmask.long 0x00 0.--31. 1. "val,select int32 - int63 (wired-OR) 1-selected 0-not selected"
group.long 0x90++0x03
line.long 0x00 "xpic_vic_fiq_default2,XPIC default interrupt vector select1 for fiq"
hexmask.long 0x00 0.--31. 1. "val,select int64 - int95 (wired-OR) 1-selected 0-not selected"
tree.end
tree "WDG_APP"
base ad:0xFF801640
group.long 0x00++0x03
line.long 0x00 "netx_sys_wdg_ctrl,netX System Watchdog Trigger Register"
bitfld.long 0x00 31. "write_enable,Write enable bit for timeout register: As long as this bit is not set all write accesses to the timeout register are ignored" "0,1"
bitfld.long 0x00 28. "wdg_counter_trigger_w,Watchdog trigger bit: Bit must be set to trigger the watchdog counter" "0,1"
bitfld.long 0x00 24. "irq_req_watchdog,IRQ request of watchdog writing 1 deletes IRQ" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "wdg_access_code,Watchdog trigger and control register access code"
rgroup.long 0x04++0x03
line.long 0x00 "netx_sys_wdg,netX System Watchdog Register The counter value is decremented each 10000 system clock cycles"
hexmask.long.tbyte 0x00 0.--16. 1. "wdg_counter,Actual watchdog counter value"
group.long 0x08++0x03
line.long 0x00 "netx_sys_wdg_irq_timeout,netX System Wachtdog Interrupt Timout Register"
hexmask.long.word 0x00 0.--15. 1. "wdg_irq_timeout,Watchdog interrupt timeout The total netx_sys_irq timeout for a netX clock of 100MHz is: wdg_irq_timeout * 100us Note: The watchdog can be stopped by programming a 0"
group.long 0x0C++0x03
line.long 0x00 "netx_sys_wdg_res_timeout,netX System Watchdog Reset Timeout Register"
hexmask.long.word 0x00 0.--15. 1. "wdg_res_timeout,Watchdog reset request timeout The total reset timeout for a netX clock of 100MHz is: (wdg_irq_timeout + wdg_res_timeout) * 100us Note: The watchdog can be stopped by programming a 0"
group.long 0x10++0x03
line.long 0x00 "netx_sys_wdg_irq_raw,netX System Wachtdog IRQ raw register: Read access shows status of unmasked IRQs"
bitfld.long 0x00 0. "wdg_res_irq,Watchdog reset request timeout interrupt" "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "netx_sys_wdg_irq_masked,netX System Wachtdog Masked IRQ register: Read access shows status of masked IRQs"
bitfld.long 0x00 0. "wdg_res_irq,Watchdog reset request timeout interrupt" "0,1"
group.long 0x18++0x03
line.long 0x00 "netx_sys_wdg_irq_msk_set,netX System Wachtdog interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 0. "wdg_res_irq,Watchdog reset request timeout interrupt" "0,1"
group.long 0x1C++0x03
line.long 0x00 "netx_sys_wdg_irq_msk_reset,netX System Wachtdog interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request.."
bitfld.long 0x00 0. "wdg_res_irq,Watchdog reset request timeout interrupt" "0,1"
tree.end
tree "WDG_XPIC_APP"
base ad:0xFF900180
group.long 0x00++0x03
line.long 0x00 "xpic_wdg_trig,netX xPIC Watchdog Trigger Register"
bitfld.long 0x00 31. "write_enable,Write enable bit for timeout register: As long as this bit is not set all write accesses to the timeout register are ignored" "0,1"
bitfld.long 0x00 28. "wdg_counter_trigger_w,Watchdog trigger bit: Bit must be set to trigger the watchdog counter" "0,1"
bitfld.long 0x00 24. "irq_req_watchdog,xPIC IRQ request of watchdog writing 1 deletes IRQ to xPIC" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "wdg_access_code,Watchdog access code for triggering"
rgroup.long 0x04++0x03
line.long 0x00 "xpic_wdg_counter,netX xPIC Watchdog Counter Register The counter value is decremented each 10000 system clock cycles"
abitfld.long 0x00 0.--16. "val,Actual watchdog counter value: Bit 16 shows" "0x00000=0: Watchdog is counting down from..,0x00001=1: Watchdog is counting down from.."
group.long 0x08++0x03
line.long 0x00 "xpic_wdg_xpic_irq_timeout,netX xPIC Watchdog xPIC interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog interrupt timeout The total xpic_irq timeout for a netX clock of 100MHz is: xpic_wdg_xpic_irq_timeout * 100us"
group.long 0x0C++0x03
line.long 0x00 "xpic_wdg_arm_irq_timeout,netX xPIC Watchdog ARM interrupt timout register: xpic_irq_timeout or arm_irq_timeout must be nonzero to enable watchdog"
hexmask.long.word 0x00 0.--15. 1. "val,Watchdog ARM interrupt timeout The total arm_irq timeout for a netX clock of 100MHz is: (xpic_wdg_xpic_irq_timeout + xpic_wdg_arm_irq_timeout) * 100us"
group.long 0x10++0x03
line.long 0x00 "xpic_wdg_irq_raw,Read access shows status of unmasked IRQs"
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "xpic_wdg_irq_masked,xpic_wdg Masked IRQ register: Shows status of masked IRQs (as connected to xPIC)"
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
group.long 0x18++0x03
line.long 0x00 "xpic_wdg_irq_msk_set,xpic_wdg interrupt mask enable: The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
group.long 0x1C++0x03
line.long 0x00 "xpic_wdg_irq_msk_reset,xpic_wdg interrupt mask disable: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding.."
bitfld.long 0x00 0. "wdg_arm_irq,Interrupt from xPIC Watchdog to ARM" "0,1"
tree.end
tree "XLINK"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0xFF900400 ad:0xFF900410 ad:0xFF900420 ad:0xFF900430 ad:0xFF900440 ad:0xFF900450 ad:0xFF900460 ad:0xFF900470)
tree "XLINK$1"
base $2
group.long 0x00++0x03
line.long 0x00 "xlink_cfg,configuration register"
bitfld.long 0x00 28.--31. "end_spl,end sample point for receive data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "start_spl,start sample point for receive data a sample period is defined as 1/16 of the bitrate period range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "bits2rec,count of bits to receive note: the reset value expect: 1stopbit 8databits 1paritybit and 1stopbit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19. "cnt_da,test feature do not set this bit!" "0,1"
bitfld.long 0x00 18. "bclk2oe_en,test feature do not set this bit!" "0,1"
bitfld.long 0x00 17. "fb_en,test feature enable internal feedback" "0,1"
newline
bitfld.long 0x00 16. "xlink_en,disable the output enable and activity" "0,1"
hexmask.long.word 0x00 0.--15. 1. "rate_inc,bitrate compare value for bit clock counter (bit_cnt) BITRATE = 100e6/(rate_inc) typical settings for IOLINK: {| cols=4 BIT_RATE | rate_inc | clock period | calc: 1/BIT_RATE 4800 | 0x5160 | 208 33 us | 208 3333us 38400 | 0xa2b | 26 04 us | 26.."
group.long 0x04++0x03
line.long 0x00 "xlink_tx,xlink transmit register"
bitfld.long 0x00 17. "idle_ro,indicates no activity on tx" "0,1"
bitfld.long 0x00 16. "rdy_ro,TX buffer ready (valid on ready) 0 TX buffer not ready 1 TX buffer ready" "0,1"
hexmask.long.word 0x00 0.--15. 1. "hold,hold register format for a valid serial DATA sequence: &lt -ctrl.DATA-&gt &lt ------------------- serial DATA --------------------&gt { END_BIT:1 }[{STOPBIT:1}{DATABITS max. 12:0101..0010}{STARTBIT:0}] notes: ENDBIT is a hardware marker to stop the.."
group.long 0x08++0x03
line.long 0x00 "xlink_rx,xlink RX register writing to the register reset the ready bit the overflow bit and the sampling error bit"
bitfld.long 0x00 21. "spl_err_ro,sampling error detected if the amount of sampled bits (HI or LOW) do not fulfill the condition: (end_spl - start_spl) &lt (count of HI/LOW bits)" "0,1"
bitfld.long 0x00 20. "ovf_err_ro,overflow error on received data" "0,1"
bitfld.long 0x00 19. "rxd_ro,current status of rx data" "0,1"
bitfld.long 0x00 16. "rdy_ro,RX buffer ready (valid on ready) 0 RX buffer not ready 1 RX buffer ready" "0,1"
hexmask.long.word 0x00 0.--15. 1. "hold_ro,RX byte (when valid) hold[15:0] is used to shift in RX(LSB first!) the amount of shifted bits is defined by bits2rec shift order is bit15 downto bit0"
group.long 0x0C++0x03
line.long 0x00 "xlink_stat,xlink status register & io control writing to this register set the bit clock counter to zero!"
bitfld.long 0x00 24. "filter_en,enable 3 majority ruling filter" "0,1"
bitfld.long 0x00 23. "set_wakeup,set the wakeup port" "0,1"
bitfld.long 0x00 22. "set_txoe,set the tx output enable" "0,1"
bitfld.long 0x00 21. "set_tx,set the tx port" "0,1"
bitfld.long 0x00 20. "io_mode,enable the io mode on tx and wakeup" "0: disable io function on tx txoe wakeup,1: enable io function on tx txoe wakeup"
bitfld.long 0x00 19. "txoe_ro,status of tx output enable" "0,1"
newline
bitfld.long 0x00 18. "rxo_ro,status of rx input" "0,1"
bitfld.long 0x00 17. "txo_ro,status of tx output" "0,1"
bitfld.long 0x00 16. "bit_clk_ro,status of bit clock signal" "0,1"
hexmask.long.word 0x00 0.--15. 1. "bit_cnt_ro,status of bit clock counter"
tree.end
repeat.end
tree.end
tree "XPIC_APP_DEBUG"
base ad:0xFF884080
group.long 0x00++0x03
line.long 0x00 "xpic_hold_pc,no Register description"
bitfld.long 0x00 7. "reset_xpic,REQUEST reset all internal internal states and the pipeline EXCEPT: the internal register (r0-r7 usr0-4) bank0 and bank1 reset this registers manually EXCEPT: xpic hard_breaker/debug registers" "0,1"
bitfld.long 0x00 6. "bank_control,control over the register bank selection WARNING: reset this BIT to 0 BEFORE start xPIC (clear hold bits)" "0,1"
bitfld.long 0x00 5. "bank_select,Select register bank (0: default bank 1: fiq bank) Access registers in xpic_regs area (xpic_r0 .. xpic_r7 xpic_stat)" "0,1"
bitfld.long 0x00 4. "misalignment_hold," "0,1"
bitfld.long 0x00 3. "disable_int,disable interrupts" "0,1"
newline
bitfld.long 0x00 2. "monitor_mode," "0,1"
bitfld.long 0x00 1. "single_step," "0,1"
bitfld.long 0x00 0. "hold," "0,1"
group.long 0x04++0x03
line.long 0x00 "xpic_break0_addr,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address value"
group.long 0x08++0x03
line.long 0x00 "xpic_break0_addr_mask,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 address mask"
group.long 0x0C++0x03
line.long 0x00 "xpic_break0_data,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data value (for data access only)"
group.long 0x10++0x03
line.long 0x00 "xpic_break0_data_mask,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 0 data mask (for data access only)"
group.long 0x14++0x03
line.long 0x00 "xpic_break0_contr,no Register description"
bitfld.long 0x00 8. "enable,Breakpoint 0" "0,1"
bitfld.long 0x00 7. "range,Breakpoint 0 input from Breakpoint 1" "0,1"
bitfld.long 0x00 6. "chain,Breakpoint 0 input from Breakpoint 1" "0,1"
bitfld.long 0x00 5. "irq_mode,Breakpoint 0 xPIC in IRQ Mode" "0,1"
bitfld.long 0x00 4. "fiq_mode,Breakpoint 0 xPIC in FIQ Mode" "0,1"
newline
bitfld.long 0x00 3. "data_access,Breakpoint 0 (1: data access 0: instruction fetch)" "0,1"
bitfld.long 0x00 1.--2. "mas,Breakpoint 0 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
bitfld.long 0x00 0. "write,Breakpoint 0 write/read access" "0,1"
group.long 0x18++0x03
line.long 0x00 "xpic_break0_contr_mask,no Register description"
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 0 control mask"
group.long 0x1C++0x03
line.long 0x00 "xpic_break1_addr,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address value"
group.long 0x20++0x03
line.long 0x00 "xpic_break1_addr_mask,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 address mask"
group.long 0x24++0x03
line.long 0x00 "xpic_break1_data,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data value (for data access only)"
group.long 0x28++0x03
line.long 0x00 "xpic_break1_data_mask,no Register description"
hexmask.long 0x00 0.--31. 1. "val,Breakpoint 1 data mask (for data access only)"
group.long 0x2C++0x03
line.long 0x00 "xpic_break1_contr,no Register description"
bitfld.long 0x00 8. "enable,Breakpoint 1" "0,1"
bitfld.long 0x00 7. "range,reserved" "0,1"
bitfld.long 0x00 6. "chain,reserved" "0,1"
bitfld.long 0x00 5. "irq_mode,Breakpoint 1 xPIC in IRQ Mode" "0,1"
bitfld.long 0x00 4. "fiq_mode,Breakpoint 1 xPIC in FIQ Mode" "0,1"
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bitfld.long 0x00 3. "data_access,Breakpoint 1 (1: data access 0: instruction fetch)" "0,1"
bitfld.long 0x00 1.--2. "mas,Breakpoint 1 memory access size (00: byte. 01: word 10 dword 11 reserved)" "0,1,2,3"
bitfld.long 0x00 0. "write,Breakpoint 1 write/read access" "0,1"
group.long 0x30++0x03
line.long 0x00 "xpic_break1_contr_mask,no Register description"
hexmask.long.byte 0x00 0.--7. 1. "val,Breakpoint 1 control mask"
rgroup.long 0x34++0x03
line.long 0x00 "xpic_break_last_pc,no Register description"
hexmask.long 0x00 0.--31. 1. "val,last PC"
rgroup.long 0x38++0x03
line.long 0x00 "xpic_break_status,Read access shows the reason why xPIC is in HOLD / BREAK"
bitfld.long 0x00 9. "xpic_reset_status," "0,1"
bitfld.long 0x00 8. "break1_read_data,Breakpoint 1 last load access (read only)" "0,1"
bitfld.long 0x00 7. "break0_read_data,Breakpoint 0 last load access (read only)" "0,1"
bitfld.long 0x00 6. "data_misalignment,Data Misaligment is active(read only)" "0,1"
bitfld.long 0x00 5. "single_step,Single Step Break is active(read only)" "0,1"
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bitfld.long 0x00 4. "soft_break,Software Break is active(read only)" "0,1"
bitfld.long 0x00 3. "break1,Breakpoint 1 is active(read only)" "0,1"
bitfld.long 0x00 2. "break0,Breakpoint 0 is active(read only)" "0,1"
bitfld.long 0x00 1. "hold,global HOLD BIT status 0- start xPIC 1- hold xPIC (read only)" "0,1"
bitfld.long 0x00 0. "xpic_in_hold,xPIC is in Break or Hold (read only)" "0,1"
group.long 0x3C++0x03
line.long 0x00 "xpic_break_irq_raw,xPIC_DEBUG Raw IRQ register: Read access shows status of unmasked IRQs"
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "xpic_break_irq_masked,xPIC_DEBUG Masked IRQ register for other CPU (ARM): Shows status of masked IRQs (as connected to ARM)"
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
group.long 0x44++0x03
line.long 0x00 "xpic_break_irq_msk_set,xPIC_DEBUG interrupt mask set for other CPU (ARM): The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
group.long 0x48++0x03
line.long 0x00 "xpic_break_irq_msk_reset,xPIC_DEBUG interrupt mask reset for other CPU (ARM): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
bitfld.long 0x00 4. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
bitfld.long 0x00 3. "single_step_irq,single step Breakpoint Interrupt" "0,1"
bitfld.long 0x00 2. "soft_break_irq,Software Breakpoint Interrupt" "0,1"
bitfld.long 0x00 1. "break1_irq,Breakpoint 1 Interrupt" "0,1"
bitfld.long 0x00 0. "break0_irq,Breakpoint 0 Interrupt" "0,1"
rgroup.long 0x4C++0x03
line.long 0x00 "xpic_break_own_irq_masked,xPIC_DEBUG own Masked IRQ register (for xPIC): Shows status of masked IRQs (as connected to xPIC)"
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
group.long 0x50++0x03
line.long 0x00 "xpic_break_own_irq_msk_set,xPIC_DEBUG own interrupt mask set (for xPIC): The IRQ mask enables interrupt requests for corresponding interrupt sources"
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
group.long 0x54++0x03
line.long 0x00 "xpic_break_own_irq_msk_reset,xPIC_DEBUG own interrupt mask reset (for XPIC): This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit (disables interrupt.."
bitfld.long 0x00 0. "misalignment_irq,Data Misalignment Error Interrupt" "0,1"
rgroup.long 0x58++0x03
line.long 0x00 "xpic_break_return_fiq_pc,xPIC_DEBUG information FIQ return PC value valid if xPIC is in FIQ"
hexmask.long 0x00 0.--31. 1. "val,xPIC FIQ return value"
rgroup.long 0x5C++0x03
line.long 0x00 "xpic_break_return_irq_pc,xPIC_DEBUG information last IRQ return PC value valid if xPIC is in IRQ"
hexmask.long 0x00 0.--31. 1. "val,xPIC last IRQ return value"
rgroup.long 0x60++0x03
line.long 0x00 "xpic_irq_status,Read access shows the xpic irq status and the xpic irq enable bits"
bitfld.long 0x00 3. "fiq_enable,FIQ enable bit" "0,1"
bitfld.long 0x00 2. "irq_enable,IRQ enable bit" "0,1"
bitfld.long 0x00 1. "fiq_status,FIQ status" "0,1"
bitfld.long 0x00 0. "irq_status,IRQ status" "0,1"
tree.end
tree "XPIC_APP_REGS"
base ad:0xFF884000
group.long 0x00++0x03
line.long 0x00 "xpic_r0,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r0,Work Register 0"
group.long 0x04++0x03
line.long 0x00 "xpic_r1,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r1,Work Register 1"
group.long 0x08++0x03
line.long 0x00 "xpic_r2,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r2,Work Register 2"
group.long 0x0C++0x03
line.long 0x00 "xpic_r3,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r3,Work Register 3"
group.long 0x10++0x03
line.long 0x00 "xpic_r4,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r4,Work Register 4"
group.long 0x14++0x03
line.long 0x00 "xpic_r5,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r5,Work Register 5"
group.long 0x18++0x03
line.long 0x00 "xpic_r6,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r6,Work Register 6"
group.long 0x1C++0x03
line.long 0x00 "xpic_r7,xPIC work register for indirect addressing"
hexmask.long 0x00 0.--31. 1. "r7,Work Register 7"
group.long 0x20++0x03
line.long 0x00 "xpic_usr0,xPIC user Register additional work register"
hexmask.long 0x00 0.--31. 1. "usr0,User Register 0"
group.long 0x24++0x03
line.long 0x00 "xpic_usr1,xPIC user Register additional work register"
hexmask.long 0x00 0.--31. 1. "usr1,User Register 1"
group.long 0x28++0x03
line.long 0x00 "xpic_usr2,xPIC user Register additional work register"
hexmask.long 0x00 0.--31. 1. "usr2,User Register 2"
group.long 0x2C++0x03
line.long 0x00 "xpic_usr3,xPIC user Register additional work register"
hexmask.long 0x00 0.--31. 1. "usr3,User Register 3"
group.long 0x30++0x03
line.long 0x00 "xpic_usr4,xPIC user Register additional work register"
hexmask.long 0x00 0.--31. 1. "usr4,User Register 4"
group.long 0x34++0x03
line.long 0x00 "xpic_pc,xPIC Program Counter Shared in xPIC 64_BIT_MUL_TARGET mode with usr32 (w mode)"
hexmask.long 0x00 0.--31. 1. "pc,Program Counter (dword address inside DPRAM)"
group.long 0x38++0x03
line.long 0x00 "xpic_stat,Processor Status Register"
hexmask.long 0x00 0.--31. 1. "stat,no field descpription"
group.long 0x3C++0x03
line.long 0x00 "xpic_zero,Zero Register Shared in xPIC 64_BIT_MUL_TARGET mode with usr10 (w mode)"
hexmask.long 0x00 0.--31. 1. "zero,Always Zero"
tree.end
autoindent.off
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