; -------------------------------------------------------------------------------- ; @Title: NANO103 On-Chip Peripherals ; @Props: Released ; @Author: NEJ, KRZ ; @Changelog: 2023-09-07 NEJ ; 2023-11-09 KRZ ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: Generated (TRACE32, build: 164352.), based on: ; NANO103AE_v1.svd (Ver. 1.0) ; @Core: Cortex-M0 ; @Chip: NANO103LD3AE, NANO103SD3AE, NANO103ZD3AE ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pernano103.per 16971 2023-11-09 16:09:22Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ACMP0 (Analog Comparator Controller)" base ad:0x401D0000 group.long 0x0++0xB line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register" bitfld.long 0x0 31. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x0 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),?,?" newline bitfld.long 0x0 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 0 hysteresis Disabled,1: Comparator 0 hysteresis Enabled" bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled. If WKEN.." newline bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled" line.long 0x4 "ACMP_STATUS,Analog Comparator Status Register" bitfld.long 0x4 1. "ACMPO,ComparatorOutput\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.\nNote: This bit is read only." "0,1" bitfld.long 0x4 0. "ACMPIF,ComparatorInterrupt Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1\nNote: Write '1' to clear this bit to 0." "0,1" line.long 0x8 "ACMP_VREF,Analog Comparator Reference Voltage Control Register" bitfld.long 0x8 5. "CRVSSEL,CRV Source Voltage Selection" "0: VDDA is selected as CRV source voltage,1: The reference voltage defined by SYS_VREFCTL.." bitfld.long 0x8 4. "CRVEN,CRV Enable Bit" "0: CRV Disabled,1: CRV Enabled" newline hexmask.long.byte 0x8 0.--3. 1. "CRVCTL,Comparator Reference Voltage Setting" tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x400E0000 rgroup.long 0x0++0x1F line.long 0x0 "ADC_DAT0,A/D Data Register 0" bitfld.long 0x0 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x0 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x0 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x4 "ADC_DAT1,A/D Data Register 1" bitfld.long 0x4 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x4 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x4 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x8 "ADC_DAT2,A/D Data Register 2" bitfld.long 0x8 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x8 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x8 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0xC "ADC_DAT3,A/D Data Register 3" bitfld.long 0xC 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0xC 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0xC 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x10 "ADC_DAT4,A/D Data Register 4" bitfld.long 0x10 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x10 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x10 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x14 "ADC_DAT5,A/D Data Register 5" bitfld.long 0x14 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x14 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x14 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x18 "ADC_DAT6,A/D Data Register 6" bitfld.long 0x18 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x18 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x18 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x1C "ADC_DAT7,A/D Data Register 7" bitfld.long 0x1C 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x1C 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x1C 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." rgroup.long 0x30++0x17 line.long 0x0 "ADC_DAT12,A/D Data Register 12" bitfld.long 0x0 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x0 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x0 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x4 "ADC_DAT13,A/D Data Register 13" bitfld.long 0x4 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x4 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x4 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x8 "ADC_DAT14,A/D Data Register 14" bitfld.long 0x8 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x8 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x8 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0xC "ADC_DAT15,A/D Data Register 15" bitfld.long 0xC 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0xC 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0xC 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x10 "ADC_DAT16,A/D Data Register 16" bitfld.long 0x10 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x10 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x10 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." line.long 0x14 "ADC_DAT17,A/D Data Register 17" bitfld.long 0x14 17. "OV,Overrun Flag\nIf converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register OVis set to 1. It is cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) is recent..,1: Data in RESULT (ADC_DAT[11:0]) overwrote" bitfld.long 0x14 16. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read." "0: Data in RESULT (ADC_DAT[11:0]) bits is not valid,1: Data in RESULT (ADC_DAT[11:0]) bits is valid" newline hexmask.long.word 0x14 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC." group.long 0x48++0x13 line.long 0x0 "ADC_CTL,A/D Control Register" hexmask.long.byte 0x0 24.--31. 1. "TMPDMACNT,Timer Event PDMA Count\nWhen each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting.\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish.." bitfld.long 0x0 18.--19. "RESSEL,Resolution Selection" "0: 6-bit. ADC result will put at..,1: 8-bit. ADC result will put at..,?,?" newline bitfld.long 0x0 16.--17. "REFSEL,Reference Voltage Source Selection" "0: Select,1: Select,?,?" bitfld.long 0x0 15. "TMTRGMOD,Timer Event Trigger ADC Conversion Mode\nNote1: setting TMSEL (ADC_CTL[13:12]) to select timer event from timer0~3.\nNote2:If timer event is used as ADC trigger source ADCEN (ADC_CTL[0]) needs to be disabled." "0: Timer event trigger ADC conversion disabled,1: setting TMSEL" newline bitfld.long 0x0 12.--13. "TMSEL,Select A/D Enable Time-out Source\nSelects one of four timer events sourceto trigger ADC starts to convert." "0: TMR0,1: TMR1,?,?" bitfld.long 0x0 11. "SWTRG,Software Trigger A/D Conversion Start\nADC can be start to convert from three sources: software write external pin STADC and PWM trigger. SWTRG(ADC_CTL[11]) is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan.." "0: Conversion stopped and A/D converter enter idle..,1: Conversion starts" newline bitfld.long 0x0 10. "DIFF,Differential Mode Selection\nNote: Calibration should calibrated each time when switching between single-ended and differential mode." "0: ADC is operated in single-ended mode,1: ADC is operated in differential mode" bitfld.long 0x0 9. "PTEN,PDMA Transfer EnableBit\nWhen A/D conversion is completed the converted data is loaded into ADC_DATx software can enable this bit to generate a PDMA data transfer request." "0: PDMA data transfer Disabled,1: PDMA data transfer in ADC_DATx Enabled" newline bitfld.long 0x0 8. "HWTRGEN,Hardware External Trigger EnableBit\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled ADC starts to convert by the selected hardware trigger source." "0: External trigger Disabled,1: External trigger Enabled" bitfld.long 0x0 6.--7. "HWTRGCOND,Hardware External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state." "0: Low level,1: High level,?,?" newline bitfld.long 0x0 4.--5. "HWTRGSEL,Hardware Trigger Source Select Bit\nIn hardware trigger mode ADC starts to convert by the external trigger from STADC pin or PWM trigger.\nNote:Software should disable HWTRGEN (ADC_CTL[8]) and clear SWTRG (ADC_CTL[11]) before change HWTRGSEL.." "0: A/D conversion is started by external STADC pin,1: Reserved,?,?" bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode" "0: Single conversion,1: Reserved,?,?" newline bitfld.long 0x0 1. "ADCIEN,A/D Interrupt EnableBit\nA/D conversion end interrupt request is generated if ADCIEN(ADC_CTL[1]) bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" bitfld.long 0x0 0. "ADCEN,A/D Converter EnableBit\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D Converter Disabled,1: A/D Converter Enabled" line.long 0x4 "ADC_CHEN,A/D Channel Enable Register" bitfld.long 0x4 17. "CHEN17,Analog Input Channel 17 EnableBit (ConvertAVSS)" "0: Channel 17 Disabled,1: Channel 17 Enabled" bitfld.long 0x4 16. "CHEN16,Analog Input Channel 16 EnableBit (Convert AVDD)" "0: Channel 16 Disabled,1: Channel 16 Enabled" newline bitfld.long 0x4 15. "CHEN15,Analog Input Channel 15 EnableBit (Convert Int_VREF)" "0: Channel 15 Disabled,1: Channel 15 Enabled" bitfld.long 0x4 14. "CHEN14,Analog Input Channel 14 EnableBit (Convert VTEMP)" "0: Channel 14 Disabled,1: Channel 14 Enabled" newline bitfld.long 0x4 13. "CHEN13,Analog Input Channel 13 Enable Bit (Convert VBAT)" "0: Channel 13 Disabled,1: Channel 13 Enabled" bitfld.long 0x4 12. "CHEN12,Analog Input Channel 12 Enable Bit (Convert VBG)" "0: Channel 12 Disabled,1: Channel 12 Enabled" newline bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 EnableBit (Convert Input Voltage From PA.7)" "0: Channel 7 Disabled,1: Channel 7 Enabled" bitfld.long 0x4 6. "CHEN6,Analog Input Channel 6 EnableBit (Convert Input Voltage From PA.6)" "0: Channel 6 Disabled,1: Channel 6 Enabled" newline bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 EnableBit (Convert Input Voltage From PA.5)" "0: Channel 5 Disabled,1: Channel 5 Enabled" bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 EnableBit (Convert Input Voltage From PA.4)" "0: Channel 4 Disabled,1: Channel 4 Enabled" newline bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 EnableBit (Convert Input Voltage From PA.3)" "0: Channel 3 Disabled,1: Channel 3 Enabled" bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 EnableBit (Convert Input Voltage From PA.2)" "0: Channel 2 Disabled,1: Channel 2 Enabled" newline bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 EnableBit (Convert Input Voltage From PA.1)" "0: Channel 1 Disabled,1: Channel 1 Enabled" bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable Bit (Convert Input Voltage From PA.0)\nNote:If software enables more than one channel the channel with the smallest number will be selected and the other enabled channels will be ignored." "0: Channel 0 Disabled,1: Channel 0 Enabled" line.long 0x8 "ADC_CMP0,A/D Compare Register 0" hexmask.long.word 0x8 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software." hexmask.long.byte 0x8 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]) the internal match counter will increase 1. \nNote:When the internal counter reaches the value to.." newline hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~17 but channel 8~12 are reserved." bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the ADCMPFx (ADC_STATUS[2:1]) bit will be set." "0: Set the compare condition as that when a A/D..,1: Set the compare condition as that when a A/D.." newline bitfld.long 0x8 1. "ADCMPIE,A/D Compare Interrupt EnableBit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]) ADCMPFx(ADC_STATUS[2:1]) bit will be asserted in the meanwhile if.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0x8 0. "ADCMPEN,A/D Compare EnableBit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register.\nNote:When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]).." "0: Compare function Disabled,1: Compare function Enabled" line.long 0xC "ADC_CMP1,A/D Compare Register 1" hexmask.long.word 0xC 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software." hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]) the internal match counter will increase 1. \nNote:When the internal counter reaches the value to.." newline hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~17 but channel 8~12 are reserved." bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the ADCMPFx (ADC_STATUS[2:1]) bit will be set." "0: Set the compare condition as that when a A/D..,1: Set the compare condition as that when a A/D.." newline bitfld.long 0xC 1. "ADCMPIE,A/D Compare Interrupt EnableBit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]) ADCMPFx(ADC_STATUS[2:1]) bit will be asserted in the meanwhile if.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0xC 0. "ADCMPEN,A/D Compare EnableBit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register.\nNote:When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]).." "0: Compare function Disabled,1: Compare function Enabled" line.long 0x10 "ADC_STATUS,A/D Status Register" bitfld.long 0x10 16. "INITRDY,ADC Initial Ready by Power-up Sequence Completed\nNote: This bit will be set after system reset occurred and automatically cleared by power-up event." "0: ADC not powered up after system reset,1: ADC has been powered up since the last system.." hexmask.long.byte 0x10 4.--8. 1. "CHANNEL,Current Conversion Channel(Read Only)" newline rbitfld.long 0x10 3. "BUSY,BUSY/IDLE(Read Only)\nNote:This bit is mirror of SWTRG (ADC_CTL [11]) bit." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" bitfld.long 0x10 2. "ADCMPF1,A/D Compare Flag1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1 this bit is set to 1.\nNote: This flag can be cleared by software writing 1 to it when this flag is set the matching counter will be.." "0: Conversion result in ADC_DATx does not meet the..,1: Conversion result in ADC_DATx meets the CMPDAT.." newline bitfld.long 0x10 1. "ADCMPF0,A/D Compare Flag0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0 this bit is set to 1.\nThis flag can be cleared by writing 1 to it.\nNote: This flag can be cleared by software writing 1 to it when this.." "0: Conversion result in ADC_DATx does not meet the..,1: Conversion result in ADC_DATx meets the CMPDAT.." bitfld.long 0x10 0. "ADIF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion ADIF (ADC_STATUS[0]) is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan.." "0,1" rgroup.long 0x60++0x3 line.long 0x0 "ADC_PDMA,A/D PDMA Current Transfer Data Register" hexmask.long.word 0x0 0.--11. 1. "AD_PDMA,ADC PDMA Current Transfer Data(Read Only)\nDuring PDMAtransfer reading these bits can monitor the current PDMA transfer data." group.long 0x64++0x13 line.long 0x0 "ADC_PWD,A/D Power Management Register" bitfld.long 0x0 2.--3. "PWDMOD,ADC Power Saving Mode\nSet this bit fields to select ADC power saving mode.\nNote1: Different power saving mode has different power down/up sequence.To avoid ADC powering up with wrong sequence user must keep PWMOD (ADC_PWD[3:2]) consistent each.." "0: Reserved,1: Different power saving mode has different power..,2: While the ADC is powered up from power saving..,?" bitfld.long 0x0 1. "PWDCALEN,Power Up Calibration Function EnableBit\nNote:This bit works together with CALSEL (ADC_CALCTL[3]) see the following\n{PWDCALEN CALFBSEL}Description:\nPWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. \nPWDCALEN is 0 and CALFBSEL is 1: No.." "0: Load calibration word when power up,1: Calibrate when power up" newline bitfld.long 0x0 0. "PWUPRDY,ADC Power-up Sequence Completed and Ready for Conversion" "0: ADC is not ready for conversion itmay be in..,1: ADC is ready for conversion" line.long 0x4 "ADC_CALCTL,A/D Calibration Control Register" bitfld.long 0x4 3. "CALSEL,Calibration Functional Block Selection" "0: Load calibration functional block,1: Calibration functional block" bitfld.long 0x4 2. "CALDONE,Calibrate Functional Block Done\nNote:This bit is set by hardware and auto cleard by hardware This bit can also be cleared by software writing 1." "0: Not yet,1: Selected calibrationfunctional block complete" newline bitfld.long 0x4 1. "CALSTART,Calibration Functional Block Start" "0: Stops calibration functional block,1: Starts calibration functional block" bitfld.long 0x4 0. "CALEN,Calibration Function EnableBit\nEnable this bit to turn on the calibration function block." "0: Bypass calibrationfunctionalblock,1: Enabledcalibrationfunctionalblock" line.long 0x8 "ADC_CALWORD,A/D Calibration Load word Register" hexmask.long.byte 0x8 0.--6. 1. "CALWORD,Calibration Word Bits\nWrite to this register with the previous calibration word before load calibration action read this register after calibration done.\nNote:The calibration block contains two parts 'CALIBRATION' and 'LOAD CALIBRATION'; if.." line.long 0xC "ADC_EXTSMPT0,A/D Sampling Time Counter Register 0" hexmask.long.byte 0xC 28.--31. 1. "EXTSMPT_CH7,Additional ADC Sample Clockfor Channel 7\nThe same as channel 0 description." hexmask.long.byte 0xC 24.--27. 1. "EXTSMPT_CH6,Additional ADC Sample Clockfor Channel 6\nThe same as channel 0 description." newline hexmask.long.byte 0xC 20.--23. 1. "EXTSMPT_CH5,Additional ADC Sample Clockfor Channel 5\nThe same as channel 0 description." hexmask.long.byte 0xC 16.--19. 1. "EXTSMPT_CH4,Additional ADC Sample Clockfor Channel 4\nThe same as channel 0 description." newline hexmask.long.byte 0xC 12.--15. 1. "EXTSMPT_CH3,Additional ADC Sample Clockfor Channel 3\nThe same as channel 0 description." hexmask.long.byte 0xC 8.--11. 1. "EXTSMPT_CH2,Additional ADC Sample Clockfor Channel 2\nThe same as channel 0 description." newline hexmask.long.byte 0xC 4.--7. 1. "EXTSMPT_CH1,Additional ADC Sample Clockfor Channel 1\nThe same as channel 0 description." hexmask.long.byte 0xC 0.--3. 1. "EXTSMPT_CH0,Additional ADC Sample Clockfor Channel 0\nIf the ADC input is unstable user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clocks. The additional clock number will be.." line.long 0x10 "ADC_EXTSMPT1,A/D Sampling Time Counter Register 1" hexmask.long.byte 0x10 16.--19. 1. "EXTSMPT_INTCH,Additional ADC Sample Clock for Internal Channel (VTEMP AVDD AVSS Int_VREF VBAT VBG)\nThe same as channel 0 description." tree.end tree "CLK (Clock Controller)" base ad:0x50000200 group.long 0x0++0xB line.long 0x0 "CLK_PWRCTL,System Power-down Control Register" bitfld.long 0x0 25. "MIRCEN,MIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4 MHz internal medium speed RC oscillator..,1: 4 MHz internal medium speed RC oscillator.." bitfld.long 0x0 24. "HIRC1EN,HIRC1 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 36 MHz internal high speed RC oscillator..,1: 36 MHz internal high speed RC oscillator.." newline bitfld.long 0x0 14. "HIRC0FSTOP,HIRC0 Stop Output When Frequency Changes (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: HIRC0 will continue to output when HIRC..,1: HIRC0will suppress to output during first 16.." bitfld.long 0x0 13. "HIRC0FSEL,HIRC0 Output Frequency Select Bit" "0: HIRC0 will output 12MHz clock,1: HIRC0 will output 16MHz Clock" newline bitfld.long 0x0 10.--12. "HXTGAIN,HXT Gain Control Bit(Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled crystal will consume more power than gain control off.\nNote: This bit is write protected." "0: HXT frequency is lower than from 4 MHz,1: HXT frequency is from 4 MHz to 8 MHz,?,?,?,?,?,?" bitfld.long 0x0 8. "HXTSLTYP,HXT Mode Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: High frequency crystal loop back path Disabled.,1: High frequency crystal loop back path Enabled." newline bitfld.long 0x0 6. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.\n(a) If the PDWTCPU is 0 then the chip enters Power-down mode immediately after the PDEN.." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instant or wait CPU.." bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt (EINT0~1 GPIO UART0~1 WDT ACMP01 BOD RTC TMR0~3 I2C0~1 or SPI0 ~3)will occur when PDWKIEN are high.\nNote2: This bit is write protected. Refer to the.." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt" newline bitfld.long 0x0 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay4096 clock cycles to wait system clock stable when chip works at 4~32 MHz external high speed crystal oscillator.." "0: Clock cycles delayDisabled,1: Clock cycles delayEnabled" bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator.." newline bitfld.long 0x0 2. "HIRC0EN,HIRC0 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 12~16 MHz internal high speed RC oscillator..,1: 12~16 MHz internal high speed RC oscillator.." bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external lowspeed crystal (LXT)..,1: 32.768 kHz external lowspeed crystal (LXT) Enabled" newline bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~32 MHz external high speed crystal (HXT)..,1: 4~32 MHz external high speed crystal (HXT) Enabled" line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register" bitfld.long 0x4 5. "STCKEN,System Tick Clock Enable Control Bit" "0: System Tick Clock Disabled,1: System Tick Clock Enabled" bitfld.long 0x4 4. "SRAMCKEN,SRAM Controller Clock Enable Control Bit" "0: SRAM peripheral clock Disabled,1: SRAM peripheral clock Enabled" newline bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled" bitfld.long 0x4 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled" newline bitfld.long 0x4 0. "GPIOCKEN,GPIO Controller Clock Enable Control" "0: GPIO peripheral clock Disabled,1: GPIO peripheral clock Enabled" line.long 0x8 "CLK_APBCLK,APB Devices Clock Enable Control Register" bitfld.long 0x8 31. "SC1CKEN,SmartCard 1 Clock Enable Control" "0: SmartCard 1 Clock Disabled,1: SmartCard 1 Clock Enabled" bitfld.long 0x8 30. "SC0CKEN,SmartCard 0 Clock Enable Control" "0: SmartCard 0 Clock Disabled,1: SmartCard 0 Clock Enabled" newline bitfld.long 0x8 28. "ADCCKEN,Analog-digital-converter (ADC) Clock Enable Control" "0: ADC Clock Disabled,1: ADC Clock Enabled" bitfld.long 0x8 20. "PWM0CKEN,PWM0 Clock Enable Control" "0: PWM0 Clock Disabled,1: PWM0 Clock Enabled" newline bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Control" "0: UART1 Clock Disabled,1: UART1 Clock Enabled" bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Control" "0: UART0 Clock Disabled,1: UART0 Clock Enabled" newline bitfld.long 0x8 15. "SPI3CKEN,SPI3 Clock Enable Control" "0: SPI3 Clock Disabled,1: SPI3 Clock Enabled" bitfld.long 0x8 14. "SPI2CKEN,SPI2 Clock Enable Control" "0: SPI2 Clock Disabled,1: SPI2 Clock Enabled" newline bitfld.long 0x8 13. "SPI1CKEN,SPI1 Clock Enable Control" "0: SPI1 Clock Disabled,1: SPI1 Clock Enabled" bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Control" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled" newline bitfld.long 0x8 11. "ACMP0CKEN,ACMP0 Clock Enable Control" "0: ACMP0 Clock Disabled,1: ACMP0 Clock Enabled" bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Control" "0: I2C1 Clock Disabled,1: I2C1 Clock Enabled" newline bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Control" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled" bitfld.long 0x8 7. "DSRCCKEN,DSRC Clock Enable Control" "0: DSRC Clock Disabled,1: DSRC Clock Enabled" newline bitfld.long 0x8 6. "CLKOCKEN,ClocK Output Clock Enable Control" "0: Clock Output Clock Disabled,1: Clock Output Clock Enabled" bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Control" "0: Timer3 Clock Disabled,1: Timer3 Clock Enabled" newline bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Control" "0: Timer2 Clock Disabled,1: Timer2 Clock Enabled" bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Control" "0: Timer1 Clock Disabled,1: Timer1 Clock Enabled" newline bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Control" "0: Timer0 Clock Disabled,1: Timer0 Clock Enabled" bitfld.long 0x8 1. "RTCCKEN,Real-time-clock Clock Enable Control \nThis bit is used to control the RTC APB clock only The RTC engine Clock Source is from LXT." "0: Real-time-clock Clock Disabled,1: Real-time-clock Clock Enabled" newline bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only The WDT engine Clock Source is from LIRC." "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled" rgroup.long 0xC++0x3 line.long 0x0 "CLK_STATUS,Clock status monitor Register" bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag(Read Only)\nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1." "0: Clock switching success,1: Clock switching failure" bitfld.long 0x0 6. "MIRCSTB,MIRCClock Source Stable Flag(Read Only)" "0: 4 MHz internal medium speed RC oscillator (MIRC)..,1: 4 MHz internal medium speed RC oscillator (MIRC).." newline bitfld.long 0x0 5. "HIRC1STB,HIRCClock Source Stable Flag(Read Only)" "0: 36 MHz internal high speed RC oscillator (HIRC1)..,1: 36 MHz internal high speed RC oscillator (HIRC1).." bitfld.long 0x0 4. "HIRC0STB,HIRC0 Clock Source Stable Flag (Read Only)" "0: 12~16 MHz internal high speed RC oscillator..,1: 12~16 MHz internal high speed RC oscillator.." newline bitfld.long 0x0 3. "LIRCSTB,LIRCClock Source Stable Flag(Read Only)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).." bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag(Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled" newline bitfld.long 0x0 1. "LXTSTB,LXTClock Source Stable Flag(Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." bitfld.long 0x0 0. "HXTSTB,HXTClock Source Stable Flag(Read Only)" "0: 4~36 MHz external high speed crystal oscillator..,1: 4~36 MHz external high speed crystal oscillator.." group.long 0x10++0x1B line.long 0x0 "CLK_CLKSEL0,Clock Source Select Control Register 0" bitfld.long 0x0 4. "ISPSEL,ISP Clock Source Selection" "0: Clock source from HIRC1 or HIRC0 depend on..,1: Clock source from MIRC" bitfld.long 0x0 3. "HIRCSEL,HIRC Source Selection" "0: Clock source from HIRC0 (12~16MHz),1: Clock source from HIRC1 (36MHz)" newline bitfld.long 0x0 0.--2. "HCLKSEL,HCLK Clock Source Selection(Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?" line.long 0x4 "CLK_CLKSEL1,Clock Source Select Control Register 1" bitfld.long 0x4 30.--31. "WWDTSEL,WDT Clock Source Selection" "0: reserved,1: reserved,?,?" bitfld.long 0x4 28.--29. "WDTSEL,WDT Clock Source Selection" "0: reserved,1: Clock source from LXT,?,?" newline bitfld.long 0x4 26.--27. "SPI2SEL,SPI2 Clock Source Selection" "0: Clock source from PLL,1: Clock source from HCLK,?,?" bitfld.long 0x4 24.--25. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from PLL,1: Clock source from HCLK,?,?" newline bitfld.long 0x4 19.--21. "ADCSEL,ADC Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" bitfld.long 0x4 12.--14. "TMR1SEL,Timer1 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline bitfld.long 0x4 8.--10. "TMR0SEL,Timer0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" bitfld.long 0x4 4. "PWM0SEL,PWM0 Clock Source Selection" "0: Clock source from PLL,1: Clock source from PCLK0" newline bitfld.long 0x4 0.--2. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" line.long 0x8 "CLK_CLKSEL2,Clock Source Select Control Register 2" bitfld.long 0x8 26.--27. "SPI3SEL,SPI3 Clock Source Selection" "0: Clock source from PLL,1: Clock source from HCLK,?,?" bitfld.long 0x8 24.--25. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from PLL,1: Clock source from HCLK,?,?" newline bitfld.long 0x8 20.--22. "SC1SEL,SC1 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?" bitfld.long 0x8 16.--18. "SC0SEL,SC0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?" newline bitfld.long 0x8 12.--14. "TMR3SEL,Timer3 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" bitfld.long 0x8 8.--10. "TMR2SEL,Timer2 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline bitfld.long 0x8 7. "DSRCSEL,DSRC Clock Source Selection" "0: Clock source from 4 MHz internal medium speed RC..,1: Clock source from 36 MHz internal high speed RC.." bitfld.long 0x8 4.--6. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" newline bitfld.long 0x8 0.--2. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?" line.long 0xC "CLK_CLKDIV0,Clock Divider Number Register 0" hexmask.long.byte 0xC 28.--31. 1. "SC0DIV,SC0Clock Divide Number From SC0Clock Source" hexmask.long.byte 0xC 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source" newline hexmask.long.byte 0xC 12.--15. 1. "UART1DIV,UART1Clock Divide Number From UART Clock Source" hexmask.long.byte 0xC 8.--11. 1. "UART0DIV,UART0Clock Divide Number From UART Clock Source" newline hexmask.long.byte 0xC 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" line.long 0x10 "CLK_CLKDIV1,Clock Divider Number Register 1" hexmask.long.byte 0x10 24.--28. 1. "DSRCDIV,DSRC Clock Divide Number From DSRCClock Source" hexmask.long.byte 0x10 20.--23. 1. "TMR3DIV,Timer3Clock Divide Number From Timer3Clock Source" newline hexmask.long.byte 0x10 16.--19. 1. "TMR2DIV,Timer2Clock Divide Number From Timer2Clock Source" hexmask.long.byte 0x10 12.--15. 1. "TMR1DIV,Timer1Clock Divide Number From Timer1Clock Source" newline hexmask.long.byte 0x10 8.--11. 1. "TMR0DIV,Timer0Clock Divide Number From Timer0Clock Source" hexmask.long.byte 0x10 0.--3. 1. "SC1DIV,SC 1Clock Divide Number From SC 1Clock Source" line.long 0x14 "CLK_PLLCTL,PLL Control Register" bitfld.long 0x14 17.--18. "PLLSRC,PLL Source Clock Select" "0: PLL source clock from HXT,1: PLL source clock from HIRC0 or HIRC1,?,?" bitfld.long 0x14 16. "PD,Power-down Mode\nIf set the PDEN bit '1' in CLK_PWRCTL register the PLL will enter Power-down mode too" "0: PLL is in normal mode,1: PLL is in power-down mode (default)" newline bitfld.long 0x14 14.--15. "STBCNT,PLL Stable Time Selection" "0: 100 cycle time of input clock source,1: 120 cycle time of input clock source,?,?" hexmask.long.byte 0x14 8.--13. 1. "INDIV,PLL Input Source Divider \nPLL input clock frequency range: 0.8MHz ~ 2MHz" newline hexmask.long.byte 0x14 0.--5. 1. "PLLMLP,PLL Multiple\n000000: Reserved\n000001: X1\n000010: X2\n000011: X3\n000100: X4\n...\n010000:X16\n...\n100000: X32\n100100: X36\n0thers: Reserved \nPLL output frequency: PLL input frequency * PLLMLP.\nPLL output frequency range: 16MHz ~ 36MHz" line.long 0x18 "CLK_CLKOCTL,Clock Output Control Register" bitfld.long 0x18 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.." bitfld.long 0x18 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled" newline hexmask.long.byte 0x18 0.--3. 1. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]." rgroup.long 0x30++0x3 line.long 0x0 "CLK_WKINTSTS,Wake-up Interrupt Status" bitfld.long 0x0 0. "PDWKIF,Wake-up Interrupt Status in Chip Power-down Mode\nThis bit indicates that some event resumes chip from Power-down mode\nThe status is set if external interrupts UART GPIO RTC USB SPI Timer WDT and BOD wake-up occurred.\nWrite 1 to clear.." "0,1" group.long 0x34++0xB line.long 0x0 "CLK_APBDIV,APB Clock Divider" bitfld.long 0x0 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 PCLK1 can be divided from HCLK." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 PCLK0 can be divided from HCLK." "0,1,2,3,4,5,6,7" line.long 0x4 "CLK_CLKDCTL,Clock Fail Detector Control Register" bitfld.long 0x4 2. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.." bitfld.long 0x4 1. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." newline bitfld.long 0x4 0. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.." line.long 0x8 "CLK_CLKDIE,Clock Fail Detector Interrupt Enable Register" bitfld.long 0x8 2. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.." bitfld.long 0x8 1. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." newline bitfld.long 0x8 0. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.." rgroup.long 0x40++0x3 line.long 0x0 "CLK_CLKDSTS,Clock Fail Detector Status Register" bitfld.long 0x0 2. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag\nNote: Write 1 to clear the bit to 0." "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.." bitfld.long 0x0 1. "LXTFIF,LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0." "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.." newline bitfld.long 0x0 0. "HXTFIF,HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0." "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.." group.long 0x44++0x7 line.long 0x0 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register" hexmask.long.word 0x0 0.--10. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1." line.long 0x4 "CLK_CDLOWB,Clock Frequency Detector Lower Boundary Register" hexmask.long.word 0x4 0.--10. 1. "LOWERBD,HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will set to 1." tree.end tree "DSRC" base ad:0x401F0000 group.long 0x0++0x13 line.long 0x0 "DSRC_CTL,DSRC Control Register" bitfld.long 0x0 28.--30. "BRATEACC,Bit Rate Accuracy Control Bits\nPlease refer to Table 6.181.\nNote: This function is only for FM0 CODEC." "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--27. "WKPOL,Wake-up Pin Polarity Control Bit" "0: Wake-up pin rising edge wake-up DSRC,1: Wake-up pin falling edge wake-up DSRC,?,?" newline bitfld.long 0x0 23. "RXON,RX_ON Control Bit" "0: RX_ON signal Enabled,1: RX_ON signal Disabled" bitfld.long 0x0 22. "FORCERX,Force RX State Control Bit\nNote: This bit will be cleared automatically." "0: No effect,1: DSRC returns Start_Rx state immediately" newline bitfld.long 0x0 21. "FORCETX,Force TX State Control Bit\nNote: This bit will be cleared automatically" "0: No effect,1: DSRC returns TX state to transmit data immediately" bitfld.long 0x0 20. "CRCBSWAP,CRC BYTE SWAP" "0: The received CRC value is not byte swap,1: The received CRC value is byte swap" newline bitfld.long 0x0 19. "TRDMAEN,TBP Receive DMA Enable Bit" "0: TBP Receiving DMA Disabled,1: TBP Receiving DMA Enabled" bitfld.long 0x0 18. "TTDMAEN,TBP Transmit DMA Enable Bit" "0: TBP Transmitting DMA Disabled,1: TBP Transmitting DMA Enabled" newline bitfld.long 0x0 17. "TRANSFIN,TBP Transfer Done\nWhen the TTDMAEN (DSRC_CTL[20]) is disabled and the transmitted data is written into DSRC_TX by user this bit shall be set into the TBP to terminate the processor before the last the transmitted data. The minimum length of.." "0: Indicate the TTBP processor is not finished,1: Inform the TTBP to finish the transparent bit.." bitfld.long 0x0 16. "TBPEN,TBP Enable Bit\nSetting this bit to 1 enables TBP operation." "0: TBP function Disabled,1: TBP function Enabled" newline bitfld.long 0x0 15. "WKHXTEN,Wake-up HXT Clock Enable Bit \nSetting this bit to 1 enables RF wake-up HXT clock." "0: RF wake-up HXT clock Disabled,1: RF T wake-up HXT clock Enabled" bitfld.long 0x0 14. "PDRXDIS,Power-down Mode RXON Disable Bit" "0: RXON signal is always controlled by..,1: RXON signal is disabled during DSRC Power-Down.." newline bitfld.long 0x0 13. "PREAMFMT,Preamble Pattern Format\nNote: It is MSB first to be sent." "0: The preamble length is half word and its pattern..,1: The preamble length is one word and its pattern.." bitfld.long 0x0 12. "SEEDM,CRC Seed Mode" "0: The transmit CRC seed initial value is CRCSEED0..,1: The transmit CRC seed initial value is CRCSEED1.." newline bitfld.long 0x0 11. "CHKSFMT,Checksum Format" "0: No 1's complement for CRC checksum,1: 1's complement for CRC checksum" bitfld.long 0x0 10. "CHKSREV,Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E the bit order reversed for CRC checksum is 0x74F0DEBB." "0: No bit order reverse for CRC checksum,1: Bit order reverse for CRC checksum" newline bitfld.long 0x0 9. "CRCMSB,CRC Generation on Data MSB\nNote: If the input data is 0xaa the sequence of CRC bit generation is 01010101 when the bit is set as 0. Otherwise the sequence of CRC bit generation is 10101010 when the bit is set as 1." "0: The CRC generation start on the LSB input data..,1: The CRC generation start on the MSB input data.." bitfld.long 0x0 8. "CRCEN,CRC Engine Enable Bit" "0: CRC function Disabled,1: CRC function Enabled" newline bitfld.long 0x0 5. "BRATEMOD,Bit Rate Error Mode" "0: The DSRC receives the start of frame again,1: The DSRC does not care the bit rate error.." bitfld.long 0x0 4. "BRDETEN,Bit Rate Detection Enable Bit \nNote: This function is only for FM0 CODEC." "0: Bit rate detection Disabled,1: Bit rate detection Enabled" newline bitfld.long 0x0 3. "CODECFMT,CODEC Format Select Bit" "0: FM0 CODEC,1: MONCHESTER CODEC" bitfld.long 0x0 2. "CODECEN,CODEC Enable Bit\nNote: When both DSRCEN and CODECEN are enabled the SPI1 will set TXNEG (SPI_CTL[2]) RXNEG (SPI_CTL[1]) CLKPOL (SPI_CTL[11]) SS (SPI_SSCTL[1:0]) SSACTPOL (SPI_SSCTL[2]) AUTOSS (SPI_SSCTL[3]) and SLV3WIRE (SPI_SSCTL[5]) as.." "0: CODEC Disabled,1: CODEC Enabled" newline bitfld.long 0x0 1. "SWRXEN,Software Control RX_ON Enable Bit" "0: Software control RX_ON signal Disabled,1: Software control RX_ON signal Enabled" bitfld.long 0x0 0. "DSRCEN,DSRC Enable Bit\nNote: When DSRC is enabled SPI1 will set SUSPITV (SPI_CTL[15:12]) DWIDTH (SPI_CTL[7:3]) REORDER (SPI_CTL[19]) FIFOM (SPI_CTL[21]) TWOBIT (SPI_CTL[22]) and DUALIOEN (SPI_CTL[29]) set as 0x0 0x8 0 1 0 and 0 automatically.." "0: DSRC Disabled,1: DSRC Enabled" line.long 0x4 "DSRC_INTEN,DSRC Interrupt Enable Register" bitfld.long 0x4 26. "EPWKIE,External Pin Wake-up Interrupt Enable Bit" "0: External Pin Wake-up event interrupt Disabled,1: External Pin Wake-up event interrupt Enabled" bitfld.long 0x4 20. "T4TOIE,Timer 4 Time-out Interrupt Enable Bit" "0: T4 Time-out interrupt Disabled,1: T4 Time-out interrupt Enabled" newline bitfld.long 0x4 19. "T3TOIE,Timer 3 Time-out Interrupt Enable Bit" "0: T3 Time-out interrupt Disabled,1: T3 Time-out interrupt Enabled" bitfld.long 0x4 18. "T2TOIE,Timer 2 Time-out Interrupt Enable Bit" "0: T2 Time-out interrupt Disabled,1: T2 Time-out interrupt Enabled" newline bitfld.long 0x4 12. "TXDONEIE,Transmit Data Done Interrupt Enable Bit" "0: Transmit data done interrupt Disabled,1: Transmit data done interrupt Enabled" bitfld.long 0x4 9. "RTBPDIE,TBP Byte Receive Done Interrupt Enable Bit" "0: The TBP byte receive done interrupt Disabled,1: The TBP byte receive done interrupt Enabled" newline bitfld.long 0x4 5. "BRATERRIE,Bit Rate Error Interrupt Enable Bit" "0: Bit Rate Error interrupt Disabled,1: Bit Rate Error interrupt Enabled" bitfld.long 0x4 4. "RXDATERRIE,Received Data Error Interrupt Enable Bit" "0: Received DATA Error interrupt Disabled,1: Received DATA Rate Error interrupt Enabled" newline bitfld.long 0x4 3. "STPFRMIE,Stop Field of Frame Detection Interrupt Enable Bit" "0: Stop Field of Frame detection Interrupt Disabled,1: Stop Field of Frame detection Interrupt Enabled" bitfld.long 0x4 2. "STRFRMIE,Start Field of Frame Detection Interrupt Enable Bit" "0: Start Field of Frame detection interrupt Disabled,1: Start Field of Frame detection interrupt Enabled" newline bitfld.long 0x4 1. "CRCERRIE,CRC Error Interrupt Enable Bit" "0: CRC error interrupt Disabled,1: CRC rate error interrupt Enabled" bitfld.long 0x4 0. "CRCCORIE,CRC Check Correct Interrupt Enable Bit" "0: CRC check done without error Interrupt Disabled,1: CRC check done without error Interrupt Enabled" line.long 0x8 "DSRC_STATUS,DSRC Status Register" bitfld.long 0x8 26. "EPWKF,External Pin Wake-up Event Flag\nNote: Write 1 to clear this flag." "0: No external pin wake-up event happened,1: External pin wake-up event happened" bitfld.long 0x8 25. "CRC1_OK,CRC1 Compare OK\nNote: Writing1 to CRCCOR (DSRC_STATUS[0]) CRCERR (DSRC_STATUS[1]) and itself can clear this flag." "0: The compare result between the receive CRC data..,1: The compare result between the receive CRC data.." newline bitfld.long 0x8 24. "CRC0_OK,CRC0 Compare OK\nNote: Writing1 to CRCCOR (DSRC_STATUS[0]) CRCERR (DSRC_STATUS[1]) and itself can clear this flag." "0: The compare result between the receive CRC data..,1: The compare result between the receive CRC data.." bitfld.long 0x8 20. "T4TO,Timer 4 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR4.\nNote1: The Timer Counter is started when SPI detected the Stop of Frame and DSRC CRC correct flag is active.\nNote2: Write 1 to clear.." "?,1: The Timer Counter is started when SPI detected.." newline bitfld.long 0x8 19. "T3TO,Timer 3 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR3.\nNote1: The Timer Counter is startedwhen the Start of Frame is detected and the counter is cleared when the Stop of Frame is detect.." "?,1: The Timer Counter is startedwhen the Start of.." bitfld.long 0x8 18. "T2TO,Timer 2 Time-out Flag\nThis flag is set after the Timer Controller finishes counting the value set by DSRC_TMR2.\nNote1: The Timer Counter is started when DSRC wake-up and the counter is cleared when the Start of Frame is detected before T2TO event.." "?,1: The Timer Counter is started when DSRC wake-up.." newline bitfld.long 0x8 15. "TTBPFULL,TTBPTransmit Full\nNote: If the TTDMAEN (DSRC_CTL[18] is disabled the transmitted data can be written into the DSRC_TX register when the TTBPDONE (DSRC_STATUS[8]) is set to 1 and the TTBPFULL must be set as 0. Otherwise the TTBP transmit done.." "0: TBP TX Transmit is not full,1: TBP TX Transmit is full" bitfld.long 0x8 12. "TXFINISH,TX Transfer Finish\nNote:Write 1 to clear this flag." "0: The TX transfer is not finished,1: All the data processed by the TTBP block and the.." newline bitfld.long 0x8 9. "RTBPDONE,TBP Byte Receive Done\nNote: This bit is automatically cleared by TBP_RXDMA_ACK when the TRDMAEN (DSRC_CTL[19]) is set or by the read signal of DSRC_RX register when the TRDMAEN (DSRC_CTL[19]) is not set." "0: The TBP byte receive is not finished,1: The TBP byte receive has done" bitfld.long 0x8 8. "TTBPDONE,TBP Byte Transfer Done\nNote 1: This bit is automatically cleared by TBP_TXDMA_ACK when the TTDMAEN (DSRC_CTL[18]) is set or by the write signal of DSRC_TX register when the TTDMAEN (DSRC_CTL[18]) is not set.\nNote 2: If the TTDMAEN.." "0: The TBP byte transfer is not finished,1: This bit is automatically cleared by.." newline bitfld.long 0x8 5. "BRATERR,Bit Rate Error Flag\nThis flag indicates FM0 or MANCHESTER bit rate error depending on CODECFMT (DSRC_CTL[3]) setting if BRDETEN (DSRC_CTL[4]) is set to 1.\nNote: Write 1 to clear this flag." "0,1" bitfld.long 0x8 4. "RXDATERR,Received Data Error Flag\nNote: Write 1 to clear this flag." "0: The received data packet error happened,1: The received data packet has successive 7 bit 1." newline bitfld.long 0x8 3. "STPFRM,Stop Field of Frame Detection Flag\nThis flag indicates stop field of frame is detected.\nNote: Write 1 to clear this flag." "0,1" bitfld.long 0x8 2. "STRFRM,Start Field of Frame Detection Flag\nThis flag indicates start field of frame is detected.\nNote: Write 1 to clear this flag." "0,1" newline bitfld.long 0x8 1. "CRCERR,CRC Error Bit" "0: This flag indicates CRC check done and result is..,1: If the CRC function is enabled.." bitfld.long 0x8 0. "CRCCOR,CRC CorrectBit" "0: This flag indicates CRC check done and result is..,1: If the CRC function is enabled.." line.long 0xC "DSRC_PREAMBLE,DSRC Preamble Pattern Register" hexmask.long 0xC 0.--31. 1. "PREPAT,The Preamble Pattern\nThe bit field indicates the preamble pattern of DSRC. If the PREAMFMT (DSRC_CTL[24]) is set to 1 32-bit preamble pattern is transmitted and the transmitted sequence is PREPAT[31:24] PREPAT[23:16] PREPAT[15:8] and.." line.long 0x10 "DSRC_CRCSEED,DSRC CRC Seed Initial Register" hexmask.long.word 0x10 16.--31. 1. "CRCSEED1,The CRC Seed Initial Pattern 1\nThe bit field indicates the CRC seed initial pattern 1 of DSRC.\nFor receiver:\nThe CRC will be calculated by the initial value. The TBP will auto compare the calculated result with the received CRC data and.." hexmask.long.word 0x10 0.--15. 1. "CRCSEED0,The CRC Seed Initial Pattern 0\nThe bits field indicates the CRC seed initial pattern 0 of DSRC.\nFor receiver:\nThe CRC will be calculated by the initial value. The TBP will auto compare the calculated result with the received CRC data and.." rgroup.long 0x14++0x7 line.long 0x0 "DSRC_RBCNT,DSRC Receive Byte Count Register" hexmask.long.word 0x0 0.--8. 1. "TBPBCNT,TBP Receive Byte Count\nThe bits field indicates the number of receive byte count on RTBP when the CRCCOR (DSRC_STATUS[0]) is set to 1 and the STPFRM(DSRC_STATUS[3]) is set to 1. Otherwise the value is 0.\nNote 1: The 2 bytes CRC is not.." line.long 0x4 "DSRC_CHKSUM,DSRC Checksum Register" hexmask.long.word 0x4 16.--31. 1. "CHECKSUM1,The CRC Checksum1\nThe bit field indicates the CRC checksum of the initial value is CHKSUM1 (DSRC_CHKSUM[31:16])" hexmask.long.word 0x4 0.--15. 1. "CHECKSUM0,The CRC Checksum0\nThe bit field indicates the CRC checksum of the initial value is CHKSUM0 (DSRC_CHKSUM[15:0])." wgroup.long 0x20++0x3 line.long 0x0 "DSRC_TX,DSRC TX Data Register" hexmask.long.byte 0x0 0.--7. 1. "TX,TBP Transmit Data\nThe bit field indicates the transmitted data on the TBP before being transmitted to TTBP." rgroup.long 0x24++0x3 line.long 0x0 "DSRC_RX,DSRC RX Data Register" hexmask.long.byte 0x0 0.--7. 1. "RX,TBP Receiver Data\nThe bit field indicates the received data on the TBP after the RTBP." group.long 0x38++0xB line.long 0x0 "DSRC_TMR2,DSRC Timer 2 Register" hexmask.long.byte 0x0 24.--31. 1. "PSC,Prescale Counter" hexmask.long.tbyte 0x0 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." line.long 0x4 "DSRC_TMR3,DSRC Timer 3 Register" hexmask.long.byte 0x4 24.--31. 1. "PSC,Prescale Counter" hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." line.long 0x8 "DSRC_TMR4,DSRC Timer 4 Register" hexmask.long.byte 0x8 24.--31. 1. "PSC,Prescale Counter" hexmask.long.tbyte 0x8 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." group.long 0x200++0x3 line.long 0x0 "DSRC_CTL2,DSRC Control Register 2" bitfld.long 0x0 8.--10. "CODECDEGSEL,FM0 CODEC Deglitch Selection\nThis bits field is used to define how much width of glitch would be filtered." "0: disable to the CODECdeglitch selection,1: Filter the glitches that the width is 0.25us or..,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "SOFNUM,Start of Frame Number for Transmission\nThis bit field is used to define the number of SOF packet which is repeated send in the SPI bus before the transmitted data." "0: 1 Start field of frame after the Preamble,1: 2Start field of frame after the Preamble,?,?" rgroup.long 0x210++0xB line.long 0x0 "DSRC_TXR,DSRC Transmit Data After TTBP Register" hexmask.long.byte 0x0 0.--7. 1. "TXDATR,Transmit Data After TTBP \nThe bits field indicates the transmitted data after the TTBP. When the 8-Bit transmitted data is processed by the TTBP the register indicates the processed content." line.long 0x4 "DSRC_RXR,DSRC Receive Data Before RTBP Register" hexmask.long.byte 0x4 0.--7. 1. "RXDATR,Receive Data Before RTBP \nThe bits field indicates the current receive data before the RTBP (It comes from the SPI RX buffer). Before the 8-Bit is processed by the RTBP the register indicates the un-processed content." line.long 0x8 "DSRC_ICR,DSRC Internal Use Control Register" tree.end tree "FMC (Flash Memory Controller)" base ad:0x5000C000 group.long 0x0++0x13 line.long 0x0 "FMC_ISPCTL,ISP Control Register" bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself.." "0,1" bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated" newline bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated" bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM" newline bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SPROM cannot be updated,1: SPROM can be updated" bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Booting from APROM,1: Booting from LDROM" newline bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled" line.long 0x4 "FMC_ISPADDR,ISP Address Register" hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address\nThe Nano103 series is equipped with embedded flash. ISPADDR [1:0] must be kept 00 for ISP 32-bit operation. \nFor both CRC-32 Checksum Calculation and Flash All-One Verification commands this field is the flash starting address for.." line.long 0x8 "FMC_ISPDAT,ISP Data Register" hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation." line.long 0xC "FMC_ISPCMD,ISP CMD Register" hexmask.long.byte 0xC 0.--5. 1. "CMD,ISP CMD\nISP command table is shown below:\nThe other commands are invalid." line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register" bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed" rgroup.long 0x14++0x3 line.long 0x0 "FMC_DFBA,Data Flash Base Address" hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1" group.long 0x18++0x3 line.long 0x0 "FMC_FTCTL,Flash Access Time Control Register" bitfld.long 0x0 7. "CACHEOFF,Flash Cache Disable Control (Write Protect)\nNote:This bit is write protected. Refer to the SYS_REGLCTL register." "0: Flash Cache function Enabled (default),1: Flash Cache function Disabled" bitfld.long 0x0 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\nThe Nano103 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register." "?,1: Frequency 20MHz,?,?,?,?,?,?" group.long 0x40++0x3 line.long 0x0 "FMC_ISPSTS,ISP Status Register" bitfld.long 0x0 31. "SCODE,Security Code Active Flag\nThis bit is set by hardware when detecting SPROM secured code is active at flash initiation or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation." "0: Secured code is inactive,1: Secured code is active" hexmask.long.tbyte 0x0 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF}\nVECMAP [18:12] should be 0." newline bitfld.long 0x0 7. "ALLONE,Flash All-one Verification Flag\nThis bit is set by hardware if all of flash bits are 1 and clear if flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit also can be clear by writing 1" "0: All of flash bits are 1 after 'Run Flash All-One..,1: Flash bits are not all 1 after 'Run Flash.." bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1).." "0,1" newline rbitfld.long 0x0 5. "PGFF,Flash Program with Fast Verification Flag(Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP flash erase or ISP read CID operation" "0: Flash Program is success,1: Flash Program is fail. Program data is different.." rbitfld.long 0x0 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0 [7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?" newline rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed" wgroup.long 0x50++0xB line.long 0x0 "FMC_KEY0,KEY0 Data Register" hexmask.long 0x0 0.--31. 1. "KEY0,KEY0 Data (Write Only)\nWrite KEY0 data to this register before KEY Comparison operation." line.long 0x4 "FMC_KEY1,KEY1 Data Register" hexmask.long 0x4 0.--31. 1. "KEY1,KEY1 Data (Write Only)\nWrite KEY1 data to this register before KEY Comparison operation." line.long 0x8 "FMC_KEY2,KEY2 Data Register" hexmask.long 0x8 0.--31. 1. "KEY2,KEY2 Data (Write Only)\nWrite KEY2 data to this register before KEY Comparison operation." group.long 0x5C++0x7 line.long 0x0 "FMC_KEYTRG,KEY Comparison Trigger Control Register" bitfld.long 0x0 1. "TCEN,Time-out Counting Enable Bit (Write Protection)\n10 minutes is at least for time-out and average is about 20 minutes.\nNote:This bit is write-protected. Refer to the SYS_REGLCTL register." "0: Time-out counting Disabled,1: Time-out counting Enabled if key is matched.." bitfld.long 0x0 0. "KEYGO,KEY Comparison Start Trigger (Write Protection)\nWrite 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. This trigger operation is valid while FORBID.." "0: KEY comparison operation is finished,1: KEY comparison is progressed" line.long 0x4 "FMC_KEYSTS,KEY Comparison Status Register" rbitfld.long 0x4 6. "SPFLAG,SPROM Write-protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [1] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0." "0: SPROM write-protection Disabled,1: SPROM write-protection Enabled" rbitfld.long 0x4 5. "CFGFLAG,CONFIG Write-protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [0] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0." "0: CONFIG write-protection Disabled,1: CONFIG write-protection Enabled" newline rbitfld.long 0x4 4. "KEYFLAG,KEY Protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM is programmed to a.." "0: Security Key protection Disabled,1: Security KeyprotectionEnabled" rbitfld.long 0x4 3. "FORBID,KEY Comparison Forbidden Flag(Read Only)\nThis bit is set to 1 whenKECNT(FMC_KECNT[4:0])is more than KEMAX (FMC_KECNT[12:8]) orKPCNT (FMC_KPCNT [2:0])is more than KPMAX (FMC_KPCNT [10:8])." "0: KEY comparison is not forbidden,1: KEY comparison is forbidden KEYGO (FMC_KEYTRG.." newline rbitfld.long 0x4 2. "KEYMATCH,KEY Match Flag(Read Only)\nThis bit is set to 1 after KEY comparison complete if the KEY0 KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched. This bit is also cleared to 0 while \nCPU.." "0: KEY0 KEY1 and KEY2 are unmatched with the KPROM..,1: KEY0 KEY1 and KEY2 are matched with the KPROM.." bitfld.long 0x4 1. "KEYLOCK,KEY LOCK Flag\nThis bit is set to 1 if KEYMATCH (FMC_KEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection. This bit also can be set to 1 while \nCPU write 1 to KEYLOCK(FMC_KEYSTS[1]) or\nKEYFLAG(FMC_KEYSTS[4]) is 1 at.." "0: KPROM and APROM (not include Data Flash) is not..,1: KPROM and APROM (not include Data Flash) is in.." newline rbitfld.long 0x4 0. "KEYBUSY,KEY Comparison Busy (Read Only)" "0: KEY comparison is finished,1: KEY comparison is busy" rgroup.long 0x64++0x7 line.long 0x0 "FMC_KECNT,KEY-Unmatched Counting Register" hexmask.long.byte 0x0 8.--13. 1. "KEMAX,Maximum Number for Error Key Entry at Each Power-on (Read Only)\nKEMAX is the maximum error key entry number at each power-on. When KEMAXROM of KPROM is erased or programmed KEMAX will also be updated. KEMAX is used to limit KECNT(FMC_KECNT[5:0]).." hexmask.long.byte 0x0 0.--5. 1. "KECNT,Error Key Entry Counter at Each Power-on (Read Only)\nKECNT is increased when entry keys is wrong in Security Key protection. KECNT is cleared to 0 if key comparison is matched or system power-on." line.long 0x4 "FMC_KPCNT,KEY-Unmatched Power-on Counting Register" hexmask.long.byte 0x4 8.--11. 1. "KPMAX,Power-on Maximum Number for Error Key Entry (Read Only)\nKPMAX is the power-on maximum number for error key entry. When KPMAXROM of KPROM is erased or programmed KPMAX will also be updated. KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum.." hexmask.long.byte 0x4 0.--3. 1. "KPCNT,Power-on Counter for Error Key Entry(Read Only)\nKPCNT is the power-on counting for error key entry in Security Key protection. KPCNT is cleared to 0 if key comparison is matched." tree.end tree "GPIO (General Purpose I/O)" base ad:0x50004000 group.long 0x0++0xF line.long 0x0 "PA_MODE,PA I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PA_DOUT,PA Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PA_DATMSK,PA Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DMASK14,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DMASK13,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DMASK12,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DMASK11,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DMASK10,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DMASK9,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DMASK8,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DMASK7,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DMASK6,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DMASK5,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DMASK4,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DMASK3,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DMASK2,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DMASK1,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DMASK0,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x10++0x3 line.long 0x0 "PA_PIN,PA Pin Value" bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" group.long 0x14++0x13 line.long 0x0 "PA_DBEN,PA De-Bounce Enable Control Register" bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PA_INTEN,PA Interrupt Enable Control Register" bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" line.long 0xC "PA_INTSRC,PA Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." line.long 0x10 "PA_PUEN,PA Pull-Up Enable Control Register" bitfld.long 0x10 15. "PUEN15,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 14. "PUEN14,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 13. "PUEN13,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 12. "PUEN12,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 11. "PUEN11,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 10. "PUEN10,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 9. "PUEN9,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 8. "PUEN8,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 7. "PUEN7,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 6. "PUEN6,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 5. "PUEN5,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 4. "PUEN4,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 3. "PUEN3,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 2. "PUEN2,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 1. "PUEN1,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 0. "PUEN0,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" rgroup.long 0x28++0x3 line.long 0x0 "PA_INTSTS,PA Interrupt Status" bitfld.long 0x0 31. "RHISTS15,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 30. "RHISTS14,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 29. "RHISTS13,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 28. "RHISTS12,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 27. "RHISTS11,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 26. "RHISTS10,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 25. "RHISTS9,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 24. "RHISTS8,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 23. "RHISTS7,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 22. "RHISTS6,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 21. "RHISTS5,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 20. "RHISTS4,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 19. "RHISTS3,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 18. "RHISTS2,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 17. "RHISTS1,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 16. "RHISTS0,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 15. "FLISTS15,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 14. "FLISTS14,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 13. "FLISTS13,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 12. "FLISTS12,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 11. "FLISTS11,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 10. "FLISTS10,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 9. "FLISTS9,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 8. "FLISTS8,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 7. "FLISTS7,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 6. "FLISTS6,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 5. "FLISTS5,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 4. "FLISTS4,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 3. "FLISTS3,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 2. "FLISTS2,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 1. "FLISTS1,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 0. "FLISTS0,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" group.long 0x40++0xF line.long 0x0 "PB_MODE,PB I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PB_DOUT,PB Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PB_DATMSK,PB Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DMASK14,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DMASK13,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DMASK12,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DMASK11,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DMASK10,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DMASK9,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DMASK8,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DMASK7,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DMASK6,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DMASK5,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DMASK4,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DMASK3,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DMASK2,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DMASK1,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DMASK0,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x50++0x3 line.long 0x0 "PB_PIN,PB Pin Value" bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" group.long 0x54++0x13 line.long 0x0 "PB_DBEN,PB De-Bounce Enable Control Register" bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register" bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" line.long 0xC "PB_INTSRC,PB Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." line.long 0x10 "PB_PUEN,PB Pull-Up Enable Control Register" bitfld.long 0x10 15. "PUEN15,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 14. "PUEN14,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 13. "PUEN13,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 12. "PUEN12,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 11. "PUEN11,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 10. "PUEN10,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 9. "PUEN9,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 8. "PUEN8,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 7. "PUEN7,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 6. "PUEN6,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 5. "PUEN5,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 4. "PUEN4,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 3. "PUEN3,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 2. "PUEN2,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 1. "PUEN1,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 0. "PUEN0,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" rgroup.long 0x68++0x3 line.long 0x0 "PB_INTSTS,PB Interrupt Status" bitfld.long 0x0 31. "RHISTS15,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 30. "RHISTS14,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 29. "RHISTS13,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 28. "RHISTS12,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 27. "RHISTS11,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 26. "RHISTS10,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 25. "RHISTS9,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 24. "RHISTS8,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 23. "RHISTS7,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 22. "RHISTS6,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 21. "RHISTS5,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 20. "RHISTS4,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 19. "RHISTS3,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 18. "RHISTS2,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 17. "RHISTS1,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 16. "RHISTS0,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 15. "FLISTS15,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 14. "FLISTS14,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 13. "FLISTS13,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 12. "FLISTS12,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 11. "FLISTS11,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 10. "FLISTS10,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 9. "FLISTS9,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 8. "FLISTS8,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 7. "FLISTS7,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 6. "FLISTS6,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 5. "FLISTS5,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 4. "FLISTS4,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 3. "FLISTS3,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 2. "FLISTS2,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 1. "FLISTS1,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 0. "FLISTS0,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" group.long 0x80++0xF line.long 0x0 "PC_MODE,PC I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PC_DOUT,PC Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PC_DATMSK,PC Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DMASK14,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DMASK13,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DMASK12,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DMASK11,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DMASK10,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DMASK9,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DMASK8,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DMASK7,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DMASK6,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DMASK5,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DMASK4,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DMASK3,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DMASK2,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DMASK1,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DMASK0,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x90++0x3 line.long 0x0 "PC_PIN,PC Pin Value" bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" group.long 0x94++0x13 line.long 0x0 "PC_DBEN,PC De-Bounce Enable Control Register" bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register" bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" line.long 0xC "PC_INTSRC,PC Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." line.long 0x10 "PC_PUEN,PC Pull-Up Enable Control Register" bitfld.long 0x10 15. "PUEN15,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 14. "PUEN14,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 13. "PUEN13,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 12. "PUEN12,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 11. "PUEN11,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 10. "PUEN10,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 9. "PUEN9,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 8. "PUEN8,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 7. "PUEN7,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 6. "PUEN6,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 5. "PUEN5,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 4. "PUEN4,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 3. "PUEN3,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 2. "PUEN2,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 1. "PUEN1,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 0. "PUEN0,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" rgroup.long 0xA8++0x3 line.long 0x0 "PC_INTSTS,PC Interrupt Status" bitfld.long 0x0 31. "RHISTS15,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 30. "RHISTS14,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 29. "RHISTS13,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 28. "RHISTS12,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 27. "RHISTS11,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 26. "RHISTS10,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 25. "RHISTS9,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 24. "RHISTS8,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 23. "RHISTS7,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 22. "RHISTS6,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 21. "RHISTS5,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 20. "RHISTS4,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 19. "RHISTS3,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 18. "RHISTS2,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 17. "RHISTS1,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 16. "RHISTS0,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 15. "FLISTS15,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 14. "FLISTS14,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 13. "FLISTS13,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 12. "FLISTS12,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 11. "FLISTS11,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 10. "FLISTS10,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 9. "FLISTS9,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 8. "FLISTS8,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 7. "FLISTS7,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 6. "FLISTS6,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 5. "FLISTS5,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 4. "FLISTS4,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 3. "FLISTS3,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 2. "FLISTS2,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 1. "FLISTS1,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 0. "FLISTS0,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" group.long 0xC0++0xF line.long 0x0 "PD_MODE,PD I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PD_DOUT,PD Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PD_DATMSK,PD Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DMASK14,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DMASK13,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DMASK12,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DMASK11,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DMASK10,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DMASK9,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DMASK8,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DMASK7,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DMASK6,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DMASK5,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DMASK4,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DMASK3,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DMASK2,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DMASK1,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DMASK0,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0xD0++0x3 line.long 0x0 "PD_PIN,PD Pin Value" bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" group.long 0xD4++0x13 line.long 0x0 "PD_DBEN,PD De-Bounce Enable Control Register" bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PD_INTEN,PD Interrupt Enable Control Register" bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" line.long 0xC "PD_INTSRC,PD Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." line.long 0x10 "PD_PUEN,PD Pull-Up Enable Control Register" bitfld.long 0x10 15. "PUEN15,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 14. "PUEN14,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 13. "PUEN13,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 12. "PUEN12,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 11. "PUEN11,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 10. "PUEN10,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 9. "PUEN9,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 8. "PUEN8,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 7. "PUEN7,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 6. "PUEN6,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 5. "PUEN5,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 4. "PUEN4,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 3. "PUEN3,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 2. "PUEN2,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 1. "PUEN1,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 0. "PUEN0,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" rgroup.long 0xE8++0x3 line.long 0x0 "PD_INTSTS,PD Interrupt Status" bitfld.long 0x0 31. "RHISTS15,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 30. "RHISTS14,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 29. "RHISTS13,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 28. "RHISTS12,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 27. "RHISTS11,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 26. "RHISTS10,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 25. "RHISTS9,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 24. "RHISTS8,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 23. "RHISTS7,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 22. "RHISTS6,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 21. "RHISTS5,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 20. "RHISTS4,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 19. "RHISTS3,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 18. "RHISTS2,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 17. "RHISTS1,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 16. "RHISTS0,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 15. "FLISTS15,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 14. "FLISTS14,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 13. "FLISTS13,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 12. "FLISTS12,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 11. "FLISTS11,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 10. "FLISTS10,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 9. "FLISTS9,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 8. "FLISTS8,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 7. "FLISTS7,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 6. "FLISTS6,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 5. "FLISTS5,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 4. "FLISTS4,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 3. "FLISTS3,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 2. "FLISTS2,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 1. "FLISTS1,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 0. "FLISTS0,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" group.long 0x100++0xF line.long 0x0 "PE_MODE,PE I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PE_DINOFF,PE Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PE_DOUT,PE Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PE_DATMSK,PE Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DMASK14,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DMASK13,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DMASK12,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DMASK11,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DMASK10,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DMASK9,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DMASK8,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DMASK7,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DMASK6,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DMASK5,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DMASK4,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DMASK3,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DMASK2,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DMASK1,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DMASK0,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x110++0x3 line.long 0x0 "PE_PIN,PE Pin Value" bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" group.long 0x114++0x13 line.long 0x0 "PE_DBEN,PE De-Bounce Enable Control Register" bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PE_INTTYPE,PE Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PE_INTEN,PE Interrupt Enable Control Register" bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" line.long 0xC "PE_INTSRC,PE Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." line.long 0x10 "PE_PUEN,PE Pull-Up Enable Control Register" bitfld.long 0x10 15. "PUEN15,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 14. "PUEN14,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 13. "PUEN13,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 12. "PUEN12,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 11. "PUEN11,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 10. "PUEN10,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 9. "PUEN9,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 8. "PUEN8,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 7. "PUEN7,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 6. "PUEN6,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 5. "PUEN5,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 4. "PUEN4,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 3. "PUEN3,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 2. "PUEN2,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 1. "PUEN1,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 0. "PUEN0,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" rgroup.long 0x128++0x3 line.long 0x0 "PE_INTSTS,PE Interrupt Status" bitfld.long 0x0 31. "RHISTS15,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 30. "RHISTS14,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 29. "RHISTS13,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 28. "RHISTS12,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 27. "RHISTS11,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 26. "RHISTS10,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 25. "RHISTS9,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 24. "RHISTS8,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 23. "RHISTS7,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 22. "RHISTS6,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 21. "RHISTS5,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 20. "RHISTS4,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 19. "RHISTS3,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 18. "RHISTS2,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 17. "RHISTS1,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 16. "RHISTS0,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 15. "FLISTS15,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 14. "FLISTS14,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 13. "FLISTS13,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 12. "FLISTS12,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 11. "FLISTS11,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 10. "FLISTS10,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 9. "FLISTS9,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 8. "FLISTS8,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 7. "FLISTS7,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 6. "FLISTS6,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 5. "FLISTS5,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 4. "FLISTS4,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 3. "FLISTS3,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 2. "FLISTS2,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 1. "FLISTS1,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 0. "FLISTS0,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" group.long 0x140++0xF line.long 0x0 "PF_MODE,PF I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n.." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?" line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.." line.long 0x8 "PF_DOUT,PF Data Output Value" bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." line.long 0xC "PF_DATMSK,PF Data Output Write Mask" bitfld.long 0xC 15. "DMASK15,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 14. "DMASK14,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 13. "DMASK13,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 12. "DMASK12,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 11. "DMASK11,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 10. "DMASK10,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 9. "DMASK9,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 8. "DMASK8,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 7. "DMASK7,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 6. "DMASK6,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 5. "DMASK5,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 4. "DMASK4,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 3. "DMASK3,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 2. "DMASK2,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0xC 1. "DMASK1,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0xC 0. "DMASK0,Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x150++0x3 line.long 0x0 "PF_PIN,PF Pin Value" bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" newline bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is.." "0,1" group.long 0x154++0x13 line.long 0x0 "PF_DBEN,PF De-Bounce Enable Control Register" bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control" bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "PF_INTEN,PF Interrupt Enable Control Register" bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled" newline bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled" line.long 0xC "PF_INTSRC,PF Interrupt Source Flag" bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." newline bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag\nWrite Operation.." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.." line.long 0x10 "PF_PUEN,PF Pull-Up Enable Control Register" bitfld.long 0x10 15. "PUEN15,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 14. "PUEN14,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 13. "PUEN13,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 12. "PUEN12,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 11. "PUEN11,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 10. "PUEN10,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 9. "PUEN9,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 8. "PUEN8,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 7. "PUEN7,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 6. "PUEN6,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 5. "PUEN5,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 4. "PUEN4,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 3. "PUEN3,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 2. "PUEN2,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" newline bitfld.long 0x10 1. "PUEN1,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" bitfld.long 0x10 0. "PUEN0,Port A-f Pin[N]Pull-up Enable Bit\nRead :\nNote2:\nThePA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is.." "0: Px.n internal pull-up resistor Disabled,1: Px.n internal pull-up resistor Enabled" rgroup.long 0x168++0x3 line.long 0x0 "PF_INTSTS,PF Interrupt Status" bitfld.long 0x0 31. "RHISTS15,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 30. "RHISTS14,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 29. "RHISTS13,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 28. "RHISTS12,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 27. "RHISTS11,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 26. "RHISTS10,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 25. "RHISTS9,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 24. "RHISTS8,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 23. "RHISTS7,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 22. "RHISTS6,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 21. "RHISTS5,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 20. "RHISTS4,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 19. "RHISTS3,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 18. "RHISTS2,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 17. "RHISTS1,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" bitfld.long 0x0 16. "RHISTS0,Port A-f Pin[N] Rising Edge Interrupt Status \nIf the interrupt is rising edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No rising edge interrupt at Px.n,1: Px.n generates an rising edge interrupt" newline bitfld.long 0x0 15. "FLISTS15,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 14. "FLISTS14,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 13. "FLISTS13,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 12. "FLISTS12,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 11. "FLISTS11,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 10. "FLISTS10,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 9. "FLISTS9,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 8. "FLISTS8,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 7. "FLISTS7,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 6. "FLISTS6,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 5. "FLISTS5,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 4. "FLISTS4,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 3. "FLISTS3,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 2. "FLISTS2,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" newline bitfld.long 0x0 1. "FLISTS1,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" bitfld.long 0x0 0. "FLISTS0,Port A-f Pin[N] Falling Edge Interrupt Status\nIf the interrupt is falling edge trigger for each of the corresponding input Px.n pin this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC.." "0: No falling edge interrupt at Px.n,1: Px.n generates an falling edge interrupt" group.long 0x180++0x3 line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control Register" bitfld.long 0x0 5. "ICLKON,Interrupt Clock on Mode\nNote:It is recommended to disable this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.." bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.." newline hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection" group.long 0x200++0x13B line.long 0x0 "PA0_PDIO,GPIO PA.0 Pin Data Input/Output Register" bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PA1_PDIO,GPIO PA.1 Pin Data Input/Output Register" bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PA2_PDIO,GPIO PA.2 Pin Data Input/Output Register" bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PA3_PDIO,GPIO PA.3 Pin Data Input/Output Register" bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PA4_PDIO,GPIO PA.4 Pin Data Input/Output Register" bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PA5_PDIO,GPIO PA.5 Pin Data Input/Output Register" bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PA6_PDIO,GPIO PA.6 Pin Data Input/Output Register" bitfld.long 0x18 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PA7_PDIO,GPIO PA.7 Pin Data Input/Output Register" bitfld.long 0x1C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x20 "PA8_PDIO,GPIO PA.8 Pin Data Input/Output Register" bitfld.long 0x20 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x24 "PA9_PDIO,GPIO PA.9 Pin Data Input/Output Register" bitfld.long 0x24 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x28 "PA10_PDIO,GPIO PA.10 Pin Data Input/Output Register" bitfld.long 0x28 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x2C "PA11_PDIO,GPIO PA.11 Pin Data Input/Output Register" bitfld.long 0x2C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x30 "PA12_PDIO,GPIO PA.12 Pin Data Input/Output Register" bitfld.long 0x30 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x34 "PA13_PDIO,GPIO PA.13 Pin Data Input/Output Register" bitfld.long 0x34 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x38 "PA14_PDIO,GPIO PA.14 Pin Data Input/Output Register" bitfld.long 0x38 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x3C "PA15_PDIO,GPIO PA.15 Pin Data Input/Output Register" bitfld.long 0x3C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x40 "PB0_PDIO,GPIO PB.0 Pin Data Input/Output Register" bitfld.long 0x40 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x44 "PB1_PDIO,GPIO PB.1 Pin Data Input/Output Register" bitfld.long 0x44 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x48 "PB2_PDIO,GPIO PB.2 Pin Data Input/Output Register" bitfld.long 0x48 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4C "PB3_PDIO,GPIO PB.3 Pin Data Input/Output Register" bitfld.long 0x4C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x50 "PB4_PDIO,GPIO PB.4 Pin Data Input/Output Register" bitfld.long 0x50 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x54 "PB5_PDIO,GPIO PB.5 Pin Data Input/Output Register" bitfld.long 0x54 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x58 "PB6_PDIO,GPIO PB.6 Pin Data Input/Output Register" bitfld.long 0x58 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x5C "PB7_PDIO,GPIO PB.7 Pin Data Input/Output Register" bitfld.long 0x5C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x60 "PB8_PDIO,GPIO PB.8 Pin Data Input/Output Register" bitfld.long 0x60 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x64 "PB9_PDIO,GPIO PB.9 Pin Data Input/Output Register" bitfld.long 0x64 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x68 "PB10_PDIO,GPIO PB.10 Pin Data Input/Output Register" bitfld.long 0x68 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x6C "PB11_PDIO,GPIO PB.11 Pin Data Input/Output Register" bitfld.long 0x6C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x70 "PB12_PDIO,GPIO PB.12 Pin Data Input/Output Register" bitfld.long 0x70 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x74 "PB13_PDIO,GPIO PB.13 Pin Data Input/Output Register" bitfld.long 0x74 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x78 "PB14_PDIO,GPIO PB.14 Pin Data Input/Output Register" bitfld.long 0x78 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x7C "PB15_PDIO,GPIO PB.15 Pin Data Input/Output Register" bitfld.long 0x7C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x80 "PC0_PDIO,GPIO PC.0 Pin Data Input/Output Register" bitfld.long 0x80 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x84 "PC1_PDIO,GPIO PC.1 Pin Data Input/Output Register" bitfld.long 0x84 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x88 "PC2_PDIO,GPIO PC.2 Pin Data Input/Output Register" bitfld.long 0x88 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8C "PC3_PDIO,GPIO PC.3 Pin Data Input/Output Register" bitfld.long 0x8C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x90 "PC4_PDIO,GPIO PC.4 Pin Data Input/Output Register" bitfld.long 0x90 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x94 "PC5_PDIO,GPIO PC.5 Pin Data Input/Output Register" bitfld.long 0x94 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x98 "PC6_PDIO,GPIO PC.6 Pin Data Input/Output Register" bitfld.long 0x98 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x9C "PC7_PDIO,GPIO PC.7 Pin Data Input/Output Register" bitfld.long 0x9C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA0 "PC8_PDIO,GPIO PC.8 Pin Data Input/Output Register" bitfld.long 0xA0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA4 "PC9_PDIO,GPIO PC.9 Pin Data Input/Output Register" bitfld.long 0xA4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xA8 "PC10_PDIO,GPIO PC.10 Pin Data Input/Output Register" bitfld.long 0xA8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xAC "PC11_PDIO,GPIO PC.11 Pin Data Input/Output Register" bitfld.long 0xAC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB0 "PC12_PDIO,GPIO PC.12 Pin Data Input/Output Register" bitfld.long 0xB0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB4 "PC13_PDIO,GPIO PC.13 Pin Data Input/Output Register" bitfld.long 0xB4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xB8 "PC14_PDIO,GPIO PC.14 Pin Data Input/Output Register" bitfld.long 0xB8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xBC "PC15_PDIO,GPIO PC.15 Pin Data Input/Output Register" bitfld.long 0xBC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC0 "PD0_PDIO,GPIO PD.0 Pin Data Input/Output Register" bitfld.long 0xC0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC4 "PD1_PDIO,GPIO PD.1 Pin Data Input/Output Register" bitfld.long 0xC4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC8 "PD2_PDIO,GPIO PD.2 Pin Data Input/Output Register" bitfld.long 0xC8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xCC "PD3_PDIO,GPIO PD.3 Pin Data Input/Output Register" bitfld.long 0xCC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xD0 "PD4_PDIO,GPIO PD.4 Pin Data Input/Output Register" bitfld.long 0xD0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xD4 "PD5_PDIO,GPIO PD.5 Pin Data Input/Output Register" bitfld.long 0xD4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xD8 "PD6_PDIO,GPIO PD.6 Pin Data Input/Output Register" bitfld.long 0xD8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xDC "PD7_PDIO,GPIO PD.7 Pin Data Input/Output Register" bitfld.long 0xDC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xE0 "PD8_PDIO,GPIO PD.8 Pin Data Input/Output Register" bitfld.long 0xE0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xE4 "PD9_PDIO,GPIO PD.9 Pin Data Input/Output Register" bitfld.long 0xE4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xE8 "PD10_PDIO,GPIO PD.10 Pin Data Input/Output Register" bitfld.long 0xE8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xEC "PD11_PDIO,GPIO PD.11 Pin Data Input/Output Register" bitfld.long 0xEC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xF0 "PD12_PDIO,GPIO PD.12 Pin Data Input/Output Register" bitfld.long 0xF0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xF4 "PD13_PDIO,GPIO PD.13 Pin Data Input/Output Register" bitfld.long 0xF4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xF8 "PD14_PDIO,GPIO PD.14 Pin Data Input/Output Register" bitfld.long 0xF8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xFC "PD15_PDIO,GPIO PD.15 Pin Data Input/Output Register" bitfld.long 0xFC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x100 "PE0_PDIO,GPIO PE.0 Pin Data Input/Output Register" bitfld.long 0x100 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x104 "PE1_PDIO,GPIO PE.1 Pin Data Input/Output Register" bitfld.long 0x104 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x108 "PE2_PDIO,GPIO PE.2 Pin Data Input/Output Register" bitfld.long 0x108 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10C "PE3_PDIO,GPIO PE.3 Pin Data Input/Output Register" bitfld.long 0x10C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x110 "PE4_PDIO,GPIO PE.4 Pin Data Input/Output Register" bitfld.long 0x110 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x114 "PE5_PDIO,GPIO PE.5 Pin Data Input/Output Register" bitfld.long 0x114 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x118 "PE6_PDIO,GPIO PE.6 Pin Data Input/Output Register" bitfld.long 0x118 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x11C "PE7_PDIO,GPIO PE.7 Pin Data Input/Output Register" bitfld.long 0x11C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x120 "PE8_PDIO,GPIO PE.8 Pin Data Input/Output Register" bitfld.long 0x120 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x124 "PE9_PDIO,GPIO PE.9 Pin Data Input/Output Register" bitfld.long 0x124 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x128 "PE10_PDIO,GPIO PE.10 Pin Data Input/Output Register" bitfld.long 0x128 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x12C "PE11_PDIO,GPIO PE.11 Pin Data Input/Output Register" bitfld.long 0x12C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x130 "PE12_PDIO,GPIO PE.12 Pin Data Input/Output Register" bitfld.long 0x130 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x134 "PE13_PDIO,GPIO PE.13 Pin Data Input/Output Register" bitfld.long 0x134 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x138 "PE14_PDIO,GPIO PE.14 Pin Data Input/Output Register" bitfld.long 0x138 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x340++0x1F line.long 0x0 "PF0_PDIO,GPIO PF.0 Pin Data Input/Output Register" bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x4 "PF1_PDIO,GPIO PF.1 Pin Data Input/Output Register" bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x8 "PF2_PDIO,GPIO PF.2 Pin Data Input/Output Register" bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0xC "PF3_PDIO,GPIO PF.3 Pin Data Input/Output Register" bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x10 "PF4_PDIO,GPIO PF.4 Pin Data Input/Output Register" bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x14 "PF5_PDIO,GPIO PF.5 Pin Data Input/Output Register" bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x18 "PF6_PDIO,GPIO PF.6 Pin Data Input/Output Register" bitfld.long 0x18 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" line.long 0x1C "PF7_PDIO,GPIO PF.7 Pin Data Input/Output Register" bitfld.long 0x1C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" tree.end tree "I2C (I2C Serial Interface Controller)" base ad:0x0 tree "I2C0" base ad:0x40020000 group.long 0x0++0x7 line.long 0x0 "I2C_CTL,I2C Control Register" bitfld.long 0x0 7. "INTEN,Interrupt EnableBit" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 4. "SI,I2C Status\nWhen a new state is present in the I2C_STATUS register if the INTEN bit is set the I2C interrupt is requested. It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go.." "0: I2C's Status disabled and the I2C protocol..,1: I2C's Status active" newline bitfld.long 0x0 3. "STA,I2C START Command\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 2. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1" newline bitfld.long 0x0 1. "AA,Assert Acknowledge Control Bit" "0,1" bitfld.long 0x0 0. "I2CEN,I2C Function EnableBit" "0: I2C function Disabled,1: I2C function Enabled" line.long 0x4 "I2C_INTSTS,I2C Interrupt Status Register" bitfld.long 0x4 7. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote:This bit can be cleared by writing'1' toit." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.." bitfld.long 0x4 1. "TOIF,Time-out Status\nNote:This bit can be cleared by writing '1' to it." "0: No Time-out flag,1: Time-out flag active and it is set by hardware." newline bitfld.long 0x4 0. "INTSTS,I2C STATUS's Interrupt Status\nWhen a new I2C state is present in the I2C_STATUS register the INTSTS flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested.This bit must be cleared by software writing '1'.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "I2C_STATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Bits (Read Only)" group.long 0xC++0x13 line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock DividedBits\nNote:The minimum value of I2C_CLKDIV is 4." line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register" bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divider by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out counter input clock divider by 4Disabled,1: Time-out counter input clock divider by 4 Enabled" bitfld.long 0x4 0. "TOCEN,Time-out Counter Enable Bit\nWhen this bit is set to enabled and clcok be stretched the 14 bits time-out counter will start counting." "0: Time-out counter Disabled,1: Time-out counter Enabled" line.long 0x8 "I2C_DAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data\nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port." line.long 0xC "I2C_ADDR0,I2C Slave Address Register0" hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call FunctionControl\nNote: Refer to Address Register section for more detailed information.." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2C_ADDR1,I2C Slave Address Register1" hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call FunctionControl\nNote: Refer to Address Register section for more detailed information.." "0: General Call Function Disabled,1: General Call Function Enabled" group.long 0x28++0x7 line.long 0x0 "I2C_ADDRMSK0,I2C Slave Address Mask Register0" hexmask.long.byte 0x0 1.--7. 1. "ADDRMSK,I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x4 "I2C_ADDRMSK1,I2C Slave Address Mask Register1" hexmask.long.byte 0x4 1.--7. 1. "ADDRMSK,I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." group.long 0x40++0x7 line.long 0x0 "I2C_CTL2,I2C Control Register 2" bitfld.long 0x0 7. "MSDAT,Master or Slave in Data Mode Enable Control" "0: Master writes data to device,1: Slave reads data from device" bitfld.long 0x0 6. "DATMODE,Data Mode Enable Bit" "0: Data mode Disabled,1: Data mode Enabled" newline bitfld.long 0x0 5. "NOSTRETCH,I2C BuS Stretch" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.." bitfld.long 0x0 4. "TWOLVBUF,Two Level Buffer Enable Bit" "0: Two level bufferDisabled,1: Two level bufferEnabled" newline bitfld.long 0x0 2. "URIEN,I2C Underrun Interrupt Control Bit" "0: Underrun event interrupt Disabled,1: Send a interrupt to system when theTWOLVBUF bit.." bitfld.long 0x0 1. "OVIEN,I2C Overrun Interrupt Control Bit" "0: Overrun event interrupt Disabled,1: Send a interrupt to system when the TWOLVBUF bit.." newline bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function EnableBit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2C_STATUS2,I2C Status Register 2" bitfld.long 0x4 6. "BUSFREE,Bus Free Status\nThe bus status in the controller." "0: I2C's 'Start' condition is detected on the bus,1: Bus is free and released by 'STOP' condition or.." bitfld.long 0x4 5. "EMPTY,I2C Two Level Buffer Empty" "0: RX buffer is not empty when the TWOLVBUF = 1,1: RX buffer is empty when the TWOLVBUF = 1" newline bitfld.long 0x4 4. "FULL,I2C Two Level Buffer Full" "0: TX buffer no full when the TWOLVBUF = 1,1: TX buffer full when the TWOLVBUF = 1" bitfld.long 0x4 3. "WRSTSWK,I2C Read/Write Status Bit in Address Wake-up Frame" "0: Write command is recorded on the address match..,1: Read command is recorded on the address match.." newline bitfld.long 0x4 2. "URIF,I2C Underrun Status Bit\nNote:This bit can be cleared by writing '1' toit." "0: The transmitted buffer is not underrun when the..,1: The transmitted buffer is underrun when the.." bitfld.long 0x4 1. "OVIF,I2C Overrun Status Bit\nNote:This bit can be cleared by writing '1' toit." "0: The received buffer is not overrun when the..,1: The received buffer is overrun when the TWOLVBUF.." newline bitfld.long 0x4 0. "WKIF,Wake-up Interrupt Flag\nNote:This bit can be cleared by writing '1' toit." "0: Wake-up flag is inactive,1: Wake-up flag is active" tree.end tree "I2C1" base ad:0x40120000 group.long 0x0++0x7 line.long 0x0 "I2C_CTL,I2C Control Register" bitfld.long 0x0 7. "INTEN,Interrupt EnableBit" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 4. "SI,I2C Status\nWhen a new state is present in the I2C_STATUS register if the INTEN bit is set the I2C interrupt is requested. It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go.." "0: I2C's Status disabled and the I2C protocol..,1: I2C's Status active" newline bitfld.long 0x0 3. "STA,I2C START Command\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1" bitfld.long 0x0 2. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1" newline bitfld.long 0x0 1. "AA,Assert Acknowledge Control Bit" "0,1" bitfld.long 0x0 0. "I2CEN,I2C Function EnableBit" "0: I2C function Disabled,1: I2C function Enabled" line.long 0x4 "I2C_INTSTS,I2C Interrupt Status Register" bitfld.long 0x4 7. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote:This bit can be cleared by writing'1' toit." "0: The ACK bit cycle of address match frame is not..,1: The ACK bit cycle of address match frame is done.." bitfld.long 0x4 1. "TOIF,Time-out Status\nNote:This bit can be cleared by writing '1' to it." "0: No Time-out flag,1: Time-out flag active and it is set by hardware." newline bitfld.long 0x4 0. "INTSTS,I2C STATUS's Interrupt Status\nWhen a new I2C state is present in the I2C_STATUS register the INTSTS flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested.This bit must be cleared by software writing '1'.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "I2C_STATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Bits (Read Only)" group.long 0xC++0x13 line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock DividedBits\nNote:The minimum value of I2C_CLKDIV is 4." line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register" bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divider by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out counter input clock divider by 4Disabled,1: Time-out counter input clock divider by 4 Enabled" bitfld.long 0x4 0. "TOCEN,Time-out Counter Enable Bit\nWhen this bit is set to enabled and clcok be stretched the 14 bits time-out counter will start counting." "0: Time-out counter Disabled,1: Time-out counter Enabled" line.long 0x8 "I2C_DAT,I2C Data Register" hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data\nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port." line.long 0xC "I2C_ADDR0,I2C Slave Address Register0" hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0xC 0. "GC,General Call FunctionControl\nNote: Refer to Address Register section for more detailed information.." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2C_ADDR1,I2C Slave Address Register1" hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0x10 0. "GC,General Call FunctionControl\nNote: Refer to Address Register section for more detailed information.." "0: General Call Function Disabled,1: General Call Function Enabled" group.long 0x28++0x7 line.long 0x0 "I2C_ADDRMSK0,I2C Slave Address Mask Register0" hexmask.long.byte 0x0 1.--7. 1. "ADDRMSK,I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." line.long 0x4 "I2C_ADDRMSK1,I2C Slave Address Mask Register1" hexmask.long.byte 0x4 1.--7. 1. "ADDRMSK,I2C Slave Address Mask Bits\nI2C bus controllers support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.." group.long 0x40++0x7 line.long 0x0 "I2C_CTL2,I2C Control Register 2" bitfld.long 0x0 7. "MSDAT,Master or Slave in Data Mode Enable Control" "0: Master writes data to device,1: Slave reads data from device" bitfld.long 0x0 6. "DATMODE,Data Mode Enable Bit" "0: Data mode Disabled,1: Data mode Enabled" newline bitfld.long 0x0 5. "NOSTRETCH,I2C BuS Stretch" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.." bitfld.long 0x0 4. "TWOLVBUF,Two Level Buffer Enable Bit" "0: Two level bufferDisabled,1: Two level bufferEnabled" newline bitfld.long 0x0 2. "URIEN,I2C Underrun Interrupt Control Bit" "0: Underrun event interrupt Disabled,1: Send a interrupt to system when theTWOLVBUF bit.." bitfld.long 0x0 1. "OVIEN,I2C Overrun Interrupt Control Bit" "0: Overrun event interrupt Disabled,1: Send a interrupt to system when the TWOLVBUF bit.." newline bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function EnableBit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" line.long 0x4 "I2C_STATUS2,I2C Status Register 2" bitfld.long 0x4 6. "BUSFREE,Bus Free Status\nThe bus status in the controller." "0: I2C's 'Start' condition is detected on the bus,1: Bus is free and released by 'STOP' condition or.." bitfld.long 0x4 5. "EMPTY,I2C Two Level Buffer Empty" "0: RX buffer is not empty when the TWOLVBUF = 1,1: RX buffer is empty when the TWOLVBUF = 1" newline bitfld.long 0x4 4. "FULL,I2C Two Level Buffer Full" "0: TX buffer no full when the TWOLVBUF = 1,1: TX buffer full when the TWOLVBUF = 1" bitfld.long 0x4 3. "WRSTSWK,I2C Read/Write Status Bit in Address Wake-up Frame" "0: Write command is recorded on the address match..,1: Read command is recorded on the address match.." newline bitfld.long 0x4 2. "URIF,I2C Underrun Status Bit\nNote:This bit can be cleared by writing '1' toit." "0: The transmitted buffer is not underrun when the..,1: The transmitted buffer is underrun when the.." bitfld.long 0x4 1. "OVIF,I2C Overrun Status Bit\nNote:This bit can be cleared by writing '1' toit." "0: The received buffer is not overrun when the..,1: The received buffer is overrun when the TWOLVBUF.." newline bitfld.long 0x4 0. "WKIF,Wake-up Interrupt Flag\nNote:This bit can be cleared by writing '1' toit." "0: Wake-up flag is inactive,1: Wake-up flag is active" tree.end tree.end tree "PDMA (Peripheral Direct Memory Access)" base ad:0x0 tree "CRC" base ad:0x50008E00 group.long 0x0++0x7 line.long 0x0 "CRC_CTL,CRC Control Register" bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode." "0: CRC-CCITT Polynomial Mode,1: CRC-8 Polynomial Mode,?,?" bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the CPU write data length only when operating in CPU mode.\nNote1: This field is only valid when operating in CPU mode.\nNote2: When the write data length is 8-bit mode the valid data in CRC_DAT.." "0: The write data length is 8-bit mode,1: This field is only valid when operating in CPU..,2: When the write data length is 8-bit mode,?" newline bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register." "0: 1's complementfor CRC checksum Disabled,1: 1's complement for CRC checksum Enabled" bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DTA register." "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled" newline bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB." "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled" bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function for writing data value in CRC_DTA register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC data write in is 0x55DD33BB." "0: Bit order reverse for CRC data write in Disabled,1: Bit order reverse for CRC data write in Enabled.." newline bitfld.long 0x0 23. "TRIGEN,Trigger Enable Bit\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode do not fill in any data in CRC_DAT register.\nNote2: When CRC DMA transfer completed this.." "0: No effect,1: If this bit asserts which indicates the CRC.." bitfld.long 0x0 1. "CRCRST,CRC Engine Reset Bit\nNote1: This bit will be cleared automatically.\nNote2: When operating in CPU mode setting this bit will reload the seed value from CRC_SEED register as checksum initial value." "0: No effect,1: This bit will be cleared automatically" newline bitfld.long 0x0 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled" line.long 0x4 "CRC_DMASA,CRC DMA Source Address Register" hexmask.long 0x4 0.--31. 1. "SA,CRC DMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment." group.long 0xC++0x3 line.long 0x0 "CRC_DMABCNT,CRC DMA Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "BCNT,CRC DMA Transfer Byte Count \nThis field indicates a 16-bit total transfer byte count number of CRC DMA." rgroup.long 0x14++0x3 line.long 0x0 "CRC_DMACSA,CRC DMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CSA,CRC DMA Current Source Address Bits (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs." rgroup.long 0x1C++0x3 line.long 0x0 "CRC_DMACBCNT,CRC DMA Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "CBCNT,CRC DMA Current Remained Byte Count (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting the CRCRST (CRC_CTL[1]) bit to 1 will clear this register value." group.long 0x20++0x7 line.long 0x0 "CRC_DMAINTEN,CRC DMA Interrupt Enable Register" bitfld.long 0x0 1. "TDIEN,CRC DMA Block Transfer Done Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Transfer Done interrupt signal while TDIF (CRC_DMAINTSTS[1]) bit is set to 1." "0: Interrupt Disabled when CRC DMA transfer done,1: Interrupt Enabled when CRC DMA transfer done" bitfld.long 0x0 0. "TABTIEN,CRC DMA Read/Write Target Abort Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Target Abort interrupt signal while TABTIF (CRC_DMAINTSTS[0]) bit is set to 1." "0: Target abort interrupt Disabled during CRC DMA..,1: Target abort interrupt Enabled during CRC DMA.." line.long 0x4 "CRC_DMAISTS,CRC DMA Interrupt Status Register" bitfld.long 0x4 1. "TDIF,CRC DMA Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA transfer has finished or not.\nNote1: This bit is cleared by writing '1' to it.\nNote2: When CRC DMA transfer is done TRIGEN (CRC_CTL[23]) will be cleared automatically." "0: Not finished if TRIGEN (CRC_CTL[23]) has enabled,1: This bit is cleared by writing '1' to it" bitfld.long 0x4 0. "TABTIF,CRC DMA Read/Write Target Abort Interrupt Flag\nThis bit indicates that CRC bus has error or not during CRC DMA transfer.\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received error response or not. If.." "0: No bus error response received during CRC DMA..,1: This bit is cleared by writing '1' to it" group.long 0x80++0x7 line.long 0x0 "CRC_DAT,CRC Write Data Register" hexmask.long 0x0 0.--31. 1. "DATA,CRC Write Data Bits\nWhen operating in CPU mode user can write data to this field to perform CRC operation.\nWhen operating in DMA mode this field indicates the DMA read data from memory and cannot be written by user.\nNote: When the write data.." line.long 0x4 "CRC_SEED,CRC Seed Register" hexmask.long 0x4 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value." rgroup.long 0x88++0x3 line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register" hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result" tree.end tree "PDMA_CH1" base ad:0x50008100 group.long 0x0++0xF line.long 0x0 "PDMA_CTLn,PDMA Channel n Control Register" bitfld.long 0x0 23. "TRIGEN,Trigger Enable Bit \nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channels and then trigger again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TOUTEN,Time-out Enable Bit" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DASEL,Transfer Destination Address Direction Selection" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SASEL,Transfer Source Address Direction Selection" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 1. "SWRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "CHEN,PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAn,PDMA Channel n Source Address Register" hexmask.long 0x4 0.--31. 1. "SA,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAn,PDMA Channel n Destination Address Register" hexmask.long 0x8 0.--31. 1. "DA,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment." line.long 0xC "PDMA_CNTn,PDMA Channel n Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "PCNTITH,PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function." hexmask.long.word 0xC 0.--15. 1. "TCNT,PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAn,PDMA Channel n Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CSA,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAn,PDMA Channel n Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "CDA,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CCNTn,PDMA Channel n Current Transfer Count Register" hexmask.long.word 0x8 0.--15. 1. "CCNT,PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA." group.long 0x20++0xB line.long 0x0 "PDMA_INTENn,PDMA Channel n Interrupt Enable Register" bitfld.long 0x0 8. "PCNTIEN,Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically." "0: Periodic transfer count interrupt Disabled,1: Periodic transfer count interrupt Enabled" bitfld.long 0x0 6. "TOUTIEN,Time-out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" newline bitfld.long 0x0 1. "TDIEN,PDMA Transfer Done Interrupt Enable Bit" "0: Interrupt Disabled when PDMA transfer is done,1: Interrupt Enabled when PDMA transfer is done" bitfld.long 0x0 0. "TABTIEN,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt Disabled during PDMA..,1: Target abort interrupt Enabled during PDMA.." line.long 0x4 "PDMA_INTSTSn,PDMA Channel n Interrupt Status Register" bitfld.long 0x4 8. "PCNTIF,Periodic Count Interrupt Status Flag\nNote: This bit is cleared by writing '1' to it." "0,1" bitfld.long 0x4 6. "TOUTIF,Time-out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" newline bitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer.\nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABTIF,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received error response or not if bus master received error response it means that PDMA transfer data from.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TOCn,PDMA Channel n Time-out Counter Register" bitfld.long 0x8 16.--18. "TPSC,PDMA Time-out Counter Clock Source Prescaler" "0: PDMA time-out clock source is HCLK/28,1: PDMA time-out clock source is HCLK/29,?,?,?,?,?,?" hexmask.long.word 0x8 0.--15. 1. "TOC,PDMA Time-out Period Counter" tree.end tree "PDMA_CH2" base ad:0x50008200 group.long 0x0++0xF line.long 0x0 "PDMA_CTLn,PDMA Channel n Control Register" bitfld.long 0x0 23. "TRIGEN,Trigger Enable Bit \nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channels and then trigger again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TOUTEN,Time-out Enable Bit" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DASEL,Transfer Destination Address Direction Selection" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SASEL,Transfer Source Address Direction Selection" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 1. "SWRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "CHEN,PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAn,PDMA Channel n Source Address Register" hexmask.long 0x4 0.--31. 1. "SA,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAn,PDMA Channel n Destination Address Register" hexmask.long 0x8 0.--31. 1. "DA,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment." line.long 0xC "PDMA_CNTn,PDMA Channel n Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "PCNTITH,PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function." hexmask.long.word 0xC 0.--15. 1. "TCNT,PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAn,PDMA Channel n Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CSA,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAn,PDMA Channel n Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "CDA,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CCNTn,PDMA Channel n Current Transfer Count Register" hexmask.long.word 0x8 0.--15. 1. "CCNT,PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA." group.long 0x20++0xB line.long 0x0 "PDMA_INTENn,PDMA Channel n Interrupt Enable Register" bitfld.long 0x0 8. "PCNTIEN,Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically." "0: Periodic transfer count interrupt Disabled,1: Periodic transfer count interrupt Enabled" bitfld.long 0x0 6. "TOUTIEN,Time-out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" newline bitfld.long 0x0 1. "TDIEN,PDMA Transfer Done Interrupt Enable Bit" "0: Interrupt Disabled when PDMA transfer is done,1: Interrupt Enabled when PDMA transfer is done" bitfld.long 0x0 0. "TABTIEN,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt Disabled during PDMA..,1: Target abort interrupt Enabled during PDMA.." line.long 0x4 "PDMA_INTSTSn,PDMA Channel n Interrupt Status Register" bitfld.long 0x4 8. "PCNTIF,Periodic Count Interrupt Status Flag\nNote: This bit is cleared by writing '1' to it." "0,1" bitfld.long 0x4 6. "TOUTIF,Time-out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" newline bitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer.\nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABTIF,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received error response or not if bus master received error response it means that PDMA transfer data from.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TOCn,PDMA Channel n Time-out Counter Register" bitfld.long 0x8 16.--18. "TPSC,PDMA Time-out Counter Clock Source Prescaler" "0: PDMA time-out clock source is HCLK/28,1: PDMA time-out clock source is HCLK/29,?,?,?,?,?,?" hexmask.long.word 0x8 0.--15. 1. "TOC,PDMA Time-out Period Counter" tree.end tree "PDMA_CH3" base ad:0x50008300 group.long 0x0++0xF line.long 0x0 "PDMA_CTLn,PDMA Channel n Control Register" bitfld.long 0x0 23. "TRIGEN,Trigger Enable Bit \nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channels and then trigger again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TOUTEN,Time-out Enable Bit" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DASEL,Transfer Destination Address Direction Selection" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SASEL,Transfer Source Address Direction Selection" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 1. "SWRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "CHEN,PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAn,PDMA Channel n Source Address Register" hexmask.long 0x4 0.--31. 1. "SA,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAn,PDMA Channel n Destination Address Register" hexmask.long 0x8 0.--31. 1. "DA,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment." line.long 0xC "PDMA_CNTn,PDMA Channel n Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "PCNTITH,PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function." hexmask.long.word 0xC 0.--15. 1. "TCNT,PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAn,PDMA Channel n Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CSA,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAn,PDMA Channel n Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "CDA,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CCNTn,PDMA Channel n Current Transfer Count Register" hexmask.long.word 0x8 0.--15. 1. "CCNT,PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA." group.long 0x20++0xB line.long 0x0 "PDMA_INTENn,PDMA Channel n Interrupt Enable Register" bitfld.long 0x0 8. "PCNTIEN,Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically." "0: Periodic transfer count interrupt Disabled,1: Periodic transfer count interrupt Enabled" bitfld.long 0x0 6. "TOUTIEN,Time-out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" newline bitfld.long 0x0 1. "TDIEN,PDMA Transfer Done Interrupt Enable Bit" "0: Interrupt Disabled when PDMA transfer is done,1: Interrupt Enabled when PDMA transfer is done" bitfld.long 0x0 0. "TABTIEN,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt Disabled during PDMA..,1: Target abort interrupt Enabled during PDMA.." line.long 0x4 "PDMA_INTSTSn,PDMA Channel n Interrupt Status Register" bitfld.long 0x4 8. "PCNTIF,Periodic Count Interrupt Status Flag\nNote: This bit is cleared by writing '1' to it." "0,1" bitfld.long 0x4 6. "TOUTIF,Time-out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" newline bitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer.\nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABTIF,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received error response or not if bus master received error response it means that PDMA transfer data from.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TOCn,PDMA Channel n Time-out Counter Register" bitfld.long 0x8 16.--18. "TPSC,PDMA Time-out Counter Clock Source Prescaler" "0: PDMA time-out clock source is HCLK/28,1: PDMA time-out clock source is HCLK/29,?,?,?,?,?,?" hexmask.long.word 0x8 0.--15. 1. "TOC,PDMA Time-out Period Counter" tree.end tree "PDMA_CH4" base ad:0x50008400 group.long 0x0++0xF line.long 0x0 "PDMA_CTLn,PDMA Channel n Control Register" bitfld.long 0x0 23. "TRIGEN,Trigger Enable Bit \nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channels and then trigger again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TOUTEN,Time-out Enable Bit" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DASEL,Transfer Destination Address Direction Selection" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SASEL,Transfer Source Address Direction Selection" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 1. "SWRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.." newline bitfld.long 0x0 0. "CHEN,PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state." "0,1" line.long 0x4 "PDMA_SAn,PDMA Channel n Source Address Register" hexmask.long 0x4 0.--31. 1. "SA,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAn,PDMA Channel n Destination Address Register" hexmask.long 0x8 0.--31. 1. "DA,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote: The Destination address must be word alignment." line.long 0xC "PDMA_CNTn,PDMA Channel n Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "PCNTITH,PDMA Periodic Count Interrupt Threshold\nThis field indicates how many data transferred to generate periodic interrupt\nNote: write 0 to this field to disable this function." hexmask.long.word 0xC 0.--15. 1. "TCNT,PDMA Transfer Count Bits\nThis field indicates a 16-bit transfer count number of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAn,PDMA Channel n Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CSA,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAn,PDMA Channel n Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "CDA,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CCNTn,PDMA Channel n Current Transfer Count Register" hexmask.long.word 0x8 0.--15. 1. "CCNT,PDMA Current Count Bits (Read Only)\nThis field indicates the current remained transfer count of PDMA." group.long 0x20++0xB line.long 0x0 "PDMA_INTENn,PDMA Channel n Interrupt Enable Register" bitfld.long 0x0 8. "PCNTIEN,Periodic Count Interrupt Enable Bit\nThis field indicates how many data transferred to generate interrupt periodically." "0: Periodic transfer count interrupt Disabled,1: Periodic transfer count interrupt Enabled" bitfld.long 0x0 6. "TOUTIEN,Time-out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" newline bitfld.long 0x0 1. "TDIEN,PDMA Transfer Done Interrupt Enable Bit" "0: Interrupt Disabled when PDMA transfer is done,1: Interrupt Enabled when PDMA transfer is done" bitfld.long 0x0 0. "TABTIEN,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt Disabled during PDMA..,1: Target abort interrupt Enabled during PDMA.." line.long 0x4 "PDMA_INTSTSn,PDMA Channel n Interrupt Status Register" bitfld.long 0x4 8. "PCNTIF,Periodic Count Interrupt Status Flag\nNote: This bit is cleared by writing '1' to it." "0,1" bitfld.long 0x4 6. "TOUTIF,Time-out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" newline bitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer.\nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABTIF,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received error response or not if bus master received error response it means that PDMA transfer data from.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TOCn,PDMA Channel n Time-out Counter Register" bitfld.long 0x8 16.--18. "TPSC,PDMA Time-out Counter Clock Source Prescaler" "0: PDMA time-out clock source is HCLK/28,1: PDMA time-out clock source is HCLK/29,?,?,?,?,?,?" hexmask.long.word 0x8 0.--15. 1. "TOC,PDMA Time-out Period Counter" tree.end tree "PDMA_GCR" base ad:0x50008F00 group.long 0x0++0xB line.long 0x0 "PDMA_GCTL,PDMA Global Control Register" bitfld.long 0x0 24. "CKENCRC,CRC Controller Clock Enable Bit" "0: CRC channel clock Disabled,1: CRC channel clock Enabled" bitfld.long 0x0 12. "CKEN4,PDMA Controller Channel 4 Clock Enable Bit" "0: PDMA channel 4 clock Disabled,1: PDMA channel 4 clock Enabled" bitfld.long 0x0 11. "CKEN3,PDMA Controller Channel 3 Clock Enable Bit" "0: PDMA channel 3 clock Disabled,1: PDMA channel 3 clock Enabled" newline bitfld.long 0x0 10. "CKEN2,PDMA Controller Channel 2 Clock Enable Bit" "0: PDMA channel 2 clock Disabled,1: PDMA channel 2 clock Enabled" bitfld.long 0x0 9. "CKEN1,PDMA Controller Channel 1 Clock Enable Bit" "0: PDMA channel 1 clock Disabled,1: PDMA channel 1 clock Enabled" line.long 0x4 "PDMA_REQSEL0,PDMA Request Source Select Register 0" hexmask.long.byte 0x4 24.--28. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the.." hexmask.long.byte 0x4 16.--20. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the.." hexmask.long.byte 0x4 8.--12. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral by setting REQSRC1" line.long 0x8 "PDMA_REQSEL1,PDMA Request Source Select Register 1" hexmask.long.byte 0x8 0.--4. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC1 field. Please refer to the.." rgroup.long 0xC++0x3 line.long 0x0 "PDMA_GINTSTS,PDMA Global Interrupt Status Register" bitfld.long 0x0 16. "IFCRC,CRC Controller Interrupt Status Flag (Read Only)\nThis bit indicates the interrupt status of CRC controller" "0,1" bitfld.long 0x0 4. "IF4,PDMA Channel 4 Interrupt Status Flag (Read Only)\nThis bit indicates the interrupt status of PDMA channel 4." "0,1" bitfld.long 0x0 3. "IF3,PDMA Channel 3 Interrupt Status (Read Only)\nThis bit indicates the interrupt status of PDMA channel 3." "0,1" newline bitfld.long 0x0 2. "IF2,PDMA Channel 2 Interrupt Status Flag of (Read Only)\nThis bit indicates the interrupt status of PDMA channel 2." "0,1" bitfld.long 0x0 1. "IF1,PDMA Channel 1 Interrupt Status (Read Only)\nThis bit indicates the interrupt status of PDMA channel 1." "0,1" tree.end tree.end tree "PWM (PWM Generator and Capture Timer)" base ad:0x40040000 group.long 0x0++0x7 line.long 0x0 "PWM0_CTL0,PWM0 Control Register 0" bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM0 pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM0 output,1: ICE debug mode acknowledgement disabled" bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM0 all counters will keep current value until exit ICE debug mode. \nNote:This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled" newline hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-load\nEach bit n controls the corresponding PWM0 channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." line.long 0x4 "PWM0_CTL1,PWM0 Control Register 1" bitfld.long 0x4 24.--26. "PWMMODEn,PWM0 Mode\nEach bit n controls the corresponding PWM0 channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: PWM0 independent mode,1: PWM0 complementary mode,?,?,?,?,?,?" bitfld.long 0x4 8.--9. "CNTTYPE4,PWM0 Counter Behavior Type 4\nEach bit n controls corresponding PWM0 channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" newline bitfld.long 0x4 4.--5. "CNTTYPE2,PWM0 Counter Behavior Type 2\nEach bit n controls corresponding PWM0 channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" bitfld.long 0x4 0.--1. "CNTTYPE0,PWM0 Counter Behavior Type 0\nEach bit n controls corresponding PWM0 channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?" group.long 0x10++0x17 line.long 0x0 "PWM0_CLKSRC,PWM0 Clock Source Register" bitfld.long 0x0 16.--18. "ECLKSRC4,PWM0_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "ECLKSRC2,PWM0_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "ECLKSRC0,PWM0_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?" line.long 0x4 "PWM0_CLKPSC0_1,PWM0 Clock Pre-Scale Register 0_1" hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM0 Counter Clock Pre-scale \nThe clock of PWM0 counter is decided by clock prescaler. Each PWM0 pair share one PWM0 counter clock prescaler. The clock of PWM0 counter is divided by (CLKPSC+ 1)." line.long 0x8 "PWM0_CLKPSC2_3,PWM0 Clock Pre-Scale Register 2_3" hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM0 Counter Clock Pre-scale \nThe clock of PWM0 counter is decided by clock prescaler. Each PWM0 pair share one PWM0 counter clock prescaler. The clock of PWM0 counter is divided by (CLKPSC+ 1)." line.long 0xC "PWM0_CLKPSC4_5,PWM0 Clock Pre-Scale Register 4_5" hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM0 Counter Clock Pre-scale \nThe clock of PWM0 counter is decided by clock prescaler. Each PWM0 pair share one PWM0 counter clock prescaler. The clock of PWM0 counter is divided by (CLKPSC+ 1)." line.long 0x10 "PWM0_CNTEN,PWM0 Counter Enable Register" bitfld.long 0x10 4. "CNTEN4,PWM0 Counter Enable Bit4" "0: PWM0 Counter4_5 and clock prescaler4 Stop..,1: PWM0 Counter4_5 and clock prescaler4 Start Running" bitfld.long 0x10 2. "CNTEN2,PWM0 Counter Enable Bit 2" "0: PWM0 Counter2_3 and clock prescaler2 Stop Running,1: PWM0 Counter2_3 and clock prescaler2 Start Running" newline bitfld.long 0x10 0. "CNTEN0,PWM0 Counter Enable Bit 0" "0: PWM0 Counter0_1 and clock prescaler0 Stop Running,1: PWM0 Counter0_1 and clock prescaler0 Start Running" line.long 0x14 "PWM0_CNTCLR,PWM0 Clear Counter Register" bitfld.long 0x14 4. "CNTCLR4,Clear PWM0 Counter Control Bit 4\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM0 counter to 0000H" bitfld.long 0x14 2. "CNTCLR2,Clear PWM0 Counter Control Bit 2\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM0 counter to 0000H" newline bitfld.long 0x14 0. "CNTCLR0,Clear PWM0 Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM0 counter to 0000H" group.long 0x30++0x3 line.long 0x0 "PWM0_PERIOD0,PWM0 Period Register 0" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM0 Period Register\nUp-Count mode: In this mode PWM0 counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM0 counter counts from PERIOD to 0 and restarts from PERIOD." group.long 0x38++0x3 line.long 0x0 "PWM0_PERIOD2,PWM0 Period Register 2" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM0 Period Register\nUp-Count mode: In this mode PWM0 counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM0 counter counts from PERIOD to 0 and restarts from PERIOD." group.long 0x40++0x3 line.long 0x0 "PWM0_PERIOD4,PWM0 Period Register 4" hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM0 Period Register\nUp-Count mode: In this mode PWM0 counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM0 counter counts from PERIOD to 0 and restarts from PERIOD." group.long 0x50++0x17 line.long 0x0 "PWM0_CMPDAT0,PWM0 Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMPDAT,PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode CMPDAT0 2 4 denote as.." line.long 0x4 "PWM0_CMPDAT1,PWM0 Comparator Register 1" hexmask.long.word 0x4 0.--15. 1. "CMPDAT,PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode CMPDAT0 2 4 denote as.." line.long 0x8 "PWM0_CMPDAT2,PWM0 Comparator Register 2" hexmask.long.word 0x8 0.--15. 1. "CMPDAT,PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode CMPDAT0 2 4 denote as.." line.long 0xC "PWM0_CMPDAT3,PWM0 Comparator Register 3" hexmask.long.word 0xC 0.--15. 1. "CMPDAT,PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode CMPDAT0 2 4 denote as.." line.long 0x10 "PWM0_CMPDAT4,PWM0 Comparator Register 4" hexmask.long.word 0x10 0.--15. 1. "CMPDAT,PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode CMPDAT0 2 4 denote as.." line.long 0x14 "PWM0_CMPDAT5,PWM0 Comparator Register 5" hexmask.long.word 0x14 0.--15. 1. "CMPDAT,PWM0 Comparator Register\nCMPDAT use to compare with CNTR to generate PWM0 waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point.\nIn complementary mode CMPDAT0 2 4 denote as.." group.long 0x70++0xB line.long 0x0 "PWM0_DTCTL0_1,PWM0 Dead-Time Control Register 0_1" bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote:This register is write protected. Refer toREGWRPROT register." "0: Dead-time clock source from PWM0_CLKn,1: Dead-time clock source from prescaler output" bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0 PWM0_CH1)(PWM0_CH2 PWM0_CH3)(PWM0_CH4 PWM0_CH5)(Write Protect)\nDead-time insertion is only active when this PWM0 pair complementary mode is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote:This register is write protected. Refer toSYS_REGLCTL register." line.long 0x4 "PWM0_DTCTL2_3,PWM0 Dead-Time Control Register 2_3" bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote:This register is write protected. Refer toREGWRPROT register." "0: Dead-time clock source from PWM0_CLKn,1: Dead-time clock source from prescaler output" bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0 PWM0_CH1)(PWM0_CH2 PWM0_CH3)(PWM0_CH4 PWM0_CH5)(Write Protect)\nDead-time insertion is only active when this PWM0 pair complementary mode is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote:This register is write protected. Refer toSYS_REGLCTL register." line.long 0x8 "PWM0_DTCTL4_5,PWM0 Dead-Time Control Register 4_5" bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote:This register is write protected. Refer toREGWRPROT register." "0: Dead-time clock source from PWM0_CLKn,1: Dead-time clock source from prescaler output" bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0 PWM0_CH1)(PWM0_CH2 PWM0_CH3)(PWM0_CH4 PWM0_CH5)(Write Protect)\nDead-time insertion is only active when this PWM0 pair complementary mode is enabled. If dead- time insertion is inactive the.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote:This register is write protected. Refer toSYS_REGLCTL register." rgroup.long 0x90++0x3 line.long 0x0 "PWM0_CNT0,PWM0 Counter Register 0" bitfld.long 0x0 16. "DIRF,PWM0 Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM0 Data Register(Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter." rgroup.long 0x98++0x3 line.long 0x0 "PWM0_CNT2,PWM0 Counter Register 2" bitfld.long 0x0 16. "DIRF,PWM0 Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM0 Data Register(Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter." rgroup.long 0xA0++0x3 line.long 0x0 "PWM0_CNT4,PWM0 Counter Register 4" bitfld.long 0x0 16. "DIRF,PWM0 Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM0 Data Register(Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter." group.long 0xB0++0x2B line.long 0x0 "PWM0_WGCTL0,PWM0Waveform Generation Control Register 0" hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,PWM0 Period (Center) Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter count to (PERIODn+1).\nNote: This bit is center point control when PWM0 counter operating in up-down.." hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,PWM0 Zero Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter count to zero." line.long 0x4 "PWM0_WGCTL1,PWM0Waveform Generation Control Register 1" hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,PWM0 Compare Down Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter down count to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4." hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,PWM0 Compare Up Point Control\nEach bit n controls the corresponding PWM0 channel n.\nPWM0 can control output level when PWM0 counter up count to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4." line.long 0x8 "PWM0_MSKEN,PWM0 Mask Enable Register" hexmask.long.byte 0x8 0.--5. 1. "MSKENn,PWM0 Mask Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nThe PWM0 output signal will be masked when this bit is enabled. The corresponding PWM0 channel n will output MSKDATn (PWM0_MSK[5:0]) data." line.long 0xC "PWM0_MSK,PWM0 Mask Data Register" hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,PWM0 Mask Data Bits\nThis data bit control the state of PWM0_CHn output pin if corresponding mask function is enabled." line.long 0x10 "PWM0_BNF,PWM0 Brake Noise Filter Register" bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1.\nBrake..,1: Brake 1 pin source come from PWM1_BRAKE1.\nBrake.." bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0.\nBrake..,1: Brake 0 pin source come from PWM1_BRAKE0.\nBrake.." newline bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.." bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "BRK1FCS,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 8. "BRK1FEN,PWM0 Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM0 Brake 1 Disabled,1: Noise filter of PWM0 Brake 1 Enabled" newline bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.." bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1.--3. "BRK0FCS,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?" bitfld.long 0x10 0. "BRK0FEN,PWM0 Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM0 Brake 0 Disabled,1: Noise filter of PWM0 Brake 0 Enabled" line.long 0x14 "PWM0_FAILBRK,PWM0 System Fail Brake Control Register" bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM0 Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.." bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM0 Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled" line.long 0x18 "PWM0_BRKCTL0_1,PWM0 Brake Edge Detect Control Register 0_1" bitfld.long 0x18 18.--19. "BRKAODD,PWM0 Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWM0 odd channel brake function not affect..,1: PWM0 odd channel output tri-state when brake..,?,?" bitfld.long 0x18 16.--17. "BRKAEVEN,PWM0 Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWM0 even channelbrake function not affect..,1: PWM0 even channel output tri-state when brake..,?,?" newline bitfld.long 0x18 15. "SYSLEN,Enable System Fail As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x18 7. "SYSEEN,Enable System Fail As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x1C "PWM0_BRKCTL2_3,PWM0 Brake Edge Detect Control Register 2_3" bitfld.long 0x1C 18.--19. "BRKAODD,PWM0 Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWM0 odd channel brake function not affect..,1: PWM0 odd channel output tri-state when brake..,?,?" bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM0 Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWM0 even channelbrake function not affect..,1: PWM0 even channel output tri-state when brake..,?,?" newline bitfld.long 0x1C 15. "SYSLEN,Enable System Fail As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x1C 7. "SYSEEN,Enable System Fail As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x20 "PWM0_BRKCTL4_5,PWM0 Brake Edge Detect Control Register 4_5" bitfld.long 0x20 18.--19. "BRKAODD,PWM0 Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWM0 odd channel brake function not affect..,1: PWM0 odd channel output tri-state when brake..,?,?" bitfld.long 0x20 16.--17. "BRKAEVEN,PWM0 Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWM0 even channelbrake function not affect..,1: PWM0 even channel output tri-state when brake..,?,?" newline bitfld.long 0x20 15. "SYSLEN,Enable System Fail As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x20 7. "SYSEEN,Enable System Fail As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" line.long 0x24 "PWM0_POLCTL,PWM0 Pin Polar Inverse Register" hexmask.long.byte 0x24 0.--5. 1. "PINVn,PWM0 PIN Polar Inverse Control\nThe register controls polarity state of PWM0 output. Each bit n controls the corresponding PWM0 channel n." line.long 0x28 "PWM0_POEN,PWM0 Output Enable Register" hexmask.long.byte 0x28 0.--5. 1. "POENn,PWM0 Pin Output Enable Bits\nEach bit n controls the corresponding PWM0 channel n." wgroup.long 0xDC++0x3 line.long 0x0 "PWM0_SWBRK,PWM0 Software Brake Control Register" bitfld.long 0x0 8.--10. "BRKLTRGn,PWM0 Level Brake Software Trigger (Write Only)(Write Protect)\nEach bit n controls the corresponding PWM0 pair n.\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM0_INTSTS1 register. \nNote:This register is write.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "BRKETRGn,PWM0 Edge Brake Software Trigger (Write Only)(Write Protect)\nEach bit n controls the corresponding PWM0 pair n.\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM0_INTSTS1 register. \nNote:This register is write.." "0,1,2,3,4,5,6,7" group.long 0xE0++0xF line.long 0x0 "PWM0_INTEN0,PWM0 Interrupt Enable Register 0" hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,PWM0 Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4." hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,PWM0 Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n.\nNote: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4." newline bitfld.long 0x0 12. "PIEN4,PWM0 Period Point Interrupt Enable Bit 4\nNote: When operating in up-down counter type period point means center point." "0: PWM0counter4_5 period point interrupt Disabled,1: PWM0counter4_5 period point interrupt Enabled" bitfld.long 0x0 10. "PIEN2,PWM0 Period Point Interrupt Enable Bit 2\nNote: When operating in up-down counter type period point means center point." "0: PWM0counter2_3 period point interrupt Disabled,1: PWM0counter2_3 period point interrupt Enabled" newline bitfld.long 0x0 8. "PIEN0,PWM0 Period Point Interrupt Enable Bit 0\nNote: When operating in up-down counter type period point means center point." "0: PWM0counter0_1 period point interrupt Disabled,1: PWM0counter0_1 period point interrupt Enabled" bitfld.long 0x0 4. "ZIEN4,PWM0 Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode." "0: PWM0counter4_5 zero point interrupt Disabled,1: PWM0counter4_5 zero point interrupt Enabled" newline bitfld.long 0x0 2. "ZIEN2,PWM0 Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode." "0: PWM0counter2_3 zero point interrupt Disabled,1: PWM0counter2_3 zero point interrupt Enabled" bitfld.long 0x0 0. "ZIEN0,PWM0 Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode." "0: PWM0counter0_1 zero point interrupt Disabled,1: PWM0counter0_1 zero point interrupt Enabled" line.long 0x4 "PWM0_INTEN1,PWM0 Interrupt Enable Register 1" bitfld.long 0x4 10. "BRKLIEN4_5,PWM0 Level-detect Brake Interrupt Enable Bit for Channel4/5(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.." bitfld.long 0x4 9. "BRKLIEN2_3,PWM0 Level-detect Brake Interrupt Enable Bitfor Channel2/3(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.." newline bitfld.long 0x4 8. "BRKLIEN0_1,PWM0 Level-detect Brake Interrupt Enable Bitfor Channel0/1(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.." bitfld.long 0x4 2. "BRKEIEN4_5,PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel4/5(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled" newline bitfld.long 0x4 1. "BRKEIEN2_3,PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel2/3(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled" bitfld.long 0x4 0. "BRKEIEN0_1,PWM0 Edge-detect Brake Interrupt Enable Bitfor Channel0/1(Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled" line.long 0x8 "PWM0_INTSTS0,PWM0 Interrupt Flag Register 0" hexmask.long.byte 0x8 24.--29. 1. "CMPDIFn,PWM0 Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM0 channel n.\nFlag is set by hardware when PWM0 counter down count and reaches PWM0_CMPDATn software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal.." hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM0 Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM0 counter up count and reaches PWM0_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM0 channel n.\nNote1: If CMPDAT equal to.." newline bitfld.long 0x8 12. "PIF4,PWM0 Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM0_CH4 counter reaches PWM0_PERIOD4 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 10. "PIF2,PWM0 Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM0_CH2 counter reaches PWM0_PERIOD2 software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 8. "PIF0,PWM0 Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM0_CH0 counter reaches PWM0_PERIOD0 software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 4. "ZIF4,PWM0 Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM0_CH4 counter reaches zero software can write 1 to clear this bit to zero." "0,1" newline bitfld.long 0x8 2. "ZIF2,PWM0 Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM0_CH2 counter reaches zero software can write 1 to clear this bit to zero." "0,1" bitfld.long 0x8 0. "ZIF0,PWM0 Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM0_CH0 counter reaches zero software can write 1 to clear this bit to zero." "0,1" line.long 0xC "PWM0_INTSTS1,PWM0 Interrupt Flag Register 1" rbitfld.long 0xC 29. "BRKLSTS5,PWM0 Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform.." "0: PWM0 channel5 level-detect brake state is released,1: When PWM0 channel5 level-detect brake detects a.." rbitfld.long 0xC 28. "BRKLSTS4,PWM0 Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform.." "0: PWM0 channel4 level-detect brake state is released,1: When PWM0 channel4 level-detect brake detects a.." newline rbitfld.long 0xC 27. "BRKLSTS3,PWM0 Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform.." "0: PWM0 channel3 level-detect brake state is released,1: When PWM0 channel3 level-detect brake detects a.." rbitfld.long 0xC 26. "BRKLSTS2,PWM0 Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform.." "0: PWM0 channel2 level-detect brake state is released,1: When PWM0 channel2 level-detect brake detects a.." newline rbitfld.long 0xC 25. "BRKLSTS1,PWM0 Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform.." "0: PWM0 channel1 level-detect brake state is released,1: When PWM0 channel1 level-detect brake detects a.." rbitfld.long 0xC 24. "BRKLSTS0,PWM0 Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM0 will release brake state until current PWM0 period finished. The PWM0 waveform.." "0: PWM0 channel0 level-detect brake state is released,1: When PWM0 channel0 level-detect brake detects a.." newline rbitfld.long 0xC 21. "BRKESTS5,PWM0 Channel5 Edge-detect Brake Status (Read Only)" "0: PWM0 channel5 edge-detect brake state is released,1: When PWM0 channel5 edge-detect brake detects a.." rbitfld.long 0xC 20. "BRKESTS4,PWM0 Channel4 Edge-detect Brake Status (Read Only)" "0: PWM0 channel4 edge-detect brake state is released,1: When PWM0 channel4 edge-detect brake detects a.." newline rbitfld.long 0xC 19. "BRKESTS3,PWM0 Channel3 Edge-detect Brake Status (Read Only)" "0: PWM0 channel3 edge-detect brake state is released,1: When PWM0 channel3 edge-detect brake detects a.." rbitfld.long 0xC 18. "BRKESTS2,PWM0 Channel2 Edge-detect Brake Status (Read Only)" "0: PWM0 channel2 edge-detect brake state is released,1: When PWM0 channel2 edge-detect brake detects a.." newline rbitfld.long 0xC 17. "BRKESTS1,PWM0 Channel1 Edge-detect Brake Status (Read Only)" "0: PWM0 channel1 edge-detect brake state is released,1: When PWM0 channel1 edge-detect brake detects a.." rbitfld.long 0xC 16. "BRKESTS0,PWM0 Channel0 Edge-detect Brake Status (Read Only)" "0: PWM0 channel0 edge-detect brake state is released,1: When PWM0 channel0 edge-detect brake detects a.." newline bitfld.long 0xC 13. "BRKLIF5,PWM0 Channel5 Level-detect Brake Interrupt Flag(Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel5 level-detect brake event do not..,1: When PWM0 channel5 level-detect brake event.." bitfld.long 0xC 12. "BRKLIF4,PWM0 Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel4 level-detect brake event do not..,1: When PWM0 channel4 level-detect brake event.." newline bitfld.long 0xC 11. "BRKLIF3,PWM0 Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel3 level-detect brake event do not..,1: When PWM0 channel3 level-detect brake event.." bitfld.long 0xC 10. "BRKLIF2,PWM0 Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel2 level-detect brake event do not..,1: When PWM0 channel2 level-detect brake event.." newline bitfld.long 0xC 9. "BRKLIF1,PWM0 Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel1 level-detect brake event do not..,1: When PWM0 channel1 level-detect brake event.." bitfld.long 0xC 8. "BRKLIF0,PWM0 Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel0 level-detect brake event do not..,1: When PWM0 channel0 level-detect brake event.." newline bitfld.long 0xC 5. "BRKEIF5,PWM0 Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel5 edge-detect brake event do not..,1: When PWM0 channel5 edge-detect brake event.." bitfld.long 0xC 4. "BRKEIF4,PWM0 Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel4 edge-detect brake event do not..,1: When PWM0 channel4 edge-detect brake event.." newline bitfld.long 0xC 3. "BRKEIF3,PWM0 Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel3 edge-detect brake event do not..,1: When PWM0 channel3 edge-detect brake event.." bitfld.long 0xC 2. "BRKEIF2,PWM0 Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel2 edge-detect brake event do not..,1: When PWM0 channel2 edge-detect brake event.." newline bitfld.long 0xC 1. "BRKEIF1,PWM0 Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel1 edge-detect brake event do not..,1: When PWM0 channel1 edge-detect brake event.." bitfld.long 0xC 0. "BRKEIF0,PWM0 Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: PWM0 channel0 edge-detect brake event do not..,1: When PWM0 channel0 edge-detect brake event.." group.long 0xF8++0x7 line.long 0x0 "PWM0_ADCTS0,PWM0 Trigger ADC Source Select Register 0" bitfld.long 0x0 31. "TRGEN3,PWM0_CH3 Trigger EADC Enable Bit" "0: PWM0_CH3 Trigger EADC Disabled,1: PWM0_CH3 Trigger EADC Enabled" hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM0_CH3 Trigger ADC Source Select\nOthers reserved" newline bitfld.long 0x0 23. "TRGEN2,PWM0_CH2 Trigger EADC Enable Bit" "0: PWM0_CH2 Trigger EADC Disabled,1: PWM0_CH2 Trigger EADC Enabled" hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM0_CH2 Trigger ADC Source Select\nOthers reserved" newline bitfld.long 0x0 15. "TRGEN1,PWM0_CH1 Trigger EADC Enable Bit" "0: PWM0_CH1 Trigger EADC Disabled,1: PWM0_CH1 Trigger EADC Enabled" hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM0_CH1 Trigger ADC Source Select\nOthers reserved" newline bitfld.long 0x0 7. "TRGEN0,PWM0_CH0 Trigger EADC Enable Bit" "0: PWM0_CH0 Trigger EADC Disabled,1: PWM0_CH0 Trigger EADC Enabled" hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM0_CH0 Trigger ADC Source Select\nOthers reserved" line.long 0x4 "PWM0_ADCTS1,PWM0 Trigger ADC Source Select Register 1" bitfld.long 0x4 15. "TRGEN5,PWM0_CH5 Trigger EADC Enable Bit" "0: PWM0_CH5 Trigger EADC Disabled,1: PWM0_CH5 Trigger EADC Enabled" hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM0_CH5 Trigger ADC Source Select\nOthers reserved" newline bitfld.long 0x4 7. "TRGEN4,PWM0_CH4 Trigger EADC Enable Bit" "0: PWM0_CH4 Trigger EADC Disabled,1: PWM0_CH4 Trigger EADC Enabled" hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM0_CH4 Trigger ADC Source Select\nOthers reserved" group.long 0x120++0x3 line.long 0x0 "PWM0_STATUS,PWM0 Status Register" hexmask.long.byte 0x0 16.--21. 1. "ADCTRGn,ADC Start of Conversion Status\nEach bit n controls the corresponding PWM0 channel n." bitfld.long 0x0 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Status" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." newline bitfld.long 0x0 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Status" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." bitfld.long 0x0 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." group.long 0x200++0x7 line.long 0x0 "PWM0_CAPINEN,PWM0 Capture Input Enable Register" hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Bits\nEach bit n controls the corresponding PWM0 channel n." line.long 0x4 "PWM0_CAPCTL,PWM0 Capture Control Register" hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload EnableBits\nEach bit n controls the corresponding PWM0 channel n." hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM0 channel n." newline hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM0 channel n." hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Bits\nEach bit n controls the corresponding PWM0 channel n." rgroup.long 0x208++0x33 line.long 0x0 "PWM0_CAPSTS,PWM0 Capture Status Register" hexmask.long.byte 0x0 8.--13. 1. "CFIFOVn,Capture Falling Interrupt Flag Overrun Status(Read Only)\nThis flag indicatesif falling latch happenedwhen the corresponding CAPFIFis 1. Each bit n controls the corresponding PWM0 channel n.\nNote:This bit will be cleared automatically when user.." hexmask.long.byte 0x0 0.--5. 1. "CRIFOVn,Capture Rising Interrupt Flag Overrun Status(Read Only)\nThis flag indicatesif rising latch happenedwhen the corresponding CAPRIFis 1. Each bit n controls the corresponding PWM0 channel n.\nNote:This bit will be cleared automatically when user.." line.long 0x4 "PWM0_RCAPDAT0,PWM0 Rising Capture Data Register 0" hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened the PWM0 counter value will be saved in this register." line.long 0x8 "PWM0_FCAPDAT0,PWM0 Falling Capture Data Register 0" hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened the PWM0 counter value will be saved in this register." line.long 0xC "PWM0_RCAPDAT1,PWM0 Rising Capture Data Register 1" hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened the PWM0 counter value will be saved in this register." line.long 0x10 "PWM0_FCAPDAT1,PWM0 Falling Capture Data Register 1" hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened the PWM0 counter value will be saved in this register." line.long 0x14 "PWM0_RCAPDAT2,PWM0 Rising Capture Data Register 2" hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened the PWM0 counter value will be saved in this register." line.long 0x18 "PWM0_FCAPDAT2,PWM0 Falling Capture Data Register 2" hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened the PWM0 counter value will be saved in this register." line.long 0x1C "PWM0_RCAPDAT3,PWM0 Rising Capture Data Register 3" hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened the PWM0 counter value will be saved in this register." line.long 0x20 "PWM0_FCAPDAT3,PWM0 Falling Capture Data Register 3" hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened the PWM0 counter value will be saved in this register." line.long 0x24 "PWM0_RCAPDAT4,PWM0 Rising Capture Data Register 4" hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened the PWM0 counter value will be saved in this register." line.long 0x28 "PWM0_FCAPDAT4,PWM0 Falling Capture Data Register 4" hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened the PWM0 counter value will be saved in this register." line.long 0x2C "PWM0_RCAPDAT5,PWM0 Rising Capture Data Register 5" hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM0 Rising Capture Data Register(Read Only)\nWhen rising capture condition happened the PWM0 counter value will be saved in this register." line.long 0x30 "PWM0_FCAPDAT5,PWM0 Falling Capture Data Register 5" hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM0 Falling Capture Data Register(Read Only)\nWhen falling capture condition happened the PWM0 counter value will be saved in this register." group.long 0x250++0x7 line.long 0x0 "PWM0_CAPIEN,PWM0 Capture Interrupt Enable Register" hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,PWM0 Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n." hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,PWM0 Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM0 channel n." line.long 0x4 "PWM0_CAPIF,PWM0 Capture Interrupt Flag Register" hexmask.long.byte 0x4 8.--13. 1. "CAPFIFn,PWM0 Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n." hexmask.long.byte 0x4 0.--5. 1. "CAPRIFn,PWM0 Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n." group.long 0x300++0x3 line.long 0x0 "PWM0_SELFTEST,PWM0 Self-test Mode Enable" rgroup.long 0x304++0x3 line.long 0x0 "PWM0_PBUF0,PWM0 PERIOD0 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM0 Period Register Buffer(Read Only)\nUsed as PERIOD active register." rgroup.long 0x30C++0x3 line.long 0x0 "PWM0_PBUF2,PWM0 PERIOD2 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM0 Period Register Buffer(Read Only)\nUsed as PERIOD active register." rgroup.long 0x314++0x3 line.long 0x0 "PWM0_PBUF4,PWM0 PERIOD4 Buffer" hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM0 Period Register Buffer(Read Only)\nUsed as PERIOD active register." rgroup.long 0x31C++0x17 line.long 0x0 "PWM0_CMPBUF0,PWM0 CMPDAT0 Buffer" hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register." line.long 0x4 "PWM0_CMPBUF1,PWM0 CMPDAT1 Buffer" hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register." line.long 0x8 "PWM0_CMPBUF2,PWM0 CMPDAT2 Buffer" hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register." line.long 0xC "PWM0_CMPBUF3,PWM0 CMPDAT3 Buffer" hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register." line.long 0x10 "PWM0_CMPBUF4,PWM0 CMPDAT4 Buffer" hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register." line.long 0x14 "PWM0_CMPBUF5,PWM0 CMPDAT5 Buffer" hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM0 Comparator Register Buffer(Read Only)\nUsed as CMP active register." rgroup.long 0xFFC++0x3 line.long 0x0 "PWM0_VERSION,PWM0 RTL Design Version Number" tree.end tree "RTC (Real Time Clock)" base ad:0x40008000 group.long 0x0++0x23 line.long 0x0 "RTC_INIT,RTC Initiation Register" hexmask.long 0x0 1.--31. 1. "INIT,RTC Initiation\nWhen RTC block is powered on RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357 the RTC will be in un-reset state permanently.\nThe INIT.." rbitfld.long 0x0 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state" line.long 0x4 "RTC_RWEN,RTC Access Enable Register" bitfld.long 0x4 24. "RTCBUSY,RTC Write Busy Flag\n0: RTC write access enable \n1: RTC write access disable RTC under Busy Status.\nNote: BUSY By Exceed RTC IP Prcessing Write Counter Capacity ( 6 counts Per 1120 PCLK cycles) ." "0: RTC write access enable \n1: RTC write access..,?" rbitfld.long 0x4 16. "RWENF,RTC Register Access Enable Flag (Read Only)" "0: RTC register read/write Disabled,1: RTC register read/write Enabled" newline hexmask.long.word 0x4 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock.\nWriting other vaule will clear RWENF." line.long 0x8 "RTC_FREQADJ,RTC Frequency Compensation Register" hexmask.long.tbyte 0x8 0.--21. 1. "FREQADJ,Frequence Compensation Register\nLXT period: the clock period (Hz) of LXT." line.long 0xC "RTC_TIME,RTC Time Loading Register" bitfld.long 0xC 20.--21. "TENHR,10-hour Time Digit (0~2)\nWhen RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1 it indicates PM time message.) the high bit of TENHR (RTC_TIME[21]) means AM/PM indication." "0,1,2,3" hexmask.long.byte 0xC 16.--19. 1. "HR,1-Hour Time Digit (0~9)" newline bitfld.long 0xC 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "MIN,1-Min Time Digit (0~9)" newline bitfld.long 0xC 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "SEC,1-Sec Time Digit (0~9)" line.long 0x10 "RTC_CAL,RTC Calendar Loading Register" hexmask.long.byte 0x10 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)" hexmask.long.byte 0x10 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)" newline bitfld.long 0x10 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1" hexmask.long.byte 0x10 8.--11. 1. "MON,1-Month Calendar Digit (0~9)" newline bitfld.long 0x10 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)" line.long 0x14 "RTC_CLKFMT,RTC Time Scale Selection Register" bitfld.long 0x14 0. "_24HEN,24-hour /12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected" line.long 0x18 "RTC_WEEKDAY,RTC Day of the Week Register" bitfld.long 0x18 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,?,?,?,?,?,?" line.long 0x1C "RTC_TALM,RTC Time Alarm Register" bitfld.long 0x1C 20.--21. "TENHR,10-hour Time Digit of Alarm Setting (0~2)\nWhen RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1 it indicates PM time message.)the high bit of TENHR (RTC_TIME[21]) means.." "0,1,2,3" hexmask.long.byte 0x1C 16.--19. 1. "HR,1-Hour Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "MIN,1-Min Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--3. 1. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" line.long 0x20 "RTC_CALM,RTC Calendar Alarm Register" hexmask.long.byte 0x20 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" hexmask.long.byte 0x20 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1" hexmask.long.byte 0x20 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" rgroup.long 0x24++0x3 line.long 0x0 "RTC_LEAPYEAR,RTC Leap Year Indicator Register" bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication Register (Read Only)" "0: This year is not a leap year,1: This year is leap year" group.long 0x28++0x2B line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register" bitfld.long 0x0 2. "SNPDIEN,Snoop Detection Interrupt Enable Bit" "0: Snoop detectedinterrupt Disabled,1: Snoop detected interrupt Enabled" bitfld.long 0x0 1. "TICKIEN,Time Tick Interrupt Enable Bit" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled" newline bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable Bit" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled" line.long 0x4 "RTC_INTSTS,RTC Interrupt Indicator Register" bitfld.long 0x4 2. "SNPDIF,Snoop Detect Interrupt Flag\nWhen tamper pin transition event is detected this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. Chip will be waken up from Power-down mode if.." "0: No snoop event is detected,1: Snoop event is detected" bitfld.long 0x4 1. "TICKIF,RTC Time Tick Interrupt Flag\nWhen RTC time tick happened this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be waken up if RTC Tick Interrupt is enabled.." "0: Tick condition does not occur,1: Tick condition occur" newline bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is.." "0: Alarm condition is not matched,1: Alarm condition is matched" line.long 0x8 "RTC_TICK,RTC Time Tick Register" bitfld.long 0x8 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote:This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active." "0: Time tick is 1 second,1: Time tick is 1/2 second,?,?,?,?,?,?" line.long 0xC "RTC_TAMSK,RTC Time Alarm Mask Register" bitfld.long 0xC 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1" bitfld.long 0xC 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "?,1: Hour Time Digit of Alarm Setting" newline bitfld.long 0xC 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1" bitfld.long 0xC 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "?,1: Min Time Digit of Alarm Setting" newline bitfld.long 0xC 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1" bitfld.long 0xC 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "?,1: Sec Time Digit of Alarm Setting" line.long 0x10 "RTC_CAMSK,RTC Calendar Alarm Mask Register" bitfld.long 0x10 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1" bitfld.long 0x10 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "?,1: Year Calendar Digit of Alarm Setting" newline bitfld.long 0x10 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1" bitfld.long 0x10 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "?,1: Month Calendar Digit of Alarm Setting" newline bitfld.long 0x10 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1" bitfld.long 0x10 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "?,1: Day Calendar Digit of Alarm Setting" line.long 0x14 "RTC_SPRCTL,RTC Spare Functional Control Register" bitfld.long 0x14 5. "SPRCSTS,SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify snoop event is detected.\nWrites 1 to clear this bit." "0: Spare register content is not cleared,1: Spare register content is cleared" bitfld.long 0x14 2. "SPRRWEN,Spare Register Enable Bit\nNote: When spare register is disabled RTC_SPR0 ~ RTC_SPR4 cannot be accessed\nDid not change the content of the spare register but read data all '0'.." "0: Spare register Disabled,1: Spare register Enabled" newline bitfld.long 0x14 1. "SNPTYPE0,Snoop Detection Level\nThis bit controls TAMPER detect event is rising edge or falling edge." "0: Rising edge detection,1: Falling edge detection" bitfld.long 0x14 0. "SNPDEN,Snoop Detection Enable Bit" "0: TAMPER pin detection Disabled,1: TAMPER pin detection Enabled" line.long 0x18 "RTC_SPR0,RTC Spare Register 0" hexmask.long 0x18 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.." line.long 0x1C "RTC_SPR1,RTC Spare Register 1" hexmask.long 0x1C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.." line.long 0x20 "RTC_SPR2,RTC Spare Register 2" hexmask.long 0x20 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.." line.long 0x24 "RTC_SPR3,RTC Spare Register 3" hexmask.long 0x24 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.." line.long 0x28 "RTC_SPR4,RTC Spare Register 4" hexmask.long 0x28 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.." group.long 0x100++0xF line.long 0x0 "RTC_LXTCTL,RTC 32.768 kHz Oscillator Control Register" bitfld.long 0x0 0. "LXT_TYPE,LXT TYPE Selection" "0: Crystal type ( Crystal connect to X32KI with..,1: Oscator illator type ( LXT source from X32KI PIN.." line.long 0x4 "RTC_LXTOCTL,X32KO Pin Control Register" bitfld.long 0x4 3. "CTLSEL,IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled X32KO (PF.6) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KO (PF.6) I/O function is controlled by system power domain GPIO module or VBAT.." "0: X32KO (PF.6) pin I/O function is controlled by..,1: X32KO (PF.6) pin I/O function is controlled by.." bitfld.long 0x4 2. "DOUT,IO Output Data" "0: X32KO (PF.6) output low,1: X32KO (PF.6) output high" newline bitfld.long 0x4 0.--1. "OPMODE,GPF0 Operation Mode" "0: X32KO (PF.6) is input only mode without pull-up..,1: X32KO (PF.6) is output push pull mode,?,?" line.long 0x8 "RTC_LXTICTL,X32KI Pin Control Register" bitfld.long 0x8 3. "CTLSEL,IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled X32KI (PF.7) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KI (PF.7) I/O function is controlled by system power domain GPIO module or VBAT.." "0: X32KI (PF.7) pin I/O function is controlled by..,1: X32KI (PF.7) pin I/O function is controlled by.." bitfld.long 0x8 2. "DOUT,IO Output Data" "0: X32KI (PF.7) output low,1: X32KI (PF.7) output high" newline bitfld.long 0x8 0.--1. "OPMODE,IO Operation Mode" "0: X32KI (PF.7) is input only mode without pull-up..,1: X32KI (PF.7) is output push pull mode,?,?" line.long 0xC "RTC_TAMPCTL,TAMPER Pin Control Register" bitfld.long 0xC 3. "CTLSEL,IO Pin State Backup Selection\nWhen tamper function is disabled TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by system power domain GPIO module or.." "0: TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O..,1: TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O.." bitfld.long 0xC 2. "DOUT,IO Output Data" "0: TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8)..,1: TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8).." newline bitfld.long 0xC 0.--1. "OPMODE,IO Operation Mode" "0: TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is..,1: TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is..,?,?" tree.end tree "SC (Smart Card Host Interface)" base ad:0x0 tree "SC0" base ad:0x40190000 group.long 0x0++0x1B line.long 0x0 "SCn_DAT,SCn Receive/Transmit Holding Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive/Transmit Holding Buffer \nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.." line.long 0x4 "SCn_CTL,SCn Control Register." rbitfld.long 0x4 30. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit before writing a new value to RXRTY and TXRTY.SYNC delay is" "0: synchronizing is completion user can write new..,1: Last value is synchronizing" bitfld.long 0x4 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved." "0: De-bounce sample card insert once per 384 (128 *..,?,?,?" newline bitfld.long 0x4 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred." "0: TX error retry function Disabled,1: TX error retry function Enabled" bitfld.long 0x4 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "?,1: The real retry number is TXRTY + 1,2: This field cannot be changed when TXRTYEN enabled,?,?,?,?,?" newline bitfld.long 0x4 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RXRTY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled" bitfld.long 0x4 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "?,1: The real retry number is RX_ERETRY + 1,2: This field cannot be changed when RX_ERETRY_EN..,?,?,?,?,?" newline bitfld.long 0x4 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length." "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU" bitfld.long 0x4 13.--14. "TMRSEL,Timer Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,?" newline hexmask.long.byte 0x4 8.--12. 1. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1." bitfld.long 0x4 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled an interrupt will be generated)." "0: INTR_RDA Trigger Level with 01 Bytes,1: INTR_RDA Trigger Level with 02 Bytes,?,?" newline bitfld.long 0x4 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) is enabled this field is ignored." "0: Direct convention,1: Reserved,?,?" bitfld.long 0x4 3. "AUTOCEN,Auto Convention Enable Bit" "0: Auto-convention Disabled,1: Auto-convention Enabled. When hardware receives.." newline bitfld.long 0x4 2. "TXOFF,TX Transition Disable Bit" "0: The transceiver Enabled,1: The transceiver Disabled" bitfld.long 0x4 1. "RXOFF,RX Transition Disable Bit\nNote1: If AUTOCEN (SC_CTL[3])is enabled these fields must be ignored.\nNote2: After hardware activation and hardware warm reset are done RXOFF is set to 0 automatically." "0: The receiver Enabled,1: If AUTOCEN" newline bitfld.long 0x4 0. "SCEN,SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared SC will force all transition to IDLE state\nNote1: SCEN must be set to 1 before filling in other registers or smart card will not work properly.\nNote2: If SCEN.." "?,1: SCEN must be set to 1 before filling in other.." line.long 0x8 "SCn_ALTCTL,SCn Alternate Control Register." bitfld.long 0x8 16. "OUTSEL,Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode." "0: Quasi mode,1: Open-drain mode" rbitfld.long 0x8 15. "ACTSTS2,Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0])." "0: Timer2 is not active,1: Timer2 is active" newline rbitfld.long 0x8 14. "ACTSTS1,Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0])." "0: Timer1 is not active,1: Timer1 is active" rbitfld.long 0x8 13. "ACTSTS0,Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0])." "0: Timer0 is not active,1: Timer0 is active" newline bitfld.long 0x8 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled" bitfld.long 0x8 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in Figure 6.154SC Activation Sequence.\nWarm-reset:.." "0,1,2,3" newline bitfld.long 0x8 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled this filed cannot be programmed." "0: Stops counting,1: Start counting" bitfld.long 0x8 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled this filed cannot be programmed." "0: Stops counting,1: Start counting" newline bitfld.long 0x8 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled this filed cannot be programmed." "0: Stops counting,1: Start counting" bitfld.long 0x8 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set.." "0: No effect,1: When the warm reset sequence completed" newline bitfld.long 0x8 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to.." "0: No effect,1: When the activation sequence completed" bitfld.long 0x8 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be.." "0: No effect,1: When the deactivation sequence completed" newline bitfld.long 0x8 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers" bitfld.long 0x8 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers" line.long 0xC "SCn_EGT,SCn Extra Guard Time Register." hexmask.long.byte 0xC 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard timer value.\nNote: The counter is ETU base ." line.long 0x10 "SCn_RXTOUT,SCn Receive buffer Time-out Register." hexmask.long.word 0x10 0.--8. 1. "RFTM,SC Receiver FIFO Time-out \nNote1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function." line.long 0x14 "SCn_ETUCTL,SCn Element Time Unit Control Register." hexmask.long.word 0x14 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field but this field must be greater than 0x004." line.long 0x18 "SCn_INTEN,SCn Interrupt Enable Control Register." bitfld.long 0x18 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit\nThis field is used to enable auto-convention error interrupt." "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled" bitfld.long 0x18 9. "RXTOEN,Receiver Buffer Time-out Interrupt Enable Bit\nThis field is used to enable receiver buffer time-out interrupt." "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled" newline bitfld.long 0x18 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled" bitfld.long 0x18 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12])" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled" newline bitfld.long 0x18 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt." "0: Block guard time Disabled,1: Block guard time Enabled" bitfld.long 0x18 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable TMR2 interrupt." "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled" newline bitfld.long 0x18 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt." "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled" bitfld.long 0x18 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt." "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled" newline bitfld.long 0x18 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]) frame error FEF(SC_STATUS[5]) parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled" bitfld.long 0x18 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt." "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled" newline bitfld.long 0x18 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt." "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled" rgroup.long 0x1C++0x7 line.long 0x0 "SCn_INTSTS,SCn Interrupt Status Register." bitfld.long 0x0 10. "ACERRIF,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F this bit will be set.\nNote: This bit is read only but it can be cleared by.." "0,1" bitfld.long 0x0 9. "RBTOIF,Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1" newline bitfld.long 0x0 8. "INITIF,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])) deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only but.." "0,1" bitfld.long 0x0 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).\nNote: This field is the status flag of CINSERT(SC_STATUS[12]) or.." "0,1" newline bitfld.long 0x0 6. "BGTIF,Block Guard Time Interrupt Status Flag (Read Only)\nThis field is used for block guard time interrupt status flag.\nNote1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.\nNote2: This bit is read only but it can be cleared by writing.." "?,1: This bit is valid when RXBGTEN" bitfld.long 0x0 5. "TMR2IF,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 4. "TMR1IF,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" bitfld.long 0x0 3. "TMR0IF,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 2. "TERRIF,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]) frame error FEF(SC_STATUS[5] .." "0,1" bitfld.long 0x0 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1" newline bitfld.long 0x0 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If.." "0,1" line.long 0x4 "SCn_STATUS,SCn Transfer Status Register." bitfld.long 0x4 31. "TXACT,Transmit in Active Status Flag (Read Only)" "0: This bit is cleared automatically when TX..,1: This bit is set by hardware when TX transfer is.." bitfld.long 0x4 30. "TXOVERR,Transmitter over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x4 29. "TXRERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU." "?,1: This bit is read only" bitfld.long 0x4 24.--25. "TXPOINT,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register TXPOINT.." "0,1,2,3" newline bitfld.long 0x4 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1" bitfld.long 0x4 22. "RXOVERR,Receiver over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by.." "?,1: This bit is read only" newline bitfld.long 0x4 21. "RXRERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "?,1: This bit is read only" bitfld.long 0x4 16.--17. "RXPOINT,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU .." "0,1,2,3" newline bitfld.long 0x4 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1" bitfld.long 0x4 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into.." "0,1" newline bitfld.long 0x4 8. "TXOV,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" bitfld.long 0x4 6. "BEF,Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "?,1: This bit is read only" newline bitfld.long 0x4 5. "FEF,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is.." "?,1: This bit is read only" bitfld.long 0x4 4. "PEF,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver.." "?,1: This bit is read only" newline bitfld.long 0x4 2. "RXFULL,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1" bitfld.long 0x4 1. "RXEMPTY,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU hardware sets this bit high. It will be cleared when SC receives any new data." "0,1" newline bitfld.long 0x4 0. "RXOV,RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing 1 to.." "0,1" group.long 0x24++0x13 line.long 0x0 "SCn_PINCTL,SCn Pin Control State Register." rbitfld.long 0x0 30. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to SC_PINCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" rbitfld.long 0x0 16. "DATSTS,SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DAT" "0: The SC_DAT pin is low,1: The SC_DAT pin is high" newline bitfld.long 0x0 11. "PWRINV,SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for.." "0,1" bitfld.long 0x0 10. "CDLV,Card Detect Level\ndetected. \nNote: Software must select card detect level before Smart Card engine is enabled." "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin from.." newline bitfld.long 0x0 9. "SCDOUT,SC Data Output Pin \nThis bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically. Thus do not.." "0: Drive SCDATOUT pin to low,1: Drive SCDATOUT pin to high" bitfld.long 0x0 7. "ADACEN,Auto Deactivation When Card Removal\nNote: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes hardware will generate an interrupt INITIF to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.." newline bitfld.long 0x0 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically. Thus do not fill in this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running" rbitfld.long 0x0 4. "CDPINSTS,Card Detect Status of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD" "0: The SC_CD pin state at low,1: The SC_CD pin state at high" newline rbitfld.long 0x0 3. "CINSERT,Card Detect Insert Status of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Thecard detect engine will start after SCEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" rbitfld.long 0x0 2. "CREMOVE,Card Detect Removal Status of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SCEN (SC_CTL[0])set." "0: No effect,1: This bit is read only" newline bitfld.long 0x0 1. "SCRST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.." bitfld.long 0x0 0. "PWREN,SC_PWREN Pin Signal\nSoftware can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage.." "0: SC_PWR pin status is low,1: SC_PWR pin status is high" line.long 0x4 "SCn_TMRCTL0,SCn Internal Timer 0 Control Register." rbitfld.long 0x4 31. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to the SC_TMRCTL0 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" hexmask.long.byte 0x4 24.--27. 1. "OPMODE,Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer0." newline hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value (ETU Based)\nThis field indicates the internal timer operation values." line.long 0x8 "SCn_TMRCTL1,SCn Internal Timer 1 Control Register." rbitfld.long 0x8 31. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to the SC_TMRCTL1 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" hexmask.long.byte 0x8 24.--27. 1. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer1." newline hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value (ETU Based)\nThis field indicates the internal timer operation values." line.long 0xC "SCn_TMRCTL2,SCn Internal Timer 2 Control Register." rbitfld.long 0xC 31. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to SC_TMRCTL2 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" hexmask.long.byte 0xC 24.--27. 1. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to Table6.153TimerOperation Modefor programming Timer2." newline hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value (ETU Based)\nThis field indicates the internal timer operation values." line.long 0x10 "SCn_UARTCTL,SCn UART Mode Control Register." bitfld.long 0x10 7. "OPE,Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'." "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or check.." bitfld.long 0x10 6. "PBOFF,Parity Bit Disable Control\nNote: In smart card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).." newline bitfld.long 0x10 4.--5. "WLS,Word Length Selection\nNote: In smart card mode this WLS must be '00'" "0: Word length is 8 bits,1: Word length is 7 bits,?,?" bitfld.long 0x10 0. "UARTEN,UART Mode Enable Bit\nNote3: When UART is enabled hardware will generate a resetto reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode" group.long 0x40++0x3 line.long 0x0 "SCn_ACTCTL,SCn Activation Control Register." hexmask.long.byte 0x0 0.--4. 1. "T1EXT,Configurable Cycles T1EXT in Hardware Activation \nThis field provide the configurable cycles to extend the Activation time T1\nThe cycle scaling factor is 2048.\nNote: setting 0 to this field conforms to the protocol ISO/IEC 7816-3" tree.end tree "SC1" base ad:0x401B0000 group.long 0x0++0x1B line.long 0x0 "SCn_DAT,SCn Receive/Transmit Holding Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive/Transmit Holding Buffer \nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.." line.long 0x4 "SCn_CTL,SCn Control Register." rbitfld.long 0x4 30. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit before writing a new value to RXRTY and TXRTY.SYNC delay is" "0: synchronizing is completion user can write new..,1: Last value is synchronizing" bitfld.long 0x4 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved." "0: De-bounce sample card insert once per 384 (128 *..,?,?,?" newline bitfld.long 0x4 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred." "0: TX error retry function Disabled,1: TX error retry function Enabled" bitfld.long 0x4 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "?,1: The real retry number is TXRTY + 1,2: This field cannot be changed when TXRTYEN enabled,?,?,?,?,?" newline bitfld.long 0x4 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RXRTY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled" bitfld.long 0x4 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "?,1: The real retry number is RX_ERETRY + 1,2: This field cannot be changed when RX_ERETRY_EN..,?,?,?,?,?" newline bitfld.long 0x4 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length." "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU" bitfld.long 0x4 13.--14. "TMRSEL,Timer Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,?" newline hexmask.long.byte 0x4 8.--12. 1. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1." bitfld.long 0x4 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled an interrupt will be generated)." "0: INTR_RDA Trigger Level with 01 Bytes,1: INTR_RDA Trigger Level with 02 Bytes,?,?" newline bitfld.long 0x4 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) is enabled this field is ignored." "0: Direct convention,1: Reserved,?,?" bitfld.long 0x4 3. "AUTOCEN,Auto Convention Enable Bit" "0: Auto-convention Disabled,1: Auto-convention Enabled. When hardware receives.." newline bitfld.long 0x4 2. "TXOFF,TX Transition Disable Bit" "0: The transceiver Enabled,1: The transceiver Disabled" bitfld.long 0x4 1. "RXOFF,RX Transition Disable Bit\nNote1: If AUTOCEN (SC_CTL[3])is enabled these fields must be ignored.\nNote2: After hardware activation and hardware warm reset are done RXOFF is set to 0 automatically." "0: The receiver Enabled,1: If AUTOCEN" newline bitfld.long 0x4 0. "SCEN,SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared SC will force all transition to IDLE state\nNote1: SCEN must be set to 1 before filling in other registers or smart card will not work properly.\nNote2: If SCEN.." "?,1: SCEN must be set to 1 before filling in other.." line.long 0x8 "SCn_ALTCTL,SCn Alternate Control Register." bitfld.long 0x8 16. "OUTSEL,Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode." "0: Quasi mode,1: Open-drain mode" rbitfld.long 0x8 15. "ACTSTS2,Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0])." "0: Timer2 is not active,1: Timer2 is active" newline rbitfld.long 0x8 14. "ACTSTS1,Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0])." "0: Timer1 is not active,1: Timer1 is active" rbitfld.long 0x8 13. "ACTSTS0,Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0])." "0: Timer0 is not active,1: Timer0 is active" newline bitfld.long 0x8 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled" bitfld.long 0x8 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in Figure 6.154SC Activation Sequence.\nWarm-reset:.." "0,1,2,3" newline bitfld.long 0x8 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled this filed cannot be programmed." "0: Stops counting,1: Start counting" bitfld.long 0x8 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled this filed cannot be programmed." "0: Stops counting,1: Start counting" newline bitfld.long 0x8 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled this filed cannot be programmed." "0: Stops counting,1: Start counting" bitfld.long 0x8 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set.." "0: No effect,1: When the warm reset sequence completed" newline bitfld.long 0x8 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to.." "0: No effect,1: When the activation sequence completed" bitfld.long 0x8 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be.." "0: No effect,1: When the deactivation sequence completed" newline bitfld.long 0x8 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers" bitfld.long 0x8 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers" line.long 0xC "SCn_EGT,SCn Extra Guard Time Register." hexmask.long.byte 0xC 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard timer value.\nNote: The counter is ETU base ." line.long 0x10 "SCn_RXTOUT,SCn Receive buffer Time-out Register." hexmask.long.word 0x10 0.--8. 1. "RFTM,SC Receiver FIFO Time-out \nNote1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function." line.long 0x14 "SCn_ETUCTL,SCn Element Time Unit Control Register." hexmask.long.word 0x14 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field but this field must be greater than 0x004." line.long 0x18 "SCn_INTEN,SCn Interrupt Enable Control Register." bitfld.long 0x18 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit\nThis field is used to enable auto-convention error interrupt." "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled" bitfld.long 0x18 9. "RXTOEN,Receiver Buffer Time-out Interrupt Enable Bit\nThis field is used to enable receiver buffer time-out interrupt." "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled" newline bitfld.long 0x18 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled" bitfld.long 0x18 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12])" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled" newline bitfld.long 0x18 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt." "0: Block guard time Disabled,1: Block guard time Enabled" bitfld.long 0x18 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable TMR2 interrupt." "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled" newline bitfld.long 0x18 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt." "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled" bitfld.long 0x18 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt." "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled" newline bitfld.long 0x18 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]) frame error FEF(SC_STATUS[5]) parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled" bitfld.long 0x18 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt." "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled" newline bitfld.long 0x18 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt." "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled" rgroup.long 0x1C++0x7 line.long 0x0 "SCn_INTSTS,SCn Interrupt Status Register." bitfld.long 0x0 10. "ACERRIF,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F this bit will be set.\nNote: This bit is read only but it can be cleared by.." "0,1" bitfld.long 0x0 9. "RBTOIF,Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1" newline bitfld.long 0x0 8. "INITIF,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])) deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only but.." "0,1" bitfld.long 0x0 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).\nNote: This field is the status flag of CINSERT(SC_STATUS[12]) or.." "0,1" newline bitfld.long 0x0 6. "BGTIF,Block Guard Time Interrupt Status Flag (Read Only)\nThis field is used for block guard time interrupt status flag.\nNote1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.\nNote2: This bit is read only but it can be cleared by writing.." "?,1: This bit is valid when RXBGTEN" bitfld.long 0x0 5. "TMR2IF,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 4. "TMR1IF,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" bitfld.long 0x0 3. "TMR0IF,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 2. "TERRIF,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]) frame error FEF(SC_STATUS[5] .." "0,1" bitfld.long 0x0 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1" newline bitfld.long 0x0 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If.." "0,1" line.long 0x4 "SCn_STATUS,SCn Transfer Status Register." bitfld.long 0x4 31. "TXACT,Transmit in Active Status Flag (Read Only)" "0: This bit is cleared automatically when TX..,1: This bit is set by hardware when TX transfer is.." bitfld.long 0x4 30. "TXOVERR,Transmitter over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x4 29. "TXRERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU." "?,1: This bit is read only" bitfld.long 0x4 24.--25. "TXPOINT,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register TXPOINT.." "0,1,2,3" newline bitfld.long 0x4 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1" bitfld.long 0x4 22. "RXOVERR,Receiver over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by.." "?,1: This bit is read only" newline bitfld.long 0x4 21. "RXRERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "?,1: This bit is read only" bitfld.long 0x4 16.--17. "RXPOINT,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU .." "0,1,2,3" newline bitfld.long 0x4 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1" bitfld.long 0x4 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into.." "0,1" newline bitfld.long 0x4 8. "TXOV,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" bitfld.long 0x4 6. "BEF,Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "?,1: This bit is read only" newline bitfld.long 0x4 5. "FEF,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is.." "?,1: This bit is read only" bitfld.long 0x4 4. "PEF,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver.." "?,1: This bit is read only" newline bitfld.long 0x4 2. "RXFULL,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1" bitfld.long 0x4 1. "RXEMPTY,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU hardware sets this bit high. It will be cleared when SC receives any new data." "0,1" newline bitfld.long 0x4 0. "RXOV,RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing 1 to.." "0,1" group.long 0x24++0x13 line.long 0x0 "SCn_PINCTL,SCn Pin Control State Register." rbitfld.long 0x0 30. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to SC_PINCTL register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" rbitfld.long 0x0 16. "DATSTS,SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DAT" "0: The SC_DAT pin is low,1: The SC_DAT pin is high" newline bitfld.long 0x0 11. "PWRINV,SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for.." "0,1" bitfld.long 0x0 10. "CDLV,Card Detect Level\ndetected. \nNote: Software must select card detect level before Smart Card engine is enabled." "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin from.." newline bitfld.long 0x0 9. "SCDOUT,SC Data Output Pin \nThis bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically. Thus do not.." "0: Drive SCDATOUT pin to low,1: Drive SCDATOUT pin to high" bitfld.long 0x0 7. "ADACEN,Auto Deactivation When Card Removal\nNote: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes hardware will generate an interrupt INITIF to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.." newline bitfld.long 0x0 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically. Thus do not fill in this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running" rbitfld.long 0x0 4. "CDPINSTS,Card Detect Status of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD" "0: The SC_CD pin state at low,1: The SC_CD pin state at high" newline rbitfld.long 0x0 3. "CINSERT,Card Detect Insert Status of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Thecard detect engine will start after SCEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" rbitfld.long 0x0 2. "CREMOVE,Card Detect Removal Status of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SCEN (SC_CTL[0])set." "0: No effect,1: This bit is read only" newline bitfld.long 0x0 1. "SCRST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.." bitfld.long 0x0 0. "PWREN,SC_PWREN Pin Signal\nSoftware can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage.." "0: SC_PWR pin status is low,1: SC_PWR pin status is high" line.long 0x4 "SCn_TMRCTL0,SCn Internal Timer 0 Control Register." rbitfld.long 0x4 31. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to the SC_TMRCTL0 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" hexmask.long.byte 0x4 24.--27. 1. "OPMODE,Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer0." newline hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value (ETU Based)\nThis field indicates the internal timer operation values." line.long 0x8 "SCn_TMRCTL1,SCn Internal Timer 1 Control Register." rbitfld.long 0x8 31. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to the SC_TMRCTL1 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" hexmask.long.byte 0x8 24.--27. 1. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer1." newline hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value (ETU Based)\nThis field indicates the internal timer operation values." line.long 0xC "SCn_TMRCTL2,SCn Internal Timer 2 Control Register." rbitfld.long 0xC 31. "SYNC,SYNC Flag Indicator(Read Only)\nDue to synchronization software should check this bit when writing a new value to SC_TMRCTL2 register." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing" hexmask.long.byte 0xC 24.--27. 1. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to Table6.153TimerOperation Modefor programming Timer2." newline hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value (ETU Based)\nThis field indicates the internal timer operation values." line.long 0x10 "SCn_UARTCTL,SCn UART Mode Control Register." bitfld.long 0x10 7. "OPE,Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'." "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or check.." bitfld.long 0x10 6. "PBOFF,Parity Bit Disable Control\nNote: In smart card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).." newline bitfld.long 0x10 4.--5. "WLS,Word Length Selection\nNote: In smart card mode this WLS must be '00'" "0: Word length is 8 bits,1: Word length is 7 bits,?,?" bitfld.long 0x10 0. "UARTEN,UART Mode Enable Bit\nNote3: When UART is enabled hardware will generate a resetto reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode" group.long 0x40++0x3 line.long 0x0 "SCn_ACTCTL,SCn Activation Control Register." hexmask.long.byte 0x0 0.--4. 1. "T1EXT,Configurable Cycles T1EXT in Hardware Activation \nThis field provide the configurable cycles to extend the Activation time T1\nThe cycle scaling factor is 2048.\nNote: setting 0 to this field conforms to the protocol ISO/IEC 7816-3" tree.end tree.end tree "SCS (System Controllers Space)" base ad:0x0 tree "INT" base ad:0x50000300 rgroup.long 0x0++0x7F line.long 0x0 "IRQ0_SRC,MCU IRQ0 (BOD_INT) interrupt source identify" hexmask.long.byte 0x0 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x4 "IRQ1_SRC,MCU IRQ1 (BOD_INT) interrupt source identify" hexmask.long.byte 0x4 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x8 "IRQ2_SRC,MCU IRQ2 (BOD_INT) interrupt source identify" hexmask.long.byte 0x8 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0xC "IRQ3_SRC,MCU IRQ3 (BOD_INT) interrupt source identify" hexmask.long.byte 0xC 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x10 "IRQ4_SRC,MCU IRQ4 (BOD_INT) interrupt source identify" hexmask.long.byte 0x10 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x14 "IRQ5_SRC,MCU IRQ5 (BOD_INT) interrupt source identify" hexmask.long.byte 0x14 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x18 "IRQ6_SRC,MCU IRQ6 (BOD_INT) interrupt source identify" hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x1C "IRQ7_SRC,MCU IRQ7 (BOD_INT) interrupt source identify" hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x20 "IRQ8_SRC,MCU IRQ8 (BOD_INT) interrupt source identify" hexmask.long.byte 0x20 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x24 "IRQ9_SRC,MCU IRQ9 (BOD_INT) interrupt source identify" hexmask.long.byte 0x24 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x28 "IRQ10_SRC,MCU IRQ10 (BOD_INT) interrupt source identify" hexmask.long.byte 0x28 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x2C "IRQ11_SRC,MCU IRQ11 (BOD_INT) interrupt source identify" hexmask.long.byte 0x2C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x30 "IRQ12_SRC,MCU IRQ12 (BOD_INT) interrupt source identify" hexmask.long.byte 0x30 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x34 "IRQ13_SRC,MCU IRQ13 (BOD_INT) interrupt source identify" hexmask.long.byte 0x34 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x38 "IRQ14_SRC,MCU IRQ14 (BOD_INT) interrupt source identify" hexmask.long.byte 0x38 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x3C "IRQ15_SRC,MCU IRQ15 (BOD_INT) interrupt source identify" hexmask.long.byte 0x3C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x40 "IRQ16_SRC,MCU IRQ16 (BOD_INT) interrupt source identify" hexmask.long.byte 0x40 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x44 "IRQ17_SRC,MCU IRQ17 (BOD_INT) interrupt source identify" hexmask.long.byte 0x44 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x48 "IRQ18_SRC,MCU IRQ18 (BOD_INT) interrupt source identify" hexmask.long.byte 0x48 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x4C "IRQ19_SRC,MCU IRQ19 (BOD_INT) interrupt source identify" hexmask.long.byte 0x4C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x50 "IRQ20_SRC,MCU IRQ20 (BOD_INT) interrupt source identify" hexmask.long.byte 0x50 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x54 "IRQ21_SRC,MCU IRQ21 (BOD_INT) interrupt source identify" hexmask.long.byte 0x54 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x58 "IRQ22_SRC,MCU IRQ22 (BOD_INT) interrupt source identify" hexmask.long.byte 0x58 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x5C "IRQ23_SRC,MCU IRQ23 (BOD_INT) interrupt source identify" hexmask.long.byte 0x5C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x60 "IRQ24_SRC,MCU IRQ24 (BOD_INT) interrupt source identify" hexmask.long.byte 0x60 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x64 "IRQ25_SRC,MCU IRQ25 (BOD_INT) interrupt source identify" hexmask.long.byte 0x64 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x68 "IRQ26_SRC,MCU IRQ26 (BOD_INT) interrupt source identify" hexmask.long.byte 0x68 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x6C "IRQ27_SRC,MCU IRQ27 (BOD_INT) interrupt source identify" hexmask.long.byte 0x6C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x70 "IRQ28_SRC,MCU IRQ28 (BOD_INT) interrupt source identify" hexmask.long.byte 0x70 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x74 "IRQ29_SRC,MCU IRQ29 (BOD_INT) interrupt source identify" hexmask.long.byte 0x74 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x78 "IRQ30_SRC,MCU IRQ30 (BOD_INT) interrupt source identify" hexmask.long.byte 0x78 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x7C "IRQ31_SRC,MCU IRQ31 (BOD_INT) interrupt source identify" hexmask.long.byte 0x7C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." group.long 0x80++0x7 line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt to Cortex-M0 Can Be Selected From One of the Interrupt[31:0]\nThe NMI_SEL bit[4:0] is used to select the NMI interrupt source" line.long 0x4 "MCU_IRQ,MCU Interrupt Request Source Register" hexmask.long 0x4 0.--31. 1. "MCU_IRQ,MCU IRQ Source Bits\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to Cortex-M0 the normal mode.\nThe MCU_IRQ collects all.." tree.end tree "SCS" base ad:0xE000E000 group.long 0x10++0xB line.long 0x0 "SYST_CTL,SysTick Control and Status" bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 If Timer Counted to 0 Since Last Time this Register Was Read" "0: COUNTFLAG is cleared on read or by a write to..,1: COUNTFLAG is set by a count transition from 1 to 0" bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Select Bit" "0: Clock source is optional refer to STCLKSEL,1: Core clock used for SysTick timer" newline bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enable Control" "0: Counting down to 0 will not cause the SysTick..,1: Counting down to 0 will cause the SysTick.." bitfld.long 0x0 0. "ENABLE,System Tick Counter Enable Control" "0: System Tick counter Disabled,1: System Tick counter will operate in a multi-shot.." line.long 0x4 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0." line.long 0x8 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.." group.long 0x100++0x3 line.long 0x0 "NVIC_ISER,IRQ0~IRQ31 Set-Enable Control Register" hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Bits\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status." group.long 0x180++0x3 line.long 0x0 "NVIC_ICER,IRQ0~IRQ31 Clear-Enable Control Register" hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status." group.long 0x200++0x3 line.long 0x0 "NVIC_ISPR,IRQ0~IRQ31 Set-Pending Control Register" hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending\nWrite Operation:\nNote: Read value indicates the current pending status." group.long 0x280++0x3 line.long 0x0 "NVIC_ICPR,IRQ0~IRQ31Clear-Pending Control Register" hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending\nWrite Operation:\nNote: Read value indicates the current pending status." group.long 0x400++0x1F line.long 0x0 "NVIC_IPR0,IRQ0~IRQ3 Priority Control Register" bitfld.long 0x0 30.--31. "PRI_3,Priority of IRQ3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x0 22.--23. "PRI_2,Priority of IRQ2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x0 14.--15. "PRI_1,Priority of IRQ1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x0 6.--7. "PRI_0,Priority of IRQ0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x4 "NVIC_IPR1,IRQ4~IRQ7 Priority Control Register" bitfld.long 0x4 30.--31. "PRI_7,Priority of IRQ7\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_6,Priority of IRQ6\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x4 14.--15. "PRI_5,Priority of IRQ5\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 6.--7. "PRI_4,Priority of IRQ4\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x8 "NVIC_IPR2,IRQ8~IRQ11 Priority Control Register" bitfld.long 0x8 30.--31. "PRI_11,Priority of IRQ11\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x8 22.--23. "PRI_10,Priority of IRQ10\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x8 14.--15. "PRI_9,Priority of IRQ9\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x8 6.--7. "PRI_8,Priority of IRQ8\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0xC "NVIC_IPR3,IRQ12~IRQ15 Priority Control Register" bitfld.long 0xC 30.--31. "PRI_15,Priorityof IRQ15\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0xC 22.--23. "PRI_14,Priority of IRQ14\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0xC 14.--15. "PRI_13,Priority of IRQ13\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0xC 6.--7. "PRI_12,Priority of IRQ12\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x10 "NVIC_IPR4,IRQ16~IRQ19 Priority Control Register" bitfld.long 0x10 30.--31. "PRI_19,Priority of IRQ19\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x10 22.--23. "PRI_18,Priority of IRQ18\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x10 14.--15. "PRI_17,Priority of IRQ17\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x10 6.--7. "PRI_16,Priority of IRQ16\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x14 "NVIC_IPR5,IRQ20~IRQ23 Priority Control Register" bitfld.long 0x14 30.--31. "PRI_23,Priority of IRQ23\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x14 22.--23. "PRI_22,Priority of IRQ22\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x14 14.--15. "PRI_21,Priority of IRQ21\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x14 6.--7. "PRI_20,Priority of IRQ20\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x18 "NVIC_IPR6,IRQ24~IRQ27 Priority Control Register" bitfld.long 0x18 30.--31. "PRI_27,Priority of IRQ27\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x18 22.--23. "PRI_26,Priority of IRQ26\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x18 14.--15. "PRI_25,Priority of IRQ25\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x18 6.--7. "PRI_24,Priority of IRQ24\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x1C "NVIC_IPR7,IRQ28~IRQ31 Priority Control Register" bitfld.long 0x1C 30.--31. "PRI_31,Priority of IRQ31\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x1C 22.--23. "PRI_30,Priority of IRQ30\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x1C 14.--15. "PRI_29,Priority of IRQ29\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x1C 6.--7. "PRI_28,Priority of IRQ28\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" rgroup.long 0xD00++0x3 line.long 0x0 "CPUID,CPUID Base Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer Code" hexmask.long.byte 0x0 16.--19. 1. "PART,Architecture of the Processor \nReads as 0xC for ARMv6-M parts" newline hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number of the Processor \nReads as 0xC20." hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision Number \nReads as 0x0" group.long 0xD04++0x3 line.long 0x0 "ICSR,Interrupt Control State Register" bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0." "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.." bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.." newline bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nThis bit is write-only. To clear the PENDSV bit you must 'write 0 to PENDSVSET andwrite 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.." bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.." newline bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This bit is write-only. When you want to clear PENDST bit you must 'write 0 toPENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.." rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit(Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1" newline rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending" hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Exception Number of the Highest Priority Pending Enabled Exception" newline hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Contains the Active Exception Number" group.long 0xD10++0x3 line.long 0x0 "SCR,System Control Register" bitfld.long 0x0 4. "SEVONPEND,Send Event on Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processorfrom WFE. If the processor is not waiting for an event the event is registered and affectsthe next WFE.\nThe processor also.." "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.." bitfld.long 0x0 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:" "0: Sleep mode,1: Deep Sleep mode" newline bitfld.long 0x0 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode." "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.." group.long 0xD1C++0x7 line.long 0x0 "SHPR2,System Handler Priority Register 2" bitfld.long 0x0 30.--31. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x4 "SHPR3,System Handler Priority Register 3" bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" tree.end tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI0" base ad:0x40030000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKCLKEN,Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up this bit must be cleared.." "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x0 30. "WKSSEN,Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any.." "0: Wake-up function Disabled,1: Wake-up function Enabled" newline bitfld.long 0x0 29. "DUALIOEN,Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section." "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" bitfld.long 0x0 28. "DUALDIR,Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section." "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function." newline bitfld.long 0x0 22. "TWOBIT,2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically" "0: 2-bit transfer mode Disabled,1: 2-bit transfer mode Enabled" bitfld.long 0x0 21. "FIFOM,FIFO Mode EnableBit\nNote: Refer to FIFO Mode section." "0: FIFO mode Disabled (in Normal mode),1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode." "0: Byte reorderfunction Disabled,1: Enable byte reorder function and insert a byte.." bitfld.long 0x0 18. "SLAVE,Slave Mode Selection\nNote: Refer to Slave Selection section" "0: SPI controller set as Master mode,1: SPI controller set as Slave mode" newline bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transferinterrupt Enabled" hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Only)" newline bitfld.long 0x0 11. "CLKPOL,Clock Polarity\nNote: Refer to Clock Parity section." "0: The default level of SCLK is low,1: The default level of SCLK is high" bitfld.long 0x0 10. "LSB,Send LSB First\nNote: Refer to LSB first section." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits." bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: Refer to Edge section." "0: The transmitted data output is changed on the..,1: The transmitted data output is changed on the.." newline bitfld.long 0x0 1. "RXNEG,Receiveon Negative Edge\nNote: Refer to Edge section." "0: The received data is latched on the rising edge..,1: The received data is latched on the falling edge.." bitfld.long 0x0 0. "GOBUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI.." "0: Writing this bit '0' will stop data transfer if..,1: In Master mode writing '1' to this bit will.." line.long 0x4 "SPI_STATUS,SPI Status Register" bitfld.long 0x4 31. "WKCLKIF,Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" bitfld.long 0x4 30. "WKSSIF,Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "TXCNT,Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." hexmask.long.byte 0x4 16.--19. 1. "RXCNT,Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x4 15. "SLVTXSKE,Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode." "0,1" bitfld.long 0x4 13. "SLVTOIF,Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1 this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit." "0: Slave time-out does not occur yet,1: Slave time-out has occurred" newline bitfld.long 0x4 12. "RXTOIF,Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it." "0: There is not time-out event on the received buffer,1: Time out event active in RX FIFO is not empty" rbitfld.long 0x4 10. "TXTHIF,Transmit FIFO Threshold Interrupt Flag(Read Only)" "0: TX valid data counts bigger than TXTH..,1: TX valid data counts small or equal than TXTH" newline bitfld.long 0x4 9. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full this bit will set to 1 and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it." "0: No FIFO over run,1: If SPI receives data when RX FIFO is full" rbitfld.long 0x4 8. "RXTHIF,RX FIFO Threshold Interrupt Flag(Read Only)" "0: RX valid data counts small or equal than RXTH..,1: RX valid data counts bigger than RXTH" newline bitfld.long 0x4 7. "UNITIF,Unit Transfer Interrupt Flag\nNote 2: This bitcan be cleared by writing '1' to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit.." bitfld.long 0x4 6. "SLVSTAIF,Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select." "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline rbitfld.long 0x4 4. "LTRIGF,Level Trigger Accomplish Flag(Read Only)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1 .." "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." rbitfld.long 0x4 3. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmitted data FIFO is not full in the FIFO mode,1: Transmitted data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 2. "TXEMPTY,Transmit FIFO Buffer Empty Indicator(Read Only)" "0: Transmitted data FIFO is not empty in the FIFO..,1: Transmitted data FIFO is empty in the FIFO mode" rbitfld.long 0x4 1. "RXFULL,Receive FIFO Buffer Full Indicator(Read Only)" "0: Received data FIFO is not full in FIFO mode,1: Received data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 0. "RXEMPTY,Receive FIFO Buffer Empty Indicator(Read Only)" "0: Received data FIFO is not empty in the FIFO mode,1: Received data FIFO is empty in the FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x8 0.--7. 1. "DIVIDER,Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the.." line.long 0xC "SPI_SSCTL,SPI Slave Select Control Register" hexmask.long.word 0xC 20.--29. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0 it indicates the.." bitfld.long 0xC 16. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." newline bitfld.long 0xC 9. "SSTAIEN,Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode." "0: Transfer start interrupt Disabled in no slave..,1: Transaction start interrupt Enabled in no slave.." bitfld.long 0xC 8. "SLVABORT,Abort in Slave Mode with No Slave Selected\nRefer to No Slave Select Mode.\nNote: It is auto cleared to '0' by hardware when the abort event is active." "0: No force the slave abort,1: Force the current transfer done in no slave.." newline bitfld.long 0xC 6. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur" "0: Slave time-out function and interrupt both..,1: Slave time-out function and interrupt both Enabled" bitfld.long 0xC 5. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nThis bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote 1:Refer to No.." "0: The controller is 4-wire bi-direction interface,1: Refer to No Slave Select Mode" newline bitfld.long 0xC 4. "SSLTRIG,Slave Select Level Trigger Control" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPI_SS0 and SPI_SS1.." newline bitfld.long 0xC 2. "SSACTPOL,Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0])." "0: The SPI_SS slave select signal is active Low,1: The SPI_SS slave select signal is active High" bitfld.long 0xC 0.--1. "SS,Slave SelectionControl (Master Only)\nIf AUTOSS bit (SPI_SSCTL[3]) is cleared writing '1' to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing '0' sets the line back to inactive state(the same as SPI_CTL[1] for.." "0: Both SPI_SS1 and SPI_SS0 are inactive,1: SPI_SS1 is inactive SPI_SS0 is active.\nSPI_SS1..,?,?" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." group.long 0x38++0x7 line.long 0x0 "SPI_PDMACTL,SPI PDMA Control Register" bitfld.long 0x0 2. "PDMARST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state.\nNote:It is auto cleared to '0' after the reset function has done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RXPDMAEN,Receiving PDMA EnableBit\nRefer to PDMA section for more detail information.\nNote:\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nIn Slave mode and the FIFO bit is disabled if the receive PDMA is enabled but the.." "0: Receiver PDMA function Disabled,1: Receiver PDMA function Enabled" newline bitfld.long 0x0 0. "TXPDMAEN,Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" line.long 0x4 "SPI_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TXTH,Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH TXTHIF(SPI_STATUS[10])will be set to 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "RXTH,Received FIFO Threshold\nIf RX valid data counts are greater than RXTH RXTHIF (SPI_STATUS[8])will be set to 1.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RXTOIEN,RX Read Time Out Interrupt Enable Bit" "0: RXread Time-out Interrupt Disabled,1: RX read Time-out Interrupt Enabled" bitfld.long 0x4 4. "RXOVIEN,ReceiveFIFO Overrun Interrupt Enable Bit" "0: RXFIFO overrun interrupt Disabled,1: RX FIFO overrun interrupt Enabled" newline bitfld.long 0x4 3. "TXTHIEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0x4 2. "RXTHIEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0x4 1. "TXFBCLR,Transmit FIFO Buffer Clear\nNote:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0: Not clear the transmitted FIFO,1: Clear the transmitted FIFO" bitfld.long 0x4 0. "RXFBCLR,Receive FIFO Buffer Clear\nNote:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0: No clear the received FIFO,1: Clear the received FIFO" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" tree.end tree "SPI1" base ad:0x40130000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKCLKEN,Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up this bit must be cleared.." "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x0 30. "WKSSEN,Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any.." "0: Wake-up function Disabled,1: Wake-up function Enabled" newline bitfld.long 0x0 29. "DUALIOEN,Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section." "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" bitfld.long 0x0 28. "DUALDIR,Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section." "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function" newline bitfld.long 0x0 22. "TWOBIT,2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically" "0: 2-bit transfer mode Disabled,1: 2-bit transfer mode Enabled" bitfld.long 0x0 21. "FIFOM,FIFO Mode EnableBit\nNote: Refer to FIFO Mode section." "0: FIFO mode Disabled (in Normal mode),1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode." "0: Byte reorderfunction Disabled,1: Enable byte reorder function and insert a byte.." bitfld.long 0x0 18. "SLAVE,Slave Mode Selection\nNote: Refer to Slave Selection section" "0: SPI controller set as Master mode,1: SPI controller set as Slave mode" newline bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transferinterrupt Enabled" hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Only)" newline bitfld.long 0x0 11. "CLKPOL,Clock Polarity\nNote: Refer to Clock Parity section." "0: The default level of SCLK is low,1: The default level of SCLK is high" bitfld.long 0x0 10. "LSB,Send LSB First\nNote: Refer to LSB first section." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits." bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: Refer to Edge section." "0: The transmitted data output is changed on the..,1: The transmitted data output is changed on the.." newline bitfld.long 0x0 1. "RXNEG,Receiveon Negative Edge\nNote: Refer to Edge section." "0: The received data is latched on the rising edge..,1: The received data is latched on the falling edge.." bitfld.long 0x0 0. "GOBUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI.." "0: Writing this bit '0' will stop data transfer if..,1: In Master mode writing '1' to this bit will.." line.long 0x4 "SPI_STATUS,SPI Status Register" bitfld.long 0x4 31. "WKCLKIF,Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" bitfld.long 0x4 30. "WKSSIF,Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "TXCNT,Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." hexmask.long.byte 0x4 16.--19. 1. "RXCNT,Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x4 15. "SLVTXSKE,Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode." "0,1" bitfld.long 0x4 13. "SLVTOIF,Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1 this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit." "0: Slave time-out does not occur yet,1: Slave time-out has occurred" newline bitfld.long 0x4 12. "RXTOIF,Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it." "0: There is not time-out event on the received buffer,1: Time out event active in RX FIFO is not empty" rbitfld.long 0x4 10. "TXTHIF,Transmit FIFO Threshold Interrupt Flag(Read Only)" "0: TX valid data counts bigger than TXTH..,1: TX valid data counts small or equal than TXTH" newline bitfld.long 0x4 9. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full this bit will set to 1 and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it." "0: No FIFO over run,1: If SPI receives data when RX FIFO is full" rbitfld.long 0x4 8. "RXTHIF,RX FIFO Threshold Interrupt Flag(Read Only)" "0: RX valid data counts small or equal than RXTH..,1: RX valid data counts bigger than RXTH" newline bitfld.long 0x4 7. "UNITIF,Unit Transfer Interrupt Flag\nNote 2: This bitcan be cleared by writing '1' to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit.." bitfld.long 0x4 6. "SLVSTAIF,Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select." "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline rbitfld.long 0x4 4. "LTRIGF,Level Trigger Accomplish Flag(Read Only)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1 .." "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." rbitfld.long 0x4 3. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmitted data FIFO is not full in the FIFO mode,1: Transmitted data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 2. "TXEMPTY,Transmit FIFO Buffer Empty Indicator(Read Only)" "0: Transmitted data FIFO is not empty in the FIFO..,1: Transmitted data FIFO is empty in the FIFO mode" rbitfld.long 0x4 1. "RXFULL,Receive FIFO Buffer Full Indicator(Read Only)" "0: Received data FIFO is not full in FIFO mode,1: Received data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 0. "RXEMPTY,Receive FIFO Buffer Empty Indicator(Read Only)" "0: Received data FIFO is not empty in the FIFO mode,1: Received data FIFO is empty in the FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x8 0.--7. 1. "DIVIDER,Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the.." line.long 0xC "SPI_SSCTL,SPI Slave Select Control Register" hexmask.long.word 0xC 20.--29. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0 it indicates the.." bitfld.long 0xC 16. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." newline bitfld.long 0xC 9. "SSTAIEN,Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode." "0: Transfer start interrupt Disabled in no slave..,1: Transaction start interrupt Enabled in no slave.." bitfld.long 0xC 8. "SLVABORT,Abort in Slave Mode with No Slave Selected\nRefer to No Slave Select Mode.\nNote: It is auto cleared to '0' by hardware when the abort event is active." "0: No force the slave abort,1: Force the current transfer done in no slave.." newline bitfld.long 0xC 6. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur" "0: Slave time-out function and interrupt both..,1: Slave time-out function and interrupt both Enabled" bitfld.long 0xC 5. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nThis bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote 1:Refer to No.." "0: The controller is 4-wire bi-direction interface,1: Refer to No Slave Select Mode" newline bitfld.long 0xC 4. "SSLTRIG,Slave Select Level Trigger Control" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPI_SS0 and SPI_SS1.." newline bitfld.long 0xC 2. "SSACTPOL,Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0])." "0: The SPI_SS slave select signal is active Low,1: The SPI_SS slave select signal is active High" bitfld.long 0xC 0.--1. "SS,Slave SelectionControl (Master Only)\nIf AUTOSS bit (SPI_SSCTL[3]) is cleared writing '1' to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing '0' sets the line back to inactive state(the same as SPI_CTL[1] for.." "0: Both SPI_SS1 and SPI_SS0 are inactive,1: SPI_SS1 is inactive SPI_SS0 is active.\nSPI_SS1..,?,?" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." group.long 0x38++0x7 line.long 0x0 "SPI_PDMACTL,SPI PDMA Control Register" bitfld.long 0x0 2. "PDMARST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state.\nNote:It is auto cleared to '0' after the reset function has done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RXPDMAEN,Receiving PDMA EnableBit\nRefer to PDMA section for more detail information.\nNote:\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nIn Slave mode and the FIFO bit is disabled if the receive PDMA is enabled but the.." "0: Receiver PDMA function Disabled,1: Receiver PDMA function Enabled" newline bitfld.long 0x0 0. "TXPDMAEN,Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" line.long 0x4 "SPI_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TXTH,Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH TXTHIF(SPI_STATUS[10])will be set to 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "RXTH,Received FIFO Threshold\nIf RX valid data counts are greater than RXTH RXTHIF (SPI_STATUS[8])will be set to 1.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RXTOIEN,RX Read Time Out Interrupt Enable Bit" "0: RXread Time-out Interrupt Disabled,1: RX read Time-out Interrupt Enabled" bitfld.long 0x4 4. "RXOVIEN,ReceiveFIFO Overrun Interrupt Enable Bit" "0: RXFIFO overrun interrupt Disabled,1: RX FIFO overrun interrupt Enabled" newline bitfld.long 0x4 3. "TXTHIEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0x4 2. "RXTHIEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0x4 1. "TXFBCLR,Transmit FIFO Buffer Clear\nNote:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0: Not clear the transmitted FIFO,1: Clear the transmitted FIFO" bitfld.long 0x4 0. "RXFBCLR,Receive FIFO Buffer Clear\nNote:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0: No clear the received FIFO,1: Clear the received FIFO" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" tree.end tree "SPI2" base ad:0x400D0000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKCLKEN,Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up this bit must be cleared.." "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x0 30. "WKSSEN,Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any.." "0: Wake-up function Disabled,1: Wake-up function Enabled" newline bitfld.long 0x0 29. "DUALIOEN,Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section." "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" bitfld.long 0x0 28. "DUALDIR,Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section." "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function" newline bitfld.long 0x0 22. "TWOBIT,2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically" "0: 2-bit transfer mode Disabled,1: 2-bit transfer mode Enabled" bitfld.long 0x0 21. "FIFOM,FIFO Mode EnableBit\nNote: Refer to FIFO Mode section." "0: FIFO mode Disabled (in Normal mode),1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode." "0: Byte reorderfunction Disabled,1: Enable byte reorder function and insert a byte.." bitfld.long 0x0 18. "SLAVE,Slave Mode Selection\nNote: Refer to Slave Selection section" "0: SPI controller set as Master mode,1: SPI controller set as Slave mode" newline bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transferinterrupt Enabled" hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Only)" newline bitfld.long 0x0 11. "CLKPOL,Clock Polarity\nNote: Refer to Clock Parity section." "0: The default level of SCLK is low,1: The default level of SCLK is high" bitfld.long 0x0 10. "LSB,Send LSB First\nNote: Refer to LSB first section." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits." bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: Refer to Edge section." "0: The transmitted data output is changed on the..,1: The transmitted data output is changed on the.." newline bitfld.long 0x0 1. "RXNEG,Receiveon Negative Edge\nNote: Refer to Edge section." "0: The received data is latched on the rising edge..,1: The received data is latched on the falling edge.." bitfld.long 0x0 0. "GOBUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI.." "0: Writing this bit '0' will stop data transfer if..,1: In Master mode writing '1' to this bit will.." line.long 0x4 "SPI_STATUS,SPI Status Register" bitfld.long 0x4 31. "WKCLKIF,Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" bitfld.long 0x4 30. "WKSSIF,Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "TXCNT,Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." hexmask.long.byte 0x4 16.--19. 1. "RXCNT,Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x4 15. "SLVTXSKE,Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode." "0,1" bitfld.long 0x4 13. "SLVTOIF,Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1 this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit." "0: Slave time-out does not occur yet,1: Slave time-out has occurred" newline bitfld.long 0x4 12. "RXTOIF,Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it." "0: There is not time-out event on the received buffer,1: Time out event active in RX FIFO is not empty" rbitfld.long 0x4 10. "TXTHIF,Transmit FIFO Threshold Interrupt Flag(Read Only)" "0: TX valid data counts bigger than TXTH..,1: TX valid data counts small or equal than TXTH" newline bitfld.long 0x4 9. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full this bit will set to 1 and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it." "0: No FIFO over run,1: If SPI receives data when RX FIFO is full" rbitfld.long 0x4 8. "RXTHIF,RX FIFO Threshold Interrupt Flag(Read Only)" "0: RX valid data counts small or equal than RXTH..,1: RX valid data counts bigger than RXTH" newline bitfld.long 0x4 7. "UNITIF,Unit Transfer Interrupt Flag\nNote 2: This bitcan be cleared by writing '1' to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit.." bitfld.long 0x4 6. "SLVSTAIF,Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select." "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline rbitfld.long 0x4 4. "LTRIGF,Level Trigger Accomplish Flag(Read Only)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1 .." "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." rbitfld.long 0x4 3. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmitted data FIFO is not full in the FIFO mode,1: Transmitted data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 2. "TXEMPTY,Transmit FIFO Buffer Empty Indicator(Read Only)" "0: Transmitted data FIFO is not empty in the FIFO..,1: Transmitted data FIFO is empty in the FIFO mode" rbitfld.long 0x4 1. "RXFULL,Receive FIFO Buffer Full Indicator(Read Only)" "0: Received data FIFO is not full in FIFO mode,1: Received data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 0. "RXEMPTY,Receive FIFO Buffer Empty Indicator(Read Only)" "0: Received data FIFO is not empty in the FIFO mode,1: Received data FIFO is empty in the FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x8 0.--7. 1. "DIVIDER,Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the.." line.long 0xC "SPI_SSCTL,SPI Slave Select Control Register" hexmask.long.word 0xC 20.--29. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0 it indicates the.." bitfld.long 0xC 16. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." newline bitfld.long 0xC 9. "SSTAIEN,Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode." "0: Transfer start interrupt Disabled in no slave..,1: Transaction start interrupt Enabled in no slave.." bitfld.long 0xC 8. "SLVABORT,Abort in Slave Mode with No Slave Selected\nRefer to No Slave Select Mode.\nNote: It is auto cleared to '0' by hardware when the abort event is active." "0: No force the slave abort,1: Force the current transfer done in no slave.." newline bitfld.long 0xC 6. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur" "0: Slave time-out function and interrupt both..,1: Slave time-out function and interrupt both Enabled" bitfld.long 0xC 5. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nThis bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote 1:Refer to No.." "0: The controller is 4-wire bi-direction interface,1: Refer to No Slave Select Mode" newline bitfld.long 0xC 4. "SSLTRIG,Slave Select Level Trigger Control" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPI_SS0 and SPI_SS1.." newline bitfld.long 0xC 2. "SSACTPOL,Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0])." "0: The SPI_SS slave select signal is active Low,1: The SPI_SS slave select signal is active High" bitfld.long 0xC 0.--1. "SS,Slave SelectionControl (Master Only)\nIf AUTOSS bit (SPI_SSCTL[3]) is cleared writing '1' to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing '0' sets the line back to inactive state(the same as SPI_CTL[1] for.." "0: Both SPI_SS1 and SPI_SS0 are inactive,1: SPI_SS1 is inactive SPI_SS0 is active.\nSPI_SS1..,?,?" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." group.long 0x38++0x7 line.long 0x0 "SPI_PDMACTL,SPI PDMA Control Register" bitfld.long 0x0 2. "PDMARST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state.\nNote:It is auto cleared to '0' after the reset function has done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RXPDMAEN,Receiving PDMA EnableBit\nRefer to PDMA section for more detail information.\nNote:\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nIn Slave mode and the FIFO bit is disabled if the receive PDMA is enabled but the.." "0: Receiver PDMA function Disabled,1: Receiver PDMA function Enabled" newline bitfld.long 0x0 0. "TXPDMAEN,Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" line.long 0x4 "SPI_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TXTH,Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH TXTHIF(SPI_STATUS[10])will be set to 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "RXTH,Received FIFO Threshold\nIf RX valid data counts are greater than RXTH RXTHIF (SPI_STATUS[8])will be set to 1.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RXTOIEN,RX Read Time Out Interrupt Enable Bit" "0: RXread Time-out Interrupt Disabled,1: RX read Time-out Interrupt Enabled" bitfld.long 0x4 4. "RXOVIEN,ReceiveFIFO Overrun Interrupt Enable Bit" "0: RXFIFO overrun interrupt Disabled,1: RX FIFO overrun interrupt Enabled" newline bitfld.long 0x4 3. "TXTHIEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0x4 2. "RXTHIEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0x4 1. "TXFBCLR,Transmit FIFO Buffer Clear\nNote:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0: Not clear the transmitted FIFO,1: Clear the transmitted FIFO" bitfld.long 0x4 0. "RXFBCLR,Receive FIFO Buffer Clear\nNote:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0: No clear the received FIFO,1: Clear the received FIFO" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" tree.end tree "SPI3" base ad:0x401E0000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKCLKEN,Wake-up by SPI Clock EnableBit\nNote: When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port. After the system wake-up this bit must be cleared.." "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x0 30. "WKSSEN,Wake-up by Slave Select EnableBit\nNote: The Slave select wake-up function is only available in SPI Slave mode. When the system enters Power-down mode the system can be wake-up from the SPI controller if this bit is enabled and there is any.." "0: Wake-up function Disabled,1: Wake-up function Enabled" newline bitfld.long 0x0 29. "DUALIOEN,Dual I/O Mode EnableBit\nRefer to Dual I/O Mode section." "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" bitfld.long 0x0 28. "DUALDIR,Dual I/O Mode Direction Control\nRefer to Dual I/O Mode section." "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function" newline bitfld.long 0x0 22. "TWOBIT,2-bit Transfer Mode Enable Bit\nRefer to Two Bit Transfer Mode section\nNote: automatically" "0: 2-bit transfer mode Disabled,1: 2-bit transfer mode Enabled" bitfld.long 0x0 21. "FIFOM,FIFO Mode EnableBit\nNote: Refer to FIFO Mode section." "0: FIFO mode Disabled (in Normal mode),1: FIFO mode Enabled" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function EnableBit\nNote: The suspend interval is defined in SUSPITV.Refer to Byte Reorder section.\nNote: Byte Suspend is only used in SPI Byte Reorder mode." "0: Byte reorderfunction Disabled,1: Enable byte reorder function and insert a byte.." bitfld.long 0x0 18. "SLAVE,Slave Mode Selection\nNote: Refer to Slave Selection section" "0: SPI controller set as Master mode,1: SPI controller set as Slave mode" newline bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transferinterrupt Enabled" hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Only)" newline bitfld.long 0x0 11. "CLKPOL,Clock Polarity\nNote: Refer to Clock Parity section." "0: The default level of SCLK is low,1: The default level of SCLK is high" bitfld.long 0x0 10. "LSB,Send LSB First\nNote: Refer to LSB first section." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits." bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: Refer to Edge section." "0: The transmitted data output is changed on the..,1: The transmitted data output is changed on the.." newline bitfld.long 0x0 1. "RXNEG,Receiveon Negative Edge\nNote: Refer to Edge section." "0: The received data is latched on the rising edge..,1: The received data is latched on the falling edge.." bitfld.long 0x0 0. "GOBUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI.." "0: Writing this bit '0' will stop data transfer if..,1: In Master mode writing '1' to this bit will.." line.long 0x4 "SPI_STATUS,SPI Status Register" bitfld.long 0x4 31. "WKCLKIF,Wake-up by SPI Clock Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_CLK port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" bitfld.long 0x4 30. "WKSSIF,Wake-up by Slave Select Interrupt Flag\nWhen chip is woken up from Power-down mode by the toggle event on SPI_SS port this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "TXCNT,Transmit FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." hexmask.long.byte 0x4 16.--19. 1. "RXCNT,Receive FIFO Data Counts (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." newline bitfld.long 0x4 15. "SLVTXSKE,Slave Mode Transmit Skew Buffer Empty Status\nThis bit indicates the empty status of transmit skew buffer which is used in Slave mode." "0,1" bitfld.long 0x4 13. "SLVTOIF,Slave Time-out Interrupt Flag\nIf SLVTOIEN (SPI_SSCTL[6]) is set to 1 this bit will be asserted when slave time-out event occur. Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit." "0: Slave time-out does not occur yet,1: Slave time-out has occurred" newline bitfld.long 0x4 12. "RXTOIF,Receive Time-outInterrupt Flag\nRefer to Time Out section.\nNote: This bit will be cleared by writing 1 to it." "0: There is not time-out event on the received buffer,1: Time out event active in RX FIFO is not empty" rbitfld.long 0x4 10. "TXTHIF,Transmit FIFO Threshold Interrupt Flag(Read Only)" "0: TX valid data counts bigger than TXTH..,1: TX valid data counts small or equal than TXTH" newline bitfld.long 0x4 9. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nNote 1: If SPI receives data when RX FIFO is full this bit will set to 1 and the received data will be dropped.\nNote 2: This bit will be cleared by writing 1 to it." "0: No FIFO over run,1: If SPI receives data when RX FIFO is full" rbitfld.long 0x4 8. "RXTHIF,RX FIFO Threshold Interrupt Flag(Read Only)" "0: RX valid data counts small or equal than RXTH..,1: RX valid data counts bigger than RXTH" newline bitfld.long 0x4 7. "UNITIF,Unit Transfer Interrupt Flag\nNote 2: This bitcan be cleared by writing '1' to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit.." bitfld.long 0x4 6. "SLVSTAIF,Slave Start Interrupt Flag\nIt is used to dedicate that the transfer has started in Slave mode with no slave select." "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline rbitfld.long 0x4 4. "LTRIGF,Level Trigger Accomplish Flag(Read Only)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GOBUSY bit to 1 .." "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." rbitfld.long 0x4 3. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmitted data FIFO is not full in the FIFO mode,1: Transmitted data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 2. "TXEMPTY,Transmit FIFO Buffer Empty Indicator(Read Only)" "0: Transmitted data FIFO is not empty in the FIFO..,1: Transmitted data FIFO is empty in the FIFO mode" rbitfld.long 0x4 1. "RXFULL,Receive FIFO Buffer Full Indicator(Read Only)" "0: Received data FIFO is not full in FIFO mode,1: Received data FIFO is full in the FIFO mode" newline rbitfld.long 0x4 0. "RXEMPTY,Receive FIFO Buffer Empty Indicator(Read Only)" "0: Received data FIFO is not empty in the FIFO mode,1: Received data FIFO is empty in the FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x8 0.--7. 1. "DIVIDER,Clock Divider\nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:\nWhere\n is the SPI peripheral clock source. It is defined in the.." line.long 0xC "SPI_SSCTL,SPI Slave Select Control Register" hexmask.long.word 0xC 20.--29. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0 it indicates the.." bitfld.long 0xC 16. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." newline bitfld.long 0xC 9. "SSTAIEN,Slave Start Interrupt EnableBit\nRefer to No Slave Select Mode." "0: Transfer start interrupt Disabled in no slave..,1: Transaction start interrupt Enabled in no slave.." bitfld.long 0xC 8. "SLVABORT,Abort in Slave Mode with No Slave Selected\nRefer to No Slave Select Mode.\nNote: It is auto cleared to '0' by hardware when the abort event is active." "0: No force the slave abort,1: Force the current transfer done in no slave.." newline bitfld.long 0xC 6. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nThis bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur" "0: Slave time-out function and interrupt both..,1: Slave time-out function and interrupt both Enabled" bitfld.long 0xC 5. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nThis bit is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote 1:Refer to No.." "0: The controller is 4-wire bi-direction interface,1: Refer to No Slave Select Mode" newline bitfld.long 0xC 4. "SSLTRIG,Slave Select Level Trigger Control" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPI_SS0 and SPI_SS1.." newline bitfld.long 0xC 2. "SSACTPOL,Slave Selection Active Polarity\nIt defines the active polarity of slave selection signal (SPI_SS[1:0])." "0: The SPI_SS slave select signal is active Low,1: The SPI_SS slave select signal is active High" bitfld.long 0xC 0.--1. "SS,Slave SelectionControl (Master Only)\nIf AUTOSS bit (SPI_SSCTL[3]) is cleared writing '1' to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing '0' sets the line back to inactive state(the same as SPI_CTL[1] for.." "0: Both SPI_SS1 and SPI_SS0 are inactive,1: SPI_SS1 is inactive SPI_SS0 is active.\nSPI_SS1..,?,?" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "RX,Receive Data Register (Read Only)\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RXEMPTY SPI_STATUS[0] to check if there is any more received data or not.\nNote:The SPI_RX1 is used only in TWOBIT bit.." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TX,Transmit Data Register (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if DWIDTH is set.." group.long 0x38++0x7 line.long 0x0 "SPI_PDMACTL,SPI PDMA Control Register" bitfld.long 0x0 2. "PDMARST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state.\nNote:It is auto cleared to '0' after the reset function has done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RXPDMAEN,Receiving PDMA EnableBit\nRefer to PDMA section for more detail information.\nNote:\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nIn Slave mode and the FIFO bit is disabled if the receive PDMA is enabled but the.." "0: Receiver PDMA function Disabled,1: Receiver PDMA function Enabled" newline bitfld.long 0x0 0. "TXPDMAEN,Transmit PDMA Enable Bit\nRefer to PDMA section for more detailed information.\nSPI_CTLNote:\n1. Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" line.long 0x4 "SPI_FIFOCTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TXTH,Transmit FIFO Threshold\nIf TX valid data counts are smaller than or equal to TXTH TXTHIF(SPI_STATUS[10])will be set to 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "RXTH,Received FIFO Threshold\nIf RX valid data counts are greater than RXTH RXTHIF (SPI_STATUS[8])will be set to 1.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RXTOIEN,RX Read Time Out Interrupt Enable Bit" "0: RXread Time-out Interrupt Disabled,1: RX read Time-out Interrupt Enabled" bitfld.long 0x4 4. "RXOVIEN,ReceiveFIFO Overrun Interrupt Enable Bit" "0: RXFIFO overrun interrupt Disabled,1: RX FIFO overrun interrupt Enabled" newline bitfld.long 0x4 3. "TXTHIEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled" bitfld.long 0x4 2. "RXTHIEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled" newline bitfld.long 0x4 1. "TXFBCLR,Transmit FIFO Buffer Clear\nNote:This bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0: Not clear the transmitted FIFO,1: Clear the transmitted FIFO" bitfld.long 0x4 0. "RXFBCLR,Receive FIFO Buffer Clear\nNote:This bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0: No clear the received FIFO,1: Clear the received FIFO" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" tree.end tree.end tree "SYS (System Manager)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "SYS_PDID,Part Device Identification Number Register" hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used." group.long 0x4++0xB line.long 0x0 "SYS_RSTSTS,System Reset Status Register" bitfld.long 0x0 8. "LOCKRF,Lockup Reset Flag" "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by software.." newline bitfld.long 0x0 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.." bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.." newline bitfld.long 0x0 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low-VoltageReset controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from LVR,1: The LVR had issued the reset signal to reset the.." bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from watchdog timer or window watchdog..,1: The watchdog timer had issued the reset signal.." newline bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.." bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.." line.long 0x4 "SYS_IPRST1,Peripheral Reset Control Resister1" bitfld.long 0x4 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA controller normal operation,1: PDMA controllerreset" bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote:This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset" newline bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset" line.long 0x8 "SYS_IPRST2,Peripheral Reset Control Resister2" bitfld.long 0x8 31. "SC1RST,SmartCard1 Controller Reset" "0: SmartCardmodule normal operation,1: SmartCardmodule reset" bitfld.long 0x8 30. "SC0RST,SmartCard0 Controller Reset" "0: SmartCardmodule normal operation,1: SmartCardmodule reset" newline bitfld.long 0x8 28. "ADCRST,ADC Controller Reset" "0: ADC module normal operation,1: ADC module reset" bitfld.long 0x8 22. "ACMP01RST,Comparator Controller Reset" "0: Comparatormodule normal operation,1: Comparatormodule reset" newline bitfld.long 0x8 20. "PWM0RST,PWM0 Controller Reset" "0: PWM0 module normal operation,1: PWM0 module reset" bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 module normal operation,1: UART1 module reset" newline bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 module normal operation,1: UART0 module reset" bitfld.long 0x8 15. "SPI3RST,SPI3 Controller Reset" "0: SPI3module normal operation,1: SPI3modulereset" newline bitfld.long 0x8 14. "SPI2RST,SPI2 Controller Reset" "0: SPI2module normal operation,1: SPI2modulereset" bitfld.long 0x8 13. "SPI1RST,SPI1 Controller Reset" "0: SPI1 module normal operation,1: SPI1 modulereset" newline bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset" "0: SPI0 module normal operation,1: SPI0 module reset" bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 module normal operation,1: I2C1 module reset" newline bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 module normal operation,1: I2C0 module reset" bitfld.long 0x8 7. "DSRCRST,DSRC Controller Reset" "0: DSRCmodule normal operation,1: DSRCmodule reset" newline bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 module normal operation,1: Timer3 module reset" bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 module normal operation,1: Timer2 module reset" newline bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 module normal operation,1: Timer1 module reset" bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 module normal operation,1: Timer0 module reset" newline bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO module normal operation,1: GPIO module reset" group.long 0x20++0x3 line.long 0x0 "SYS_TEMPCTL,Temperature Sensor Control Register" bitfld.long 0x0 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled" group.long 0x28++0x3 line.long 0x0 "SYS_RCCFCTL,RC Clock Filter Control Register" bitfld.long 0x0 2. "MRCFEN,MRC Clock Filter Enable Bit\nThis bit is used to enable/disable MRC clock filter function." "0: 4MHz MRC clock filter function Disabled,1: 4MHz MRC clock filter function Enabled (default)" bitfld.long 0x0 1. "HIRC1FEN,HIRC1 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC1clock filter function." "0: HIRC1clock filter function Disabled,1: HIRC1clock filter function Enabled (default)" newline bitfld.long 0x0 0. "HIRC0FEN,HIRC0 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC0clock filter function." "0: HIRC0clock filter function Disabled,1: HIRC0clock filter function Enabled (default)" group.long 0x30++0x23 line.long 0x0 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register" hexmask.long.byte 0x0 24.--27. 1. "PA6MFP,PA.6 Multi-function Pin Selection" hexmask.long.byte 0x0 20.--23. 1. "PA5MFP,PA.5 Multi-function Pin Selection" newline hexmask.long.byte 0x0 16.--19. 1. "PA4MFP,PA.4 Multi-function Pin Selection" hexmask.long.byte 0x0 12.--15. 1. "PA3MFP,PA.3 Multi-function Pin Selection" newline hexmask.long.byte 0x0 8.--11. 1. "PA2MFP,PA.2 Multi-function Pin Selection" hexmask.long.byte 0x0 4.--7. 1. "PA1MFP,PA.1 Multi-function Pin Selection" newline hexmask.long.byte 0x0 0.--3. 1. "PA0MFP,PA.0 Multi-function Pin Selection" line.long 0x4 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register" hexmask.long.byte 0x4 28.--31. 1. "PA15MFP,PA.15 Multi-function Pin Selection" hexmask.long.byte 0x4 24.--27. 1. "PA14MFP,PA.14 Multi-function Pin Selection" newline hexmask.long.byte 0x4 20.--23. 1. "PA13MFP,PA.13 Multi-function Pin Selection" hexmask.long.byte 0x4 16.--19. 1. "PA12MFP,PA.12 Multi-function Pin Selection" newline hexmask.long.byte 0x4 12.--15. 1. "PA11MFP,PA.11 Multi-function Pin Selection" hexmask.long.byte 0x4 8.--11. 1. "PA10MFP,PA.10 Multi-function Pin Selection" newline hexmask.long.byte 0x4 4.--7. 1. "PA9MFP,PA.9 Multi-function Pin Selection" hexmask.long.byte 0x4 0.--3. 1. "PA8MFP,PA.8 Multi-function Pin Selection" line.long 0x8 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register" hexmask.long.byte 0x8 28.--31. 1. "PB7MFP,PB.7 Multi-function Pin Selection" hexmask.long.byte 0x8 24.--27. 1. "PB6MFP,PB.6 Multi-function Pin Selection" newline hexmask.long.byte 0x8 20.--23. 1. "PB5MFP,PB.5 Multi-function Pin Selection" hexmask.long.byte 0x8 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection" newline hexmask.long.byte 0x8 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection" hexmask.long.byte 0x8 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection" newline hexmask.long.byte 0x8 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection" hexmask.long.byte 0x8 0.--3. 1. "PB0MFP,PB.0 Multi-function Pin Selection" line.long 0xC "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register" hexmask.long.byte 0xC 28.--31. 1. "PB15MFP,PB.15 Multi-function Pin Selection" hexmask.long.byte 0xC 24.--27. 1. "PB14MFP,PB.14 Multi-function Pin Selection" newline hexmask.long.byte 0xC 20.--23. 1. "PB13MFP,PB.13 Multi-function Pin Selection" hexmask.long.byte 0xC 12.--15. 1. "PB11MFP,PB.11 Multi-function Pin Selection" newline hexmask.long.byte 0xC 8.--11. 1. "PB10MFP,PB.10 Multi-function Pin Selection" hexmask.long.byte 0xC 4.--7. 1. "PB9MFP,PB.9 Multi-function Pin Selection" newline hexmask.long.byte 0xC 0.--3. 1. "PB8MFP,PB.8 Multi-function Pin Selection" line.long 0x10 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register" hexmask.long.byte 0x10 28.--31. 1. "PC7MFP,PC.7 Multi-function Pin Selection" hexmask.long.byte 0x10 24.--27. 1. "PC6MFP,PC.6 Pin Fuction Selection" newline hexmask.long.byte 0x10 12.--15. 1. "PC3MFP,PC.3 Multi-function Pin Selection" hexmask.long.byte 0x10 8.--11. 1. "PC2MFP,PC.2 Multi-function Pin Selection" newline hexmask.long.byte 0x10 4.--7. 1. "PC1MFP,PC.1 Multi-function Pin Selection" hexmask.long.byte 0x10 0.--3. 1. "PC0MFP,PC.0 Multi-function Pin Selection" line.long 0x14 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register" hexmask.long.byte 0x14 28.--31. 1. "PC15MFP,PC.15 Multi-function Pin Selection" hexmask.long.byte 0x14 24.--27. 1. "PC14MFP,PC.14 Multi-function Pin Selection" newline hexmask.long.byte 0x14 12.--15. 1. "PC11MFP,PC.11 Multi-function Pin Selection" hexmask.long.byte 0x14 8.--11. 1. "PC10MFP,PC.10 Multi-function Pin Selection" newline hexmask.long.byte 0x14 4.--7. 1. "PC9MFP,PC.9 Multi-function Pin Selection" hexmask.long.byte 0x14 0.--3. 1. "PC8MFP,PC.8 Multi-function Pin Selection" line.long 0x18 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register" hexmask.long.byte 0x18 28.--31. 1. "PD7MFP,PD.7 Multi-function Pin Selection" hexmask.long.byte 0x18 24.--27. 1. "PD6MFP,PD.6 Multi-function Pin Selection" line.long 0x1C "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register" hexmask.long.byte 0x1C 28.--31. 1. "PD15MFP,PD.15 Multi-function Pin Selection" hexmask.long.byte 0x1C 24.--27. 1. "PD14MFP,PD.14 Multi-function Pin Selection" line.long 0x20 "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register" hexmask.long.byte 0x20 20.--23. 1. "PE5MFP,PE.5 Multi-function Pin Selection" group.long 0x58++0x3 line.long 0x0 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register" hexmask.long.byte 0x0 28.--31. 1. "PF7MFP,PF.7 Multi-function Pin Selection" hexmask.long.byte 0x0 24.--27. 1. "PF6MFP,PF.6 Multi-function Pin Selection" newline hexmask.long.byte 0x0 12.--15. 1. "PF3MFP,PF.3 Multi-function Pin Selection" hexmask.long.byte 0x0 8.--11. 1. "PF2MFP,PF.2 Multi-function Pin Selection" newline hexmask.long.byte 0x0 4.--7. 1. "PF1MFP,PF.1 Multi-function Pin Selection" hexmask.long.byte 0x0 0.--3. 1. "PF0MFP,PF.0 Multi-function Pin Selection" group.long 0x60++0x7 line.long 0x0 "SYS_PORCTL,Power-on-Reset Controller Register" hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.." line.long 0x4 "SYS_BODCTL,Brown-out Detector Controller Register" bitfld.long 0x4 28.--30. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?" bitfld.long 0x4 24.--26. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),?,?,?,?,?,?" newline hexmask.long.byte 0x4 20.--23. 1. "LPBOD25TRIM,Low Power BOD 2.5 TRIM Value(Write Protect)\nThis value is used to control LPBOD25 detect voltage level in power-down mode nominal 2.5 V. Higher trim value higher detection voltage.\nNote: These bits are write protected. Refer to the.." hexmask.long.byte 0x4 16.--19. 1. "LPBOD20TRIM,Low Power BOD 2.0 TRIM Value(Write Protect)\nThis value is used to control BOD20 detect voltage level in power-down mode nominal 2.0 V. Higher trim value higher detection voltage.\nNote: These bits are write protected. Refer to the.." newline hexmask.long.byte 0x4 12.--15. 1. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." bitfld.long 0x4 11. "LPBODREN,Low Power Brown-out Reset Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN.." "0: Low power Brown-out dector 'RESET' function..,1: While the Low power Brown-out Detector function.." newline bitfld.long 0x4 10. "LPBODIE,Low Power BOD Interrupt Enable Control(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIEhigh) LPBOD will assert.." "0: Interrupt does not issue when LPBOD occurs in..,1: While the LPBOD function is enabled" bitfld.long 0x4 9. "LPBODVL,Low Power Brown-out Detector Threshold Voltage Selection(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Low Power Brown-Out Detector threshold voltageis..,1: This bit is write protected" newline bitfld.long 0x4 8. "LPBODEN,Low Power Brown-out Detector Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD." "0: Low Power Brown-out Detector function Disabled..,1: This bit is write protected" bitfld.long 0x4 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit" newline bitfld.long 0x4 6. "BODOUT,Brown-out DetectorOutuput Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function disabled this bit always responds 0.\nNote: This bit is ready-only." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1" bitfld.long 0x4 4. "BODIF,Brown-out DetectorInterrupt Flag\nNote: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detectordetects the VDD is.." newline bitfld.long 0x4 3. "BODREN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit.\nNote1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled.." "0: Brown-out 'RESET' function Disabled in Normal Mode,1: While the Brown-out Detector function is enabled" bitfld.long 0x4 2. "BODIE,BOD Interrupt Enable Control(Write Protect)\nNote1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low) BOD will assert an interrupt if BODOUT is high.\nNote2: This bit is write protected. Refer to.." "0: Interrupt does not issue when BOD occurs in..,1: While the BOD function is enabled" newline bitfld.long 0x4 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 []).This Brown-out Detecto only valid in Normal Mode.\nNote1: This bit is write protected. Refer to the.." "0: Brown-out Detector function Disabled in Normal..,1: This bit is write protected" rgroup.long 0x68++0x3 line.long 0x0 "SYS_BODSTS,Brown-out Detector Status Register" group.long 0x6C++0xB line.long 0x0 "SYS_IVREFCTL,Internal Voltage Reference Control Register" hexmask.long.byte 0x0 8.--11. 1. "VREFTRIM,Internal Voltage Reference Trim(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." bitfld.long 0x0 4. "EXTMODE,Regulator External Mode(Write Protect)\nUsers can output regulator output voltage in VREF pin if EXT_MODE is high.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: No connection with external VREF pin,1: Connet to external VREF pin. Connect a 1uF to.." newline bitfld.long 0x0 2.--3. "SEL25,Regulator Output Voltage Selection(Write Protect)\nSelect internal reference voltage level.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 1.5V,1: 1.8V,?,?" bitfld.long 0x0 1. "REGEN,Regulator Enable Control(Write Protect)\nEnable internal 1.5 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Regulator Disabled,1: Regulator Enabled" newline bitfld.long 0x0 0. "BGPEN,Band-gap Enable Control(Write Protect)\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the.." "0: Band-gap Disabled,1: Band-gap Enabled" line.long 0x4 "SYS_LDOCTL,LDO Control Register" bitfld.long 0x4 5. "FMCLVEN,Flash Memory Low Voltage Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Flash memory low voltage(1.2V) mode Enabled,1: Flash memory low voltage(1.2V) mode Disabled" bitfld.long 0x4 4. "LPRMEN,Low-power Run Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Low-Power runmode Enabled,1: Low-Power runmode Disabled" newline bitfld.long 0x4 2.--3. "LDOLVL,LDO Output Voltage Select(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 1.2V,1: 1.6V,?,?" bitfld.long 0x4 1. "FASTWK,Fast Wake-up Control Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Fast Wake-up from Power-Down mode Disabled,1: Fast Wake-up from Power-Down mode Enabled" line.long 0x8 "SYS_BATDCTL,Battery Voltage Divider Control Register" bitfld.long 0x8 0. "BATDIV2EN,Battery Voltageg Divide 2 Enable Bit\nThis bit is used to enable/disable battery voltageg divider function." "0: Battery voltageg divide 2 function Disabled..,1: Battery voltageg divide 2 function Enabled" rgroup.long 0x7C++0x3 line.long 0x0 "SYS_WKSTS,System Wake-up Status Register" bitfld.long 0x0 16. "GPIOWK,GPIO Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with GPIO wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 15. "RTCWK,RTC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with a RTCalarm or tick time happened. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 14. "UART0WK,UART0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART0 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 13. "UART1WK,UART1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART1 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 12. "SPI0WK,SPI0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI0 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 11. "SPI1WK,SPI1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI1 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 10. "SPI2WK,SPI2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI2 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 9. "SPI3WK,SPI3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI3 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 8. "BODWK,BOD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with BOD wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 7. "WDTWK,WDT Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with WDT wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 6. "TMR0WK,TMR0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR0 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 5. "TMR1WK,TMR1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR1 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 4. "TMR2WK,TMR2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR2 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 3. "TMR3WK,TMR3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR3 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 2. "I2C0WK,I2C0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C0 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" bitfld.long 0x0 1. "I2C1WK,I2C1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C1 wake-up event. This flag is cleared when Power-down mode is entered." "0,1" newline bitfld.long 0x0 0. "ACMPWK,ACMP Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with ACMP wake-up event. This flag is cleared when Power-down mode is entered." "0,1" group.long 0x80++0xB line.long 0x0 "SYS_RC0TCTL,HIRC0 Trim Control Register" bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected the status CLKERRIF (SYS_IRC0TISTS[2]) would be set.." "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?" newline bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" bitfld.long 0x0 0.--2. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry.." "0: Disable HIRC0 auto trim function,1: Enable HIRC0 auto trim function and trim HIRC to..,?,?,?,?,?,?" line.long 0x4 "SYS_RC0TIEN,HIRC0 Trim Interrupt Enable Register" bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRC0TSTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_IRC0TSTS[2]) status to..,1: Enable CLKERRIF(SYS_IRC0TSTS[2]) status to.." bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL(SYS_IRC0TCTL[1:0]).\nIf this.." "0: Disable TFAILIF(SYS_IRC0TSTS[1]) status to..,1: Enable TFAILIF(SYS_IRC0TSTS[1]) status to.." line.long 0x8 "SYS_RC0TISTS,HIRC0 Trim Interrupt Status Register" bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value this bit will be set and to be an indicate that clock.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy" bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]).." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.." newline bitfld.long 0x8 0. "FREQLOCK,HIRC0 Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.." group.long 0x90++0xB line.long 0x0 "SYS_RC1TCTL,HIRC1 Trim Control Register" bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected the status CLKERRIF (SYS_IRC1TISTS[2]) would be set.." "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?" newline bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry.." "0: Disable HIRC1 auto trim function,1: Reserved,?,?" line.long 0x4 "SYS_RC1TIEN,HIRC1 Trim Interrupt Enable Register" bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRC1TSTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_IRC1TSTS[2]) status to..,1: Enable CLKERRIF(SYS_IRC1TSTS[2]) status to.." bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRC1TCTL[1:0]).\nIf this.." "0: Disable TFAILIF(SYS_IRC1TSTS[1]) status to..,1: Enable TFAILIF(SYS_IRC1TSTS[1]) status to.." line.long 0x8 "SYS_RC1TISTS,HIRC1 Trim Interrupt Status Register" bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy" bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]).." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.." newline bitfld.long 0x8 0. "FREQLOCK,HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.." group.long 0xA0++0xB line.long 0x0 "SYS_MRCTCTL,MIRC Trim Control Register" bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit\nThis bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high.." "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?" newline bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?" bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry.." "0: Disable MIRC auto trim function,1: Reserved,?,?" line.long 0x4 "SYS_MRCTIEN,MIRC Trim Interrupt Enable Register" bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_MIRCTSTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_MIRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_MIRCTSTS[2]) status to.." bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_MIRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_MIRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_MIRCTSTS[1]) status to.." line.long 0x8 "SYS_MRCTISTS,MIRC Trim Interrupt Status Register" bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 4 MHz internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy" bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.." newline bitfld.long 0x8 0. "FREQLOCK,MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt." "0: The internal medium-speed oscillator frequency..,1: The internal medium-speed oscillator frequency.." group.long 0x100++0x3 line.long 0x0 "SYS_REGLCTL,Register Lock Control Register" hexmask.long.byte 0x0 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.." group.long 0x120++0x3 line.long 0x0 "SYS_RPDBCLK,Reset Pin Debounce Clock Selection Register" bitfld.long 0x0 6. "RSTPDBCLK,Reset Pin Debounce Clock Selection Bit\nBefore swtch clock both clock sources must be enabled." "0: HIRC2 is slected as reset pin debounce clock,1: HIRC0 is slected as reset pin debounce.." tree.end tree "TMR (Timer Controller)" base ad:0x0 tree "TMR01" base ad:0x40010000 group.long 0x0++0x17 line.long 0x0 "TIMER0_CTL,Timer 0 Control and Status Register" rbitfld.long 0x0 31. "DSRCCTLF,DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1 write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't.." "0: DSRC control Timer Disabled,1: This bit is read only" bitfld.long 0x0 28. "TRGPWM,Trigger PWM EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x0 25. "INTRTGMD,Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL this bit is always 0." "0: TIMERx count the all input events from Tx pin,1: TIMERx ignored the number of first incoming.." bitfld.long 0x0 24. "INTRTGEN,Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL this bit is always 0." "0: Inter-timer trigger function Disabled,1: Inter-timer trigger function Enabled" newline bitfld.long 0x0 23. "CMPCTL,Timer Compared Mode Selection\nIf updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT) CNT (TIMERx_CNT) will be reset to default value. At the same time prescale counter reloaded." "0: The behavior selection in one-shot periodic or..,1: The behavior selection in one-shot periodic or.." bitfld.long 0x0 22. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3 when INTRTGEN (TIMERx_CTL[24]) is high the capture signal is from.." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: If this bit is enabled" newline bitfld.long 0x0 20. "CAPCNTMD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "CAPEDGE,Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function the configurations are:" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?" newline bitfld.long 0x0 17. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 16. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 14. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1 the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" bitfld.long 0x0 13. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.." newline bitfld.long 0x0 12. "EXTCNTEN,Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and HCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x0 11. "TRGSSEL,Trigger Source Selection\nIf this bit is set to 1 capture interrupt can trigger ADC PDMA and PWM. Otherwise time-out interrupt can trigger ADC PDMA and PWM." "0: Time-out interrupt is used to trigger ADC PDMA..,1: Capture interrupt is used to trigger ADC PDMA.." newline bitfld.long 0x0 10. "TRGPDMA,Timer Trigger PDMA EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]).." "0: Timer interrupt trigger PDMADisabled,1: Timer interrupt trigger PDMAEnabled" bitfld.long 0x0 8. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to.." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline rbitfld.long 0x0 7. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 4.--5. "OPMODE,Timer Counting Mode Selection" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 3. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement affects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 2. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1 the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x0 1. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3.." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.." bitfld.long 0x0 0. "CNTEN,Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time." "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TIMER0_PRECNT,Timer 0 Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PSC,Prescale Counter\nNote: If the PSC value is changed CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded." line.long 0x8 "TIMER0_CMP,Timer 0 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." line.long 0xC "TIMER0_INTEN,Timer 0 Interrupt Enable Register" bitfld.long 0xC 1. "CAPIEN,Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1." "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" bitfld.long 0xC 0. "CNTIEN,Timer Interrupt EnableBit\nNote:If this bit is enabled when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1 the timer interrupt signal is generated and informed to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TIMER0_INTSTS,Timer 0 Interrupt Status Register" bitfld.long 0x10 6. "CAPFEDF,Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming.." "0: Rising edge detected on Tx_EXT pin,1: The timer updates this flag when it updates the.." bitfld.long 0x10 5. "CAPDATOF,Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred the Timer will keep register TIMERx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." newline bitfld.long 0x10 4. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x10 1. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status the Timer will keep register TIMERx_CAP unchanged and.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" newline bitfld.long 0x10 0. "CNTIF,Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT (TIMERx_CNT[23:0])value matches the CMPDAT.." line.long 0x14 "TIMER0_CNT,Timer 0Counter Data Register" bitfld.long 0x14 31. "RSTACT,Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time timer set this flag to 1 to.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0x14 0.--23. 1. "CNT,Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After.." rgroup.long 0x18++0x3 line.long 0x0 "TIMER0_CAP,Timer 0 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set CAPFUNCS (TIMERx_CTL[17]) bit is 0 CAPCNTMD (TIMERx_CTL[20]) bit is 0 and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting CAPIF (TIMERx_INTSTS[1]).." group.long 0x20++0x3 line.long 0x0 "TIMER0_ECTL,Timer 0Extended Control Register" hexmask.long.byte 0x0 24.--31. 1. "EVNTDPCNT,Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example if user configured EVNTDPCNT to 7 timer would drop 7 first incoming events and starts the inter-timer trigger.." group.long 0x100++0x17 line.long 0x0 "TIMER1_CTL,Timer 1 Control and Status Register" rbitfld.long 0x0 31. "DSRCCTLF,DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1 write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't.." "0: DSRC control Timer Disabled,1: This bit is read only" bitfld.long 0x0 28. "TRGPWM,Trigger PWM EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x0 25. "INTRTGMD,Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL this bit is always 0." "0: TIMERx count the all input events from Tx pin,1: TIMERx ignored the number of first incoming.." bitfld.long 0x0 24. "INTRTGEN,Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL this bit is always 0." "0: Inter-timer trigger function Disabled,1: Inter-timer trigger function Enabled" newline bitfld.long 0x0 23. "CMPCTL,Timer Compared Mode Selection\nIf updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT) CNT (TIMERx_CNT) will be reset to default value. At the same time prescale counter reloaded." "0: The behavior selection in one-shot periodic or..,1: The behavior selection in one-shot periodic or.." bitfld.long 0x0 22. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3 when INTRTGEN (TIMERx_CTL[24]) is high the capture signal is from.." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: If this bit is enabled" newline bitfld.long 0x0 20. "CAPCNTMD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "CAPEDGE,Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function the configurations are:" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?" newline bitfld.long 0x0 17. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 16. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 14. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1 the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" bitfld.long 0x0 13. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.." newline bitfld.long 0x0 12. "EXTCNTEN,Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and HCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x0 11. "TRGSSEL,Trigger Source Selection\nIf this bit is set to 1 capture interrupt can trigger ADC PDMA and PWM. Otherwise time-out interrupt can trigger ADC PDMA and PWM." "0: Time-out interrupt is used to trigger ADC PDMA..,1: Capture interrupt is used to trigger ADC PDMA.." newline bitfld.long 0x0 10. "TRGPDMA,Timer Trigger PDMA EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]).." "0: Timer interrupt trigger PDMADisabled,1: Timer interrupt trigger PDMAEnabled" bitfld.long 0x0 8. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to.." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline rbitfld.long 0x0 7. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 4.--5. "OPMODE,Timer Counting Mode Selection" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 3. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement affects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 2. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1 the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x0 1. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3.." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.." bitfld.long 0x0 0. "CNTEN,Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time." "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TIMER1_PRECNT,Timer 1 Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PSC,Prescale Counter\nNote: If the PSC value is changed CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded." line.long 0x8 "TIMER1_CMP,Timer 1 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." line.long 0xC "TIMER1_INTEN,Timer 1 Interrupt Enable Register" bitfld.long 0xC 1. "CAPIEN,Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1." "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" bitfld.long 0xC 0. "CNTIEN,Timer Interrupt EnableBit\nNote:If this bit is enabled when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1 the timer interrupt signal is generated and informed to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TIMER1_INTSTS,Timer 1 Interrupt Status Register" bitfld.long 0x10 6. "CAPFEDF,Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming.." "0: Rising edge detected on Tx_EXT pin,1: The timer updates this flag when it updates the.." bitfld.long 0x10 5. "CAPDATOF,Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred the Timer will keep register TIMERx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." newline bitfld.long 0x10 4. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x10 1. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status the Timer will keep register TIMERx_CAP unchanged and.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" newline bitfld.long 0x10 0. "CNTIF,Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT (TIMERx_CNT[23:0])value matches the CMPDAT.." line.long 0x14 "TIMER1_CNT,Timer 1 Counter Data Register" bitfld.long 0x14 31. "RSTACT,Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time timer set this flag to 1 to.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0x14 0.--23. 1. "CNT,Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After.." rgroup.long 0x118++0x3 line.long 0x0 "TIMER1_CAP,Timer 1 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set CAPFUNCS (TIMERx_CTL[17]) bit is 0 CAPCNTMD (TIMERx_CTL[20]) bit is 0 and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting CAPIF (TIMERx_INTSTS[1]).." group.long 0x120++0x3 line.long 0x0 "TIMER1_ECTL,Timer 1 Extended Control Register" hexmask.long.byte 0x0 24.--31. 1. "EVNTDPCNT,Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example if user configured EVNTDPCNT to 7 timer would drop 7 first incoming events and starts the inter-timer trigger.." rgroup.long 0x200++0x17 line.long 0x0 "GPA_SHADOW,GPIO Port A Pin Value Shadow Register" bitfld.long 0x0 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x0 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x0 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x0 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x0 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x0 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x0 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x0 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x0 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x0 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" line.long 0x4 "GPB_SHADOW,GPIO Port B Pin Value Shadow Register" bitfld.long 0x4 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x4 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x4 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x4 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x4 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x4 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x4 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x4 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x4 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x4 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" line.long 0x8 "GPC_SHADOW,GPIO Port C Pin Value Shadow Register" bitfld.long 0x8 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x8 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x8 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x8 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x8 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x8 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x8 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x8 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x8 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x8 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" line.long 0xC "GPD_SHADOW,GPIO Port D Pin Value Shadow Register" bitfld.long 0xC 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0xC 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0xC 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0xC 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0xC 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0xC 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0xC 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0xC 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0xC 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0xC 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" line.long 0x10 "GPE_SHADOW,GPIO Port E Pin Value Shadow Register" bitfld.long 0x10 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x10 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x10 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x10 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x10 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x10 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x10 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x10 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x10 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x10 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" line.long 0x14 "GPF_SHADOW,GPIO Port F Pin Value Shadow Register" bitfld.long 0x14 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x14 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x14 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" bitfld.long 0x14 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x14 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x14 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x14 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x14 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" newline bitfld.long 0x14 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" bitfld.long 0x14 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote 1: For GPE_SHADOW bits [15:10] are reserved.\nNote2:.." "?,1: For GPE_SHADOW" tree.end tree "TMR23" base ad:0x40110000 group.long 0x0++0x17 line.long 0x0 "TIMER2_CTL,Timer 2 Control and Status Register" rbitfld.long 0x0 31. "DSRCCTLF,DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1 write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't.." "0: DSRC control Timer Disabled,1: This bit is read only" bitfld.long 0x0 28. "TRGPWM,Trigger PWM EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x0 25. "INTRTGMD,Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL this bit is always 0." "0: TIMERx count the all input events from Tx pin,1: TIMERx ignored the number of first incoming.." bitfld.long 0x0 24. "INTRTGEN,Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL this bit is always 0." "0: Inter-timer trigger function Disabled,1: Inter-timer trigger function Enabled" newline bitfld.long 0x0 23. "CMPCTL,Timer Compared Mode Selection\nIf updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT) CNT (TIMERx_CNT) will be reset to default value. At the same time prescale counter reloaded." "0: The behavior selection in one-shot periodic or..,1: The behavior selection in one-shot periodic or.." bitfld.long 0x0 22. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3 when INTRTGEN (TIMERx_CTL[24]) is high the capture signal is from.." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: If this bit is enabled" newline bitfld.long 0x0 20. "CAPCNTMD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "CAPEDGE,Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function the configurations are:" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?" newline bitfld.long 0x0 17. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 16. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 14. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1 the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" bitfld.long 0x0 13. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.." newline bitfld.long 0x0 12. "EXTCNTEN,Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and HCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x0 11. "TRGSSEL,Trigger Source Selection\nIf this bit is set to 1 capture interrupt can trigger ADC PDMA and PWM. Otherwise time-out interrupt can trigger ADC PDMA and PWM." "0: Time-out interrupt is used to trigger ADC PDMA..,1: Capture interrupt is used to trigger ADC PDMA.." newline bitfld.long 0x0 10. "TRGPDMA,Timer Trigger PDMA EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]).." "0: Timer interrupt trigger PDMADisabled,1: Timer interrupt trigger PDMAEnabled" bitfld.long 0x0 8. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to.." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline rbitfld.long 0x0 7. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 4.--5. "OPMODE,Timer Counting Mode Selection" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 3. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement affects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 2. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1 the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x0 1. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3.." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.." bitfld.long 0x0 0. "CNTEN,Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time." "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TIMER2_PRECNT,Timer 2 Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PSC,Prescale Counter\nNote: If the PSC value is changed CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded." line.long 0x8 "TIMER2_CMP,Timer 2 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." line.long 0xC "TIMER2_INTEN,Timer 2 Interrupt Enable Register" bitfld.long 0xC 1. "CAPIEN,Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1." "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" bitfld.long 0xC 0. "CNTIEN,Timer Interrupt EnableBit\nNote:If this bit is enabled when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1 the timer interrupt signal is generated and informed to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TIMER2_INTSTS,Timer 2 Interrupt Status Register" bitfld.long 0x10 6. "CAPFEDF,Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming.." "0: Rising edge detected on Tx_EXT pin,1: The timer updates this flag when it updates the.." bitfld.long 0x10 5. "CAPDATOF,Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred the Timer will keep register TIMERx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." newline bitfld.long 0x10 4. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x10 1. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status the Timer will keep register TIMERx_CAP unchanged and.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" newline bitfld.long 0x10 0. "CNTIF,Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT (TIMERx_CNT[23:0])value matches the CMPDAT.." line.long 0x14 "TIMER2_CNT,Timer 2Counter Data Register" bitfld.long 0x14 31. "RSTACT,Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time timer set this flag to 1 to.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0x14 0.--23. 1. "CNT,Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After.." rgroup.long 0x18++0x3 line.long 0x0 "TIMER2_CAP,Timer 2 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set CAPFUNCS (TIMERx_CTL[17]) bit is 0 CAPCNTMD (TIMERx_CTL[20]) bit is 0 and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting CAPIF (TIMERx_INTSTS[1]).." group.long 0x20++0x3 line.long 0x0 "TIMER2_ECTL,Timer 2Extended Control Register" hexmask.long.byte 0x0 24.--31. 1. "EVNTDPCNT,Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example if user configured EVNTDPCNT to 7 timer would drop 7 first incoming events and starts the inter-timer trigger.." group.long 0x100++0x17 line.long 0x0 "TIMER3_CTL,Timer 3 Control and Status Register" rbitfld.long 0x0 31. "DSRCCTLF,DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1 write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't.." "0: DSRC control Timer Disabled,1: This bit is read only" bitfld.long 0x0 28. "TRGPWM,Trigger PWM EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x0 25. "INTRTGMD,Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL this bit is always 0." "0: TIMERx count the all input events from Tx pin,1: TIMERx ignored the number of first incoming.." bitfld.long 0x0 24. "INTRTGEN,Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL this bit is always 0." "0: Inter-timer trigger function Disabled,1: Inter-timer trigger function Enabled" newline bitfld.long 0x0 23. "CMPCTL,Timer Compared Mode Selection\nIf updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT) CNT (TIMERx_CNT) will be reset to default value. At the same time prescale counter reloaded." "0: The behavior selection in one-shot periodic or..,1: The behavior selection in one-shot periodic or.." bitfld.long 0x0 22. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3 when INTRTGEN (TIMERx_CTL[24]) is high the capture signal is from.." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: If this bit is enabled" newline bitfld.long 0x0 20. "CAPCNTMD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "CAPEDGE,Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function the configurations are:" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?" newline bitfld.long 0x0 17. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x0 16. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled" newline bitfld.long 0x0 14. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1 the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled" bitfld.long 0x0 13. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.." newline bitfld.long 0x0 12. "EXTCNTEN,Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and HCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x0 11. "TRGSSEL,Trigger Source Selection\nIf this bit is set to 1 capture interrupt can trigger ADC PDMA and PWM. Otherwise time-out interrupt can trigger ADC PDMA and PWM." "0: Time-out interrupt is used to trigger ADC PDMA..,1: Capture interrupt is used to trigger ADC PDMA.." newline bitfld.long 0x0 10. "TRGPDMA,Timer Trigger PDMA EnableBit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]).." "0: Timer interrupt trigger PDMADisabled,1: Timer interrupt trigger PDMAEnabled" bitfld.long 0x0 8. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0 the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to.." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline rbitfld.long 0x0 7. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active" bitfld.long 0x0 4.--5. "OPMODE,Timer Counting Mode Selection" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?" newline bitfld.long 0x0 3. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement affects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x0 2. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1 the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x0 1. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3.." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.." bitfld.long 0x0 0. "CNTEN,Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time." "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TIMER3_PRECNT,Timer 3 Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PSC,Prescale Counter\nNote: If the PSC value is changed CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded." line.long 0x8 "TIMER3_CMP,Timer 3 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT or.." line.long 0xC "TIMER3_INTEN,Timer 3 Interrupt Enable Register" bitfld.long 0xC 1. "CAPIEN,Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1." "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled" bitfld.long 0xC 0. "CNTIEN,Timer Interrupt EnableBit\nNote:If this bit is enabled when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1 the timer interrupt signal is generated and informed to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TIMER3_INTSTS,Timer 3 Interrupt Status Register" bitfld.long 0x10 6. "CAPFEDF,Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming.." "0: Rising edge detected on Tx_EXT pin,1: The timer updates this flag when it updates the.." bitfld.long 0x10 5. "CAPDATOF,Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred the Timer will keep register TIMERx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." newline bitfld.long 0x10 4. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x10 1. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status the Timer will keep register TIMERx_CAP unchanged and.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred" newline bitfld.long 0x10 0. "CNTIF,Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT (TIMERx_CNT[23:0])value matches the CMPDAT.." line.long 0x14 "TIMER3_CNT,Timer 3 Counter Data Register" bitfld.long 0x14 31. "RSTACT,Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time timer set this flag to 1 to.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.." hexmask.long.tbyte 0x14 0.--23. 1. "CNT,Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After.." rgroup.long 0x118++0x3 line.long 0x0 "TIMER3_CAP,Timer 3 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set CAPFUNCS (TIMERx_CTL[17]) bit is 0 CAPCNTMD (TIMERx_CTL[20]) bit is 0 and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting CAPIF (TIMERx_INTSTS[1]).." group.long 0x120++0x3 line.long 0x0 "TIMER3_ECTL,Timer 3 Extended Control Register" hexmask.long.byte 0x0 24.--31. 1. "EVNTDPCNT,Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example if user configured EVNTDPCNT to 7 timer would drop 7 first incoming events and starts the inter-timer trigger.." tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x0 tree "UART0" base ad:0x40050000 rgroup.long 0x0++0x3 line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive /Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT.\nRead.." group.long 0x4++0xB line.long 0x0 "UART_CTRL,UART Control Register." bitfld.long 0x0 13.--14. "ABRDBITS,Auto-baud Rate Detect Bit Length\nNote: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" bitfld.long 0x0 12. "ABRDEN,Auto-baud Rate Detect EnableBit\nNote: When the auto-baud rate detect operation finishes hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_INTEN [7]) be enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x0 8. "FTOEN,Frame Time Out Enable Bit\nThis bit is used to enable the timer counter even the FIFO is still empty." "0: Frame time out Disabled,1: Frame time out Enabled" bitfld.long 0x0 7. "TXDMAEN,TX DMA Enable Bit\nThis bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled" newline bitfld.long 0x0 6. "RXDMAEN,RX DMA Enable Bit\nThis bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled" bitfld.long 0x0 5. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote:When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x0 4. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_LINE[13:12]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x0 3. "TXOFF,Transfer Disable Bit" "0: Transfer Enabled,1: Transfer Disabled" newline bitfld.long 0x0 2. "RXOFF,Receiver Disable Bit\nNote1:In RS-485 NMM mode user can set this bit to receive data before detecting address byte.\nNote2: In RS-485 AAD mode this bit will be setting to '1' automatically.\nNote3: In RS-485 AUD mode and LIN 'break + sync +PID'.." "0: Receiver Enabled,1: In RS-485 NMM mode" bitfld.long 0x0 1. "TXRST,TX Field Software Reset\nWhen TXRST (UART_CTRL[1]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles" "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x0 0. "RXRST,RX Field Software Reset\nWhen RXRST (UART_CTRL[0]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x4 "UART_LINE,UART Transfer Line Control Register." bitfld.long 0x4 12.--13. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control." "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,?,?" bitfld.long 0x4 8.--9. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated).\nNote: When operating in IrDA mode or RS-485 mode the.." "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,?,?" newline bitfld.long 0x4 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled" bitfld.long 0x4 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled" newline bitfld.long 0x4 4. "EPE,Even Parity EnableBit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x4 3. "PBE,Parity Bit EnableBit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: No parity bit generated Disabled,1: Parity bit generated Enabled" newline bitfld.long 0x4 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x4 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?" line.long 0x8 "UART_INTEN,UART Interrupt Enable Register." bitfld.long 0x8 9. "TXENDIEN,Transmitter Empty FInterrupt Enable Bit\nNote: If the bit is enabled there is interrupt event when the TXENDF (UART_FIFOSTS[11]) is actived." "0: Transmit Empty interrupt Disabled,1: Transmit Empty interrupt Enabled" bitfld.long 0x8 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote:This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" newline bitfld.long 0x8 7. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x8 6. "WKUPIEN,Wake-up Interrupt EnableBit\nNote: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and 'system clock' work stable." "0: Wake-up system function Disabled,1: Wake-up system function Enabled when the system.." newline bitfld.long 0x8 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" bitfld.long 0x8 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-outinterrupt Enabled" newline bitfld.long 0x8 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem statusinterrupt Enabled" bitfld.long 0x8 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" newline bitfld.long 0x8 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled" bitfld.long 0x8 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" rgroup.long 0x10++0xB line.long 0x0 "UART_INTSTS,UART Interrupt Status Register." bitfld.long 0x0 8. "LINIF,LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted RX header received or the SIN does not equal SOUT and if LINIEN(UART_INTEN[8]) is set then the LIN interrupt will be generated.\nNote1: This bit is read.." "0: No LIN interrupt is generated,1: This bit is read only" bitfld.long 0x0 7. "ABRIF,Auto-baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[7]) is set then the auto-baud rate interrupt will be.." "0: No Auto-Baud Rate interrupt is generated,1: This bit is read only" newline bitfld.long 0x0 6. "WKUPIF,Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by one of UART controller wake-up event.\nNote1: If WKDATEN (UART_INTEN[6]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only .." "0: Chip stays in power-down state,1: If WKDATEN" bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[8]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set the transfer is not correct. If BFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x0 4. "RXTOIF,Rime-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled the Tout interrupt will be.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEM[18])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" line.long 0x4 "UART_TRSR,UART Transfer Status Register." bitfld.long 0x4 8. "SLVSYNCF,LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic '1' when LIN received incorrect SYNC field.\nUser can choose the header by setting LINHSEL (UART_ATLCTL[5:4]) register.\nNote: This bit is read only but can be cleared by writing '1'.." "0: No LIN Rx sync error is generated,1: LIN Rx sync error is generated" bitfld.long 0x4 7. "RXBUSY,Receive Busy Status(Read Only)\nNote: The user can use this to check the busy status in receiver mode. If the user wants to enter power down this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin." "0: The receiver machine stays in idle state,1: The receiver machine stays in no Idle state" newline bitfld.long 0x4 5. "BITEF,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state is not equal to the output pin (SOUT) state BITEF will be set.\nWhen occur bit error hardware will generate an.." "0: No Bit error interrupt is generated,1: Bit error interrupt is generated" bitfld.long 0x4 4. "LINRXIF,LIN RX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when received LIN header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' and it can be choose by setting LINHSEL.." "0: No LIN Rx interrupt is generated,1: LIN Rx interrupt is generated" newline bitfld.long 0x4 3. "LINTXIF,LIN TX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when LIN transmitted header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' it can be choose by setting LINHSEL.." "0: No LIN Transmit interrupt is generated,1: LIN Transmit interrupt is generated" bitfld.long 0x4 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt(Read Only)\nNote1:This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: This bit is set to logic '1' in Auto-baud Rate.." newline bitfld.long 0x4 1. "ABRDIF,Auto-baud Rate Interrupt (Read Only)\nThis bit is set to logic '1' when auto-baud rate detect function finished.\nNote: This bit is read only but can be cleared by writing '1' to it." "0: No Auto- Baud Rate interrupt is generated,1: Auto-Baud Rate interrupt is generated" bitfld.long 0x4 0. "ADDRDETF,RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only but can be cleared by writing.." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.." line.long 0x8 "UART_FIFOSTS,UART FIFO Status Register." hexmask.long.byte 0x8 24.--28. 1. "TXPTR,TX-fIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.." hexmask.long.byte 0x8 16.--20. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.." newline bitfld.long 0x8 11. "TXENDF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote:This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x8 10. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote:This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" newline bitfld.long 0x8 9. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty" bitfld.long 0x8 8. "TXOVIF,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote:This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO did not overflow,1: TX FIFO overflowed" newline bitfld.long 0x8 6. "BIF,Break Interrupt Flag( Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x8 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x8 4. "PEF,Parity Error State Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x8 2. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline bitfld.long 0x8 1. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" bitfld.long 0x8 0. "RXOVIF,RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size this bit will be set.\nNote:This bit is read only but can be cleared by writing '1'.." "0: RX FIFO is not overflow,1: RX FIFO is overflow" group.long 0x1C++0xB line.long 0x0 "UART_MODE,UART Modem Control Status Register." rbitfld.long 0x0 18. "CTSDETF,Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]).\nNote: This bit is read only but it can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state" rbitfld.long 0x0 17. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" newline bitfld.long 0x0 16. "CTSACTLV,nCTS Trigger Level\nThis bit defines the active level state of nCTS pin input." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)" rbitfld.long 0x0 1. "RTSSTS,nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state" newline bitfld.long 0x0 0. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output." "0: nRTS pin output is high level active,1: nRTS pin output is low level active. (Default)" line.long 0x4 "UART_TOUT,UART Time-Out Control Register." hexmask.long.byte 0x4 16.--23. 1. "DLY,TX Delay Time Value\nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.\nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real delay value is.." hexmask.long.word 0x4 0.--8. 1. "TOIC,Time-out Comparator\nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real time-out value is TOIC + 1.\nNote3: The counting clock is baud rate clock.\nNote4: The UART data format is start bit + 8 data bits + parity.." line.long 0x8 "UART_BAUD,UART Baud Rate Divisor Register." bitfld.long 0x8 31. "DIV16EN,Divider 16 Enable Control\nNote: In IrDA mode this bit must clear to '0'." "0: The equation of baud rate is UART_CLK / [(BRD+1)],1: The equation of baud rate is UART_CLK / [16 *.." hexmask.long.word 0x8 0.--15. 1. "BRD,Baud Rate Divider \nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown inUART Controller Baud Rate Generation." group.long 0x30++0x13 line.long 0x0 "UART_IRDA,UART IrDA Control Register." bitfld.long 0x0 6. "RXINV,IrDA Inverse Receive Input Signal" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)" bitfld.long 0x0 5. "TXINV,IrDA Inverse Transmitting Output Signal" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal" newline bitfld.long 0x0 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0x4 "UART_ATLCTL,UART Alternate Control State Register." hexmask.long.byte 0x4 24.--31. 1. "ADRMPID,Address / PID Match Value Register\nWhen in the RS-485 Function Mode this field contains the RS-485 address match values.\nWhen in the LIN Function mode this field contains the LIN protected identifier field software fills ID0~ID5 (PID [5:0]) .." bitfld.long 0x4 19. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0x4 18. "RS485AUD,RS-485 Auto Direction Function (AUD)\nNote: It can be active with RS485AAD or RS485NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).." bitfld.long 0x4 17. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0x4 16. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0x4 8. "BITERREN,Bit Error Detect EnableBit" "0: Bit error detection Disabled,1: Bit error detection Enabled" newline bitfld.long 0x4 7. "LINTXEN,LIN TX Header Trigger EnableBit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LINHSEL (UART_ATLCTL[5:4]).\nNote1: This bit will be cleared automatically and generate.." "0: Send LIN TX header Disabled,1: This bit will be cleared automatically and.." bitfld.long 0x4 6. "LINRXEN,LIN RX Enable Control\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL) the controller will generator a interrupt to CPU (LININT)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x4 4.--5. "LINHSEL,LIN Header Selection" "0: The LIN header includes 'break field',1: The LIN header includes 'break field + sync field',?,?" bitfld.long 0x4 0.--2. "BRKFL,LIN TX Break Field Count \nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is BRKFL + 8." "?,?,?,3: bit LIN TX break field count,?,?,?,?" line.long 0x8 "UART_FUNCSEL,UART Function Select Register." bitfld.long 0x8 0.--1. "FUNCSEL,Function Selection" "0: UART function mode,1: LIN function mode,?,?" line.long 0xC "UART_BRCOMPAT,UART Baud Rate Compensation Register." bitfld.long 0xC 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0xC 0.--8. 1. "BRCOMPAT,Baud Rate Compensation Patten\nThese 9bits are used to define the relative bit is compensated or not. BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit." line.long 0x10 "UART_WKUPEN,UART Wake-up Enable Register." bitfld.long 0x10 4. "WKADRMEN,RS-485 Address Match Wake-up Enable Bit" "0: RS-485 ADD mode address match wake-up function..,1: RS-485 AAD mode address match wake-up function.." bitfld.long 0x10 3. "WKTHRTOEN,FIFO Threshold Reach Time Out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1." "0: Received FIFO threshold no reach and time out..,1: Received FIFO threshold no reach and time out.." newline bitfld.long 0x10 2. "WKTHREN,FIFO Threshold Reach Wake-up Enable Bit\nNote: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K." "0: Received FIFO threshold reach wake-up function..,1: Received FIFO threshold reach wake-up function.." bitfld.long 0x10 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up function Disabled,1: Incoming data wake-up function Enabled when the.." newline bitfld.long 0x10 0. "WKCTSEN,CTSn Wake-up Enable Bit\nWhen the system is in power-down mode an external nCTS change will wake-up system from power-down mode." "0: nCTS wake-up function Disabled,1: nCTS wake-up function Enabled" rgroup.long 0x44++0x3 line.long 0x0 "UART_WKUPSTS,UART Wake-up Status Register." bitfld.long 0x0 4. "ADRWKSTS,RS-485 Address Byte Detection Wake-up Flag (Read Only)\nNote1: If WKADRMEN (UART_WKUPEN[4])is enabled the wake-up function is generated.\nNote2: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable.." "0: Chip stays in power-down state,1: If WKADRMEN" bitfld.long 0x0 3. "THRTOWKSTS,Threshold Wake-up Time Out Flag (Read Only)\nNote1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKTHRTOEN" newline bitfld.long 0x0 2. "THRWKSTS,Threshold Wake-up Flag (Read Only)\nNote1: If WKTHREN (UART_ WKUPEN [2])is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKTHREN" bitfld.long 0x0 1. "DATWKSTS,Data Wake-up Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_ WKUPEN [1]) is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: If WKDATEN" newline bitfld.long 0x0 0. "CTSWKSTS,nCTS Wake-up Flag (Read Only)\nNote1: If WKCTSEN (UART_ WKUPEN [0])is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN" tree.end tree "UART1" base ad:0x40150000 rgroup.long 0x0++0x3 line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive /Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT.\nRead.." group.long 0x4++0xB line.long 0x0 "UART_CTRL,UART Control Register." bitfld.long 0x0 13.--14. "ABRDBITS,Auto-baud Rate Detect Bit Length\nNote: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?" bitfld.long 0x0 12. "ABRDEN,Auto-baud Rate Detect EnableBit\nNote: When the auto-baud rate detect operation finishes hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_INTEN [7]) be enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x0 8. "FTOEN,Frame Time Out Enable Bit\nThis bit is used to enable the timer counter even the FIFO is still empty." "0: Frame time out Disabled,1: Frame time out Enabled" bitfld.long 0x0 7. "TXDMAEN,TX DMA Enable Bit\nThis bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled" newline bitfld.long 0x0 6. "RXDMAEN,RX DMA Enable Bit\nThis bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled" bitfld.long 0x0 5. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote:When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x0 4. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_LINE[13:12]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x0 3. "TXOFF,Transfer Disable Bit" "0: Transfer Enabled,1: Transfer Disabled" newline bitfld.long 0x0 2. "RXOFF,Receiver Disable Bit\nNote1:In RS-485 NMM mode user can set this bit to receive data before detecting address byte.\nNote2: In RS-485 AAD mode this bit will be setting to '1' automatically.\nNote3: In RS-485 AUD mode and LIN 'break + sync +PID'.." "0: Receiver Enabled,1: In RS-485 NMM mode" bitfld.long 0x0 1. "TXRST,TX Field Software Reset\nWhen TXRST (UART_CTRL[1]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles" "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x0 0. "RXRST,RX Field Software Reset\nWhen RXRST (UART_CTRL[0]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x4 "UART_LINE,UART Transfer Line Control Register." bitfld.long 0x4 12.--13. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control." "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,?,?" bitfld.long 0x4 8.--9. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated).\nNote: When operating in IrDA mode or RS-485 mode the.." "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,?,?" newline bitfld.long 0x4 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled" bitfld.long 0x4 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled" newline bitfld.long 0x4 4. "EPE,Even Parity EnableBit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x4 3. "PBE,Parity Bit EnableBit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: No parity bit generated Disabled,1: Parity bit generated Enabled" newline bitfld.long 0x4 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.." bitfld.long 0x4 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?" line.long 0x8 "UART_INTEN,UART Interrupt Enable Register." bitfld.long 0x8 9. "TXENDIEN,Transmitter Empty FInterrupt Enable Bit\nNote: If the bit is enabled there is interrupt event when the TXENDF (UART_FIFOSTS[11]) is actived." "0: Transmit Empty interrupt Disabled,1: Transmit Empty interrupt Enabled" bitfld.long 0x8 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote:This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" newline bitfld.long 0x8 7. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" bitfld.long 0x8 6. "WKUPIEN,Wake-up Interrupt EnableBit\nNote: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and 'system clock' work stable." "0: Wake-up system function Disabled,1: Wake-up system function Enabled when the system.." newline bitfld.long 0x8 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" bitfld.long 0x8 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-outinterrupt Enabled" newline bitfld.long 0x8 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem statusinterrupt Enabled" bitfld.long 0x8 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" newline bitfld.long 0x8 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled" bitfld.long 0x8 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" rgroup.long 0x10++0xB line.long 0x0 "UART_INTSTS,UART Interrupt Status Register." bitfld.long 0x0 8. "LINIF,LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted RX header received or the SIN does not equal SOUT and if LINIEN(UART_INTEN[8]) is set then the LIN interrupt will be generated.\nNote1: This bit is read.." "0: No LIN interrupt is generated,1: This bit is read only" bitfld.long 0x0 7. "ABRIF,Auto-baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[7]) is set then the auto-baud rate interrupt will be.." "0: No Auto-Baud Rate interrupt is generated,1: This bit is read only" newline bitfld.long 0x0 6. "WKUPIF,Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by one of UART controller wake-up event.\nNote1: If WKDATEN (UART_INTEN[6]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only .." "0: Chip stays in power-down state,1: If WKDATEN" bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[8]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set the transfer is not correct. If BFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline bitfld.long 0x0 4. "RXTOIF,Rime-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled the Tout interrupt will be.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated" bitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEM[18])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" line.long 0x4 "UART_TRSR,UART Transfer Status Register." bitfld.long 0x4 8. "SLVSYNCF,LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic '1' when LIN received incorrect SYNC field.\nUser can choose the header by setting LINHSEL (UART_ATLCTL[5:4]) register.\nNote: This bit is read only but can be cleared by writing '1'.." "0: No LIN Rx sync error is generated,1: LIN Rx sync error is generated" bitfld.long 0x4 7. "RXBUSY,Receive Busy Status(Read Only)\nNote: The user can use this to check the busy status in receiver mode. If the user wants to enter power down this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin." "0: The receiver machine stays in idle state,1: The receiver machine stays in no Idle state" newline bitfld.long 0x4 5. "BITEF,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state is not equal to the output pin (SOUT) state BITEF will be set.\nWhen occur bit error hardware will generate an.." "0: No Bit error interrupt is generated,1: Bit error interrupt is generated" bitfld.long 0x4 4. "LINRXIF,LIN RX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when received LIN header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' and it can be choose by setting LINHSEL.." "0: No LIN Rx interrupt is generated,1: LIN Rx interrupt is generated" newline bitfld.long 0x4 3. "LINTXIF,LIN TX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when LIN transmitted header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' it can be choose by setting LINHSEL.." "0: No LIN Transmit interrupt is generated,1: LIN Transmit interrupt is generated" bitfld.long 0x4 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt(Read Only)\nNote1:This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: This bit is set to logic '1' in Auto-baud Rate.." newline bitfld.long 0x4 1. "ABRDIF,Auto-baud Rate Interrupt (Read Only)\nThis bit is set to logic '1' when auto-baud rate detect function finished.\nNote: This bit is read only but can be cleared by writing '1' to it." "0: No Auto- Baud Rate interrupt is generated,1: Auto-Baud Rate interrupt is generated" bitfld.long 0x4 0. "ADDRDETF,RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only but can be cleared by writing.." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.." line.long 0x8 "UART_FIFOSTS,UART FIFO Status Register." hexmask.long.byte 0x8 24.--28. 1. "TXPTR,TX-fIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.." hexmask.long.byte 0x8 16.--20. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.." newline bitfld.long 0x8 11. "TXENDF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote:This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x8 10. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote:This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full" newline bitfld.long 0x8 9. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty" bitfld.long 0x8 8. "TXOVIF,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote:This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO did not overflow,1: TX FIFO overflowed" newline bitfld.long 0x8 6. "BIF,Break Interrupt Flag( Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x8 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x8 4. "PEF,Parity Error State Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x8 2. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full" newline bitfld.long 0x8 1. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty" bitfld.long 0x8 0. "RXOVIF,RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size this bit will be set.\nNote:This bit is read only but can be cleared by writing '1'.." "0: RX FIFO is not overflow,1: RX FIFO is overflow" group.long 0x1C++0xB line.long 0x0 "UART_MODE,UART Modem Control Status Register." rbitfld.long 0x0 18. "CTSDETF,Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]).\nNote: This bit is read only but it can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state" rbitfld.long 0x0 17. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state" newline bitfld.long 0x0 16. "CTSACTLV,nCTS Trigger Level\nThis bit defines the active level state of nCTS pin input." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)" rbitfld.long 0x0 1. "RTSSTS,nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state" newline bitfld.long 0x0 0. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output." "0: nRTS pin output is high level active,1: nRTS pin output is low level active. (Default)" line.long 0x4 "UART_TOUT,UART Time-Out Control Register." hexmask.long.byte 0x4 16.--23. 1. "DLY,TX Delay Time Value\nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.\nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real delay value is.." hexmask.long.word 0x4 0.--8. 1. "TOIC,Time-out Comparator\nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real time-out value is TOIC + 1.\nNote3: The counting clock is baud rate clock.\nNote4: The UART data format is start bit + 8 data bits + parity.." line.long 0x8 "UART_BAUD,UART Baud Rate Divisor Register." bitfld.long 0x8 31. "DIV16EN,Divider 16 Enable Control\nNote: In IrDA mode this bit must clear to '0'." "0: The equation of baud rate is UART_CLK / [(BRD+1)],1: The equation of baud rate is UART_CLK / [16 *.." hexmask.long.word 0x8 0.--15. 1. "BRD,Baud Rate Divider \nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown inUART Controller Baud Rate Generation." group.long 0x30++0x13 line.long 0x0 "UART_IRDA,UART IrDA Control Register." bitfld.long 0x0 6. "RXINV,IrDA Inverse Receive Input Signal" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)" bitfld.long 0x0 5. "TXINV,IrDA Inverse Transmitting Output Signal" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal" newline bitfld.long 0x0 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled" line.long 0x4 "UART_ATLCTL,UART Alternate Control State Register." hexmask.long.byte 0x4 24.--31. 1. "ADRMPID,Address / PID Match Value Register\nWhen in the RS-485 Function Mode this field contains the RS-485 address match values.\nWhen in the LIN Function mode this field contains the LIN protected identifier field software fills ID0~ID5 (PID [5:0]) .." bitfld.long 0x4 19. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0x4 18. "RS485AUD,RS-485 Auto Direction Function (AUD)\nNote: It can be active with RS485AAD or RS485NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).." bitfld.long 0x4 17. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0x4 16. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0x4 8. "BITERREN,Bit Error Detect EnableBit" "0: Bit error detection Disabled,1: Bit error detection Enabled" newline bitfld.long 0x4 7. "LINTXEN,LIN TX Header Trigger EnableBit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LINHSEL (UART_ATLCTL[5:4]).\nNote1: This bit will be cleared automatically and generate.." "0: Send LIN TX header Disabled,1: This bit will be cleared automatically and.." bitfld.long 0x4 6. "LINRXEN,LIN RX Enable Control\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL) the controller will generator a interrupt to CPU (LININT)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x4 4.--5. "LINHSEL,LIN Header Selection" "0: The LIN header includes 'break field',1: The LIN header includes 'break field + sync field',?,?" bitfld.long 0x4 0.--2. "BRKFL,LIN TX Break Field Count \nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is BRKFL + 8." "?,?,?,3: bit LIN TX break field count,?,?,?,?" line.long 0x8 "UART_FUNCSEL,UART Function Select Register." bitfld.long 0x8 0.--1. "FUNCSEL,Function Selection" "0: UART function mode,1: LIN function mode,?,?" line.long 0xC "UART_BRCOMPAT,UART Baud Rate Compensation Register." bitfld.long 0xC 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0xC 0.--8. 1. "BRCOMPAT,Baud Rate Compensation Patten\nThese 9bits are used to define the relative bit is compensated or not. BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit." line.long 0x10 "UART_WKUPEN,UART Wake-up Enable Register." bitfld.long 0x10 4. "WKADRMEN,RS-485 Address Match Wake-up Enable Bit" "0: RS-485 ADD mode address match wake-up function..,1: RS-485 AAD mode address match wake-up function.." bitfld.long 0x10 3. "WKTHRTOEN,FIFO Threshold Reach Time Out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1." "0: Received FIFO threshold no reach and time out..,1: Received FIFO threshold no reach and time out.." newline bitfld.long 0x10 2. "WKTHREN,FIFO Threshold Reach Wake-up Enable Bit\nNote: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K." "0: Received FIFO threshold reach wake-up function..,1: Received FIFO threshold reach wake-up function.." bitfld.long 0x10 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up function Disabled,1: Incoming data wake-up function Enabled when the.." newline bitfld.long 0x10 0. "WKCTSEN,CTSn Wake-up Enable Bit\nWhen the system is in power-down mode an external nCTS change will wake-up system from power-down mode." "0: nCTS wake-up function Disabled,1: nCTS wake-up function Enabled" rgroup.long 0x44++0x3 line.long 0x0 "UART_WKUPSTS,UART Wake-up Status Register." bitfld.long 0x0 4. "ADRWKSTS,RS-485 Address Byte Detection Wake-up Flag (Read Only)\nNote1: If WKADRMEN (UART_WKUPEN[4])is enabled the wake-up function is generated.\nNote2: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable.." "0: Chip stays in power-down state,1: If WKADRMEN" bitfld.long 0x0 3. "THRTOWKSTS,Threshold Wake-up Time Out Flag (Read Only)\nNote1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKTHRTOEN" newline bitfld.long 0x0 2. "THRWKSTS,Threshold Wake-up Flag (Read Only)\nNote1: If WKTHREN (UART_ WKUPEN [2])is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKTHREN" bitfld.long 0x0 1. "DATWKSTS,Data Wake-up Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_ WKUPEN [1]) is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by.." "0: Chip stays in power-down state,1: If WKDATEN" newline bitfld.long 0x0 0. "CTSWKSTS,nCTS Wake-up Flag (Read Only)\nNote1: If WKCTSEN (UART_ WKUPEN [0])is enabled the wake-up function is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN" tree.end tree.end tree "WDT (Watchdog Timer)" base ad:0x40004000 group.long 0x0++0xB line.long 0x0 "WDT_CTL,Watchdog Timer Control Register" bitfld.long 0x0 31. "DBGEN,WDT Debug Mode Enable Control (Write Protect)" "0: WDT stopped counting if system is in Debug mode,1: WDT still counted even system is in Debug mode" bitfld.long 0x0 8.--9. "WTRDSEL,Watchdog Timer Reset Delay Selection\nWhen watchdog time-out happened software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay.." "0: Watchdog reset delay period is 1026 watchdog clock,1: Watchdog reset delay period is 130 watchdog clock,?,?" newline bitfld.long 0x0 4.--6. "WTIS,Watchdog Timer Interval Selection(Write Protect)\nPlease refer to open lock sequence to program it.\nThe three bits select the time-out interval for the Watchdog timer. This count is free running counter.\nPlease refer toTable6.111." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "WDTEN,Watchdog Timer EnableBit(Write Protect)\nPlease refer to open lock sequence to program it." "0: Watchdog timer Disabled (this action will reset..,1: Watchdog timer Enabled" newline bitfld.long 0x0 2. "WKEN,Watchdog Timer Wake-up Function EnableBit(Write Protect)\nPlease refer to open lock sequence to program it." "0: Watchdog timer Wake-up CPU function Disabled,1: Wake-up function Enabled so that Watchdog timer.." bitfld.long 0x0 1. "RSTEN,Watchdog Timer Reset Function EnableBit (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will enable the Watchdog timer reset function." "0: Watchdog timer reset function Disabled,1: Watchdog timer reset function Enabled" newline bitfld.long 0x0 0. "RSTCNT,Reset Watchdog TimerCounter (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will reset the Watchdog timer counter.\nNote: This bit will be auto cleared after 1 PCLK clock cycle." "0: No effect,1: Reset the contents of the Watchdog timer" line.long 0x4 "WDT_INTEN,Watchdog Timer Interrupt Enable Register" bitfld.long 0x4 0. "WDTIEN,Watchdog Timer Time-out Interrupt EnableBit" "0: Watchdog timer time-out interrupt Disabled,1: Watchdog timer time-out interrupt Enabled" line.long 0x8 "WDT_STATUS,Watchdog Timer Status Register" bitfld.long 0x8 2. "WKF,Watchdog Timer Wake-up StatusFlag\nIf Watchdog timer causes system to wake up from Power-down mode this bit will be set to 1. It must be cleared by software with a write '1' to this bit.\nNote1: When system in Power-down mode and watchdog time-out .." "0: Watchdog timer does not cause system wake-up,1: When system in Power-down mode and watchdog.." bitfld.long 0x8 1. "RSTF,Watchdog Timer Reset StatusFlag\nWhen the Watchdog timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing '1' to it. If.." "0: Watchdog timer reset did not occur,1: Watchdog timer reset occurred" newline bitfld.long 0x8 0. "WDTIF,Watchdog Timer Time-out Interrupt StatusFlag\nIf the Watchdog timer time-out interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer time-out interrupt has occurred. If the Watchdog timer time-out interrupt is.." "0: Watchdog timer time-out interrupt did not occur,1: Watchdog timer time-out interrupt occurred" tree.end tree "WWDT (Window Watchdog Timer)" base ad:0x40004100 wgroup.long 0x0++0x3 line.long 0x0 "WWDT_RLDCNT,Window Watchdog Timer Reload Counter Register" hexmask.long 0x0 0.--31. 1. "RLDCNT,Window Watchdog Timer Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.\nNote:This registercan only be written when WWDT counter value between 0 and WINCMP otherwise WWDT.." group.long 0x4++0xB line.long 0x0 "WWDT_CTL,Window Watchdog Timer Control Register" bitfld.long 0x0 31. "DBGEN,WWDT Debug EnableBit" "0: WWDT stopped count if system is in Debug mode,1: WWDT still counted even system is in Debug mode" hexmask.long.byte 0x0 16.--21. 1. "WINCMP,WWDT Window Compare Bits\nSet this register to adjust the valid reload window.\nNote:WWDT_RLDCNTregistercan only be written when WWDT counter value between 0 and WINCMP otherwise WWDT will generate RESET signal." hexmask.long.byte 0x0 8.--11. 1. "PERIODSEL,WWDT Pre-scale Period Select\nThese three bits select the pre-scale for the WWDT counter period.\nPlease refer toTable 6.121WWDT Prescaler Value Selection." bitfld.long 0x0 0. "WWDTEN,Window Watchdog EnableBit\nSet this bit to enable Window Watchdog timer." "0: Window Watchdog timer function Disabled,1: Window Watchdog timer function Enabled" line.long 0x4 "WWDT_INTEN,Window Watchdog Timer Interrupt Enable Register" bitfld.long 0x4 0. "WWDTIEN,WWDT Interrupt Enable Bit\nSetting this bit will enable the Window Watchdog timer interrupt function." "0: Watchdog timer interrupt function Disabled,1: Watchdog timer interrupt function Enabled" line.long 0x8 "WWDT_STATUS,Window Watchdog Timer Status Register" bitfld.long 0x8 1. "WWDTRF,WWDT Reset Flag\nWhen the WWDT counter down counts to 0 or writes WWDT_RLDCNT during WWDT counter larger than WINCMP chip will be reset and this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" bitfld.long 0x8 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter this bit is set to 1. This bit can be cleared by writing '1' to it." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "WWDT_CNT,Window Watchdog Timer Counter Value Register" hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value\nThis register reflects the current counter value of window watchdog." tree.end AUTOINDENT.OFF