; -------------------------------------------------------------------------------- ; @Title: NANO100 On-Chip Peripherals ; @Props: Released ; @Author: NEJ, KRZ ; @Changelog: 2023-09-07 NEJ ; 2023-11-09 KRZ ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: Generated (TRACE32, build: 164352.), based on: ; NANO100AN_v1.svd (Ver. 1.0), NANO100BN_v1.svd (Ver. 1.0) ; @Core: Cortex-M0 ; @Chip: NANO100KD3BN, NANO100KE3BN, NANO100LC2AN, NANO100LC2BN, ; NANO100LD2AN, NANO100LD2BN, NANO100LD3AN, NANO100LD3BN, ; NANO100LE3BN, NANO100NC2BN, NANO100ND2BN, NANO100ND3BN, ; NANO100NE3BN, NANO100SC2BN, NANO100SD2AN, NANO100SD2BN, ; NANO100SD3AN, NANO100SD3BN, NANO100SE3BN, NANO100ZC2AN, ; NANO100ZD2AN, NANO100ZD3AN, NANO110KC2BN, NANO110KD2BN, ; NANO110KD3BN, NANO110KE3BN, NANO110RC2BN, NANO110RD2BN, ; NANO110RD3BN, NANO110RE3BN, NANO110SC2BN, NANO110SD2BN, ; NANO110SD3BN, NANO110SE3BN, NANO120KD3BN, NANO120KE3BN, ; NANO120LC2AN, NANO120LC2BN, NANO120LD2AN, NANO120LD2BN, ; NANO120LD3AN, NANO120LD3BN, NANO120LE3BN, NANO120SC2BN, ; NANO120SD2AN, NANO120SD2BN, NANO120SD3AN, NANO120SD3BN, ; NANO120SE3BN, NANO120ZC2AN, NANO120ZD2AN, NANO120ZD3AN, ; NANO130KC2BN, NANO130KD2BN, NANO130KD3BN, NANO130KE3BN, ; NANO130SC2BN, NANO130SD2BN, NANO130SD3BN, NANO130SE3BN ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pernano100.per 16971 2023-11-09 16:09:22Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x400E0000 rgroup.long 0x0++0x1F line.long 0x0 "ADC_RESULT0,A/D Result Register 0" sif (cpuis("NANO1*BN")) hexmask.long.word 0x0 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x0 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x0 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0x4 "ADC_RESULT1,A/D Result Register 1" sif (cpuis("NANO1*BN")) hexmask.long.word 0x4 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x4 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x4 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x4 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0x8 "ADC_RESULT2,A/D Result Register 2" sif (cpuis("NANO1*BN")) hexmask.long.word 0x8 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x8 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x8 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x8 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0xC "ADC_RESULT3,A/D Result Register 3" sif (cpuis("NANO1*BN")) hexmask.long.word 0xC 18.--31. 1. "Reserve,Reserved" rbitfld.long 0xC 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0xC 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0xC 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0x10 "ADC_RESULT4,A/D Result Register 4" sif (cpuis("NANO1*BN")) hexmask.long.word 0x10 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x10 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x10 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x10 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0x14 "ADC_RESULT5,A/D Result Register 5" sif (cpuis("NANO1*BN")) hexmask.long.word 0x14 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x14 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x14 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x14 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0x18 "ADC_RESULT6,A/D Result Register 6" sif (cpuis("NANO1*BN")) hexmask.long.word 0x18 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x18 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x18 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x18 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." line.long 0x1C "ADC_RESULT7,A/D Result Register 7" sif (cpuis("NANO1*BN")) hexmask.long.word 0x1C 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x1C 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x1C 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x1C 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." sif (cpuis("NANO1*BN")) rgroup.long 0x20++0x7 line.long 0x0 "ADC_RESULT8,A/D Data Register 8" hexmask.long.word 0x0 18.--31. 1. "Reserve,Reserved" bitfld.long 0x0 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x0 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0x4 "ADC_RESULT9,A/D Data Register 9" hexmask.long.word 0x4 18.--31. 1. "Reserve,Reserved" bitfld.long 0x4 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x4 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x4 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." rgroup.long 0x2C++0x1B line.long 0x0 "ADC_RESULT11,A/D Data Register 11" hexmask.long.word 0x0 18.--31. 1. "Reserve,Reserved" bitfld.long 0x0 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x0 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0x4 "ADC_RESULT12,A/D Data Register 12" hexmask.long.word 0x4 18.--31. 1. "Reserve,Reserved" bitfld.long 0x4 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x4 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x4 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0x8 "ADC_RESULT13,A/D Data Register 13" hexmask.long.word 0x8 18.--31. 1. "Reserve,Reserved" bitfld.long 0x8 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x8 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x8 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0xC "ADC_RESULT14,A/D Data Register 14" hexmask.long.word 0xC 18.--31. 1. "Reserve,Reserved" bitfld.long 0xC 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0xC 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0xC 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0x10 "ADC_RESULT15,A/D Data Register 15" hexmask.long.word 0x10 18.--31. 1. "Reserve,Reserved" bitfld.long 0x10 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x10 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x10 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0x14 "ADC_RESULT16,A/D Data Register 16" hexmask.long.word 0x14 18.--31. 1. "Reserve,Reserved" bitfld.long 0x14 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x14 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x14 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." line.long 0x18 "ADC_RESULT17,A/D Data Register 17" hexmask.long.word 0x18 18.--31. 1. "Reserve,Reserved" bitfld.long 0x18 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" newline bitfld.long 0x18 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" hexmask.long.word 0x18 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion results." group.long 0x48++0x13 line.long 0x0 "ADCR,A/D Control Register" hexmask.long.byte 0x0 24.--31. 1. "TMPDMACNT,PDMA Count\nWhen each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set ADC.." bitfld.long 0x0 18.--19. "RESSEL,Resolution Selection" "0,1,2,3" newline bitfld.long 0x0 16.--17. "REFSEL,Reference Voltage Source Selection" "0,1,2,3" bitfld.long 0x0 15. "TMTRGMOD,Timer Event Trigger ADC Conversion" "0: This function Disabled,1: ADC Enabled by TIMER OUT event" newline bitfld.long 0x0 12.--13. "TMSEL,Select A/D Enable Time-out Source" "0,1,2,3" bitfld.long 0x0 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan.." "0: Conversion stopped and A/D converter enter idle..,1: Conversion starts" newline bitfld.long 0x0 10. "DIFF,Differential Mode Selection\n1:ADC is operated in differential mode\n0:ADC is operated in single-ended mode\nNote: Calibration should calibrated each time when switching between single-ended and differential mode" "?,1: ADC is operated in differential mode\n0:ADC is.." bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADC_RESULT 0~17 Enabled" newline bitfld.long 0x0 8. "TRGE,External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin." "0: Disabled,1: Enabled" bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source\n" "0,1,2,3" bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode\n" "0,1,2,3" newline bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" bitfld.long 0x0 0. "ADEN,A/D Converter Enable\nBefore starting A/D conversion this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption." "0: Disabled,1: Enabled" line.long 0x4 "ADCHER,A/D Channel Enable Register" bitfld.long 0x4 17. "CHEN17,Analog Input Channel 17 Enable (Convert AVSS)" "0: Disabled,1: Enabled" bitfld.long 0x4 16. "CHEN16,Analog Input Channel 16 Enable (Convert AVDD)" "0: Disabled,1: Enabled" newline bitfld.long 0x4 15. "CHEN15,Analog Input Channel 15 Enable (Convert Int_VREF)" "0: Disabled,1: Enabled" bitfld.long 0x4 14. "CHEN14,Analog Input Channel 14 Enable (Convert VTEMP)" "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "CHEN13,Analog Input Channel 13 Enable (Convert DAC1 Output Voltage)" "0: Disabled,1: Enabled" bitfld.long 0x4 12. "CHEN12,Analog Input Channel 12 Enable (Convert DAC0 Output Voltage)" "0: Disabled,1: Enabled" newline bitfld.long 0x4 11. "CHEN11,Analog Input Channel 11 Enable(Convert input voltage from PD.3 )" "0: Disabled,1: Enabled" bitfld.long 0x4 10. "CHEN10,Analog Input Channel 10 Enable (Convert Input Voltage from PD.2 )" "0: Disabled,1: Enabled" newline bitfld.long 0x4 9. "CHEN9,Analog Input Channel 9 Enable for DAC1 (Convert Input Voltage from PD.1 )" "0: Disabled,1: Enabled" bitfld.long 0x4 8. "CHEN8,Analog Input Channel 8 Enable for DAC0 (Convert Input Voltage from PD.0 )" "0: Disabled,1: Enabled" newline bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable (Convert Input Voltage from PA.7 )" "0: Disabled,1: Enabled" bitfld.long 0x4 6. "CHEN6,Anaslog Input Channel 6 Enable (Convert Input Voltage from PA.6 )" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable (Convert Input Voltage from PA.5 )" "0: Disabled,1: Enabled" bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable (Convert Input Voltage from PA.4 )" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable(Convert input voltage from PA.3 )" "0: Disabled,1: Enabled" bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable (Convert Input Voltage from PA.2 )" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable(Convert input voltage from PA.1 )" "0: Disabled,1: Enabled" bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable (Convert Input Voltage from PA.0 )\nIf more than one channel in single mode is enabled by software the least channel is converted and other enabled channels will be ignored." "0: Disabled,1: Enabled" line.long 0x8 "ADCMPR0,A/D Compare Register 0" hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software." hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.." newline hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection" bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPF bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.." newline bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0x8 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1 and CMPMATCNT is 0 the CMPF will be set once the match is.." "0: Compare Disabled,1: Compare Enabled" line.long 0xC "ADCMPR1,A/D Compare Register 1" hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software." hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.." newline hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection" bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPF bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.." newline bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0xC 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1 and CMPMATCNT is 0 the CMPF will be set once the match is.." "0: Compare Disabled,1: Compare Enabled" line.long 0x10 "ADSR,A/D Status Register" bitfld.long 0x10 16. "INITRDY,ADC Power-up Sequence Completed\nNote: This bit will be set after system reset occurred and automatically cleared by power-up event." "0: ADC has been powered up since he last system reset,1: ADC not powered up after system reset" hexmask.long.byte 0x10 4.--8. 1. "CHANNEL,Current Conversion Channel\nIt is read only." newline bitfld.long 0x10 3. "BUSY,BUSY/IDLE\nIt is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" bitfld.long 0x10 2. "CMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set the.." "0: Conversion result in ADC_RESULTx does not meet..,1: Conversion result in ADC_RESULTx meets ADCMPR1.." newline bitfld.long 0x10 1. "CMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: When this flag is set the.." "0: Conversion result in ADC_RESULTx does not meet..,1: Conversion result in ADC_RESULTx meets.." bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nThis flag can be.." "0,1" endif rgroup.long 0x28++0x3 line.long 0x0 "ADC_RESULT10,A/D Result Register 10" sif (cpuis("NANO1*BN")) hexmask.long.word 0x0 18.--31. 1. "Reserve,Reserved" rbitfld.long 0x0 17. "OVERRUN,Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx" "0,1" rbitfld.long 0x0 16. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx" "0,1" endif hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12 bits conversion result." sif (cpuis("NANO1*AN")) group.long 0x30++0x13 line.long 0x0 "ADCR,A/D Control Register" bitfld.long 0x0 16.--17. "REFSEL,Reference Voltage Source Selection\n" "0: Select power as reference voltage,1: Select VBG as reference voltage,?,?" bitfld.long 0x0 15. "TMTRGMOD,Timer Event Trigger ADC Conversion\nsetting TMSEL to select timer event from timer0~3" "0: This function Disabled,1: ADC Enabled by TIMER out event" newline bitfld.long 0x0 12.--13. "TMSEL,Select A/D Enable Time-Out Source \n" "0: TMR0,1: TMR1,?,?" bitfld.long 0x0 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan.." "0: Conversion stopped and A/D converter enter idle..,1: Conversion starts" newline bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable\n" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADC_RESULT 0~10 Enabled" bitfld.long 0x0 8. "TRGEN,External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.\n" "0: Low level,1: High level,?,?" bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source\nSoftware should disable TRGE and ADST before change TRGS. \nIn hardware trigger mode the ADST bit is set by the external trigger from STADC However software has the highest priority to set or cleared ADST bit at any time." "0: A/D conversion is started by external STADC pin,1: Reserved,?,?" newline bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode\n" "0: Single conversion,1: Reserved,?,?" bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" newline bitfld.long 0x0 0. "ADEN,A/D Converter Enable\nBefore starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption." "0: Disabled,1: Enabled" line.long 0x4 "ADCHER,A/D Channel Enable Register" bitfld.long 0x4 11.--12. "CH10SEL,Select Channel10 Input\n" "0: Select VTEMP as channel10 input,1: Reserved,?,?" bitfld.long 0x4 10. "CHEN10,Analog Input Channel 10 Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x4 6. "CHEN6,Anaslog Input Channel 6 Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable Control\nIf more than one channel in single mode is enabled by software the least channel is converted and other enabled channels will be ignored." "0: Disabled,1: Enabled" line.long 0x8 "ADCMPR0,A/D Compare Register 0" hexmask.long.word 0x8 18.--27. 1. "CMPD,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software." hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.." newline hexmask.long.byte 0x8 3.--6. 1. "CMPCH,Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~10." bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPF (ADSR[2 1]) will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.." newline bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF (ADSR[2 1]) will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0x8 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1 and CMPMATCNT is 0 the CMPF (ADSR[2 1]) will be set once.." "0: Compare Disabled,1: Compare Enabled" line.long 0xC "ADCMPR1,A/D Compare Register 1" hexmask.long.word 0xC 18.--27. 1. "CMPD,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software." hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.." newline hexmask.long.byte 0xC 3.--6. 1. "CMPCH,Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~10." bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPF (ADSR[2 1]) will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.." newline bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF (ADSR[2 1]) will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" bitfld.long 0xC 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1 and CMPMATCNT is 0 the CMPF (ADSR[2 1]) will be set once.." "0: Compare Disabled,1: Compare Enabled" line.long 0x10 "ADSR,A/D Status Register" bitfld.long 0x10 30. "OVERRUN30,Over Run Flag\nWhen VALID is high and ADC converts finish this field will set to high.\nNote: This flag is for ADC_RESULT10" "0,1" hexmask.long.byte 0x10 20.--27. 1. "OVERRUN27_24,Over Run Flag\nWhen VALID is high and ADC converts finish this field will set to high.\nNote: Those flag are for ADC_RESULT0~7" newline bitfld.long 0x10 18. "VALID18,Data Valid Flag\nAfter ADC converts finish this field will set to high.\nThis field will clear when ADC_RESULTx be read.\nNote: This flag is for ADC_RESULT10" "0,1" hexmask.long.byte 0x10 8.--15. 1. "VALID15_8,Data Valid Flag\nAfter ADC converts finish this field will set to high.\nThis field will clear when ADC_RESULTx be read.\nNote: Those flags are for ADC_RESULT0~7" newline hexmask.long.byte 0x10 4.--7. 1. "CHANNEL,Current Conversion Channel (Read Only)\n" bitfld.long 0x10 3. "BUSY,BUSY/IDLE\n" "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline bitfld.long 0x10 2. "CMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set the.." "0: Conversion result in ADC_RESULTx does not meet..,1: Conversion result in ADC_RESULTx meets ADCMPR1.." bitfld.long 0x10 1. "CMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set the.." "0: Conversion result in ADC_RESULTx does not meet..,1: Conversion result in ADC_RESULTx meets.." newline bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nThis flag can be.." "0,1" group.long 0x54++0x3 line.long 0x0 "ADFCR,A/D FPGA Control Register+" group.long 0x64++0x3 line.long 0x0 "ADCDELSEL,PDMA Counter for Delay Time and PDMA Transfer Count and ADC Start Hold Counter" hexmask.long.byte 0x0 16.--23. 1. "ADCSTHOLDCNT,ADC Start Hold Time Counter\nThis ADC start is the start signal from ADC controller to analog ADC not the ADST in ADCR[11] .\nIn Figure 517 when ADC start signal transition from high to low the ADC reset signal will transition from low to.." hexmask.long.byte 0x0 8.--15. 1. "TMPDMACNT,PDMA Count\nWhen each time out event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set .." newline hexmask.long.byte 0x0 0.--7. 1. "En2StDelay,A/D Delay Time Select Register\nSet this register to adjust the time interval (in PCLK unit )between start signal and enable signal of ADC\nNote: The time interval is En2StDelay+1 PCLK cycle" endif rgroup.long 0x60++0x3 line.long 0x0 "ADPDMA,A/D PDMA Current Transfer Data Register" hexmask.long.word 0x0 0.--11. 1. "AD_PDMA,ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring read this register can monitor current PDMA transfer data." sif (cpuis("NANO1*BN")) group.long 0x64++0x13 line.long 0x0 "ADCPWD,ADC Power Management Register" bitfld.long 0x0 2.--3. "PWDMOD,Power-down Mode" "0,1,2,3" bitfld.long 0x0 1. "PWDCALEN,Power up Calibration Function Enable" "0: Power up without calibration,1: Power up with calibration" newline bitfld.long 0x0 0. "PWUPRDY,ADC Power-up Sequence Completed and Ready for Conversion" "0: ADC is not ready for conversion;may be in power..,1: ADC is ready for conversion" line.long 0x4 "ADCCALCTL,ADC Calibration Control Register" bitfld.long 0x4 3. "CALSEL,Select Calibration Functional Block" "0: Load calibration functional block,1: Calibration functional block" bitfld.long 0x4 2. "CALDONE,Calibrate Functional Block Complete" "0: Not yet,1: Selected functional block complete" newline bitfld.long 0x4 1. "CALSTART,Calibration Functional Blcok Start" "0: Stops calibration functional block,1: Starts calibration functional block" bitfld.long 0x4 0. "CALEN,Calibraion Function Enable\nEnable this bit to turn on the calibration function block." "0: (BYPASSCAL),1: Enabled" line.long 0x8 "ADCCALWORD,A/D calibration load word register" hexmask.long.byte 0x8 0.--6. 1. "CALWORD,Calibration Word Register \nWrite to this register with the previous calibration word before load calibration action\nRead this register after calibration done \nNote: The calibration block contains two parts 'CALIBRATION' and 'LOAD CALIBRATION';.." line.long 0xC "ADCCHSAMP0,ADC Channel Sampling Time Counter Register Group 0" hexmask.long.byte 0xC 28.--31. 1. "CH7SAMPCNT,Channel 7 Sampling Counter\nThe same as Channel 0 sampling counter table." hexmask.long.byte 0xC 24.--27. 1. "CH6SAMPCNT,Channel 6 Sampling Counter\nThe same as Channel 0 sampling counter table." newline hexmask.long.byte 0xC 20.--23. 1. "CH5SAMPCNT,Channel 5 Sampling Counter\nThe same as Channel 0 sampling counter table." hexmask.long.byte 0xC 16.--19. 1. "CH4SAMPCNT,Channel 4 Sampling Counter\nThe same as Channel 0 sampling counter table." newline hexmask.long.byte 0xC 12.--15. 1. "CH3SAMPCNT,Channel 3 Sampling Counter\nThe same as Channel 0 sampling counter table." hexmask.long.byte 0xC 8.--11. 1. "CH2SAMPCNT,Channel 2 Sampling Counter\nThe same as Channel 0 sampling counter table." newline hexmask.long.byte 0xC 4.--7. 1. "CH1SAMPCNT,Channel 1 Sampling Counter\nThe same as Channel 0 sampling counter table." hexmask.long.byte 0xC 0.--3. 1. "CH0SAMPCNT,Channel 0 Sampling Counter" line.long 0x10 "ADCCHSAMP1,ADC Channel Sampling Time Counter Register Group 1" hexmask.long.byte 0x10 16.--19. 1. "INTCHSAMPCNT,Internal Channel (VTEMP AVDD AVSS Int_VREF DAC0 DAC1) Sampling Counter\nThe same as Channel 0 sampling counter table." hexmask.long.byte 0x10 12.--15. 1. "CH11SAMPCNT,Channel 11 Sampling Counter\nThe same as Channel 0 sampling counter table." newline hexmask.long.byte 0x10 8.--11. 1. "CH10SAMPCNT,Channel 10 Sampling Counter\nThe same as Channel 0 sampling counter table." hexmask.long.byte 0x10 4.--7. 1. "CH9SAMPCNT,Channel 9 Sampling Counter\nThe same as Channel 0 sampling counter table." newline hexmask.long.byte 0x10 0.--3. 1. "CH8SAMPCNT,Channel 8 Sampling Counter\nThe same as Channel 0 sampling counter table." endif tree.end tree "CLK (Clock Controller)" base ad:0x50000200 group.long 0x0++0xB line.long 0x0 "PWRCTL,System Power Down Control Register" sif (cpuis("NANO1*BN")) bitfld.long 0x0 11.--12. "HXT_HF_ST,HXT_HF_ST" "0,1,2,3" endif bitfld.long 0x0 10. "LXT_SCNT,LXT Stable Time Control\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: Delay 4096 LXT before LXT output,1: Delay 8192 LXT before LXT output" newline bitfld.long 0x0 9. "HXT_GAIN,HXT Gain Control Bit\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled crystal will consume more.." "0: Gain control Disabled. It means HXT gain is..,1: Gain control Enabled. HXT gain will be high.." bitfld.long 0x0 8. "HXT_SELXT,HXT SELXT\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: High frequency crystal loop back path Disabled.,1: High frequency crystal loop back path Enabled." newline bitfld.long 0x0 6. "PD_EN,Chip Power-Down Mode Enable Bit\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen CPU sets this bit the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active." "0: Chip operated in Normal mode,1: Chip power down Enabled" bitfld.long 0x0 5. "PD_WK_IE,Power-Down Mode Wake-Up Interrupt Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nPD_WK_INT will be set if both PD_WK_IS (PD_WK_IS[0]) and PD_WK_IE (PWRCTL[5]) are high." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "WK_DLY,Wake-Up Delay Counter Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen chip wakes up from Power-down mode the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait.." "0: Delay clock cycle delay Disabled,1: Delay clock cycle delay Enabled" bitfld.long 0x0 3. "LIRC_EN,LIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLIRC is enabled by default." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "HIRC_EN,HIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nHIRC is enabled by default." "0: Disabled,1: Enabled" bitfld.long 0x0 1. "LXT_EN,LXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLXT is disabled by default." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "HXT_EN,HXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe bit default value is set by flash controller user configuration register config0 [26]. \nHXT is disabled by default." "0: Disabled,1: Enabled" line.long 0x4 "AHBCLK,AHB Devices Clock Enable Control Register" bitfld.long 0x4 5. "TICK_EN,System Tick Clock Enable\n" "0: Disabled,1: Enabled" bitfld.long 0x4 4. "SRAM_EN,SRAM Controller Clock Enable\n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "EBI_EN,EBI Controller Clock Enable\n" "0: Disabled,1: Enabled" bitfld.long 0x4 2. "ISP_EN,Flash ISP Controller Clock Enable\n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "DMA_EN,DMA Controller Clock Enable\n" "0: Disabled,1: Enabled" bitfld.long 0x4 0. "GPIO_EN,GPIO Controller Clock Enable \n" "0: Disabled,1: Enabled" line.long 0x8 "APBCLK,APB Devices Clock Enable Control Register" bitfld.long 0x8 31. "SC1_EN,SmartCard 1 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 30. "SC0_EN,SmartCard 0 Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 29. "I2S_EN,I2S Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 28. "ADC_EN,Analog-Digital-Converter (ADC) Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 27. "USBD_EN,USB FS Device Controller Clock Enable Control\n" "0: Disabled,1: Enabled" sif (cpuis("NANO1*BN")) bitfld.long 0x8 26. "LCD_EN,LCD controller Clock Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x8 25. "DAC_EN,12-bit DAC Clock Enable Control" "0: Disabled,1: Enabled" endif bitfld.long 0x8 23. "PWM1_CH23_EN,PWM1 Channel 2 And Channel 3 Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 22. "PWM1_CH01_EN,PWM1 Channel 0 And Channel 1 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 21. "PWM0_CH23_EN,PWM0 Channel 2 And Channel 3 Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 20. "PWM0_CH01_EN,PWM0 Channel 0 And Channel 1Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 17. "UART1_EN,UART1 Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 16. "UART0_EN,UART0 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 14. "SPI2_EN,SPI2 Clock Enable Control \n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 13. "SPI1_EN,SPI1 Clock Enable Control \n" "0: Disabled,1: Enabled" bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable Control \n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 9. "I2C1_EN,I2C1 Clock Enable Control \n" "0: Disabled,1: Enabled" bitfld.long 0x8 8. "I2C0_EN,I2C0 Clock Enable Control \n" "0: Disabled,1: Enabled" newline sif (cpuis("NANO1*BN")) bitfld.long 0x8 7. "SC2_EN,SmartCard 2 Clock Enable Control." "0: Disabled,1: Enabled" endif bitfld.long 0x8 6. "FDIV_EN,Frequency Divider Output Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 5. "TMR3_EN,Timer3 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable Control\n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 1. "RTC_EN,Real-Time-Clock Clock Enable Control \nThis bit is used to control the RTC APB clock only The RTC engine Clock Source is from LXT.\n" "0: Disabled,1: Enabled" bitfld.long 0x8 0. "WDT_EN,Watch-Dog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only The WDT engine Clock Source is from LIRC.\n" "0: Disabled,1: Enabled" rgroup.long 0xC++0x3 line.long 0x0 "CLKSTATUS,Clock Status Monitor Register" bitfld.long 0x0 7. "CLK_SW_FAIL,Clock Switch Fail Flag\nThis bit will be set when target switch Clock Source is not stable. This bit is write 1 clear" "0: Clock switch success,1: Clock switch fail" bitfld.long 0x0 4. "HIRC_STB,HIRC Clock Source Stable Flag\n" "0: HIRC clock is not stable or not enable,1: HIRC clock is stable" newline bitfld.long 0x0 3. "LIRC_STB,LIRC Clock Source Stable Flag\n" "0: LIRC clock is not stable or not enable,1: LIRC clock is stable" bitfld.long 0x0 2. "PLL_STB,PLL Clock Source Stable Flag\n" "0: PLL clock is not stable or not enable,1: PLL clock is stable" newline bitfld.long 0x0 1. "LXT_STB,LEXT Clock Source Stable Flag\n" "0: LXT clock is not stable or not enable,1: LXT clock is stable" bitfld.long 0x0 0. "HXT_STB,HEXT Clock Source Stable Flag\n" "0: HXT clock is not stable or not enable,1: HXT clock is stable" group.long 0x10++0x1B line.long 0x0 "CLKSEL0,Clock Source Select Control Register 0" bitfld.long 0x0 0.--2. "HCLK_S,HCLK Clock Source Selection\n" "0,1,2,3,4,5,6,7" line.long 0x4 "CLKSEL1,Clock Source Select Control Register 1" sif (cpuis("NANO1*BN")) bitfld.long 0x4 18. "LCD_S,LCD Clock Source Selection" "0: Clock Source from LXT,1: Reserved" endif bitfld.long 0x4 12.--14. "TMR1_S,TIMER 1 Clock Source Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "TMR0_S,TIMER 0 Clock Source Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "PWM0_CH23_S,PWM0 Channel 2 And Channel 3 Clock Source Selection\n" "0,1,2,3" newline bitfld.long 0x4 4.--5. "PWM0_CH01_S,PWM0 Channel 0 And Channel 1 Clock Source Selection\n" "0,1,2,3" bitfld.long 0x4 2.--3. "ADC_S,ADC Clock Source Selection\n" "0,1,2,3" newline bitfld.long 0x4 0.--1. "UART_S,UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)\n" "0,1,2,3" line.long 0x8 "CLKSEL2,Clock Source Select Control Register 2" sif (cpuis("NANO1*BN")) bitfld.long 0x8 22. "SPI2_S,SPI2 Clock Source Selection" "0: PLL,1: HCLK" bitfld.long 0x8 21. "SPI1_S,SPI1 Clock Source Selection" "0: PLL,1: HCLK" newline bitfld.long 0x8 20. "SPI0_S,SPI0 Clock Source Selection" "0: PLL,1: HCLK" endif bitfld.long 0x8 18.--19. "SC_S,SC Clock Source Selection\n" "0,1,2,3" newline bitfld.long 0x8 16.--17. "I2S_S,I2S Clock Source Selection\n" "0,1,2,3" bitfld.long 0x8 12.--14. "TMR3_S,TIMER 3 Clock Source Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "TMR2_S,TIMER 2 Clock Source Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--7. "PWM1_CH23_S,PWM1 Channel 2 And Channel 2 Clock Source Selection\n" "0,1,2,3" newline bitfld.long 0x8 4.--5. "PWM1_CH01_S,PWM1 Channel 0 And Channel 1 Clock Source Selection\n" "0,1,2,3" bitfld.long 0x8 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\n" "0,1,2,3" line.long 0xC "CLKDIV0,Clock Divider Number Register 0" hexmask.long.byte 0xC 28.--31. 1. "SC0_N,SC 0 Clock Divide Number From SC 0 Clock Source\n" hexmask.long.byte 0xC 16.--23. 1. "ADC_N,ADC Clock Divide Number From ADC Clock Source\n" newline hexmask.long.byte 0xC 12.--15. 1. "I2S_N,I2S Clock Divide Number From I2S Clock Source\n" hexmask.long.byte 0xC 8.--11. 1. "UART_N,UART Clock Divide Number From UART Clock Source\n" newline hexmask.long.byte 0xC 4.--7. 1. "USB_N,USB Clock Divide Number From PLL Clock \n" hexmask.long.byte 0xC 0.--3. 1. "HCLK_N,HCLK Clock Divide Number From HCLK Clock Source\n" line.long 0x10 "CLKDIV1,Clock Divider Number Register 1" sif (cpuis("NANO1*BN")) hexmask.long.byte 0x10 4.--7. 1. "SC2_N,SC 2 clock divide number from SC2 clock source" endif hexmask.long.byte 0x10 0.--3. 1. "SC1_N,SC 1 Clock Divide Number From SC 1 Clock Source\n" line.long 0x14 "PLLCTL,PLL Control Register" bitfld.long 0x14 17. "PLL_SRC,PLL Source Clock Select\n" "0: PLL source clock from HXT,1: PLL source clock from HIRC" bitfld.long 0x14 16. "PD,Power-Down Mode \nIf set the PD_EN(PWRCTL[6]) '1' the PLL will enter Power-down mode too\n" "0: PLL is in normal mode,1: PLL is in power-down mode (default)" newline bitfld.long 0x14 12. "OUT_DV,PLL Output Divider Control Pins \nRefer to the formulas below the table." "0,1" bitfld.long 0x14 8.--9. "IN_DV,PLL Input Divider Control Pins\nRefer to the formulas below the table." "0,1,2,3" newline hexmask.long.byte 0x14 0.--4. 1. "FB_DV,PLL Feedback Divider Control Pins \nRefer to the formulas below the table.\nThe range of FB_DV is from 0 to 63." line.long 0x18 "FRQDIV,Frequency Divider Control Register" bitfld.long 0x18 4. "FDIV_EN,Frequency Divider Enable Bit\n" "0: Frequency Divider Disabled,1: Frequency Divider Enabled" hexmask.long.byte 0x18 0.--3. 1. "FSEL,Divider Output Frequency Selection Bits\nThe formula of output frequency is\nWhere Fin is the input clock frequency Fout is the frequency of divider output clock and N is the 4-bit value of FSEL(FRQDIV[3:0])." sif (cpuis("NANO1*AN")) rgroup.long 0x30++0x3 line.long 0x0 "PD_WK_IS,Power-down Wake-up Interrupt Status Register" bitfld.long 0x0 0. "PD_WK_IS,Wake-Up Interrupt Sstatus In Chip Power-Down Mode\nThis bit indicates that some event resumes chip from Power-down mode \nThe status is set if external interrupts UART GPIO RTC USB SPI Timer WDT and BOD wake-up occurred.\nWrite 1 to.." "0,1" endif sif (cpuis("NANO1*BN")) rgroup.long 0x30++0x3 line.long 0x0 "WK_INTSTS,Wake-up interrupt status" bitfld.long 0x0 0. "PD_WK_IS,Wake-up Interrupt Sstatus in chip Power-down Mode\nThis bit indicates that some event resumes chip from Power-down mode \nThe status is set if external interrupts UART GPIO RTC USB SPI Timer WDT and BOD wake-up occurred.\nWrite 1 to.." "0,1" endif tree.end sif (cpuis("NANO1*BN")) tree "CRC (Cyclic Redundancy Check)" base ad:0x50008E00 group.long 0x0++0x7 line.long 0x0 "CRC_CTL,CRC Control Register" bitfld.long 0x0 30.--31. "CRC_MODE,CRC Polynomial Mode\n" "0,1,2,3" bitfld.long 0x0 28.--29. "CPU_WDLEN,CPU Write Data Length" "0,1,2,3" newline bitfld.long 0x0 27. "CHECKSUM_COM,Checksum Complement" "0: No bit order reverse for CRC checksum,1: 1's complement for CRC checksum" bitfld.long 0x0 26. "WDATA_COM,Write Data Complement" "0: No bit order reverse for CRC write data in,1: 1's complement for CRC write data in" newline bitfld.long 0x0 25. "CHECKSUM_RVS,Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: No bit order reverse for CRC checksum,1: Bit order reverse for CRC checksum" bitfld.long 0x0 24. "WDATA_RVS,Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: No bit order reverse for CRC write data in,1: Bit order reverse for CRC write data in (per byre)" newline bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote1: If this bit assert that indicates the CRC engine operation in CRC DMA mode so don't filled any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed this bit will be cleared automatically.\nNote3: If the bus.." "0: No effect,1: If this bit assert that indicates the CRC engine.." bitfld.long 0x0 1. "CRC_RST,CRC Engine Reset\nNote: When operating in CPU PIO mode setting this bit will reload the initial seed value" "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.." newline bitfld.long 0x0 0. "CRCCEN,CRC Channel Enable\nSetting this bit to 1 enables CRC's operation." "0,1" line.long 0x4 "CRC_DMASAR,CRC DMA Source Address Register" hexmask.long 0x4 0.--31. 1. "CRC_DMASAR,CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote : The source address must be word alignment" group.long 0xC++0x3 line.long 0x0 "CRC_DMABCR,CRC Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "CRC_DMABCR,CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA" rgroup.long 0x14++0x3 line.long 0x0 "CRC_DMACSAR,CRC Current Source Address Register" hexmask.long 0x0 0.--31. 1. "CRC_DMACSAR,CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer is just occurring." rgroup.long 0x1C++0x3 line.long 0x0 "CRC_DMACBCR,CRC Current Transfer Byte Count Register" hexmask.long.word 0x0 0.--15. 1. "CRC_DMACBCR,CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value." group.long 0x20++0x7 line.long 0x0 "CRC_DMAIER,CRC Interrupt Enable Register" bitfld.long 0x0 1. "BLKD_IE,CRC DMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled during CRC DMA..,1: Interrupt generator Enabled during CRC DMA.." bitfld.long 0x0 0. "TABORT_IE,CRC DMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "CRC_DMAISR,CRC Interrupt Status Register" bitfld.long 0x4 1. "BLKD_IF,Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero" "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IF,CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero\nNote: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not. If bus master received ERROR response it means that target.." "0: No bus ERROR response received,1: Bus ERROR response received" group.long 0x80++0x7 line.long 0x0 "CRC_WDATA,CRC Write Data Register" hexmask.long 0x0 0.--31. 1. "CRC_WDATA,CRC Write Data Register" line.long 0x4 "CRC_SEED,CRC Seed Register" hexmask.long 0x4 0.--31. 1. "CRC_SEED,CRC Seed Register\nThis field indicates the CRC seed value." rgroup.long 0x88++0x3 line.long 0x0 "CRC_CHECKSUM,CRC Check Sum Register" hexmask.long 0x0 0.--31. 1. "CRC_CHECKSUM,CRC Checksum Register\nThis field indicates the CRC checksum" tree.end tree "DAC (Digital-to-Analog Controller)" base ad:0x400A0000 group.long 0x0++0xB line.long 0x0 "DAC0_CTL,DAC0 Control Register" hexmask.long.word 0x0 8.--21. 1. "DACPWONSTBCNT,DACPWONSTBCNT\nDAC need 6 us to be stable after DAC is power on from power down state.\nThis fied controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement." bitfld.long 0x0 4.--6. "DACLSEL,DAC Load Selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "DACIE,DAC Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "DACEN,DAC Enable\nNote: When DAC is powered on DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle." "0: Power down DAC,1: Power on DAC" line.long 0x4 "DAC0_DATA,DAC0 Data Register" hexmask.long.word 0x4 0.--11. 1. "DACData,DAC data" line.long 0x8 "DAC0_STS,DAC0 Status Register" bitfld.long 0x8 2. "BUSY,BUSY bit" "0: DAC is not busy,1: DAC is busy" bitfld.long 0x8 1. "DACSTFG,DAC start flag\nNote: this bit is read only." "0: DAC is not start yet,1: DAC has been started" bitfld.long 0x8 0. "DACIFG,DAC Interrupt flag\nNote: This bit is read only." "0: No interrupt pending,1: Interrupt pending" group.long 0x10++0xB line.long 0x0 "DAC1_CTL,DAC1 Control Register" hexmask.long.word 0x0 8.--21. 1. "DACPWONSTBCNT,DACPWONSTBCNT\nDAC need 6 us to be stable after DAC is power on from power down state.\nThis fied controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement." bitfld.long 0x0 4.--6. "DACLSEL,DAC Load Selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "DACIE,DAC Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "DACEN,DAC Enable\nNote: When DAC is powered on DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle." "0: Power down DAC,1: Power on DAC" line.long 0x4 "DAC1_DATA,DAC1 Data Register" hexmask.long.word 0x4 0.--11. 1. "DACData,DAC data" line.long 0x8 "DAC1_STS,DAC1 Status Register" bitfld.long 0x8 2. "BUSY,BUSY bit" "0: DAC is not busy,1: DAC is busy" bitfld.long 0x8 1. "DACSTFG,DAC start flag\nNote: this bit is read only." "0: DAC is not start yet,1: DAC has been started" bitfld.long 0x8 0. "DACIFG,DAC Interrupt flag\nNote: This bit is read only." "0: No interrupt pending,1: Interrupt pending" group.long 0x20++0x3 line.long 0x0 "DAC01_COMCTL,DAC01 Common Control Register" bitfld.long 0x0 9.--10. "REFSEL,Reference Voltage Selection" "0,1,2,3" bitfld.long 0x0 8. "DAC01GRP,Group DAC0 and DAC1." "0: Not grouped,1: Grouped" hexmask.long.byte 0x0 0.--7. 1. "WAITDACCONV,Wait DAC Conversion Complete\nThe DAC needs at least 2 us to settle down every time when each data deliver to DAC which means user cannot update each DACx_data register faster than 2 us; otherwise data will lost. Setting this register can.." tree.end tree "DMA (Direct Memory Access)" base ad:0x50008F00 group.long 0x0++0xB line.long 0x0 "DMA_GCRCSR,DMA Global Control and Status Register" bitfld.long 0x0 24. "CRC_CLK_EN,CRC Controller Clock Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 14. "CLK6_EN,DMA Controller Channel 6 Clock Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 13. "CLK5_EN,DMA Controller Channel 5 Clock Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 12. "CLK4_EN,DMA Controller Channel 4 Clock Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "CLK3_EN,DMA Controller Channel 3 Clock Enable Control" "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "CLK2_EN,DMA Controller Channel 2 Clock Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 9. "CLK1_EN,DMA Controller Channel 1 Clock Enable Control" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "CLK0_EN,DMA Controller Channel 0 Clock Enable Control" "0: Disabled,1: Enabled" line.long 0x4 "DMA_DSSR0,DMA Service Selection Control Register 0" hexmask.long.byte 0x4 24.--28. 1. "CH3_SEL,Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. Software can configure the peripheral setting by CH3_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL." hexmask.long.byte 0x4 16.--20. 1. "CH2_SEL,Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. Software can configure the peripheral setting by CH2_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL." hexmask.long.byte 0x4 8.--12. 1. "CH1_SEL,Channel 1 Selection" line.long 0x8 "DMA_DSSR1,DMA Service Selection Control Register 1" hexmask.long.byte 0x8 16.--20. 1. "CH6_SEL,Channel 6 Selection \nThis filed defines which peripheral is connected to PDMA channel 6. Software can configure the peripheral setting by CH6_SEL. The channel configuration is the same as CH4_SEL field. Please refer to the explanation of CH4_SEL." hexmask.long.byte 0x8 8.--12. 1. "CH5_SEL,Channel 5 Selection \nThis filed defines which peripheral is connected to PDMA channel 5. Software can configure the peripheral setting by CH5_SEL. The channel configuration is the same as CH4_SEL field. Please refer to the explanation of CH4_SEL." hexmask.long.byte 0x8 0.--4. 1. "CH4_SEL,Channel 4 Selection" rgroup.long 0xC++0x3 line.long 0x0 "DMA_GCRISR,DMA Global Interrupt Status Register" bitfld.long 0x0 16. "CRC_INTR,Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller\nNote: This bit is read only" "0,1" bitfld.long 0x0 6. "INTR6,Interrupt Pin Status Of Channel 6 (Read Only)\nThis bit is the Interrupt pin status of DMA channel4.\nNote: This bit is read only" "0,1" bitfld.long 0x0 5. "INTR5,Interrupt Pin Status Of Channel 5 (Read Only)\nThis bit is the Interrupt pin status of DMA channel4.\nNote: This bit is read only" "0,1" bitfld.long 0x0 4. "INTR4,Interrupt Pin Status Of Channel 4 (Read Only)\nThis bit is the Interrupt pin status of DMA channel4.\nNote: This bit is read only" "0,1" bitfld.long 0x0 3. "INTR3,Interrupt Pin Status Of Channel 3 (Read Only)\nThis bit is the Interrupt pin status of DMA channel3.\nNote: This bit is read only" "0,1" newline bitfld.long 0x0 2. "INTR2,Interrupt Pin Status Of Channel 2 (Read Only)\nThis bit is the Interrupt pin status of DMA channel2.\nNote: This bit is read only" "0,1" bitfld.long 0x0 1. "INTR1,Interrupt Pin Status Of Channel 1 (Read Only)\nThis bit is the Interrupt pin status of DMA channel1.\nNote: This bit is read only" "0,1" bitfld.long 0x0 0. "INTR0,Interrupt Pin Status Of Channel 0 (Read Only)\nThis bit is the Interrupt pin status of DMA channel0.\nNote: This bit is read only" "0,1" tree.end tree "LCD (LCD Display Driver)" base ad:0x400B0000 group.long 0x0++0x37 line.long 0x0 "LCD_CTL,LCD Control Register" bitfld.long 0x0 9. "PDINT_EN,Power Down Interrupt Enable\nIf the power down request is triggered from system management LCD controller will execute the frame completely to avoid the DC component. When the frame is executed completely the LCD power down interrupt signal is.." "0: Power Down Interrupt Disabled,1: Power Down Interrupt Enabled" bitfld.long 0x0 8. "PDDISP_EN,Power Down Display Enable\nThe LCD can be programmed to be displayed or not be displayed at power down state by PDDISP_EN setting." "0: LCD display Disabled ( LCD unlit) at power down..,1: LCD display Enabled (LCD keeps the display) at.." newline bitfld.long 0x0 7. "BLINK,LCD Blinking Enable" "0: Blinking Disabled,1: Blinking Enabled" bitfld.long 0x0 4.--6. "FREQ,LCD Frequency Selection" "0: LCDCLK Divided by 32,1: LCDCLK Divided by 64,?,?,?,?,?,?" newline bitfld.long 0x0 1.--3. "MUX,Mux select" "0: Static,1: 1/2 duty,?,?,?,?,?,?" bitfld.long 0x0 0. "EN,LCD Enable" "0: LCD controller operation Disabled,1: LCD controller operation Enabled" line.long 0x4 "LCD_DISPCTL,LCD Display Control Register" bitfld.long 0x4 11.--13. "CPUMP_FREQ,Charge Pump Frequency Selection" "0: LCDCLK,1: LCDCLK/2,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "CPUMP_VOL_SET,Charge Pump Voltage Selection" "0: 2.7V,1: 2.8V,?,?,?,?,?,?" newline bitfld.long 0x4 6. "BV_SEL,Bias Voltage Type Selection\n0: Reserved\nNote: The external resistor ladder should be connected to the V1 pin V2 pin V3 pin and VSS. The VLCD pin should also be connected to VDD." "0: Reserved\nNote: The external resistor ladder..,1: R-Type bias mode. Bias voltage source from.." bitfld.long 0x4 4. "IBRL_EN,Internal Bias Reference ladder Enable" "0: Bias reference ladder Disabled,1: Bias reference ladder Dnabled" newline bitfld.long 0x4 1.--2. "BIAS_SEL,Bias Selection" "0: Static,1: 1/2 Bias,?,?" bitfld.long 0x4 0. "CPUMP_EN,Charge Pump Enable" "0: Disabled,1: Enabled" line.long 0x8 "LCD_MEM_0,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x8 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x8 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x8 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x8 0.--5. 1. "SEG_0_4xdata," line.long 0xC "LCD_MEM_1,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0xC 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0xC 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0xC 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0xC 0.--5. 1. "SEG_0_4xdata," line.long 0x10 "LCD_MEM_2,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x10 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x10 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x10 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x10 0.--5. 1. "SEG_0_4xdata," line.long 0x14 "LCD_MEM_3,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x14 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x14 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x14 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x14 0.--5. 1. "SEG_0_4xdata," line.long 0x18 "LCD_MEM_4,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x18 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x18 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x18 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x18 0.--5. 1. "SEG_0_4xdata," line.long 0x1C "LCD_MEM_5,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x1C 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x1C 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x1C 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x1C 0.--5. 1. "SEG_0_4xdata," line.long 0x20 "LCD_MEM_6,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x20 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x20 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x20 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x20 0.--5. 1. "SEG_0_4xdata," line.long 0x24 "LCD_MEM_7,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x24 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x24 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x24 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x24 0.--5. 1. "SEG_0_4xdata," line.long 0x28 "LCD_MEM_8,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x28 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x28 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x28 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x28 0.--5. 1. "SEG_0_4xdata," line.long 0x2C "LCD_MEM_9,LCD SEG3 ~ SEG0 data" hexmask.long.byte 0x2C 24.--29. 1. "SEG_3_4xdata," hexmask.long.byte 0x2C 16.--21. 1. "SEG_2_4xdata," newline hexmask.long.byte 0x2C 8.--14. 1. "SEG_1_4xdata," hexmask.long.byte 0x2C 0.--5. 1. "SEG_0_4xdata," line.long 0x30 "LCD_FCR,LCD frame counter control register" hexmask.long.byte 0x30 4.--9. 1. "FCV,Frame Counter Top Value\nThese 6 bits contain the top value of the Frame counter." bitfld.long 0x30 2.--3. "PRESCL,Frame Counter Pre-scaler Value" "0: CLKframe/1,1: CLKframe/2,?,?" newline bitfld.long 0x30 1. "FCINTEN,LCD Frame Counter Interrupt Enable" "0: Frame counter interrupt Disabled,1: Frame counter interrupt Enabled" bitfld.long 0x30 0. "FCEN,LCD Frame Counter Enable" "0: Disabled,1: Enabled" line.long 0x34 "LCD_FCSTS,LCD frame counter status" bitfld.long 0x34 1. "PDSTS,Power-down Interrupt Status" "0: LCD power down is not ready,1: LCD power down is ready" bitfld.long 0x34 0. "FCSTS,LCD Frame Counter Status" "0: Frame counter value does not reach FCV (Frame..,1: Frame counter value reaches FCV (Frame Count TOP.." tree.end tree "PDMA (Peripheral Direct Memory Access)" base ad:0x0 tree "PDMA_CH1" base ad:0x50008100 group.long 0x0++0xF line.long 0x0 "PDMA_CSR1,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,TRIG_EN\nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trig again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection" "0,1,2,3" newline bitfld.long 0x0 12. "TO_EN,Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero the TO_IS will be set." "0: PDMA internal Timer Disabled,1: PDMA internal Timer Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to '1' enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "PDMA_SAR1,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR1,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR1,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR1,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring." line.long 0x4 "PDMA_CDAR1,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring." line.long 0x8 "PDMA_CBCR1,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address) " group.long 0x20++0xB line.long 0x0 "PDMA_IER1,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR1,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to itself." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to itself." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to itself.\nNote2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not if bus master received occur it means that target.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to itself" line.long 0x8 "PDMA_TCR1,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register clearing and restart counting when complete each peripheral request service." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF1,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer." tree.end tree "PDMA_CH2" base ad:0x50008200 group.long 0x0++0xF line.long 0x0 "PDMA_CSR2,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,TRIG_EN\nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trig again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection" "0,1,2,3" newline bitfld.long 0x0 12. "TO_EN,Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero the TO_IS will be set." "0: PDMA internal Timer Disabled,1: PDMA internal Timer Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to '1' enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "PDMA_SAR2,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR2,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR2,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR2,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring." line.long 0x4 "PDMA_CDAR2,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring." line.long 0x8 "PDMA_CBCR2,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address) " group.long 0x20++0xB line.long 0x0 "PDMA_IER2,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR2,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to itself." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to itself." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to itself.\nNote2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not if bus master received occur it means that target.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to itself" line.long 0x8 "PDMA_TCR2,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register clearing and restart counting when complete each peripheral request service." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF2,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer." tree.end tree "PDMA_CH3" base ad:0x50008300 group.long 0x0++0xF line.long 0x0 "PDMA_CSR3,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,TRIG_EN\nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trig again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection" "0,1,2,3" newline bitfld.long 0x0 12. "TO_EN,Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero the TO_IS will be set." "0: PDMA internal Timer Disabled,1: PDMA internal Timer Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to '1' enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "PDMA_SAR3,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR3,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR3,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR3,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring." line.long 0x4 "PDMA_CDAR3,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring." line.long 0x8 "PDMA_CBCR3,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address) " group.long 0x20++0xB line.long 0x0 "PDMA_IER3,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR3,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to itself." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to itself." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to itself.\nNote2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not if bus master received occur it means that target.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to itself" line.long 0x8 "PDMA_TCR3,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register clearing and restart counting when complete each peripheral request service." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF3,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer." tree.end tree "PDMA_CH4" base ad:0x50008400 group.long 0x0++0xF line.long 0x0 "PDMA_CSR4,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,TRIG_EN\nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trig again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection" "0,1,2,3" newline bitfld.long 0x0 12. "TO_EN,Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero the TO_IS will be set." "0: PDMA internal Timer Disabled,1: PDMA internal Timer Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to '1' enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "PDMA_SAR4,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR4,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR4,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR4,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring." line.long 0x4 "PDMA_CDAR4,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring." line.long 0x8 "PDMA_CBCR4,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address) " group.long 0x20++0xB line.long 0x0 "PDMA_IER4,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR4,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to itself." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to itself." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to itself.\nNote2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not if bus master received occur it means that target.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to itself" line.long 0x8 "PDMA_TCR4,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register clearing and restart counting when complete each peripheral request service." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF4,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer." tree.end tree "PDMA_CH5" base ad:0x50008500 group.long 0x0++0xF line.long 0x0 "PDMA_CSR5,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,TRIG_EN\nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trig again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection" "0,1,2,3" newline bitfld.long 0x0 12. "TO_EN,Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero the TO_IS will be set." "0: PDMA internal Timer Disabled,1: PDMA internal Timer Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to '1' enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "PDMA_SAR5,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR5,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR5,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR5,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring." line.long 0x4 "PDMA_CDAR5,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring." line.long 0x8 "PDMA_CBCR5,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address) " group.long 0x20++0xB line.long 0x0 "PDMA_IER5,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR5,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to itself." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to itself." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to itself.\nNote2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not if bus master received occur it means that target.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to itself" line.long 0x8 "PDMA_TCR5,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register clearing and restart counting when complete each peripheral request service." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF5,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer." tree.end tree "PDMA_CH6" base ad:0x50008600 group.long 0x0++0xF line.long 0x0 "PDMA_CSR6,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,TRIG_EN\nNote1: When PDMA transfer completed this bit will be cleared automatically.\nNote2: If the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trig again." "0: No effect,1: When PDMA transfer completed" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection" "0,1,2,3" newline bitfld.long 0x0 12. "TO_EN,Time-out Enable\nThis bit will enable PDMA internal Timer. While Timer is counted to zero the TO_IS will be set." "0: PDMA internal Timer Disabled,1: PDMA internal Timer Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to '1' enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "PDMA_SAR6,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR6,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR6,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count of PDMA." rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR6,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer is just occurring." line.long 0x4 "PDMA_CDAR6,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer is just occurring." line.long 0x8 "PDMA_CBCR6,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: These fields will be changed when PDMA finish data transfer (data transfer to destination address) " group.long 0x20++0xB line.long 0x0 "PDMA_IER6,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR6,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to itself." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to itself." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to itself.\nNote2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not if bus master received occur it means that target.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to itself" line.long 0x8 "PDMA_TCR6,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Register\nEach PDMA controller contains an internal counter. The internal counter starts counting when setting PDMA_CSRx [TO_EN] register clearing and restart counting when complete each peripheral request service." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF6,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 words internal buffer." tree.end tree.end tree "WWDT (Window Watchdog Timer)" base ad:0x40004100 wgroup.long 0x0++0x3 line.long 0x0 "WWDTRLD,Window Watchdog Timer Reload Counter Register" hexmask.long 0x0 0.--31. 1. "WWDTRLD,Window Watchdog Timer Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP. If SW writes WWDTRLD.." group.long 0x4++0xB line.long 0x0 "WWDTCR,Window Watchdog Timer Control Register" bitfld.long 0x0 31. "DBGEN,WWDT Debug Enable" "0: WWDT stopped count if system is in Debug mode,1: WWDT still counted even system is in Debug mode" hexmask.long.byte 0x0 16.--21. 1. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP. If SW writes WWDTRLD when WWDT counter value larger than WWCMP WWDT will generate.." hexmask.long.byte 0x0 8.--11. 1. "PERIODSEL,WWDT Pre-scale Period Select\nThese three bits select the pre-scale for the WWDT counter period.\nPlease refer to Table 5 17" bitfld.long 0x0 0. "WWDTEN,Window Watchdog Enable\nSet this bit to enable Window Watchdog timer." "0: Window Watchdog timer function Disabled,1: Window Watchdog timer function Enabled" line.long 0x4 "WWDT_IER,Window Watchdog Timer Interrupt Enable Register" bitfld.long 0x4 0. "WWDTIE,WWDT Interrupt Enable\nSetting this bit will enable the Watchdog timer interrupt function." "0: Watchdog timer interrupt function Disabled,1: Watchdog timer interrupt function Enabled" line.long 0x8 "WWDTSTS,Window Watchdog Timer Status Register" bitfld.long 0x8 1. "WWDTRF,WWDT Reset Flag\nWhen WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0." "0,1" bitfld.long 0x8 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nWhen WWCMP match the WWDT counter then this bit is set to 1. This bit will be cleared by software write 1 to this bit." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "WWDTVAL,Window Watchdog Timer Counter Value Register" hexmask.long.byte 0x0 0.--5. 1. "WWDTVAL,WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only" tree.end endif tree "EBI (External Bus Interface)" base ad:0x50010000 group.long 0x0++0x7 line.long 0x0 "EBICON,External Bus Interface General Control Register" bitfld.long 0x0 16.--18. "ExttALE,Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n" "0,1,2,3,4,5,6,7" sif (cpuis("NANO1*AN")) bitfld.long 0x0 11. "MCLKEN,External Clock Enable Control\nThis bit control if EBI generates the clock to external device.\nIf external device is a synchronous device it's necessary to set this bit high to enable EBI generating clock to external device.\n" "?,1: Enabled EBI to generate clock to external device" newline bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock is controlled by MCLKDIV as shown in the following table.\n" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/1,7: HCLK/1" endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 11. "MCLKEN,External Clock Enable\nThis bit control if EBI generates the clock to external device.\nIf external device is a synchronous device it's necessary to set this bit high to enable EBI generating clock to external device.\nIf the external device is.." "0: EBI Disabled to generate clock to external device,1: EBI Enabled to generate clock to external device" newline bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider" "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 1. "ExtBW16,EBI Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n" "0: EBI data width is 8-bit,1: EBI data width is 16-bit" newline bitfld.long 0x0 0. "ExtEN,EBI Enable Control\nThis bit is the functional enable bit for EBI.\n" "0: EBI function is disabled,1: EBI function is enabled" line.long 0x4 "EXTIME,External Bus Interface Timing Control Register" hexmask.long.byte 0x4 24.--27. 1. "ExtIR2R,Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read idle state is inserted and nCS return to high if ExtIR2R is not zero.\n" hexmask.long.byte 0x4 16.--19. 1. "ExtIR2W,Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write idle state is inserted and nCS return to high if ExtIR2W is not zero.\n" newline hexmask.long.byte 0x4 12.--15. 1. "ExtIW2X,Idle State Cycle After Write\nWhen write action is finish idle state is inserted and nCS return to high if ExtIW2X is not zero.\n" bitfld.long 0x4 8.--10. "ExttAHD,EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).\n" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "ExttACC,EBI Data Access Time\nExttACC define data access time (tACC).\n" tree.end tree "FMC (Flash Memory Controller)" base ad:0x5000C000 group.long 0x0++0x13 line.long 0x0 "ISPCON,ISP Control Register" bitfld.long 0x0 12.--14. "ET,Flash Erase Time (Write-Protection Bits)\n" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "PT,Flash Program Time (Write-Protection Bits)\n" "0,1,2,3,4,5,6,7" newline sif (cpuis("NANO1*AN")) bitfld.long 0x0 7. "SWRST,Software Reset\nWriting 1 to this bit to start software reset. \nIt is cleared by hardware after reset is finished." "0,1" endif bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed when the MCU is running in.." "0,1" newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 5. "LDUEN,LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit." "0: LDROM cannot be updated,1: LDROM can be updated when the chip runs in APROM" bitfld.long 0x0 4. "CFGUEN,Enable Config-bits Update by ISP (Write-protection Bit)" "0: Disabling ISP can update config-bits,1: Enabling ISP can update config-bits" newline bitfld.long 0x0 3. "APUEN,APROM Update Enable (Write-protection Bit)\nAPROM update enable bit." "0: APROM can not be updated,1: APROM can be updated when the MCU runs in APROM" endif bitfld.long 0x0 1. "BS,Boot Select (Write-Protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the.." "0: boot from APROM,1: boot from LDROM" newline bitfld.long 0x0 0. "ISPEN,ISP Enable (Erite-Protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled" line.long 0x4 "ISPADR,ISP Address Register" hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address\nThis chip supports word program only. ISPADR[1:0] must be kept 00b for ISP operation." line.long 0x8 "ISPDAT,ISP Data Register" hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation." line.long 0xC "ISPCMD,ISP Command Register" bitfld.long 0xC 5. "FOEN,ISP Command\nThe ISP command table is shown as follows." "0,1" bitfld.long 0xC 4. "FCEN,ISP Command\nThe ISP command table is shown as follows." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "FCTRL,ISP Command\n" line.long 0x10 "ISPTRG,ISP Trigger Control Register" bitfld.long 0x10 0. "ISPGO,ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n" "0: ISP operation is finished,1: ISP is on going" rgroup.long 0x14++0x3 line.long 0x0 "DFBADR,Data Flash Base Address" hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes it is mandatory to keep bit 8-0 as 0." group.long 0x40++0x3 line.long 0x0 "ISPSTA,ISP Status Register" sif (cpuis("NANO1*AN")) hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current system memory space 0x0000_0000~0x0000_01FF is mapped to flash memory page with base address (VECMAP[11:0] 9). When chip is reset the remapping address (VECMAP) is clear to CONFIG0 (CBS).." endif sif (cpuis("NANO1*BN")) hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VEC}AP[11:0] '000000000b'} ~ {VEC}AP[11:0] '111111111b'}\n Read Only" newline endif bitfld.long 0x0 6. "ISPFF,ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself. \n(3) CONFIG is erased/programmed when the MCU is running in APROM.\n(4) Destination.." "0,1" bitfld.long 0x0 1.--2. "CBS,Config Boot Selection Status\n" "0,1,2,3" newline bitfld.long 0x0 0. "ISPBUSY,ISP BUSY\n\nRead Only" "0: ISP operation is finished,1: ISP operation is busy" tree.end tree "GCR (System Management Control Registers)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "PDID,Part Device Identification Number Register" hexmask.long 0x0 0.--31. 1. "PDID,Part Device ID \nThis register reflects device part number code. Software can read this register to identify which device is used." group.long 0x4++0xB line.long 0x0 "RST_SRC,System Reset Source Register" bitfld.long 0x0 7. "RSTS_CPU,The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) '1' To Rest Cortex-M0 CPU Kernel And Flash Memory Controller (FMC)\nThis bit is cleared by writing 1 to itself." "0: No reset from CPU,1: The Cortex-M0 CPU kernel and FMC are reset by.." bitfld.long 0x0 5. "RSTS_SYS,The RSTS_SYS Flag Is Set By The 'Reset Signal' From The Cortex_M0 Kernel To Indicate The Previous Reset Source\nThis bit is cleared by writing 1 to itself." "0: No reset from Cortex_M0,1: The Cortex_M0 had issued the reset signal to.." newline bitfld.long 0x0 4. "RSTS_BOD,The RSTS_BOD Flag Is Set By The 'Reset Signal' From The Brown-Out-Detected Module To Indicate The Previous Reset Source\nThis bit is cleared by writing 1 to itself." "0: No reset from BOD,1: The Brown-Out-Detected module had issued the.." bitfld.long 0x0 2. "RSTS_WDT,The RSTS_WDT Flag Is Set By The 'Reset Signal' From The Watch-Dog Timer Module To Indicate The Previous Reset Source\nThis bit is cleared by writing 1 to itself." "0: No reset from Watch-Dog Timer,1: The Watch-Dog Timer module had issued the reset.." newline bitfld.long 0x0 1. "RSTS_PAD,The RSTS_PAD Flag Is Set By The 'Reset Signal' From The /RESET Pin To Indicate The Previous Reset Source\nThis bit is cleared by writing 1 to itself." "0: No reset from /RESET pin,1: The /RESET pin had issued the reset signal to.." bitfld.long 0x0 0. "RSTS_POR,The RSTS_POR Flag Is Set By The 'Reset Signal' From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRST_CTL1[0]) To Indicate The Previous Reset Source\nThis bit is cleared by writing 1 to itself." "0: No reset from POR or CHIP_RST,1: The Power-On Reset (POR) or CHIP_RST had issued.." line.long 0x4 "IPRST_CTL1,IP Reset Control Resister 1" bitfld.long 0x4 3. "EBI_RST,EBI Controller Reset\nThis is a protected register. Please refer to open lock sequence to program it.\nSet this bit '1' will generate a reset signal to the EBI. SW needs to set this bit to low to release reset signal.\n" "0: Normal operation,1: EBI IP reset" bitfld.long 0x4 2. "DMA_RST,DMA Controller Reset\nThis is a protected register. Please refer to open lock sequence to program it.\nSet this bit '1' will generate a reset signal to the DMA. SW needs to set this bit to low to release reset signal.\n" "0: Normal operation,1: DMA IP reset" newline bitfld.long 0x4 1. "CPU_RST,CPU Kernel One Shot Reset \nThis is a protected register. Please refer to open lock sequence to program it.\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC) and this bit will automatically return to '0' after the.." "0: Normal,1: Reset CPU" bitfld.long 0x4 0. "CHIP_RST,CHIP One Shot Reset \nThis is a protected register. Please refer to open lock sequence to program it.\nSetting this bit will reset the whole chip including CPU kernel and all peripherals like power-on reset and this bit will automatically.." "0: Normal,1: Reset CHIP" line.long 0x8 "IPRST_CTL2,IP Reset Control Resister 2" bitfld.long 0x8 31. "SC1_RST,SC 1 Controller Reset\n" "0: SC block normal operation,1: SC block reset" bitfld.long 0x8 30. "SC0_RST,SC 0 Controller Reset\n" "0: SC block normal operation,1: SC block reset" newline bitfld.long 0x8 29. "I2S_RST,I2S Controller Reset\n" "0: I2S block normal operation,1: I2S block reset" bitfld.long 0x8 28. "ADC_RST,ADC Controller Reset\n" "0: ADC block normal operation,1: ADC block reset" newline bitfld.long 0x8 27. "USBD_RST,USB Device Controller Reset\n" "0: USB block normal operation,1: USB block reset" sif (cpuis("NANO1*BN")) bitfld.long 0x8 26. "LCD_RST,LCD Controller Reset" "0: LCD block normal operation,1: LCD block reset" newline bitfld.long 0x8 25. "DAC_RST,DAC Controller Reset" "0: DAC block normal operation,1: DAC block reset" endif bitfld.long 0x8 21. "PWM1_RST,PWM1 Controller Reset\n" "0: PWM1 block normal operation,1: PWM1 block reset" newline bitfld.long 0x8 20. "PWM0_RST,PWM0 Controller Reset\n" "0: PWM0 block normal operation,1: PWM0 block reset" bitfld.long 0x8 17. "UART1_RST,UART1 Controller Reset\n" "0: UART1 normal operation,1: UART1 block reset" newline bitfld.long 0x8 16. "UART0_RST,UART0 Controller Reset\n" "0: UART0 normal operation,1: UART0 block reset" bitfld.long 0x8 14. "SPI2_RST,SPI2 Controller Reset\n" "0: SPI2 normal operation,1: SPI2 block reset" newline bitfld.long 0x8 13. "SPI1_RST,SPI1 Controller Reset\n" "0: SPI1 normal operation,1: SPI1 block reset" bitfld.long 0x8 12. "SPI0_RST,SPI0 Controller Reset\n" "0: SPI0 block normal operation,1: SPI0 block reset" newline bitfld.long 0x8 9. "I2C1_RST,I2C1 Controller Reset\n" "0: I2C1 block normal operation,1: I2C1 block reset" bitfld.long 0x8 8. "I2C0_RST,I2C0 Controller Reset\n" "0: I2C0 normal operation,1: I2C0 block reset" newline sif (cpuis("NANO1*BN")) bitfld.long 0x8 7. "SC2_RST,SmartCard 2 Controller Reset" "0: SmartCard 2 block normal operation,1: SmartCard 2 block reset" endif bitfld.long 0x8 5. "TMR3_RST,Timer3 Controller Reset\n" "0: Timer3 normal operation,1: Timer3 block reset" newline bitfld.long 0x8 4. "TMR2_RST,Timer2 Controller Reset\n" "0: Timer2 normal operation,1: Timer2 block reset" bitfld.long 0x8 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 normal operation,1: Timer1 block reset" newline bitfld.long 0x8 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 normal operation,1: Timer0 reset" bitfld.long 0x8 1. "GPIO_RST,GPIO Controller Reset\n" "0: GPIO normal operation,1: GPIO reset" sif (cpuis("NANO1*AN")) group.long 0x10++0x3 line.long 0x0 "CPR,Chip Performance Register" bitfld.long 0x0 0. "HPE,High Performance Enable\nThis bit is used to control chip operation performance.\nWhen this bit set internal RAM and GPIO access is working with zero wait state Flash controller will predict next address more efficiently \n" "0: Chip operation at normal mode,1: Chip operation at high performance mode" group.long 0x6C++0x3 line.long 0x0 "VREFCTL,Voltage Reference Control Register" bitfld.long 0x0 3. "EXT_MODE,Regulator External Mode\nThis is a protected register. Please refer to open lock sequence to program it.\nUsers can output regulator output voltage in Vref pin if EXT_MODE is high.\n" "0: No connection with external VREF pin,1: Connet to external VREF pin. Connect a 1uF to.." bitfld.long 0x0 2. "SEL25,Regulator Output Voltage Selection\nSelect internal reference voltage level.\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: 1.5V,1: 2.5V" newline bitfld.long 0x0 1. "REG_EN,Regulator Enable\nEnable internal 1.5V or 2.5V reference voltage.\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: Disabled,1: Enabled" bitfld.long 0x0 0. "BGP_EN,Band-Gap Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5V or 2.5V reference voltage.\n" "0: Disabled,1: Enabled" endif group.long 0x20++0x3 line.long 0x0 "TEMPCTL,Temperature Sensor Control Register" bitfld.long 0x0 0. "VTEMP_EN,Temperature Sensor Enable\n" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled" group.long 0x30++0x2B line.long 0x0 "PA_L_MFP,Port A Low Byte Multiple Function Control Register" bitfld.long 0x0 28.--30. "PA7_MFP,PA.7 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "PA6_MFP,PA.6 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "PA5_MFP,PA.5 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "PA4_MFP,PA.4 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PA3_MFP,PA.3 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "PA2_MFP,PA.2 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "PA1_MFP,PA.1 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "PA0_MFP,PA.0 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x4 "PA_H_MFP,Port A High Byte Multiple Function Control Register" bitfld.long 0x4 28.--30. "PA15_MFP,PA.15 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PA14_MFP,PA.14 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "PA13_MFP,PA.13 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PA12_MFP,PA.12 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "PA11_MFP,PA.11 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "PA10_MFP,PA.10 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "PA9_MFP,PA.9 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "PA8_MFP,PA.8 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x8 "PB_L_MFP,Port B Low Byte Multiple Function Control Register" bitfld.long 0x8 28.--30. "PB7_MFP,PB.7 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "PB6_MFP,PB.6 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "PB5_MFP,PB.5 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "PB4_MFP,PB.4 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--14. "PB3_MFP,PB.3 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "PB2_MFP,PB.2 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "PB1_MFP,PB.1 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "PB0_MFP,PB.0 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0xC "PB_H_MFP,Port B High Byte Multiple Function Control Register" bitfld.long 0xC 28.--30. "PB15_MFP,PB.15 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "PB14_MFP,PB.14 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "PB13_MFP,PB.13 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "PB12_MFP,PB.12 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PB11_MFP,PB.11 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "PB10_MFP,PB.10 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "PB9_MFP,PB.9 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "PB8_MFP,PB.8 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x10 "PC_L_MFP,Port C Low Byte Multiple Function Control Register" bitfld.long 0x10 28.--30. "PC7_MFP,PC.7 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PC6_MFP,PC.6 Pin Function Selection\n\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "PC5_MFP,PC.5 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PC4_MFP,PC.4 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PC3_MFP,PC.3 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PC2_MFP,PC.2 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "PC1_MFP,PC.1 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PC0_MFP,PC.0 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x14 "PC_H_MFP,Port C High Byte Multiple Function Control Register" bitfld.long 0x14 28.--30. "PC15_MFP,PC.15 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PC14_MFP,PC.14 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "PC13_MFP,PC.13 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PC12_MFP,PC.12 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PC11_MFP,PC.11 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PC10_MFP,PC.10 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "PC9_MFP,PC.9 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PC8_MFP,PC.8 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x18 "PD_L_MFP,Port D Low Byte Multiple Function Control Register" bitfld.long 0x18 28.--30. "PD7_MFP,PD.7 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PD6_MFP,PD.6 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "PD5_MFP,PD.5 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PD4_MFP,PD.4 Pin Function Selection\n\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PD3_MFP,PD.3 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PD2_MFP,PD.2 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "PD1_MFP,PD.1 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PD0_MFP,PD.0 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x1C "PD_H_MFP,Port D High Byte Multiple Function Control Register" bitfld.long 0x1C 28.--30. "PD15_MFP,PD.15 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PD14_MFP,PD.14 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "PD13_MFP,PD.13 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PD12_MFP,PD.12 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PD11_MFP,PD.11 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PD10_MFP,PD.10 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "PD9_MFP,PD.9 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PD8_MFP,PD.8 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x20 "PE_L_MFP,Port E Low Byte Multiple Function Control Register" bitfld.long 0x20 28.--30. "PE7_MFP,PE.7 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x20 24.--26. "PE6_MFP,PE.6 Pin Function Selection\nAll setting : GPIOE[6]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "PE5_MFP,PE.5 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x20 16.--18. "PE4_MFP,PE.4 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 12.--14. "PE3_MFP,PE.3 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "PE2_MFP,PE.2 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 4.--6. "PE1_MFP,PE.1 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "PE0_MFP,PE.0 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x24 "PE_H_MFP,Port E High Byte Multiple Function Control Register" bitfld.long 0x24 28.--30. "PE15_MFP,PE.15 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x24 24.--26. "PE14_MFP,PE.14 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--22. "PE13_MFP,PE.13 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--18. "PE12_MFP,PE.12 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12.--14. "PE11_MFP,PE.11 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "PE10_MFP,PE.10 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4.--6. "PE9_MFP,PE.9 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--2. "PE8_MFP,PE.8 Pin Function Selection\n" "0,1,2,3,4,5,6,7" line.long 0x28 "PF_L_MFP,Port F Low Byte Multiple Function Control Register" bitfld.long 0x28 20.--22. "PF5_MFP,PF.5 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x28 16.--18. "PF4_MFP,PF.4 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 12.--14. "PF3_MFP,PF.3 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "PF2_MFP,PF.2 Pin Function Selection\n" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 4.--6. "PF1_MFP,PF.1 Pin Function Selection\n" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "PF0_MFP,PF.0 Pin Function Selection\n" "0,1,2,3,4,5,6,7" group.long 0x60++0x7 line.long 0x0 "PORCTL,Power-On-reset Controller Register" hexmask.long.word 0x0 0.--15. 1. "POR_DIS_CODE,Power-On Reset Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the.." line.long 0x4 "BODCTL,Brown-out Detector Control Register" bitfld.long 0x4 10. "BOD25_INT_EN,BOD 2.5 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: Interrupt does not issue when BOD25 occurs,1: Interrupt issues when BOD25 occurs" bitfld.long 0x4 9. "BOD20_INT_EN,BOD 2.0 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: Interrupt does not issue when BOD20 occurs,1: Interrupt issues when BOD20 occurs" newline bitfld.long 0x4 8. "BOD17_INT_EN,BOD 1.7 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: Interrupt does not issue when BOD17 occurs,1: Interrupt issues when BOD17 occurs" bitfld.long 0x4 6. "BOD25_RST_EN,BOD 2.5 V Reset Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19]" "0: Reset does not issue when BOD25 occurs,1: Reset issues when BOD25 occurs" newline bitfld.long 0x4 5. "BOD20_RST_EN,BOD 2.0 V Reset Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19]" "0: Reset does not issue when BOD20 occurs,1: Reset issues when BOD20 occurs" bitfld.long 0x4 4. "BOD17_RST_EN,BOD 1.7 V Reset Enable\n" "0: Reset does not issue when BOD17 occurs,1: Reset issues when BOD17 occurs" newline bitfld.long 0x4 2. "BOD25_EN,Brown-Out Detector 2.5 V Function Enable \nThis is a protected register. Please refer to open lock sequence to program it.\n" "0: Brown-out Detector 2.5 V function Disabled,1: Brown-out Detector 2.5 V function Enabled" bitfld.long 0x4 1. "BOD20_EN,Brown-Out Detector 2.0 V Function Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nBOD20_EN is default on. If SW disables it Brown-out Detector 2.0 V function is not disabled until chip enters power-down.." "0: Brown-out Detector 2.0 V function Disabled,1: Brown-out Detector 2.0 V function Enabled" newline bitfld.long 0x4 0. "BOD17_EN,Brown-Out Detector 1.7V Function Enable \n" "0: Brown-out Detector 1.7V function Disabled,1: Brown-out Detector 1.7V function Enabled" rgroup.long 0x68++0x3 line.long 0x0 "BODSTS,Brown-out Detector Status Register" sif (cpuis("NANO1*BN")) rbitfld.long 0x0 6. "BOD25_rise,Brown-out Detector higher than 2.5V Status\nSetting BOD25_rise high means once the detected voltage is higher than target detected voltage setting (2.5V). Software can write 1 to clear BOD25_rise." "0,1" rbitfld.long 0x0 5. "BOD20_rise,Brown-out Detector higher than 2.0V Status\nSetting BOD20_rise high means once the detected voltage is higher than target detected voltage setting (2.0V). Software can write 1 to clear BOD20_rise" "0,1" newline rbitfld.long 0x0 4. "BOD17_rise,Brown-out Detector higher than 1.7V Status\nSetting BOD17_rise high means once the detected voltage is higher than target detected voltage setting (1.7V). Software can write 1 to clear BOD17_rise" "0,1" rbitfld.long 0x0 3. "BOD25_drop,Brown-out Detector lower than 2.5V Status\nSetting BOD25_drop high means once the detected voltage is lower than target detected voltage setting (2.5V). Software can write 1 to clear BOD25_drop" "0,1" newline rbitfld.long 0x0 2. "BOD20_drop,Brown-out Detector lower than 2.0V Status\nSetting BOD20_drop high means once the detected voltage is lower than target detected voltage setting (2.0V). Software can write 1 to clear BOD20_drop" "0,1" rbitfld.long 0x0 1. "BOD17_drop,Brown-out Detector lower than 1.7V Status\nSetting BOD17_drop high means once the detected voltage is lower than target detected voltage setting (1.7V). Software can write 1 to clear BOD17_drop" "0,1" newline endif sif (cpuis("NANO1*AN")) rbitfld.long 0x0 3. "BOD25_OUT,Brown-Out Detector Output Status\n" "0: Brown-out Detector output status is 0. It means..,1: Brown-out Detector output status is 1. It means.." rbitfld.long 0x0 2. "BOD20_OUT,Brown-Out Detector Output Status\n" "0: Brown-out Detector output status is 0. It means..,1: Brown-out Detector output status is 1. It means.." newline rbitfld.long 0x0 1. "BOD17_OUT,Brown-Out Detector Output Status\n" "0: Brown-out Detector output status is 0. It means..,1: Brown-out Detector output status is 1. It means.." endif rbitfld.long 0x0 0. "BOD_INT,Brown-Out Detector Interrupt Status\nThis bit is cleared by writing 1 to itself." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.." sif (cpuis("NANO1*BN")) group.long 0x6C++0x3 line.long 0x0 "Int_VREFCTL,Voltage reference Control register" bitfld.long 0x0 3. "EXT_MODE,Regulator External Mode\nThis is a protected register. Please refer to open lock sequence to program it.\nUsers can output regulator output voltage in VREF pin if EXT_MODE is high." "0: No connection with external VREF pin,1: Connet to external VREF pin. Connect a 1uF to.." bitfld.long 0x0 2. "SEL25,Regulator Output Voltage Selection\nSelect internal reference voltage level.\nThis is a protected register. Please refer to open lock sequence to program it." "0: 1.8V,1: 2.5V" newline bitfld.long 0x0 1. "REG_EN,Regulator Enable\nEnable internal 1.8V or 2.5V reference voltage.\nThis is a protected register. Please refer to open lock sequence to program it." "0: Disabled,1: Enabled" bitfld.long 0x0 0. "BGP_EN,Band-gap Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.8V or 2.5V reference voltage." "0: Disabled,1: Enabled" endif group.long 0x80++0xB line.long 0x0 "IRCTRIMCTL,HIRC Trim Control Register" sif (cpuis("NANO1*BN")) bitfld.long 0x0 8. "ERR_STOP,Trim Stop When 32.768 kHz Error Detected\nThis bit is used to control if stop the HIRC trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected the status 32K_ERR_INT would be set high.." "0: Continue the HIRC trim operation even if 32.768..,1: Stop the HIRC trim operation if 32.768 kHz clock.." endif bitfld.long 0x0 6.--7. "TRIM_RETRY_CNT,Trim Value Update Limitation Count\n" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TRIM_LOOP,Trim Calculation Loop\n" "0,1,2,3" bitfld.long 0x0 0.--1. "TRIM_SEL,Trim Frequency Selection\n" "0,1,2,3" line.long 0x4 "IRCTRIMIEN,HIRC Trim Interrupt Enable Register" bitfld.long 0x4 2. "_32K_ERR_IEN,32.768 KHz Clock Error Interrupt Enable\nThis bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.\nIf this bit is high and 32K_ERR_INT (IRCTRIMINT[2]) is set during auto trim.." "0: 32K_ERR_INT (IRCTRIMINT[2]) status Disabled to..,1: 32K_ERR_INT (IRCTRIMINT[2]) status Enabled to.." bitfld.long 0x4 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTRIMCTL[1:0]).\nIf this bit.." "0: TRIM_FAIL_INT (IRCTRIMINT[1]) status Disabled to..,1: TRIM_FAIL_INT (IRCTRIMINT[1]) status Enabled to.." line.long 0x8 "IRCTRIMINT,HIRC Trim Interrupt Status Register" bitfld.long 0x8 2. "_32K_ERR_INT,32.768 KHz Clock Error Interrupt Status\nThis bit indicates that 32.768 kHz clock frequency is inaccuracy. Once this bit is set the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware.." "0: 32.768 kHz clock frequency is accuracy,1: 32.768 kHz clock frequency is inaccuracy" bitfld.long 0x8 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be.." "0: Trim value update limitation count doesn't reach,1: Trim value update limitation count reached and.." newline bitfld.long 0x8 0. "FREQ_LOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt." "0,1" group.long 0x100++0x3 line.long 0x0 "RegLockAddr,Register Lock Key Address Register" bitfld.long 0x0 0. "RegUnLock," "0: Protected register are locked. Any write to the..,1: Protected registers are Unlock" tree.end tree "GPIO (General Purpose I/O)" base ad:0x50004000 group.long 0x0++0xF line.long 0x0 "GPIOA_PMD,GPIO Port A Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" line.long 0x4 "GPIOA_OFFD,GPIO Port A Pin OFF Digital Enable Register" bitfld.long 0x4 31. "OFFD15,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 30. "OFFD14,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 29. "OFFD13,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 28. "OFFD12,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 27. "OFFD11,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 26. "OFFD10,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 25. "OFFD9,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 24. "OFFD8,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 23. "OFFD7,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 22. "OFFD6,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 21. "OFFD5,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 20. "OFFD4,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 19. "OFFD3,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 18. "OFFD2,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 17. "OFFD1,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 16. "OFFD0,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." line.long 0x8 "GPIOA_DOUT,GPIO Port A Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 14. "DOUT14,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 13. "DOUT13,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 12. "DOUT12,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 11. "DOUT11,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 10. "DOUT10,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 9. "DOUT9,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 8. "DOUT8,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 7. "DOUT7,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 6. "DOUT6,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 5. "DOUT5,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 4. "DOUT4,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 3. "DOUT3,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 2. "DOUT2,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 1. "DOUT1,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 0. "DOUT0,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." line.long 0xC "GPIOA_DMASK,GPIO Port A Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 14. "DMASK14,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 13. "DMASK13,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 12. "DMASK12,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 11. "DMASK11,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 10. "DMASK10,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 9. "DMASK9,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 8. "DMASK8,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 7. "DMASK7,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 6. "DMASK6,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 5. "DMASK5,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 4. "DMASK4,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 3. "DMASK3,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 2. "DMASK2,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 1. "DMASK1,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 0. "DMASK0,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_PIN,GPIO Port A Pin Value Register" bitfld.long 0x0 15. "PIN15,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 13. "PIN13,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 11. "PIN11,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 9. "PIN9,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 7. "PIN7,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 5. "PIN5,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 3. "PIN3,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" group.long 0x14++0x13 line.long 0x0 "GPIOA_DBEN,GPIO Port A De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 14. "DBEN14,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 13. "DBEN13,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 12. "DBEN12,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 11. "DBEN11,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 10. "DBEN10,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 9. "DBEN9,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 8. "DBEN8,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 7. "DBEN7,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 6. "DBEN6,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 5. "DBEN5,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 4. "DBEN4,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 3. "DBEN3,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 2. "DBEN2,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 1. "DBEN1,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 0. "DBEN0,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." line.long 0x4 "GPIOA_IMD,GPIO Port A Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOA_IER,GPIO Port A Interrupt Enable Register" bitfld.long 0x8 31. "RIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 30. "RIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 29. "RIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 28. "RIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 27. "RIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 26. "RIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 25. "RIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 24. "RIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 23. "RIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 22. "RIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 21. "RIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 20. "RIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 19. "RIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 18. "RIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 17. "RIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 16. "RIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 15. "FIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 14. "FIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 13. "FIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 12. "FIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 11. "FIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 10. "FIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 9. "FIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 8. "FIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 7. "FIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 6. "FIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 5. "FIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 4. "FIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 3. "FIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 2. "FIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 1. "FIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 0. "FIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." line.long 0xC "GPIOA_ISRC,GPIO Port A Interrupt Trigger Source Status Register" bitfld.long 0xC 15. "ISRC15,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 14. "ISRC14,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 13. "ISRC13,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 12. "ISRC12,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 11. "ISRC11,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 10. "ISRC10,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 9. "ISRC9,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 8. "ISRC8,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 7. "ISRC7,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 6. "ISRC6,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 5. "ISRC5,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 4. "ISRC4,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 3. "ISRC3,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 2. "ISRC2,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 1. "ISRC1,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 0. "ISRC0,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." line.long 0x10 "GPIOA_PUEN,GPIO Port A Pull-up Enable Register" bitfld.long 0x10 15. "PUEN15,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 14. "PUEN14,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 13. "PUEN13,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 12. "PUEN12,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 11. "PUEN11,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 10. "PUEN10,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 9. "PUEN9,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 8. "PUEN8,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 7. "PUEN7,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 6. "PUEN6,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 5. "PUEN5,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 4. "PUEN4,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 3. "PUEN3,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 2. "PUEN2,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 1. "PUEN1,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 0. "PUEN0,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." group.long 0x40++0xF line.long 0x0 "GPIOB_PMD,GPIO Port B Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" line.long 0x4 "GPIOB_OFFD,GPIO Port B Pin OFF Digital Enable Register" bitfld.long 0x4 31. "OFFD15,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 30. "OFFD14,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 29. "OFFD13,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 28. "OFFD12,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 27. "OFFD11,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 26. "OFFD10,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 25. "OFFD9,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 24. "OFFD8,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 23. "OFFD7,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 22. "OFFD6,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 21. "OFFD5,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 20. "OFFD4,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 19. "OFFD3,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 18. "OFFD2,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 17. "OFFD1,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 16. "OFFD0,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." line.long 0x8 "GPIOB_DOUT,GPIO Port B Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 14. "DOUT14,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 13. "DOUT13,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 12. "DOUT12,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 11. "DOUT11,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 10. "DOUT10,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 9. "DOUT9,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 8. "DOUT8,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 7. "DOUT7,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 6. "DOUT6,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 5. "DOUT5,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 4. "DOUT4,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 3. "DOUT3,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 2. "DOUT2,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 1. "DOUT1,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 0. "DOUT0,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." line.long 0xC "GPIOB_DMASK,GPIO Port B Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 14. "DMASK14,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 13. "DMASK13,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 12. "DMASK12,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 11. "DMASK11,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 10. "DMASK10,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 9. "DMASK9,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 8. "DMASK8,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 7. "DMASK7,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 6. "DMASK6,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 5. "DMASK5,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 4. "DMASK4,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 3. "DMASK3,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 2. "DMASK2,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 1. "DMASK1,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 0. "DMASK0,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" rgroup.long 0x50++0x3 line.long 0x0 "GPIOB_PIN,GPIO Port B Pin Value Register" bitfld.long 0x0 15. "PIN15,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 13. "PIN13,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 11. "PIN11,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 9. "PIN9,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 7. "PIN7,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 5. "PIN5,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 3. "PIN3,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" group.long 0x54++0x13 line.long 0x0 "GPIOB_DBEN,GPIO Port B De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 14. "DBEN14,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 13. "DBEN13,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 12. "DBEN12,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 11. "DBEN11,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 10. "DBEN10,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 9. "DBEN9,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 8. "DBEN8,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 7. "DBEN7,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 6. "DBEN6,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 5. "DBEN5,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 4. "DBEN4,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 3. "DBEN3,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 2. "DBEN2,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 1. "DBEN1,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 0. "DBEN0,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." line.long 0x4 "GPIOB_IMD,GPIO Port B Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOB_IER,GPIO Port B Interrupt Enable Register" bitfld.long 0x8 31. "RIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 30. "RIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 29. "RIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 28. "RIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 27. "RIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 26. "RIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 25. "RIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 24. "RIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 23. "RIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 22. "RIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 21. "RIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 20. "RIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 19. "RIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 18. "RIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 17. "RIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 16. "RIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 15. "FIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 14. "FIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 13. "FIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 12. "FIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 11. "FIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 10. "FIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 9. "FIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 8. "FIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 7. "FIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 6. "FIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 5. "FIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 4. "FIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 3. "FIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 2. "FIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 1. "FIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 0. "FIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." line.long 0xC "GPIOB_ISRC,GPIO Port B Interrupt Trigger Source Status Register" bitfld.long 0xC 15. "ISRC15,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 14. "ISRC14,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 13. "ISRC13,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 12. "ISRC12,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 11. "ISRC11,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 10. "ISRC10,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 9. "ISRC9,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 8. "ISRC8,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 7. "ISRC7,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 6. "ISRC6,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 5. "ISRC5,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 4. "ISRC4,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 3. "ISRC3,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 2. "ISRC2,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 1. "ISRC1,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 0. "ISRC0,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." line.long 0x10 "GPIOB_PUEN,GPIO Port B Pull-up Enable Register" bitfld.long 0x10 15. "PUEN15,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 14. "PUEN14,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 13. "PUEN13,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 12. "PUEN12,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 11. "PUEN11,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 10. "PUEN10,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 9. "PUEN9,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 8. "PUEN8,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 7. "PUEN7,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 6. "PUEN6,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 5. "PUEN5,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 4. "PUEN4,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 3. "PUEN3,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 2. "PUEN2,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 1. "PUEN1,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 0. "PUEN0,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." group.long 0x80++0xF line.long 0x0 "GPIOC_PMD,GPIO Port C Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" line.long 0x4 "GPIOC_OFFD,GPIO Port C Pin OFF Digital Enable Register" bitfld.long 0x4 31. "OFFD15,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 30. "OFFD14,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 29. "OFFD13,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 28. "OFFD12,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 27. "OFFD11,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 26. "OFFD10,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 25. "OFFD9,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 24. "OFFD8,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 23. "OFFD7,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 22. "OFFD6,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 21. "OFFD5,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 20. "OFFD4,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 19. "OFFD3,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 18. "OFFD2,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 17. "OFFD1,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 16. "OFFD0,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." line.long 0x8 "GPIOC_DOUT,GPIO Port C Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 14. "DOUT14,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 13. "DOUT13,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 12. "DOUT12,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 11. "DOUT11,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 10. "DOUT10,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 9. "DOUT9,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 8. "DOUT8,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 7. "DOUT7,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 6. "DOUT6,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 5. "DOUT5,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 4. "DOUT4,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 3. "DOUT3,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 2. "DOUT2,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 1. "DOUT1,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 0. "DOUT0,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." line.long 0xC "GPIOC_DMASK,GPIO Port C Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 14. "DMASK14,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 13. "DMASK13,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 12. "DMASK12,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 11. "DMASK11,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 10. "DMASK10,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 9. "DMASK9,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 8. "DMASK8,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 7. "DMASK7,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 6. "DMASK6,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 5. "DMASK5,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 4. "DMASK4,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 3. "DMASK3,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 2. "DMASK2,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 1. "DMASK1,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 0. "DMASK0,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" rgroup.long 0x90++0x3 line.long 0x0 "GPIOC_PIN,GPIO Port C Pin Value Register" bitfld.long 0x0 15. "PIN15,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 13. "PIN13,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 11. "PIN11,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 9. "PIN9,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 7. "PIN7,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 5. "PIN5,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 3. "PIN3,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" group.long 0x94++0x13 line.long 0x0 "GPIOC_DBEN,GPIO Port C De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 14. "DBEN14,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 13. "DBEN13,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 12. "DBEN12,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 11. "DBEN11,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 10. "DBEN10,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 9. "DBEN9,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 8. "DBEN8,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 7. "DBEN7,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 6. "DBEN6,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 5. "DBEN5,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 4. "DBEN4,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 3. "DBEN3,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 2. "DBEN2,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 1. "DBEN1,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 0. "DBEN0,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." line.long 0x4 "GPIOC_IMD,GPIO Port C Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOC_IER,GPIO Port C Interrupt Enable Register" bitfld.long 0x8 31. "RIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 30. "RIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 29. "RIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 28. "RIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 27. "RIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 26. "RIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 25. "RIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 24. "RIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 23. "RIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 22. "RIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 21. "RIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 20. "RIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 19. "RIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 18. "RIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 17. "RIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 16. "RIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 15. "FIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 14. "FIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 13. "FIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 12. "FIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 11. "FIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 10. "FIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 9. "FIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 8. "FIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 7. "FIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 6. "FIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 5. "FIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 4. "FIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 3. "FIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 2. "FIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 1. "FIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 0. "FIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." line.long 0xC "GPIOC_ISRC,GPIO Port C Interrupt Trigger Source Status Register" bitfld.long 0xC 15. "ISRC15,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 14. "ISRC14,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 13. "ISRC13,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 12. "ISRC12,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 11. "ISRC11,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 10. "ISRC10,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 9. "ISRC9,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 8. "ISRC8,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 7. "ISRC7,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 6. "ISRC6,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 5. "ISRC5,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 4. "ISRC4,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 3. "ISRC3,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 2. "ISRC2,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 1. "ISRC1,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 0. "ISRC0,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." line.long 0x10 "GPIOC_PUEN,GPIO Port C Pull-up Enable Register" bitfld.long 0x10 15. "PUEN15,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 14. "PUEN14,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 13. "PUEN13,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 12. "PUEN12,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 11. "PUEN11,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 10. "PUEN10,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 9. "PUEN9,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 8. "PUEN8,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 7. "PUEN7,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 6. "PUEN6,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 5. "PUEN5,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 4. "PUEN4,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 3. "PUEN3,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 2. "PUEN2,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 1. "PUEN1,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 0. "PUEN0,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." group.long 0xC0++0xF line.long 0x0 "GPIOD_PMD,GPIO Port D Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" line.long 0x4 "GPIOD_OFFD,GPIO Port D Pin OFF Digital Enable Register" bitfld.long 0x4 31. "OFFD15,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 30. "OFFD14,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 29. "OFFD13,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 28. "OFFD12,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 27. "OFFD11,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 26. "OFFD10,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 25. "OFFD9,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 24. "OFFD8,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 23. "OFFD7,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 22. "OFFD6,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 21. "OFFD5,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 20. "OFFD4,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 19. "OFFD3,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 18. "OFFD2,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 17. "OFFD1,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 16. "OFFD0,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." line.long 0x8 "GPIOD_DOUT,GPIO Port D Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 14. "DOUT14,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 13. "DOUT13,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 12. "DOUT12,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 11. "DOUT11,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 10. "DOUT10,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 9. "DOUT9,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 8. "DOUT8,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 7. "DOUT7,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 6. "DOUT6,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 5. "DOUT5,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 4. "DOUT4,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 3. "DOUT3,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 2. "DOUT2,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 1. "DOUT1,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 0. "DOUT0,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." line.long 0xC "GPIOD_DMASK,GPIO Port D Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 14. "DMASK14,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 13. "DMASK13,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 12. "DMASK12,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 11. "DMASK11,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 10. "DMASK10,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 9. "DMASK9,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 8. "DMASK8,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 7. "DMASK7,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 6. "DMASK6,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 5. "DMASK5,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 4. "DMASK4,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 3. "DMASK3,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 2. "DMASK2,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 1. "DMASK1,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 0. "DMASK0,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" rgroup.long 0xD0++0x3 line.long 0x0 "GPIOD_PIN,GPIO Port D Pin Value Register" bitfld.long 0x0 15. "PIN15,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 13. "PIN13,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 11. "PIN11,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 9. "PIN9,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 7. "PIN7,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 5. "PIN5,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 3. "PIN3,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" group.long 0xD4++0x13 line.long 0x0 "GPIOD_DBEN,GPIO Port D De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 14. "DBEN14,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 13. "DBEN13,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 12. "DBEN12,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 11. "DBEN11,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 10. "DBEN10,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 9. "DBEN9,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 8. "DBEN8,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 7. "DBEN7,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 6. "DBEN6,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 5. "DBEN5,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 4. "DBEN4,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 3. "DBEN3,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 2. "DBEN2,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 1. "DBEN1,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 0. "DBEN0,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." line.long 0x4 "GPIOD_IMD,GPIO Port D Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOD_IER,GPIO Port D Interrupt Enable Register" bitfld.long 0x8 31. "RIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 30. "RIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 29. "RIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 28. "RIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 27. "RIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 26. "RIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 25. "RIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 24. "RIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 23. "RIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 22. "RIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 21. "RIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 20. "RIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 19. "RIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 18. "RIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 17. "RIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 16. "RIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 15. "FIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 14. "FIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 13. "FIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 12. "FIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 11. "FIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 10. "FIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 9. "FIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 8. "FIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 7. "FIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 6. "FIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 5. "FIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 4. "FIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 3. "FIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 2. "FIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 1. "FIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 0. "FIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." line.long 0xC "GPIOD_ISRC,GPIO Port D Interrupt Trigger Source Status Register" bitfld.long 0xC 15. "ISRC15,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 14. "ISRC14,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 13. "ISRC13,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 12. "ISRC12,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 11. "ISRC11,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 10. "ISRC10,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 9. "ISRC9,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 8. "ISRC8,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 7. "ISRC7,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 6. "ISRC6,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 5. "ISRC5,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 4. "ISRC4,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 3. "ISRC3,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 2. "ISRC2,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 1. "ISRC1,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 0. "ISRC0,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." line.long 0x10 "GPIOD_PUEN,GPIO Port D Pull-up Enable Register" bitfld.long 0x10 15. "PUEN15,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 14. "PUEN14,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 13. "PUEN13,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 12. "PUEN12,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 11. "PUEN11,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 10. "PUEN10,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 9. "PUEN9,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 8. "PUEN8,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 7. "PUEN7,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 6. "PUEN6,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 5. "PUEN5,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 4. "PUEN4,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 3. "PUEN3,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 2. "PUEN2,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 1. "PUEN1,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 0. "PUEN0,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." group.long 0x100++0xF line.long 0x0 "GPIOE_PMD,GPIO Port E Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" line.long 0x4 "GPIOE_OFFD,GPIO Port E Pin OFF Digital Enable Register" bitfld.long 0x4 31. "OFFD15,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 30. "OFFD14,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 29. "OFFD13,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 28. "OFFD12,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 27. "OFFD11,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 26. "OFFD10,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 25. "OFFD9,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 24. "OFFD8,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 23. "OFFD7,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 22. "OFFD6,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 21. "OFFD5,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 20. "OFFD4,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 19. "OFFD3,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 18. "OFFD2,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 17. "OFFD1,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 16. "OFFD0,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." line.long 0x8 "GPIOE_DOUT,GPIO Port E Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 14. "DOUT14,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 13. "DOUT13,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 12. "DOUT12,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 11. "DOUT11,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 10. "DOUT10,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 9. "DOUT9,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 8. "DOUT8,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 7. "DOUT7,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 6. "DOUT6,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 5. "DOUT5,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 4. "DOUT4,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 3. "DOUT3,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 2. "DOUT2,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 1. "DOUT1,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 0. "DOUT0,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." line.long 0xC "GPIOE_DMASK,GPIO Port E Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 14. "DMASK14,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 13. "DMASK13,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 12. "DMASK12,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 11. "DMASK11,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 10. "DMASK10,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 9. "DMASK9,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 8. "DMASK8,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 7. "DMASK7,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 6. "DMASK6,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 5. "DMASK5,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 4. "DMASK4,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 3. "DMASK3,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 2. "DMASK2,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 1. "DMASK1,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 0. "DMASK0,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" rgroup.long 0x110++0x3 line.long 0x0 "GPIOE_PIN,GPIO Port E Pin Value Register" bitfld.long 0x0 15. "PIN15,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 13. "PIN13,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 11. "PIN11,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 9. "PIN9,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 7. "PIN7,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 5. "PIN5,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 3. "PIN3,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" group.long 0x114++0x13 line.long 0x0 "GPIOE_DBEN,GPIO Port E De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 14. "DBEN14,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 13. "DBEN13,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 12. "DBEN12,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 11. "DBEN11,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 10. "DBEN10,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 9. "DBEN9,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 8. "DBEN8,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 7. "DBEN7,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 6. "DBEN6,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 5. "DBEN5,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 4. "DBEN4,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 3. "DBEN3,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 2. "DBEN2,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 1. "DBEN1,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 0. "DBEN0,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." line.long 0x4 "GPIOE_IMD,GPIO Port E Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOE_IER,GPIO Port E Interrupt Enable Register" bitfld.long 0x8 31. "RIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 30. "RIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 29. "RIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 28. "RIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 27. "RIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 26. "RIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 25. "RIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 24. "RIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 23. "RIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 22. "RIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 21. "RIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 20. "RIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 19. "RIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 18. "RIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 17. "RIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 16. "RIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 15. "FIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 14. "FIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 13. "FIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 12. "FIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 11. "FIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 10. "FIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 9. "FIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 8. "FIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 7. "FIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 6. "FIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 5. "FIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 4. "FIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 3. "FIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 2. "FIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 1. "FIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 0. "FIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." line.long 0xC "GPIOE_ISRC,GPIO Port E Interrupt Trigger Source Status Register" bitfld.long 0xC 15. "ISRC15,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 14. "ISRC14,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 13. "ISRC13,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 12. "ISRC12,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 11. "ISRC11,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 10. "ISRC10,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 9. "ISRC9,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 8. "ISRC8,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 7. "ISRC7,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 6. "ISRC6,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 5. "ISRC5,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 4. "ISRC4,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 3. "ISRC3,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 2. "ISRC2,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 1. "ISRC1,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 0. "ISRC0,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." line.long 0x10 "GPIOE_PUEN,GPIO Port E Pull-up Enable Register" bitfld.long 0x10 15. "PUEN15,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 14. "PUEN14,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 13. "PUEN13,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 12. "PUEN12,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 11. "PUEN11,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 10. "PUEN10,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 9. "PUEN9,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 8. "PUEN8,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 7. "PUEN7,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 6. "PUEN6,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 5. "PUEN5,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 4. "PUEN4,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 3. "PUEN3,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 2. "PUEN2,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 1. "PUEN1,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 0. "PUEN0,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." group.long 0x140++0xF line.long 0x0 "GPIOF_PMD,GPIO Port F Pin I/O Mode Control Register" bitfld.long 0x0 30.--31. "PMD15,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "PMD14,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "PMD13,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "PMD12,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "PMD11,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "PMD10,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "PMD9,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "PMD8,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "PMD7,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "PMD6,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "PMD5,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "PMD4,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "PMD3,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "PMD2,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "PMD1,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "PMD0,GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD PMD0~PMD4 and PMD6~PMD15 are.." "0: GPIO port [x] pin [n] is in INPUT mode,1: GPIO port [x] pin [n] is in OUTPUT mode,?,?" line.long 0x4 "GPIOF_OFFD,GPIO Port F Pin OFF Digital Enable Register" bitfld.long 0x4 31. "OFFD15,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 30. "OFFD14,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 29. "OFFD13,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 28. "OFFD12,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 27. "OFFD11,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 26. "OFFD10,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 25. "OFFD9,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 24. "OFFD8,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 23. "OFFD7,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 22. "OFFD6,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 21. "OFFD5,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 20. "OFFD4,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 19. "OFFD3,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 18. "OFFD2,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." newline bitfld.long 0x4 17. "OFFD1,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." bitfld.long 0x4 16. "OFFD0,GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD bits [21:16] and [29:24] are reserved.\nFor.." "0: digital input path of GPIO port [x] pin [n]..,1: digital input path of GPIO port [x] pin [n].." line.long 0x8 "GPIOF_DOUT,GPIO Port F Data Output Value Register" bitfld.long 0x8 15. "DOUT15,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 14. "DOUT14,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 13. "DOUT13,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 12. "DOUT12,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 11. "DOUT11,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 10. "DOUT10,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 9. "DOUT9,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 8. "DOUT8,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 7. "DOUT7,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 6. "DOUT6,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 5. "DOUT5,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 4. "DOUT4,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 3. "DOUT3,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 2. "DOUT2,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." newline bitfld.long 0x8 1. "DOUT1,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." bitfld.long 0x8 0. "DOUT0,GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD bits.." "0: GPIO port [x] Pin [n] will drive Low if the..,1: GPIO port [x] Pin [n] will drive High if the.." line.long 0xC "GPIOF_DMASK,GPIO Port F Data Output Write Mask Register" bitfld.long 0xC 15. "DMASK15,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 14. "DMASK14,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 13. "DMASK13,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 12. "DMASK12,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 11. "DMASK11,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 10. "DMASK10,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 9. "DMASK9,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 8. "DMASK8,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 7. "DMASK7,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 6. "DMASK6,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 5. "DMASK5,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 4. "DMASK4,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 3. "DMASK3,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 2. "DMASK2,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" newline bitfld.long 0xC 1. "DMASK1,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" bitfld.long 0xC 0. "DMASK0,GPIO Port [X] Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to '1' the corresponding DOUT[n] bit is protected. The write signal is masked write data to the.." "0: the corresponding GPIO_DOUT bit [n] can be updated,1: the corresponding GPIO_DOUT bit [n] is protected" rgroup.long 0x150++0x3 line.long 0x0 "GPIOF_PIN,GPIO Port F Pin Value Register" bitfld.long 0x0 15. "PIN15,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 13. "PIN13,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 11. "PIN11,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor.." "0,1" newline bitfld.long 0x0 9. "PIN9,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 7. "PIN7,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 5. "PIN5,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 3. "PIN3,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN .." "0,1" group.long 0x154++0x13 line.long 0x0 "GPIOF_DBEN,GPIO Port F De-bounce Enable Register" bitfld.long 0x0 15. "DBEN15,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 14. "DBEN14,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 13. "DBEN13,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 12. "DBEN12,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 11. "DBEN11,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 10. "DBEN10,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 9. "DBEN9,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 8. "DBEN8,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 7. "DBEN7,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 6. "DBEN6,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 5. "DBEN5,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 4. "DBEN4,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 3. "DBEN3,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 2. "DBEN2,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." newline bitfld.long 0x0 1. "DBEN1,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." bitfld.long 0x0 0. "DBEN0,GPIO Port [X] Pin [N] Input Signal De-Bounce Enable\nDBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is.." "0: The GPIO port [x] Pin [n] input signal de-bounce..,1: The GPIO port [x] Pin [n] input signal de-bounce.." line.long 0x4 "GPIOF_IMD,GPIO Port F Interrupt Mode Control Register" bitfld.long 0x4 15. "IMD15,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 14. "IMD14,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 13. "IMD13,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 12. "IMD12,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 11. "IMD11,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 10. "IMD10,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 9. "IMD9,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 8. "IMD8,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 7. "IMD7,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 6. "IMD6,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 5. "IMD5,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 4. "IMD4,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 3. "IMD3,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 2. "IMD2,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x4 1. "IMD1,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x4 0. "IMD0,GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger the trigger source is sampled by.." "0: Edge trigger interrupt,1: Level trigger interrupt" line.long 0x8 "GPIOF_IER,GPIO Port F Interrupt Enable Register" bitfld.long 0x8 31. "RIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 30. "RIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 29. "RIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 28. "RIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 27. "RIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 26. "RIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 25. "RIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 24. "RIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 23. "RIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 22. "RIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 21. "RIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 20. "RIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 19. "RIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 18. "RIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 17. "RIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" bitfld.long 0x8 16. "RIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High\nRIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit '1' also enable the pin wake-up function \nWhen set the RIER[x] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt Enabled" newline bitfld.long 0x8 15. "FIER15,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 14. "FIER14,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 13. "FIER13,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 12. "FIER12,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 11. "FIER11,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 10. "FIER10,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 9. "FIER9,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 8. "FIER8,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 7. "FIER7,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 6. "FIER6,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 5. "FIER5,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 4. "FIER4,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 3. "FIER3,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 2. "FIER2,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." newline bitfld.long 0x8 1. "FIER1,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." bitfld.long 0x8 0. "FIER0,GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low\nFIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit '1' also enable the pin wake-up function\nWhen set the FIER[n] bit.." "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.." line.long 0xC "GPIOF_ISRC,GPIO Port F Interrupt Trigger Source Status Register" bitfld.long 0xC 15. "ISRC15,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 14. "ISRC14,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 13. "ISRC13,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 12. "ISRC12,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 11. "ISRC11,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 10. "ISRC10,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 9. "ISRC9,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 8. "ISRC8,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 7. "ISRC7,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 6. "ISRC6,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 5. "ISRC5,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 4. "ISRC4,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 3. "ISRC3,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 2. "ISRC2,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." newline bitfld.long 0xC 1. "ISRC1,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." bitfld.long 0xC 0. "ISRC0,GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC bits [4:0] and [15:6] are reserved.\nFor.." "0: No interrupt at Port x[n].\nNo action,1: Port x[n] generate an interrupt.\nClear the.." line.long 0x10 "GPIOF_PUEN,GPIO Port F Pull-up Enable Register" bitfld.long 0x10 15. "PUEN15,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 14. "PUEN14,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 13. "PUEN13,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 12. "PUEN12,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 11. "PUEN11,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 10. "PUEN10,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 9. "PUEN9,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 8. "PUEN8,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 7. "PUEN7,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 6. "PUEN6,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 5. "PUEN5,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 4. "PUEN4,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 3. "PUEN3,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 2. "PUEN2,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." newline bitfld.long 0x10 1. "PUEN1,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." bitfld.long 0x10 0. "PUEN0,GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN bits.." "0: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor..,1: GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor.." group.long 0x180++0x3 line.long 0x0 "DBNCECON,De-bounce Cycle Control Register" bitfld.long 0x0 5. "DBCLK_ON,De-Bounce Clock Enable\nThis bit controls if the de-bounce clock is enabled.\nHowever if GPIO pin's interrupt is enabled the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is.\n" "0: De-bounce clock Disabled,1: De-bounce clock Enabled" bitfld.long 0x0 4. "DBCLKSRC,De-Bounce Counter Clock Source Selection\n" "0: De-bounce counter Clock Source is the HCLK,1: De-bounce counter Clock Source is the internal.." newline sif (cpuis("NANO1*AN")) hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-Bounce Sampling Cycle Selection\n" endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 0. "PUEN,De-bounce Sampling Cycle Selection" "0,1" endif group.long 0x200++0x157 line.long 0x0 "GPIOA0,GPIO Port A Bit 0 Data Register" bitfld.long 0x0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x4 "GPIOA1,GPIO Port A Bit 1 Data Register" bitfld.long 0x4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x8 "GPIOA2,GPIO Port A Bit 2 Data Register" bitfld.long 0x8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xC "GPIOA3,GPIO Port A Bit 3 Data Register" bitfld.long 0xC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x10 "GPIOA4,GPIO Port A Bit 4 Data Register" bitfld.long 0x10 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x14 "GPIOA5,GPIO Port A Bit 5 Data Register" bitfld.long 0x14 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x18 "GPIOA6,GPIO Port A Bit 6 Data Register" bitfld.long 0x18 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x1C "GPIOA7,GPIO Port A Bit 7 Data Register" bitfld.long 0x1C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x20 "GPIOA8,GPIO Port A Bit 8 Data Register" bitfld.long 0x20 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x24 "GPIOA9,GPIO Port A Bit 9 Data Register" bitfld.long 0x24 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x28 "GPIOA10,GPIO Port A Bit 10 Data Register" bitfld.long 0x28 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x2C "GPIOA11,GPIO Port A Bit 11 Data Register" bitfld.long 0x2C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x30 "GPIOA12,GPIO Port A Bit 12 Data Register" bitfld.long 0x30 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x34 "GPIOA13,GPIO Port A Bit 13 Data Register" bitfld.long 0x34 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x38 "GPIOA14,GPIO Port A Bit 14 Data Register" bitfld.long 0x38 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x3C "GPIOA15,GPIO Port A Bit 15 Data Register" bitfld.long 0x3C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x40 "GPIOB0,GPIO Port B Bit 0 Data Register" bitfld.long 0x40 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x44 "GPIOB1,GPIO Port B Bit 1 Data Register" bitfld.long 0x44 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x48 "GPIOB2,GPIO Port B Bit 2 Data Register" bitfld.long 0x48 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x4C "GPIOB3,GPIO Port B Bit 3 Data Register" bitfld.long 0x4C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x50 "GPIOB4,GPIO Port B Bit 4 Data Register" bitfld.long 0x50 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x54 "GPIOB5,GPIO Port B Bit 5 Data Register" bitfld.long 0x54 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x58 "GPIOB6,GPIO Port B Bit 6 Data Register" bitfld.long 0x58 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x5C "GPIOB7,GPIO Port B Bit 7 Data Register" bitfld.long 0x5C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x60 "GPIOB8,GPIO Port B Bit 8 Data Register" bitfld.long 0x60 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x64 "GPIOB9,GPIO Port B Bit 9 Data Register" bitfld.long 0x64 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x68 "GPIOB10,GPIO Port B Bit 10 Data Register" bitfld.long 0x68 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x6C "GPIOB11,GPIO Port B Bit 11 Data Register" bitfld.long 0x6C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x70 "GPIOB12,GPIO Port B Bit 12 Data Register" bitfld.long 0x70 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x74 "GPIOB13,GPIO Port B Bit 13 Data Register" bitfld.long 0x74 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x78 "GPIOB14,GPIO Port B Bit 14 Data Register" bitfld.long 0x78 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x7C "GPIOB15,GPIO Port B Bit 15 Data Register" bitfld.long 0x7C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x80 "GPIOC0,GPIO Port C Bit 0 Data Register" bitfld.long 0x80 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x84 "GPIOC1,GPIO Port C Bit 1 Data Register" bitfld.long 0x84 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x88 "GPIOC2,GPIO Port C Bit 2 Data Register" bitfld.long 0x88 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x8C "GPIOC3,GPIO Port C Bit 3 Data Register" bitfld.long 0x8C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x90 "GPIOC4,GPIO Port C Bit 4 Data Register" bitfld.long 0x90 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x94 "GPIOC5,GPIO Port C Bit 5 Data Register" bitfld.long 0x94 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x98 "GPIOC6,GPIO Port C Bit 6 Data Register" bitfld.long 0x98 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x9C "GPIOC7,GPIO Port C Bit 7 Data Register" bitfld.long 0x9C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xA0 "GPIOC8,GPIO Port C Bit 8 Data Register" bitfld.long 0xA0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xA4 "GPIOC9,GPIO Port C Bit 9 Data Register" bitfld.long 0xA4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xA8 "GPIOC10,GPIO Port C Bit 10 Data Register" bitfld.long 0xA8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xAC "GPIOC11,GPIO Port C Bit 11 Data Register" bitfld.long 0xAC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xB0 "GPIOC12,GPIO Port C Bit 12 Data Register" bitfld.long 0xB0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xB4 "GPIOC13,GPIO Port C Bit 13 Data Register" bitfld.long 0xB4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xB8 "GPIOC14,GPIO Port C Bit 14 Data Register" bitfld.long 0xB8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xBC "GPIOC15,GPIO Port C Bit 15 Data Register" bitfld.long 0xBC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xC0 "GPIOD0,GPIO Port D Bit 0 Data Register" bitfld.long 0xC0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xC4 "GPIOD1,GPIO Port D Bit 1 Data Register" bitfld.long 0xC4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xC8 "GPIOD2,GPIO Port D Bit 2 Data Register" bitfld.long 0xC8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xCC "GPIOD3,GPIO Port D Bit 3 Data Register" bitfld.long 0xCC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xD0 "GPIOD4,GPIO Port D Bit 4 Data Register" bitfld.long 0xD0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xD4 "GPIOD5,GPIO Port D Bit 5 Data Register" bitfld.long 0xD4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xD8 "GPIOD6,GPIO Port D Bit 6 Data Register" bitfld.long 0xD8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xDC "GPIOD7,GPIO Port D Bit 7 Data Register" bitfld.long 0xDC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xE0 "GPIOD8,GPIO Port D Bit 8 Data Register" bitfld.long 0xE0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xE4 "GPIOD9,GPIO Port D Bit 9 Data Register" bitfld.long 0xE4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xE8 "GPIOD10,GPIO Port D Bit 10 Data Register" bitfld.long 0xE8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xEC "GPIOD11,GPIO Port D Bit 11 Data Register" bitfld.long 0xEC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xF0 "GPIOD12,GPIO Port D Bit 12 Data Register" bitfld.long 0xF0 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xF4 "GPIOD13,GPIO Port D Bit 13 Data Register" bitfld.long 0xF4 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xF8 "GPIOD14,GPIO Port D Bit 14 Data Register" bitfld.long 0xF8 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0xFC "GPIOD15,GPIO Port D Bit 15 Data Register" bitfld.long 0xFC 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x100 "GPIOE0,GPIO Port E Bit 0 Data Register" bitfld.long 0x100 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x104 "GPIOE1,GPIO Port E Bit 1 Data Register" bitfld.long 0x104 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x108 "GPIOE2,GPIO Port E Bit 2 Data Register" bitfld.long 0x108 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x10C "GPIOE3,GPIO Port E Bit 3 Data Register" bitfld.long 0x10C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x110 "GPIOE4,GPIO Port E Bit 4 Data Register" bitfld.long 0x110 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x114 "GPIOE5,GPIO Port E Bit 5 Data Register" bitfld.long 0x114 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x118 "GPIOE6,GPIO Port E Bit 6 Data Register" bitfld.long 0x118 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x11C "GPIOE7,GPIO Port E Bit 7 Data Register" bitfld.long 0x11C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x120 "GPIOE8,GPIO Port E Bit 8 Data Register" bitfld.long 0x120 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x124 "GPIOE9,GPIO Port E Bit 9 Data Register" bitfld.long 0x124 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x128 "GPIOE10,GPIO Port E Bit 10 Data Register" bitfld.long 0x128 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x12C "GPIOE11,GPIO Port E Bit 11 Data Register" bitfld.long 0x12C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x130 "GPIOE12,GPIO Port E Bit 12 Data Register" bitfld.long 0x130 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x134 "GPIOE13,GPIO Port E Bit 13 Data Register" bitfld.long 0x134 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x138 "GPIOE14,GPIO Port E Bit 14 Data Register" bitfld.long 0x138 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x13C "GPIOE15,GPIO Port E Bit 15 Data Register" bitfld.long 0x13C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x140 "GPIOF0,GPIO Port F Bit 0 Data Register" bitfld.long 0x140 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x144 "GPIOF1,GPIO Port F Bit 1 Data Register" bitfld.long 0x144 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x148 "GPIOF2,GPIO Port F Bit 2 Data Register" bitfld.long 0x148 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x14C "GPIOF3,GPIO Port F Bit 3 Data Register" bitfld.long 0x14C 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x150 "GPIOF4,GPIO Port F Bit 4 Data Register" bitfld.long 0x150 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." line.long 0x154 "GPIOF5,GPIO Port F Bit 5 Data Register" bitfld.long 0x154 0. "GPIO,GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port.." "0: The corresponding GPIO port [x] pin [n] value is..,1: The corresponding GPIO port [x] pin [n] value is.." tree.end tree "I2C (I2C Serial Interface Controller)" base ad:0x0 tree "I2C0" base ad:0x40020000 sif (cpuis("NANO1*AN")) group.long 0x0++0x3 line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "INTEN,Interrupt Enable Control\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 4. "I2C_STS,I2C Status\nWhen a new state is present in the I2CSTATUS register if the INTEN bit is set the I2C interrupt is requested. It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead.." "0: I2C's Status disabled and the I2C protocol..,1: I2C's Status active" newline bitfld.long 0x0 3. "START,I2C START Command\nSetting this bit to 1 to enter Master mode the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.\n" "0: After START or repeat START is active,1: Sends a START or repeat START condition to bus" bitfld.long 0x0 2. "STOP,I2C STOP Control Bit \nIn Master mode set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.\nIn Slave mode set.." "0: Will be cleared by hardware automatically if a..,1: Sends a STOP condition to bus in Master mode or.." newline bitfld.long 0x0 1. "ACK,Assert Acknowledge Control Bit\n" "0: When this bit is set to 0 prior to address or..,1: When this bit is set to 1 prior to address or.." bitfld.long 0x0 0. "IPEN,I2C Function Enable Control\n" "0: I2C function Disabled,1: I2C function Enabled" endif sif (cpuis("NANO1*BN")) group.long 0x0++0x3 line.long 0x0 "I2CCON,I2C Control Register" bitfld.long 0x0 7. "INTEN,Interrupt Enable." "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 4. "I2C_STS,I2C Status. \nWhen a new state is present in the I2CSTATUS register this bit will be set automatically and if the INTEN bit is set the I2C interrupt is requested. It must be cleared by software by writing one to this bit and the I2C protocol.." "0: I2C's Status disabled and the I2C protocol..,1: I2C's Status active" newline bitfld.long 0x0 3. "START,I2C START Command\nSetting this bit to 1 to enter Master mode the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated." "0: After START or repeat START is active,1: Sends a START or repeat START condition to bus" bitfld.long 0x0 2. "STOP,I2C STOP Control Bit. \nIn Master mode set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.\nIn Slave mode .." "0: Will be cleared by hardware automatically if a..,1: Sends a STOP condition to bus in Master mode or.." newline bitfld.long 0x0 1. "ACK,Assert Acknowledge Control Bit" "0: : When this bit is set to 0 prior to address or..,1: When this bit is set to 1 prior to address or.." bitfld.long 0x0 0. "IPEN,I2C Function Enable\nWhen this bit is set to 1 the I2C serial function is enabled." "0: I2C function Disabled,1: I2C function Enabled" endif group.long 0x4++0x3 line.long 0x0 "I2CINTSTS,I2C Interrupt Status Register" bitfld.long 0x0 1. "TIF,Time-Out Status\n" "0: No Time-out flag. Software can cleat this flag,1: Time-Out flag active and it is set by hardware." sif (cpuis("NANO1*AN")) bitfld.long 0x0 0. "INTSTS,I2C STATUS's Interrupt Status\n" "0: No bus event occurred,1: New state is presented in the I2CSTATUS." endif rgroup.long 0x8++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Bits (Read Only)\nIndicates the current status code of the bus information. The detail information about the status is described in the sections of I2C protocol register and operation mode." group.long 0xC++0x13 line.long 0x0 "I2CDIV,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "CLK_DIV,I2C Clock Divided Bits\nNote: the minimum value of CLK_DIV is 4." line.long 0x4 "I2CTOUT,I2C Time Out Counter Register" bitfld.long 0x4 1. "DIV4,Time-Out Counter Input Clock Divider By 4 \nWhen Enabled the time-out period is extended 4 times." "0: Disabled,1: Enabled" bitfld.long 0x4 0. "TOUTEN,Time-Out Counter Enable/Disable Control\nWhen set this bit to enable the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared. Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset.." "0: Disabled,1: Enabled" line.long 0x8 "I2CDATA,I2C DATA Register" hexmask.long.byte 0x8 0.--7. 1. "DATA,I2C Data Bits\nThe DATA contains a byte of serial data to be transmitted or a byte which has just been received. \nNote: Refer to Data register section for more detail information." line.long 0xC "I2CSADDR0,Slave Address Register 0" hexmask.long.byte 0xC 1.--7. 1. "SADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0xC 0. "GCALL,General Call Function \nNote: Refer to Address Register section for more detail information.." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CSADDR1,Slave Address Register 1" hexmask.long.byte 0x10 1.--7. 1. "SADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0x10 0. "GCALL,General Call Function \nNote: Refer to Address Register section for more detail information.." "0: General Call Function Disabled,1: General Call Function Enabled" group.long 0x28++0x7 line.long 0x0 "I2CSAMASK0,Slave Address Mask Register 0" hexmask.long.byte 0x0 1.--7. 1. "SAMASK,I2C Slave Address Mask Bits\n" sif (cpuis("NANO1*BN")) bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function Enable" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" endif line.long 0x4 "I2CSAMASK1,Slave Address Mask Register 1" hexmask.long.byte 0x4 1.--7. 1. "SAMASK,I2C Slave Address Mask Bits\n" sif (cpuis("NANO1*BN")) bitfld.long 0x4 0. "WKUPEN,I2C Wake-up Function Enable" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" endif sif (cpuis("NANO1*BN")) group.long 0x3C++0x3 line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function Enable" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" rgroup.long 0x40++0x3 line.long 0x0 "I2CWKUPSTS,I2C Wake-up Status Register" bitfld.long 0x0 0. "WKUPIF,Wake-up Interrupt Flag\nSoftware can write one to clear this flag" "0: Wake-up flag inactive,1: Wake-up flag active" endif tree.end tree "I2C1" base ad:0x40120000 sif (cpuis("NANO1*AN")) group.long 0x0++0x3 line.long 0x0 "I2CON,I2C Control Register" bitfld.long 0x0 7. "INTEN,Interrupt Enable Control\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 4. "I2C_STS,I2C Status\nWhen a new state is present in the I2CSTATUS register if the INTEN bit is set the I2C interrupt is requested. It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead.." "0: I2C's Status disabled and the I2C protocol..,1: I2C's Status active" newline bitfld.long 0x0 3. "START,I2C START Command\nSetting this bit to 1 to enter Master mode the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.\n" "0: After START or repeat START is active,1: Sends a START or repeat START condition to bus" bitfld.long 0x0 2. "STOP,I2C STOP Control Bit \nIn Master mode set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.\nIn Slave mode set.." "0: Will be cleared by hardware automatically if a..,1: Sends a STOP condition to bus in Master mode or.." newline bitfld.long 0x0 1. "ACK,Assert Acknowledge Control Bit\n" "0: When this bit is set to 0 prior to address or..,1: When this bit is set to 1 prior to address or.." bitfld.long 0x0 0. "IPEN,I2C Function Enable Control\n" "0: I2C function Disabled,1: I2C function Enabled" endif sif (cpuis("NANO1*BN")) group.long 0x0++0x3 line.long 0x0 "I2CCON,I2C Control Register" bitfld.long 0x0 7. "INTEN,Interrupt Enable." "0: I2C interrupt Disabled,1: I2C interrupt Enabled" bitfld.long 0x0 4. "I2C_STS,I2C Status. \nWhen a new state is present in the I2CSTATUS register this bit will be set automatically and if the INTEN bit is set the I2C interrupt is requested. It must be cleared by software by writing one to this bit and the I2C protocol.." "0: I2C's Status disabled and the I2C protocol..,1: I2C's Status active" newline bitfld.long 0x0 3. "START,I2C START Command\nSetting this bit to 1 to enter Master mode the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated." "0: After START or repeat START is active,1: Sends a START or repeat START condition to bus" bitfld.long 0x0 2. "STOP,I2C STOP Control Bit. \nIn Master mode set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.\nIn Slave mode .." "0: Will be cleared by hardware automatically if a..,1: Sends a STOP condition to bus in Master mode or.." newline bitfld.long 0x0 1. "ACK,Assert Acknowledge Control Bit" "0: : When this bit is set to 0 prior to address or..,1: When this bit is set to 1 prior to address or.." bitfld.long 0x0 0. "IPEN,I2C Function Enable\nWhen this bit is set to 1 the I2C serial function is enabled." "0: I2C function Disabled,1: I2C function Enabled" endif group.long 0x4++0x3 line.long 0x0 "I2CINTSTS,I2C Interrupt Status Register" bitfld.long 0x0 1. "TIF,Time-Out Status\n" "0: No Time-out flag. Software can cleat this flag,1: Time-Out flag active and it is set by hardware." sif (cpuis("NANO1*AN")) bitfld.long 0x0 0. "INTSTS,I2C STATUS's Interrupt Status\n" "0: No bus event occurred,1: New state is presented in the I2CSTATUS." endif rgroup.long 0x8++0x3 line.long 0x0 "I2CSTATUS,I2C Status Register" hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Bits (Read Only)\nIndicates the current status code of the bus information. The detail information about the status is described in the sections of I2C protocol register and operation mode." group.long 0xC++0x13 line.long 0x0 "I2CDIV,I2C Clock Divided Register" hexmask.long.byte 0x0 0.--7. 1. "CLK_DIV,I2C Clock Divided Bits\nNote: the minimum value of CLK_DIV is 4." line.long 0x4 "I2CTOUT,I2C Time Out Counter Register" bitfld.long 0x4 1. "DIV4,Time-Out Counter Input Clock Divider By 4 \nWhen Enabled the time-out period is extended 4 times." "0: Disabled,1: Enabled" bitfld.long 0x4 0. "TOUTEN,Time-Out Counter Enable/Disable Control\nWhen set this bit to enable the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared. Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset.." "0: Disabled,1: Enabled" line.long 0x8 "I2CDATA,I2C DATA Register" hexmask.long.byte 0x8 0.--7. 1. "DATA,I2C Data Bits\nThe DATA contains a byte of serial data to be transmitted or a byte which has just been received. \nNote: Refer to Data register section for more detail information." line.long 0xC "I2CSADDR0,Slave Address Register 0" hexmask.long.byte 0xC 1.--7. 1. "SADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0xC 0. "GCALL,General Call Function \nNote: Refer to Address Register section for more detail information.." "0: General Call Function Disabled,1: General Call Function Enabled" line.long 0x10 "I2CSADDR1,Slave Address Register 1" hexmask.long.byte 0x10 1.--7. 1. "SADDR,I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is.." bitfld.long 0x10 0. "GCALL,General Call Function \nNote: Refer to Address Register section for more detail information.." "0: General Call Function Disabled,1: General Call Function Enabled" group.long 0x28++0x7 line.long 0x0 "I2CSAMASK0,Slave Address Mask Register 0" hexmask.long.byte 0x0 1.--7. 1. "SAMASK,I2C Slave Address Mask Bits\n" sif (cpuis("NANO1*BN")) bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function Enable" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" endif line.long 0x4 "I2CSAMASK1,Slave Address Mask Register 1" hexmask.long.byte 0x4 1.--7. 1. "SAMASK,I2C Slave Address Mask Bits\n" sif (cpuis("NANO1*BN")) bitfld.long 0x4 0. "WKUPEN,I2C Wake-up Function Enable" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" endif sif (cpuis("NANO1*BN")) group.long 0x3C++0x3 line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register" bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function Enable" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled" rgroup.long 0x40++0x3 line.long 0x0 "I2CWKUPSTS,I2C Wake-up Status Register" bitfld.long 0x0 0. "WKUPIF,Wake-up Interrupt Flag\nSoftware can write one to clear this flag" "0: Wake-up flag inactive,1: Wake-up flag active" endif tree.end tree.end tree "I2S (I2S Controller)" base ad:0x401A0000 group.long 0x0++0xF line.long 0x0 "I2S_CTRL,I2S Control Register" sif (cpuis("NANO1*BN")) bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable" "0: Receives right channel data when monaural format..,1: Receives left channel data when monaural format.." endif bitfld.long 0x0 21. "RXDMA,Enable Receive DMA\nWhen RX DMA is enabled I2S requests PDMA to transfer data from receiving FIFO to memory if FIFO is not empty.\n" "0: RX DMA Disabled,1: RX DMA Enabled" newline bitfld.long 0x0 20. "TXDMA,Enable Transmit DMA\nWhen TX DMA is enabled I2S requests PDMA to transfer data from memory to transmitting FIFO if FIFO is not full\n" "0: TX DMA Disabled,1: TX DMA Enabled" bitfld.long 0x0 19. "CLR_RXFIFO,Clear Receiving FIFO\nWrite '1' to clear receiving FIFO internal pointer is reset to FIFO start point and RX_LEVEL[3:0] returns to zero and receiving FIFO becomes empty.\nThis bit is cleared by hardware automatically and read it return zero." "0,1" newline bitfld.long 0x0 18. "CLR_TXFIFO,Clear Transmit FIFO\nWrite '1' to clear transmitting FIFO internal pointer is reset to FIFO start point TX_LEVEL[3:0] returns to zero and transmitting FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is clear by.." "0,1" bitfld.long 0x0 17. "LCHZCEN,Left Channel Zero Cross Detect Enable\nIf this bit is set to '1' when left channel data sign bit is changed or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to '1'. It works on transmitting mode only.\n" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled" newline bitfld.long 0x0 16. "RCHZCEN,Right Channel Zero Cross Detect Enable\nIf this bit is set to '1' when right channel data sign bit is changed or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to '1'. It works on transmitting mode only.\n" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled" bitfld.long 0x0 15. "MCLKEN,Master Clock Enable\nEnable master MCLK timing output to the external audio codec device. The output frequency is according to MCLK_DIV[2:0] in the I2S_CLKDIV register.\n" "0: Master Clock Disabled,1: Master Clock Enabled" newline sif (cpuis("NANO1*AN")) bitfld.long 0x0 12.--14. "RXTH,Receiving FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n" "0: 1 word data in receiving FIFO,1: 2 words data in receiving FIFO,2: 3 words data in receiving FIFO,3: 4 words data in receiving FIFO,4: 5 words data in receiving FIFO,5: 6 words data in receiving FIFO,6: 7 words data in receiving FIFO,7: 8 words data in receiving FIFO" bitfld.long 0x0 9.--11. "TXTH,Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmitting FIFO is the same or less than threshold level then TXTHF flag is set.\n" "0: 1 word data in transmitting FIFO,1: 2 words data in transmitting FIFO,2: 3 words data in transmitting FIFO,3: 4 words data in transmitting FIFO,4: 5 words data in transmitting FIFO,5: 6 words data in transmitting FIFO,6: 7 words data in transmitting FIFO,7: 8 words data in transmitting FIFO" newline bitfld.long 0x0 4.--5. "WORDWIDTH,Word Width \nThis bit field indicates the bit-width of data word.\n" "0: data word is 8-bit,1: data word is 16-bit,2: data word is 24-bit,3: data word is 32-bit" endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 12.--14. "RXTH,Receiving FIFO Threshold Level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "TXTH,Transmit FIFO Threshold Level" "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 8. "SLAVE,Slave Mode Selection\nI2S can operate as master or Slave mode. For Master mode I2S_BCLK and I2S_LRCLK pins are output mode and also outputs I2S_BCLK and I2S_LRCLK signals to the audio CODEC. When act as Slave mode I2S_BCLK and I2S_LRCLK pins are.." "0: Master mode,1: Slave mode" newline bitfld.long 0x0 7. "FORMAT,Data Format Selection\n" "0: I2S data format,1: MSB justified data format" bitfld.long 0x0 6. "MONO,Monaural Data Selection\n" "0: Data is stereo format,1: Data is monaural format and gets the right.." newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 4.--5. "WORDWIDTH,Word width" "0,1,2,3" endif bitfld.long 0x0 3. "MUTE,Transmitting Mute Enable\n" "0: Transmit data in buffer to channel,1: Transmit '0' to channel" newline bitfld.long 0x0 2. "RXEN,Receive Enable\n" "0: Data receiving Disabled,1: Data receiving Enabled" bitfld.long 0x0 1. "TXEN,Transmit Enable\n" "0: Data transmitting Disabled,1: Data transmitting Enabled" newline bitfld.long 0x0 0. "I2SEN,I2S Controller Enable\n" "0: Disabled,1: Enabled" line.long 0x4 "I2S_CLKDIV,I2S Clock Divider Register" hexmask.long.byte 0x4 8.--15. 1. "BCLK_DIV,Bit Clock Divider\nIf I2S is operated in Master mode bit clock is provided by this chip. Software can program these bits to generate sampling rate clock frequency.\n" bitfld.long 0x4 0.--2. "MCLK_DIV,Master Clock Divider\nIf the external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio CODEC chip. If MCLK_DIV is set to '0' MCLK is the same as external clock input.\n" "0,1,2,3,4,5,6,7" line.long 0x8 "I2S_INTEN,I2S Interrupt Enable Register" bitfld.long 0x8 12. "LZCIE,Left Channel Zero Cross Interrupt Enable\nInterrupt occurs if this bit is set to '1' and left channel is zero crossing.\n" "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x8 11. "RZCIE,Right Channel Zero Cross Interrupt Enable\nInterrupt occurs if this bit is set to '1' and right channel is zero crossing. \n" "0: Interrupt Disabled,1: Interrupt Enabled" newline bitfld.long 0x8 10. "TXTHIE,Transmitting FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to '1' and data words in transmitting FIFO is less than TXTH[2:0].\n" "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x8 9. "TXOVFIE,Transmitting FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to '1' and transmitting FIFO overflow flag is set to '1'\n" "0: Interrupt Disabled,1: Interrupt Enabled" newline bitfld.long 0x8 8. "TXUDFIE,Transmitting FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to '1' and transmitting FIFO underflow flag is set to '1'.\n" "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x8 2. "RXTHIE,Receiving FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to '1' and data words in receiving FIFO is less than RXTH[2:0].\n" "0: Interrupt Disabled,1: Interrupt Enabled" newline bitfld.long 0x8 1. "RXOVFIE,Receiving FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to '1' and receiving FIFO overflow flag is set to '1'\n" "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x8 0. "RXUDFIE,Receiving FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to '1' and receiving FIFO underflow flag is set to '1'.\n" "0: Interrupt Disabled,1: Interrupt Enabled" line.long 0xC "I2S_STATUS,I2S Status Register" sif (cpuis("NANO1*AN")) hexmask.long.byte 0xC 28.--31. 1. "TX_LEVEL,Transmitting FIFO Level\nThese bits indicate the number of data word(s) in the transmitting FIFO.\n" hexmask.long.byte 0xC 24.--27. 1. "RX_LEVEL,Receive FIFO Level\nThese bits indicate the number of data word(s) in the receiving FIFO.\n" newline endif sif (cpuis("NANO1*BN")) hexmask.long.byte 0xC 28.--31. 1. "TX_LEVEL,Transmitting FIFO Level" hexmask.long.byte 0xC 24.--27. 1. "RX_LEVEL,Receive FIFO Level" newline endif bitfld.long 0xC 23. "LZCF,Left Channel Zero Cross Flag \nIt indicates the next sample data sign bit of left channel is changed or all data bits are zero.\nNote: This bit is cleared by writing 1." "0: No zero cross,1: Left channel zero cross is detected" bitfld.long 0xC 22. "RZCF,Right Channel Zero Cross Flag \nIt indicates the data sign of right channel next sample data is changed or all data bits are zero.\nNote: This bit is cleared by writing 1." "0: No zero cross,1: Right channel zero cross is detected" newline bitfld.long 0xC 21. "TXBUSY,Transmitting Busy\nThis bit is clear to 0 when all data in the transmitting FIFO and shift buffer is shifted out. Set this bit to 1 when 1st data is loading to shift buffer. \nNote: This bit is read only." "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy" bitfld.long 0xC 20. "TXEMPTY,Transmitting FIFO Empty\nThis bit reflect data word number in the transmitting FIFO is zero\nNote: This bit is read only." "0: Empty,1: Not empty" newline bitfld.long 0xC 19. "TXFULL,Transmitting FIFO Full\nThis bit reflect data word number in the transmitting FIFO is 8\nNote: This bit is read only" "0: Full,1: Not full" bitfld.long 0xC 18. "TXTHF,Transmitting FIFO Threshold Flag\nWhen data word(s) in the transmitting FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to '1'. It keeps at 1 till TX_LEVEL[3:0] is higher than TXTH[1:0] after software writes.." "0: Data word(s) in transmitting FIFO is higher than..,1: Data word(s) in transmitting FIFO is equal or.." newline bitfld.long 0xC 17. "TXOVF,Transmit FIFO Overflow Flag\nWrite data to the transmitting FIFO when it is full and this bit will set to '1'\nNote: This bit is cleared by writing 1." "0: No overflow,1: Overflow" bitfld.long 0xC 16. "TXUDF,Transmitting FIFO Underflow Flag\nWhen the transmitting FIFO is empty and shift logic hardware read data from the data FIFO causes this set to '1'. \nNote: This bit is cleared by writing 1." "0: No underflow,1: Underflow" newline bitfld.long 0xC 12. "RXEMPTY,Receiving FIFO Empty\nThis bit reflect data word number in the receiving FIFO is zero\nNote: This bit is read only." "0: Empty,1: Not empty" bitfld.long 0xC 11. "RXFULL,Receiving FIFO Full\nThis bit reflect data word number in the receiving FIFO is 8\nNote: This bit is read only" "0: Full,1: Not full" newline bitfld.long 0xC 10. "RXTHF,Receiving FIFO Threshold Flag\nWhen data word(s) in the receiving FIFO is equal to or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to '1'. It keeps at '1' till RX_LEVEL[3:0] less than RXTH[1:0] after software reads data from.." "0: Data word(s) in receiving FIFO is lower than..,1: Data word(s) in receiving FIFO is equal to or.." bitfld.long 0xC 9. "RXOVF,Receiving FIFO Overflow Flag\nWhen the receiving FIFO is full and receiving hardware attempts to write data into receiving FIFO then this bit is set to '1'. Data in 1st buffer is overwritten.\nNote: This bit is cleared by writing 1." "0: No overflow occur,1: Overflow occurs" newline bitfld.long 0xC 8. "RXUDF,Receiving FIFO Underflow Flag\nRead the receiving FIFO when it is empty this bit set to '1' indicate underflow occur. \nNote: This bit is cleared by writing 1." "0: No underflow occur,1: Underflow occurs" bitfld.long 0xC 3. "RIGHT,Right Channel\nThis bit indicates the current transmitting data is belong to right channel\nNote: This bit is read only" "0: Left channel,1: Right channel" newline bitfld.long 0xC 2. "I2STXINT,I2S Transmit Interrupt\nNote: This bit is read only" "0: No transmit interrupt occurs,1: Transmit interrupt occurs" bitfld.long 0xC 1. "I2SRXINT,I2S Receiving Interrupt\nNote: This bit is read only" "0: No receiving interrupt occurs,1: Receiving interrupt occurs" newline bitfld.long 0xC 0. "I2SINT,I2S Interrupt Flag\nNote: This bit is read only and it is wire-OR of I2STXINT and I2SRXINT bits." "0: No I2S interrupt,1: I2S interrupt occurs" wgroup.long 0x10++0x3 line.long 0x0 "I2S_TXFIFO,I2S Transmit FIFO Register" hexmask.long 0x0 0.--31. 1. "TXFIFO,Transmitting FIFO Register\nI2S contains 8 words (8x32-bit) data buffer for data transmitting. Write data to this register in order to prepare data for transmitting. The remaining word number is indicated by TX_LEVEL[3:0] in the I2S_STATUS.." rgroup.long 0x14++0x3 line.long 0x0 "I2S_RXFIFO,I2S Receive FIFO Register" hexmask.long 0x0 0.--31. 1. "RXFIFO,Receiving FIFO Register\nI2S contains 8 words (8x32-bit) data buffer for data receiving. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in the I2S_STATUS register. This register is read only." tree.end tree "INT (Interrupt Multiplexer Control Registers)" base ad:0x50000300 rgroup.long 0x0++0x7F line.long 0x0 "IRQ0_SRC,MCU IRQ0 (BOD_INT) Interrupt Source Identify" hexmask.long.byte 0x0 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x4 "IRQ1_SRC,MCU IRQ1 (WDT_INT) Interrupt Source Identify" hexmask.long.byte 0x4 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x8 "IRQ2_SRC,MCU IRQ2 (EINT0) Interrupt Source Identify" hexmask.long.byte 0x8 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0xC "IRQ3_SRC,MCU IRQ3 (EINT1) Interrupt Source Identify" hexmask.long.byte 0xC 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x10 "IRQ4_SRC,MCU IRQ4 (GPABC_INT) Interrupt Source Identify" hexmask.long.byte 0x10 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x14 "IRQ5_SRC,MCU IRQ5 (GPDEF_INT) Interrupt Source Identify" hexmask.long.byte 0x14 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x18 "IRQ6_SRC,MCU IRQ6 (PWM0_INT) Interrupt Source Identify" hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x1C "IRQ7_SRC,MCU IRQ7 (PWM1_INT) Interrupt Source Identify" hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x20 "IRQ8_SRC,MCU IRQ8 (TMR0_INT) Interrupt Source Identify" hexmask.long.byte 0x20 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x24 "IRQ9_SRC,MCU IRQ9 (TMR1_INT) Interrupt Source Identify" hexmask.long.byte 0x24 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x28 "IRQ10_SRC,MCU IRQ10 (TMR2_INT) Interrupt Source Identify" hexmask.long.byte 0x28 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x2C "IRQ11_SRC,MCU IRQ11 (TMR3_INT) Interrupt Source Identify" hexmask.long.byte 0x2C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x30 "IRQ12_SRC,MCU IRQ12 (UART0_INT) Interrupt Source Identify" hexmask.long.byte 0x30 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x34 "IRQ13_SRC,MCU IRQ13 (UART1_INT) Interrupt Source Identify" hexmask.long.byte 0x34 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x38 "IRQ14_SRC,MCU IRQ14 (SPI0_INT) Interrupt Source Identify" hexmask.long.byte 0x38 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x3C "IRQ15_SRC,MCU IRQ15 (SPI1_INT) Interrupt Source Identify" hexmask.long.byte 0x3C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x40 "IRQ16_SRC,MCU IRQ16 (SPI2_INT) Interrupt Source Identify" hexmask.long.byte 0x40 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x44 "IRQ17_SRC,MCU IRQ17 (IRC_INT) Interrupt Source Identify" hexmask.long.byte 0x44 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x48 "IRQ18_SRC,MCU IRQ18 (I2C0_INT) Interrupt Source Identify" hexmask.long.byte 0x48 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x4C "IRQ19_SRC,MCU IRQ19 (I2C1_INT) Interrupt Source Identify" hexmask.long.byte 0x4C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x50 "IRQ20_SRC,MCU IRQ20 (Reserved) Interrupt Source Identify" hexmask.long.byte 0x50 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x54 "IRQ21_SRC,MCU IRQ21 (SC0_INT) Interrupt Source Identify" hexmask.long.byte 0x54 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x58 "IRQ22_SRC,MCU IRQ22 (SC1_INT) Interrupt Source Identify" hexmask.long.byte 0x58 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x5C "IRQ23_SRC,MCU IRQ23 (USB_INT) Interrupt Source Identify" hexmask.long.byte 0x5C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x60 "IRQ24_SRC,Reserved" hexmask.long.byte 0x60 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x64 "IRQ25_SRC,Reserved" hexmask.long.byte 0x64 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x68 "IRQ26_SRC,MCU IRQ26 (DMA_INT) Interrupt Source Identify" hexmask.long.byte 0x68 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x6C "IRQ27_SRC,MCU IRQ27 (I2S_INT) Interrupt Source Identify" hexmask.long.byte 0x6C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x70 "IRQ28_SRC,MCU IRQ28 (PDWU_INT) Interrupt Source Identify" hexmask.long.byte 0x70 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x74 "IRQ29_SRC,MCU IRQ29 (ADC_INT) Interrupt Source Identify" hexmask.long.byte 0x74 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x78 "IRQ30_SRC,Reserved" hexmask.long.byte 0x78 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." line.long 0x7C "IRQ31_SRC,MCU IRQ31 (RTC_INT) Interrupt Source Identify" hexmask.long.byte 0x7C 0.--3. 1. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event." group.long 0x80++0x7 line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register" hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,The NMI Interrupt To Cortex-M0 Can Be Selected From One Of The Interrupt[31:0]\nThe NMI_SEL bit[4:0] used to select the NMI interrupt source" line.long 0x4 "MCU_IRQ,MCU Interrupt Request Source Register" hexmask.long 0x4 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register \nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to Cortex-M0 the normal mode.\nWhen the MCU_IRQ[n] is '0' .." tree.end tree "PWM (Pulse Width Modulation)" base ad:0x0 tree "PWM0" base ad:0x40040000 sif (cpuis("NANO1*AN")) group.long 0x0++0x17 line.long 0x0 "PWM0_PRES,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZ23,Dead Zone Interval Register For CH2 And CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2." hexmask.long.byte 0x0 16.--23. 1. "DZ01,Dead Zone Interval Register For CH0 And CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 For PWM Timer 2 3\nClock input is divided by (CP23 + 1) before it is fed to the counter 2 3\n" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 For PWM Timer 0 1\nClock input is divided by (CP01 + 1) before it is fed to the counter 0 1\n" line.long 0x4 "PWM0_CLKSEL,PWM Clock Select Register" bitfld.long 0x4 12.--14. "CLKSEL3,Timer 3 Clock Source Selection\nSelect clock input for timer 3.\n" "0: input clock is divided by 2,1: input clock is divided by 4,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "CLKSEL2,Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CLKSEL1,Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CLKSEL0,Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PWM0_CTL,PWM Control Register" bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY3 to be cleared." "0: One-shot Mode,1: Continuous Mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable/Disable Start Run\n" "0: PWM-Timer 3 Running Stopped,1: PWM-Timer 3 Start Run Enabled" bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY2 be cleared." "0: One-shot Mode,1: Continuous Mode" newline bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable/Disable Start Run\n" "0: PWM-Timer 2 Running Stopped,1: PWM-Timer 2 Start Run Enabled" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY1 to be cleared." "0: One-shot Mode,1: Continuous Mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable/Disable Start Run\n" "0: PWM-Timer 1 Running Stopped,1: PWM-Timer 1 Start Run Enabled" bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair." "0: Disabled,1: Enabled" bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY0 to be cleared." "0: One-shot Mode,1: Continuous Mode" newline bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run\n" "0: PWM-Timer 0 Running Stopped,1: PWM-Timer 0 Start Run Enabled" line.long 0xC "PWM0_INTEN,PWM Interrupt Enable Register" bitfld.long 0xC 3. "TMIE3,PWM Timer 3 Interrupt Enable\n" "0: Disabled,1: Enabled" bitfld.long 0xC 2. "TMIE2,PWM Timer 2 Interrupt Enable\n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 1. "TMIE1,PWM Timer 1 Interrupt Enable\n" "0: Disabled,1: Enabled" bitfld.long 0xC 0. "TMIE0,PWM Timer 0 Interrupt Enable\n" "0: Disabled,1: Enabled" line.long 0x10 "PWM0_INTSTS,PWM Interrupt Indication Register" bitfld.long 0x10 8. "PresSyncFlag,Prescale Synchronize Flag\nNote: software should check this flag when writing Prescale if this flag is set and user ignore this flag and change Prescale the Prescale may be wrong for one prescale cycle" "0: Prescale has been synchronized to ECLK domain,1: Prescale is synchronizing to ECLK domain" bitfld.long 0x10 7. "Duty3Syncflag,Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3 if this flag is set and user ignore this flag and change duty3 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty3 has been synchronized to ECLK domain,1: Duty3 is synchronizing to ECLK domain" newline bitfld.long 0x10 6. "Duty2Syncflag,Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2 if this flag is set and user ignore this flag and change duty2 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty2 has been synchronized to ECLK domain,1: Duty2 is synchronizing to ECLK domain" bitfld.long 0x10 5. "Duty1Syncflag,Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1 if this flag is set and user ignore this flag and change duty1 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty1 has been synchronized to ECLK domain,1: Duty1 is synchronizing to ECLK domain" newline bitfld.long 0x10 4. "Duty0Syncflag,Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0 if this flag is set and user ignore this flag and change duty0 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty0 has been synchronized to ECLK domain,1: Duty0 is synchronizing to ECLK domain" bitfld.long 0x10 3. "TMINT3,PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 2. "TMINT2,PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero software can clear this bit by writing a one to it." "0,1" bitfld.long 0x10 1. "TMINT1,PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 0. "TMINT0,PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero software can clear this bit by writing a one to it." "0,1" line.long 0x14 "PWM0_OE,PWM Output Enable Register for CH0 ~ CH3" bitfld.long 0x14 3. "CH3_OE,PWM CH3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH3 output to pin Disabled,1: PWM CH3 output to pin Enabled" bitfld.long 0x14 2. "CH2_OE,PWM CH2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH2 output to pin Disabled,1: PWM CH2 output to pin Enabled" newline bitfld.long 0x14 1. "CH1_OE,PWM CH1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH1 output to pin Disabled,1: PWM CH1 output to pin Enabled" bitfld.long 0x14 0. "CH0_OE,PWM CH0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH0 output to pin Disabled,1: PWM CH0 output to pin Enabled" group.long 0x1C++0x3 line.long 0x0 "PWM0_DUTY0,PWM Counter/Comparator Register 0" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PWM0_DATA0,PWM Data Register 0" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x28++0x3 line.long 0x0 "PWM0_DUTY1,PWM Counter/Comparator Register 1" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PWM0_DATA1,PWM Data Register 1" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x34++0x3 line.long 0x0 "PWM0_DUTY2,PWM Counter/Comparator Register 2" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PWM0_DATA2,PWM Data Register 2" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x40++0x3 line.long 0x0 "PWM0_DUTY3,PWM Counter/Comparator Register 3" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x44++0x3 line.long 0x0 "PWM0_DATA3,PWM Data Register 3" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x54++0xB line.long 0x0 "PWM0_CAPCTL,Capture Control Register" bitfld.long 0x0 31. "CAPRELOADFEN3,Reload CNR3 When CH3 Falling Capture Event Comes \n" "0: Falling capture reload for CH3 Disabled,1: Falling capture reload for CH3 Enabled" bitfld.long 0x0 30. "CAPRELOADREN3,Reload CNR3 When CH3 Rising Capture Event Comes\n" "0: Rising capture reload for CH3 Disabled,1: Rising capture reload for CH3 Enabled" newline bitfld.long 0x0 29. "CH23CASK,Cascade channel 2 and channel 3 PWM counter for capturing usage" "0,1" bitfld.long 0x0 28. "CH2RFORDER," "0: PWMx_CFL2 is the first captured data to memory,1: PWMx_CRL2 is the first captured data to memory" newline bitfld.long 0x0 26. "CAPCH3PADEN,Capture Input Enable Register\n" "0: Disable the channel 3 input capture signal from..,1: Enable the channel 3 input capture signal from.." bitfld.long 0x0 25. "CAPCH3EN,Capture Channel 3 Transition Enable/Disable\nWhen Enabled Capture latched the PMW-timer and saved to PWMx_CRL3 (Rising latch) and PWMx_CFL3 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL3 and PWMx_CFL3 and disable Channel 3.." "0: Capture function on channel 3 Disabled,1: Capture function on channel 3 Enabled" newline bitfld.long 0x0 24. "INV3,Channel 3 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 23. "CAPRELOADFEN2,Reload CNR2 When CH2 Capture Failing Event Coming \n" "0: Failing capture reload for CH2 Disabled,1: Failing capture reload for CH2 Enabled" newline bitfld.long 0x0 22. "CAPRELOADREN2,Reload CNR2 When CH2 Capture Rising Event Coming \n" "0: Rising capture reload for CH2 Disabled,1: Rising capture reload for CH2 Enabled" bitfld.long 0x0 20.--21. "PDMACAPMOD2,Select CRL2 Or CFL2 For PDMA Transfer\n" "0: reserved,1: CRL2 will be transmitted,?,?" newline bitfld.long 0x0 19. "CH2PDMAEN,Channel 2 PDMA Enable\n" "0: Channel 2 PDMA function Disabled,1: Channel 2 PDMA function Enabled for the channel.." bitfld.long 0x0 18. "CAPCH2PADEN,Capture Input Enable Register\n" "0: Disable the channel 2 input capture signal from..,1: Enable the channel 2 input capture signal from.." newline bitfld.long 0x0 17. "CAPCH2EN,Capture Channel 2 Transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWMx_CRL2 (Rising latch) and PWMx_CFL2 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL2 and PWMx_CFL2 and disable.." "0: Capture function on channel 2 Disabled,1: Capture function on channel 2 Enabled" bitfld.long 0x0 16. "INV2,Channel 2 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." newline bitfld.long 0x0 15. "CAPRELOADFEN1,Reload CNR1 When CH1 Capture Falling Event Coming \n" "0: Capture falling reload for CH1 Disabled,1: Capture falling reload for CH1 Enabled" bitfld.long 0x0 14. "CAPRELOADREN1,Reload CNR1 When CH1 Capture Rising Event Comes\n" "0: Rising capture reload for CH1 Disabled,1: Rising capture reload for CH1 Enabled" newline bitfld.long 0x0 13. "CH01CASK,Cascade channel 0 and channel 1 PWM timer for capturing usage" "0,1" bitfld.long 0x0 12. "CH0RFORDER," "0: PWMx_CFL0 is the first captured data to memory,1: PWMx_CRL0 is the first captured data to memory" newline bitfld.long 0x0 10. "CAPCH1PADEN,Capture Input Enable Register\n" "0: Disable the channel 1 input capture signal from..,1: Enable the channel 1 input capture signal from.." bitfld.long 0x0 9. "CAPCH1EN,Capture Channel 1 Transition Enable/Disable\nWhen Enabled Capture latched the PMW-counter and saved to PWMx_CRL1 (Rising latch) and PWMx_CFL1 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL1 and PWMx_CFL1 and disable Channel.." "0: Capture function on channel 1 Disabled,1: Capture function on channel 1 Enabled" newline bitfld.long 0x0 8. "INV1,Channel 1 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 7. "CAPRELOADFEN0,Reload CNR0 When CH0 Capture Falling Event Comes\n" "0: Falling capture reload for CH0 Disabled,1: Falling capture reload for CH0 Enabled" newline bitfld.long 0x0 6. "CAPRELOADREN0,Reload CNR0 When CH0 Capture Rising Event Comes \n" "0: Rising capture reload for CH0 Disabled,1: Rising capture reload for CH0 Enabled" bitfld.long 0x0 4.--5. "PDMACAPMOD0,Select CRL0 Or CFL0 For PDMA Transfer\n" "0: reserved,1: CRL0 will be transmitted,?,?" newline bitfld.long 0x0 3. "CH0PDMAEN,Channel 0 PDMA Enable\n" "0: Channel 0 PDMA function Disabled,1: Channel 0 PDMA function Enabled for the channel.." bitfld.long 0x0 2. "CAPCH0PADEN,Capture Input Enable Register\n" "0: Disable the channel 0 input capture signal from..,1: Enable the channel 0 input capture signal from.." newline bitfld.long 0x0 1. "CAPCH0EN,Capture Channel 0 Transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWMx_CRL0 (Rising latch) and PWMx_CFL0 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL0 and PWMx_CFL0 and disable.." "0: Capture function on channel 0 Disabled,1: Capture function on channel 0 Enabled" bitfld.long 0x0 0. "INV0,Channel 0 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." line.long 0x4 "PWM0_CAPINTEN,Capture Interrupt Enable Register" bitfld.long 0x4 25. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 24. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 17. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 16. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 9. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 8. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 1. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 0 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 0. "CRL_IE0,When Enabled if Capture detects Channel 0 has rising transition Capture issues an Interrupt." "?,1: Rising latch interrupt Enabled" line.long 0x8 "PWM0_CAPINTSTS,Capture Interrupt Indication Register" bitfld.long 0x8 28. "CAPOVF3,Capture Falling Flag Over Run For Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 (PWMx_CAPINTSTS[26])" "0,1" bitfld.long 0x8 27. "CAPOVR3,Capture Rising Flag Over Run For Channel 3\nThis flag indicate CRL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 (PWMx_CAPINTSTS[25])" "0,1" newline bitfld.long 0x8 26. "CFLI3,PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition PWMx_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 25. "CRLI3,PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition PWMx_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 24. "CAPIF3,Capture3 Interrupt Indication Flag\nIf channel 3 rising latch interrupt (CRL_IE3 PWMx_CAPINTEN[24]) is enabled a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly a falling transition will cause CAPIF3 to be.." "0,1" bitfld.long 0x8 20. "CAPOVF2,Capture Falling Flag Over Run For Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 (PWMx_CAPINTSTS[18])" "0,1" newline bitfld.long 0x8 19. "CAPOVR2,Capture Rising Flag Over Run For Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 (PWMx_CAPINTSTS[17])" "0,1" bitfld.long 0x8 18. "CFLI2,PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition PWMx_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 17. "CRLI2,PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition PWMx_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 16. "CAPIF2,Capture2 Interrupt Indication Flag\nIf channel 2 rising latch interrupt (CRL_IE2 PWMx_CAPINTEN[16]) is enabled a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly a falling transition will cause CAPIF2 to be.." "0,1" newline bitfld.long 0x8 12. "CAPOVF1,Capture Falling Flag Over Run For Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 (PWMx_CAPINTSTS[10])" "0,1" bitfld.long 0x8 11. "CAPOVR1,Capture Rising Flag Over Run For Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 (PWMx_CAPINTSTS[9])" "0,1" newline bitfld.long 0x8 10. "CFLI1,PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition PWMx_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a 1 to it." "0,1" bitfld.long 0x8 9. "CRLI1,PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition PWMx_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 8. "CAPIF1,Capture1 Interrupt Indication Flag\nIf channel 1 rising latch interrupt (CRL_IE1 PWMx_CAPINTEN[8]) is enabled a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly a falling transition will cause CAPIF1 to be.." "0,1" bitfld.long 0x8 4. "CAPOVF0,Capture Falling Flag Over Run For Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI0 (PWMx_CAPINTSTS[2])" "0,1" newline bitfld.long 0x8 3. "CAPOVR0,Capture Rising Flag Over Run For Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 (PWMx_CAPINTSTS[1])." "0,1" bitfld.long 0x8 2. "CFLI0,PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition PWMx_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 1. "CRLI0,PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition PWMx_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 0. "CAPIF0,Capture0 Interrupt Indication Flag\nIf channel 0 rising latch interrupt (CRL_IE0 PWMx_CAPINTEN[0]) is enabled a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly a falling transition will cause CAPIF0 to be.." "0,1" rgroup.long 0x60++0x27 line.long 0x0 "PWM0_CRL0,Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x0 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "PWM0_CFL0,Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x4 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x8 "PWM0_CRL1,Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x8 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "PWM0_CFL1,Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0xC 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x10 "PWM0_CRL2,Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x10 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "PWM0_CFL2,Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x14 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x18 "PWM0_CRL3,Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x18 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "PWM0_CFL3,Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x1C 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x20 "PWM0_PDMACH0,PDMA Channel 0 Captured Data" hexmask.long.byte 0x20 24.--31. 1. "PDMACH04,Captured Data Of Channel 0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the fourth byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 16.--23. 1. "PDMACH03,Captured Data Of Channel 0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the third byte of 32 bit capturing data for channel 0" newline hexmask.long.byte 0x20 8.--15. 1. "PDMACH02,Captured Data Of Channel 0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the second byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 0.--7. 1. "PDMACH01,Captured Data Of Channel 0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the for the first byte of 32 bit capturing data for channel 0" line.long 0x24 "PWM0_PDMACH2,PDMA Channel 2 Captured Data" hexmask.long.byte 0x24 24.--31. 1. "PDMACH24,Captured Data Of Channel 2\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the fourth byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 16.--23. 1. "PDMACH23,Captured Data Of Channel 2\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the third byte of 32 bit capturing data for channel 2" newline hexmask.long.byte 0x24 8.--15. 1. "PDMACH22,Captured Data Of Channel 2\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the second byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 0.--7. 1. "PDMACH21,Captured Data Of Channel 2\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the for the first byte of 32 bit capturing data for channel 2" endif sif (cpuis("NANO1*BN")) group.long 0x0++0x17 line.long 0x0 "PWM_PRES,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZ23,Dead Zone Interval Register for CH2 and CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2." hexmask.long.byte 0x0 16.--23. 1. "DZ01,Dead Zone Interval Register for CH0 and CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 for PWM Timer 2 3\nClock input is divided by (CP23 + 1) before it is fed to the counter 2 3" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 for PWM Timer 0 1\nClock input is divided by (CP01 + 1) before it is fed to the counter 0 1" line.long 0x4 "PWM_CLKSEL,PWM Clock Select Register" bitfld.long 0x4 12.--14. "CLKSEL3,Timer 3 Clock Source Selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "CLKSEL2,Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CLKSEL1,Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CLKSEL0,Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PWM_CTL,PWM Control Register" bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY3 to be cleared." "0: One-Shot Mode,1: Continuous Mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable/Disable Start Run" "0: PWM-Timer 3 Running Stopped,1: PWM-Timer 3 Start Run Enabled" bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY2 be cleared." "0: One-Shot Mode,1: Continuous Mode" newline bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable/Disable Start Run" "0: PWM-Timer 2 Running Stopped,1: PWM-Timer 2 Start Run Enabled" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY1 to be cleared." "0: One-Shot Mode,1: Continuous Mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable/Disable Start Run" "0: PWM-Timer 1 Running Stopped,1: PWM-Timer 1 Start Run Enabled" bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair." "0: Disabled,1: Enabled" bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY0 to be cleared." "0: One-Shot Mode,1: Continuous Mode" newline bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run" "0: PWM-Timer 0 Running Stopped,1: PWM-Timer 0 Start Run Enabled" line.long 0xC "PWM_INTEN,PWM Interrupt Enable Register" bitfld.long 0xC 3. "TMIE3,PWM Timer 3 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 2. "TMIE2,PWM Timer 2 Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 1. "TMIE1,PWM Timer 1 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 0. "TMIE0,PWM Timer 0 Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x10 "PWM_INTSTS,PWM Interrupt Indication Register" bitfld.long 0x10 8. "PresSyncFlag,Prescale Synchronize Flag\nNote: software should check this flag when writing Prescale if this flag is set and user ignore this flag and change Prescale the Prescale may be wrong for one prescale cycle" "0: Prescale has been synchronized to ECLK domain,1: Prescale is synchronizing to ECLK domain" bitfld.long 0x10 7. "Duty3Syncflag,Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3 if this flag is set and user ignore this flag and change duty3 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty3 has been synchronized to ECLK domain,1: Duty3 is synchronizing to ECLK domain" newline bitfld.long 0x10 6. "Duty2Syncflag,Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2 if this flag is set and user ignore this flag and change duty2 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty2 has been synchronized to ECLK domain,1: Duty2 is synchronizing to ECLK domain" bitfld.long 0x10 5. "Duty1Syncflag,Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1 if this flag is set and user ignore this flag and change duty1 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty1 has been synchronized to ECLK domain,1: Duty1 is synchronizing to ECLK domain" newline bitfld.long 0x10 4. "Duty0Syncflag,Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0 if this flag is set and user ignore this flag and change duty0 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty0 has been synchronized to ECLK domain,1: Duty0 is synchronizing to ECLK domain" bitfld.long 0x10 3. "TMINT3,PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 2. "TMINT2,PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero software can clear this bit by writing a one to it." "0,1" bitfld.long 0x10 1. "TMINT1,PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 0. "TMINT0,PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero software can clear this bit by writing a one to it." "0,1" line.long 0x14 "PWM_OE,PWM Output Enable for PWM0~PWM3" bitfld.long 0x14 3. "CH3_OE,PWM CH3 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH3 output to pin Disabled,1: PWM CH3 output to pin Enabled" bitfld.long 0x14 2. "CH2_OE,PWM CH2 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH2 output to pin Disabled,1: PWM CH2 output to pin Enabled" newline bitfld.long 0x14 1. "CH1_OE,PWM CH1 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH1 output to pin Disabled,1: PWM CH1 output to pin Enabled" bitfld.long 0x14 0. "CH0_OE,PWM CH0 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH0 output to pin Disabled,1: PWM CH0 output to pin Enabled" group.long 0x1C++0x3 line.long 0x0 "PWM_DUTY0,PWM Counter/Comparator Register 0" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PWM_DATA0,PWM Data Register 0" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x28++0x3 line.long 0x0 "PWM_DUTY1,PWM Counter/Comparator Register 1" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PWM_DATA1,PWM Data Register 1" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x34++0x3 line.long 0x0 "PWM_DUTY2,PWM Counter/Comparator Register 2" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PWM_DATA2,PWM Data Register 2" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x40++0x3 line.long 0x0 "PWM_DUTY3,PWM Counter/Comparator Register 3" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x44++0x3 line.long 0x0 "PWM_DATA3,PWM Data Register 3" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x54++0xB line.long 0x0 "PWM_CAPCTL,Capture Control Register" bitfld.long 0x0 31. "CAPRELOADFEN3,Reload CNR3 when CH3 falling capture Event Comes" "0: Falling capture reload for CH3 Disabled,1: Falling capture reload for CH3 Enabled" bitfld.long 0x0 30. "CAPRELOADREN3,Reload CNR3 when CH3 Rising Capture Event Comes" "0: Rising capture reload for CH3 Disabled,1: Rising capture reload for CH3 Enabled" newline bitfld.long 0x0 29. "CH23CASK,Cascade channel 2 and channel 3 PWM counter for capturing usage" "0,1" bitfld.long 0x0 28. "CH2RFORDER," "0: PWM_CFL2 is the first captured data to memory,1: PWM_CRL2 is the first captured data to memory" newline bitfld.long 0x0 26. "CAPCH3PADEN,Capture Input Enable Register" "0: OFF,1: ON" bitfld.long 0x0 25. "CAPCH3EN,Capture Channel 3 transition Enable/Disable\nWhen Enabled Capture latched the PMW-timer and saved to PWM_CRL3 (Rising latch) and PWM_CFL3 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL3 and PWM_CFL3 and disable Channel 3.." "0: Capture function on channel 3 Disabled,1: Capture function on channel 3 Enabled" newline bitfld.long 0x0 24. "INV3,Channel 3 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 23. "CAPRELOADFEN2,Reload CNR2 when CH2 capture failing event coming" "0: Failing capture reload for CH2 Disabled,1: Failing capture reload for CH2 Enabled" newline bitfld.long 0x0 22. "CAPRELOADREN2,Reload CNR2 when CH2 capture rising event coming" "0: Rising capture reload for CH2 Disabled,1: Rising capture reload for CH2 Enabled" bitfld.long 0x0 20.--21. "PDMACAPMOD2,Select CRL2 or CFL2 for PDMA Transfer" "0,1,2,3" newline bitfld.long 0x0 19. "CH2PDMAEN,Channel 2 PDMA Enable" "0: Channel 2 PDMA function Disabled,1: Channel 2 PDMA function Enabled for the channel.." bitfld.long 0x0 18. "CAPCH2PADEN,Capture Input Enable Register" "0: OFF,1: ON" newline bitfld.long 0x0 17. "CAPCH2EN,Capture Channel 2 transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWM_CRL2 (Rising latch) and PWM_CFL2 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL2 and PWM_CFL2 and disable Channel.." "0: Capture function on channel 2 Disabled,1: Capture function on channel 2 Enabled" bitfld.long 0x0 16. "INV2,Channel 2 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." newline bitfld.long 0x0 15. "CAPRELOADFEN1,Reload CNR1 when CH1 capture falling event coming" "0: Capture falling reload for CH1 Disabled,1: Capture falling reload for CH1 Enabled" bitfld.long 0x0 14. "CAPRELOADREN1,Reload CNR1 when CH1 Capture Rising Event Comes" "0: Rising capture reload for CH1 Disabled,1: Rising capture reload for CH1 Enabled" newline bitfld.long 0x0 13. "CH01CASK,Cascade channel 0 and channel 1 PWM timer for capturing usage" "0,1" bitfld.long 0x0 12. "CH0RFORDER," "0: PWM_CFL0 is the first captured data to memory,1: PWM_CRL0 is the first captured data to memory" newline bitfld.long 0x0 10. "CAPCH1PADEN,Capture Input Enable Register" "0: OFF,1: ON" bitfld.long 0x0 9. "CAPCH1EN,Capture Channel 1 transition Enable/Disable\nWhen Enabled Capture latched the PMW-counter and saved to PWM_CRL1 (Rising latch) and PWM_CFL1 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL1 and PWM_CFL1 and disable Channel 1.." "0: Capture function on channel 1 Disabled,1: Capture function on channel 1 Enabled" newline bitfld.long 0x0 8. "INV1,Channel 1 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 7. "CAPRELOADFEN0,Reload CNR0 when CH0 Capture Falling Event Comes" "0: Falling capture reload for CH0 Disabled,1: Falling capture reload for CH0 Enabled" newline bitfld.long 0x0 6. "CAPRELOADREN0,Reload CNR0 when CH0 Capture Rising Event Comes" "0: Rising capture reload for CH0 Disabled,1: Rising capture reload for CH0 Enabled" bitfld.long 0x0 4.--5. "PDMACAPMOD0,Select CRL0 or CFL0 for PDMA Transfer" "0,1,2,3" newline bitfld.long 0x0 3. "CH0PDMAEN,Channel 0 PDMA Enable" "0: Channel 0 PDMA function Disabled,1: Channel 0 PDMA function Enabled for the channel.." bitfld.long 0x0 2. "CAPCH0PADEN,Capture Input Enable Register" "0: OFF,1: ON" newline bitfld.long 0x0 1. "CAPCH0EN,Capture Channel 0 transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWM_CRL0 (Rising latch) and PWM_CFL0 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL0 and PWM_CFL0 and disable Channel.." "0: Capture function on channel 0 Disabled,1: Capture function on channel 0 Enabled" bitfld.long 0x0 0. "INV0,Channel 0 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." line.long 0x4 "PWM_CAPINTEN,Capture interrupt enable Register" bitfld.long 0x4 25. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 24. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 17. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 16. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 9. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 8. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 1. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 0 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 0. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 0 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" line.long 0x8 "PWM_CAPINTSTS,Capture Interrupt Indication Register" bitfld.long 0x8 28. "CAPOVF3,Capture Falling Flag Over Run for Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 bit 26 of PWM_CAPINTSTS" "0,1" bitfld.long 0x8 27. "CAPOVR3,Capture Rising Flag Over Run for Channel 3\nThis flag indicate CRL3update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 bit 25 of PWM_CAPINTSTS" "0,1" newline bitfld.long 0x8 26. "CFLI3,PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 25. "CRLI3,PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 24. "CAPIF3,Capture3 Interrupt Indication Flag" "0,1" bitfld.long 0x8 20. "CAPOVF2,Capture Falling Flag Over Run for Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 bit 18 of PWM_CAPINTSTS" "0,1" newline bitfld.long 0x8 19. "CAPOVR2,Capture Rising Flag Over Run for Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 bit 17 of PWM_CAPINTSTS" "0,1" bitfld.long 0x8 18. "CFLI2,PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 17. "CRLI2,PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 16. "CAPIF2,Capture2 Interrupt Indication Flag" "0,1" newline bitfld.long 0x8 12. "CAPOVF1,Capture Falling Flag Over Run for Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 bit 10 of PWM_CAPINTSTS" "0,1" bitfld.long 0x8 11. "CAPOVR1,Capture Rising Flag Over Run for Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 bit 9 of PWM_CAPINTSTS" "0,1" newline bitfld.long 0x8 10. "CFLI1,PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition PWM0_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 9. "CRLI1,PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition PWM0_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 8. "CAPIF1,Capture1 Interrupt Indication Flag" "0,1" bitfld.long 0x8 4. "CAPOVF0,Capture Falling Flag Over Run for Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set." "0,1" newline bitfld.long 0x8 3. "CAPOVR0,Capture Rising Flag Over Run for Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 bit 1 of PWM_CAPINTSTS." "0,1" bitfld.long 0x8 2. "CFLRI0,PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 1. "CRLI0,PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 0. "CAPIF0,Capture0 Interrupt Indication Flag" "0,1" rgroup.long 0x60++0x27 line.long 0x0 "PWM_CRL0,Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x0 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "PWM_CFL0,Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x4 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x8 "PWM_CRL1,Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x8 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "PWM_CFL1,Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0xC 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x10 "PWM_CRL2,Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x10 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "PWM_CFL2,Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x14 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x18 "PWM_CRL3,Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x18 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "PWM_CFL3,Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x1C 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x20 "PWM_PDMACH0,PDMA channel 0 captured data" hexmask.long.byte 0x20 24.--31. 1. "Captureddata31_24,PDMACH0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the 4th byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 16.--23. 1. "Captureddata23_16,PDMACH0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the third byte of 32 bit capturing data for channel 0" newline hexmask.long.byte 0x20 8.--15. 1. "Captureddata15_8,PDMACH0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the second byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 0.--7. 1. "Captureddata7_0,PDMACH0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the for the first byte of 32 bit capturing data for channel 0" line.long 0x24 "PWM_PDMACH2,PDMA channel 2 captured data" hexmask.long.byte 0x24 24.--31. 1. "Captureddata31_24,PDMACH0\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the 4th byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 16.--23. 1. "Captureddata23_16,PDMACH0\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the third byte of 32 bit capturing data for channel 2" newline hexmask.long.byte 0x24 8.--15. 1. "Captureddata15_8,PDMACH0\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the second byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 0.--7. 1. "Captureddata7_0,PDMACH0\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the for the first byte of 32 bit capturing data for channel 2" endif tree.end tree "PWM1" base ad:0x40140000 sif (cpuis("NANO1*AN")) group.long 0x0++0x17 line.long 0x0 "PWM1_PRES,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZ23,Dead Zone Interval Register For CH2 And CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2." hexmask.long.byte 0x0 16.--23. 1. "DZ01,Dead Zone Interval Register For CH0 And CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 For PWM Timer 2 3\nClock input is divided by (CP23 + 1) before it is fed to the counter 2 3\n" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 For PWM Timer 0 1\nClock input is divided by (CP01 + 1) before it is fed to the counter 0 1\n" line.long 0x4 "PWM1_CLKSEL,PWM Clock Select Register" bitfld.long 0x4 12.--14. "CLKSEL3,Timer 3 Clock Source Selection\nSelect clock input for timer 3.\n" "0: input clock is divided by 2,1: input clock is divided by 4,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "CLKSEL2,Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CLKSEL1,Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CLKSEL0,Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PWM1_CTL,PWM Control Register" bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY3 to be cleared." "0: One-shot Mode,1: Continuous Mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable/Disable Start Run\n" "0: PWM-Timer 3 Running Stopped,1: PWM-Timer 3 Start Run Enabled" bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY2 be cleared." "0: One-shot Mode,1: Continuous Mode" newline bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable/Disable Start Run\n" "0: PWM-Timer 2 Running Stopped,1: PWM-Timer 2 Start Run Enabled" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY1 to be cleared." "0: One-shot Mode,1: Continuous Mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable/Disable Start Run\n" "0: PWM-Timer 1 Running Stopped,1: PWM-Timer 1 Start Run Enabled" bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair." "0: Disabled,1: Enabled" bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWMx_DUTY0 to be cleared." "0: One-shot Mode,1: Continuous Mode" newline bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run\n" "0: PWM-Timer 0 Running Stopped,1: PWM-Timer 0 Start Run Enabled" line.long 0xC "PWM1_INTEN,PWM Interrupt Enable Register" bitfld.long 0xC 3. "TMIE3,PWM Timer 3 Interrupt Enable\n" "0: Disabled,1: Enabled" bitfld.long 0xC 2. "TMIE2,PWM Timer 2 Interrupt Enable\n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 1. "TMIE1,PWM Timer 1 Interrupt Enable\n" "0: Disabled,1: Enabled" bitfld.long 0xC 0. "TMIE0,PWM Timer 0 Interrupt Enable\n" "0: Disabled,1: Enabled" line.long 0x10 "PWM1_INTSTS,PWM Interrupt Indication Register" bitfld.long 0x10 8. "PresSyncFlag,Prescale Synchronize Flag\nNote: software should check this flag when writing Prescale if this flag is set and user ignore this flag and change Prescale the Prescale may be wrong for one prescale cycle" "0: Prescale has been synchronized to ECLK domain,1: Prescale is synchronizing to ECLK domain" bitfld.long 0x10 7. "Duty3Syncflag,Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3 if this flag is set and user ignore this flag and change duty3 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty3 has been synchronized to ECLK domain,1: Duty3 is synchronizing to ECLK domain" newline bitfld.long 0x10 6. "Duty2Syncflag,Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2 if this flag is set and user ignore this flag and change duty2 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty2 has been synchronized to ECLK domain,1: Duty2 is synchronizing to ECLK domain" bitfld.long 0x10 5. "Duty1Syncflag,Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1 if this flag is set and user ignore this flag and change duty1 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty1 has been synchronized to ECLK domain,1: Duty1 is synchronizing to ECLK domain" newline bitfld.long 0x10 4. "Duty0Syncflag,Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0 if this flag is set and user ignore this flag and change duty0 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty0 has been synchronized to ECLK domain,1: Duty0 is synchronizing to ECLK domain" bitfld.long 0x10 3. "TMINT3,PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 2. "TMINT2,PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero software can clear this bit by writing a one to it." "0,1" bitfld.long 0x10 1. "TMINT1,PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 0. "TMINT0,PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero software can clear this bit by writing a one to it." "0,1" line.long 0x14 "PWM1_OE,PWM Output Enable Register for CH0 ~ CH3" bitfld.long 0x14 3. "CH3_OE,PWM CH3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH3 output to pin Disabled,1: PWM CH3 output to pin Enabled" bitfld.long 0x14 2. "CH2_OE,PWM CH2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH2 output to pin Disabled,1: PWM CH2 output to pin Enabled" newline bitfld.long 0x14 1. "CH1_OE,PWM CH1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH1 output to pin Disabled,1: PWM CH1 output to pin Enabled" bitfld.long 0x14 0. "CH0_OE,PWM CH0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH0 output to pin Disabled,1: PWM CH0 output to pin Enabled" group.long 0x1C++0x3 line.long 0x0 "PWM1_DUTY0,PWM Counter/Comparator Register 0" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PWM1_DATA0,PWM Data Register 0" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x28++0x3 line.long 0x0 "PWM1_DUTY1,PWM Counter/Comparator Register 1" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PWM1_DATA1,PWM Data Register 1" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x34++0x3 line.long 0x0 "PWM1_DUTY2,PWM Counter/Comparator Register 2" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PWM1_DATA2,PWM Data Register 2" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x40++0x3 line.long 0x0 "PWM1_DUTY3,PWM Counter/Comparator Register 3" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x44++0x3 line.long 0x0 "PWM1_DATA3,PWM Data Register 3" bitfld.long 0x0 31. "sync,Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "DATA_H,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set" newline hexmask.long.word 0x0 0.--15. 1. "DATA,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y." group.long 0x54++0xB line.long 0x0 "PWM1_CAPCTL,Capture Control Register" bitfld.long 0x0 31. "CAPRELOADFEN3,Reload CNR3 When CH3 Falling Capture Event Comes \n" "0: Falling capture reload for CH3 Disabled,1: Falling capture reload for CH3 Enabled" bitfld.long 0x0 30. "CAPRELOADREN3,Reload CNR3 When CH3 Rising Capture Event Comes\n" "0: Rising capture reload for CH3 Disabled,1: Rising capture reload for CH3 Enabled" newline bitfld.long 0x0 29. "CH23CASK,Cascade channel 2 and channel 3 PWM counter for capturing usage" "0,1" bitfld.long 0x0 28. "CH2RFORDER," "0: PWMx_CFL2 is the first captured data to memory,1: PWMx_CRL2 is the first captured data to memory" newline bitfld.long 0x0 26. "CAPCH3PADEN,Capture Input Enable Register\n" "0: Disable the channel 3 input capture signal from..,1: Enable the channel 3 input capture signal from.." bitfld.long 0x0 25. "CAPCH3EN,Capture Channel 3 Transition Enable/Disable\nWhen Enabled Capture latched the PMW-timer and saved to PWMx_CRL3 (Rising latch) and PWMx_CFL3 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL3 and PWMx_CFL3 and disable Channel 3.." "0: Capture function on channel 3 Disabled,1: Capture function on channel 3 Enabled" newline bitfld.long 0x0 24. "INV3,Channel 3 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 23. "CAPRELOADFEN2,Reload CNR2 When CH2 Capture Failing Event Coming \n" "0: Failing capture reload for CH2 Disabled,1: Failing capture reload for CH2 Enabled" newline bitfld.long 0x0 22. "CAPRELOADREN2,Reload CNR2 When CH2 Capture Rising Event Coming \n" "0: Rising capture reload for CH2 Disabled,1: Rising capture reload for CH2 Enabled" bitfld.long 0x0 20.--21. "PDMACAPMOD2,Select CRL2 Or CFL2 For PDMA Transfer\n" "0: reserved,1: CRL2 will be transmitted,?,?" newline bitfld.long 0x0 19. "CH2PDMAEN,Channel 2 PDMA Enable\n" "0: Channel 2 PDMA function Disabled,1: Channel 2 PDMA function Enabled for the channel.." bitfld.long 0x0 18. "CAPCH2PADEN,Capture Input Enable Register\n" "0: Disable the channel 2 input capture signal from..,1: Enable the channel 2 input capture signal from.." newline bitfld.long 0x0 17. "CAPCH2EN,Capture Channel 2 Transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWMx_CRL2 (Rising latch) and PWMx_CFL2 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL2 and PWMx_CFL2 and disable.." "0: Capture function on channel 2 Disabled,1: Capture function on channel 2 Enabled" bitfld.long 0x0 16. "INV2,Channel 2 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." newline bitfld.long 0x0 15. "CAPRELOADFEN1,Reload CNR1 When CH1 Capture Falling Event Coming \n" "0: Capture falling reload for CH1 Disabled,1: Capture falling reload for CH1 Enabled" bitfld.long 0x0 14. "CAPRELOADREN1,Reload CNR1 When CH1 Capture Rising Event Comes\n" "0: Rising capture reload for CH1 Disabled,1: Rising capture reload for CH1 Enabled" newline bitfld.long 0x0 13. "CH01CASK,Cascade channel 0 and channel 1 PWM timer for capturing usage" "0,1" bitfld.long 0x0 12. "CH0RFORDER," "0: PWMx_CFL0 is the first captured data to memory,1: PWMx_CRL0 is the first captured data to memory" newline bitfld.long 0x0 10. "CAPCH1PADEN,Capture Input Enable Register\n" "0: Disable the channel 1 input capture signal from..,1: Enable the channel 1 input capture signal from.." bitfld.long 0x0 9. "CAPCH1EN,Capture Channel 1 Transition Enable/Disable\nWhen Enabled Capture latched the PMW-counter and saved to PWMx_CRL1 (Rising latch) and PWMx_CFL1 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL1 and PWMx_CFL1 and disable Channel.." "0: Capture function on channel 1 Disabled,1: Capture function on channel 1 Enabled" newline bitfld.long 0x0 8. "INV1,Channel 1 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 7. "CAPRELOADFEN0,Reload CNR0 When CH0 Capture Falling Event Comes\n" "0: Falling capture reload for CH0 Disabled,1: Falling capture reload for CH0 Enabled" newline bitfld.long 0x0 6. "CAPRELOADREN0,Reload CNR0 When CH0 Capture Rising Event Comes \n" "0: Rising capture reload for CH0 Disabled,1: Rising capture reload for CH0 Enabled" bitfld.long 0x0 4.--5. "PDMACAPMOD0,Select CRL0 Or CFL0 For PDMA Transfer\n" "0: reserved,1: CRL0 will be transmitted,?,?" newline bitfld.long 0x0 3. "CH0PDMAEN,Channel 0 PDMA Enable\n" "0: Channel 0 PDMA function Disabled,1: Channel 0 PDMA function Enabled for the channel.." bitfld.long 0x0 2. "CAPCH0PADEN,Capture Input Enable Register\n" "0: Disable the channel 0 input capture signal from..,1: Enable the channel 0 input capture signal from.." newline bitfld.long 0x0 1. "CAPCH0EN,Capture Channel 0 Transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWMx_CRL0 (Rising latch) and PWMx_CFL0 (Falling latch).\nWhen Disabled Capture does not update PWMx_CRL0 and PWMx_CFL0 and disable.." "0: Capture function on channel 0 Disabled,1: Capture function on channel 0 Enabled" bitfld.long 0x0 0. "INV0,Channel 0 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." line.long 0x4 "PWM1_CAPINTEN,Capture Interrupt Enable Register" bitfld.long 0x4 25. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 24. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 17. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 16. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 9. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 8. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 1. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 0 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 0. "CRL_IE0,When Enabled if Capture detects Channel 0 has rising transition Capture issues an Interrupt." "?,1: Rising latch interrupt Enabled" line.long 0x8 "PWM1_CAPINTSTS,Capture Interrupt Indication Register" bitfld.long 0x8 28. "CAPOVF3,Capture Falling Flag Over Run For Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 (PWMx_CAPINTSTS[26])" "0,1" bitfld.long 0x8 27. "CAPOVR3,Capture Rising Flag Over Run For Channel 3\nThis flag indicate CRL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 (PWMx_CAPINTSTS[25])" "0,1" newline bitfld.long 0x8 26. "CFLI3,PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition PWMx_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 25. "CRLI3,PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition PWMx_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 24. "CAPIF3,Capture3 Interrupt Indication Flag\nIf channel 3 rising latch interrupt (CRL_IE3 PWMx_CAPINTEN[24]) is enabled a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly a falling transition will cause CAPIF3 to be.." "0,1" bitfld.long 0x8 20. "CAPOVF2,Capture Falling Flag Over Run For Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 (PWMx_CAPINTSTS[18])" "0,1" newline bitfld.long 0x8 19. "CAPOVR2,Capture Rising Flag Over Run For Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 (PWMx_CAPINTSTS[17])" "0,1" bitfld.long 0x8 18. "CFLI2,PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition PWMx_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 17. "CRLI2,PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition PWMx_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 16. "CAPIF2,Capture2 Interrupt Indication Flag\nIf channel 2 rising latch interrupt (CRL_IE2 PWMx_CAPINTEN[16]) is enabled a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly a falling transition will cause CAPIF2 to be.." "0,1" newline bitfld.long 0x8 12. "CAPOVF1,Capture Falling Flag Over Run For Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 (PWMx_CAPINTSTS[10])" "0,1" bitfld.long 0x8 11. "CAPOVR1,Capture Rising Flag Over Run For Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 (PWMx_CAPINTSTS[9])" "0,1" newline bitfld.long 0x8 10. "CFLI1,PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition PWMx_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a 1 to it." "0,1" bitfld.long 0x8 9. "CRLI1,PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition PWMx_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 8. "CAPIF1,Capture1 Interrupt Indication Flag\nIf channel 1 rising latch interrupt (CRL_IE1 PWMx_CAPINTEN[8]) is enabled a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly a falling transition will cause CAPIF1 to be.." "0,1" bitfld.long 0x8 4. "CAPOVF0,Capture Falling Flag Over Run For Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI0 (PWMx_CAPINTSTS[2])" "0,1" newline bitfld.long 0x8 3. "CAPOVR0,Capture Rising Flag Over Run For Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 (PWMx_CAPINTSTS[1])." "0,1" bitfld.long 0x8 2. "CFLI0,PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition PWMx_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 1. "CRLI0,PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition PWMx_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 0. "CAPIF0,Capture0 Interrupt Indication Flag\nIf channel 0 rising latch interrupt (CRL_IE0 PWMx_CAPINTEN[0]) is enabled a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly a falling transition will cause CAPIF0 to be.." "0,1" rgroup.long 0x60++0x27 line.long 0x0 "PWM1_CRL0,Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x0 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "PWM1_CFL0,Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x4 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x8 "PWM1_CRL1,Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x8 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "PWM1_CFL1,Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0xC 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x10 "PWM1_CRL2,Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x10 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "PWM1_CFL2,Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x14 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x18 "PWM1_CRL3,Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 16.--31. 1. "CRL_H,Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x18 0.--15. 1. "CRL,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "PWM1_CFL3,Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 16.--31. 1. "CFL_H,Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x1C 0.--15. 1. "CFL,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x20 "PWM1_PDMACH0,PDMA Channel 0 Captured Data" hexmask.long.byte 0x20 24.--31. 1. "PDMACH04,Captured Data Of Channel 0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the fourth byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 16.--23. 1. "PDMACH03,Captured Data Of Channel 0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the third byte of 32 bit capturing data for channel 0" newline hexmask.long.byte 0x20 8.--15. 1. "PDMACH02,Captured Data Of Channel 0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the second byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 0.--7. 1. "PDMACH01,Captured Data Of Channel 0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the for the first byte of 32 bit capturing data for channel 0" line.long 0x24 "PWM1_PDMACH2,PDMA Channel 2 Captured Data" hexmask.long.byte 0x24 24.--31. 1. "PDMACH24,Captured Data Of Channel 2\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the fourth byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 16.--23. 1. "PDMACH23,Captured Data Of Channel 2\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the third byte of 32 bit capturing data for channel 2" newline hexmask.long.byte 0x24 8.--15. 1. "PDMACH22,Captured Data Of Channel 2\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the second byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 0.--7. 1. "PDMACH21,Captured Data Of Channel 2\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the for the first byte of 32 bit capturing data for channel 2" endif sif (cpuis("NANO1*BN")) group.long 0x0++0x17 line.long 0x0 "PWM_PRES,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZ23,Dead Zone Interval Register for CH2 and CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2." hexmask.long.byte 0x0 16.--23. 1. "DZ01,Dead Zone Interval Register for CH0 and CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0." newline hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 for PWM Timer 2 3\nClock input is divided by (CP23 + 1) before it is fed to the counter 2 3" hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 for PWM Timer 0 1\nClock input is divided by (CP01 + 1) before it is fed to the counter 0 1" line.long 0x4 "PWM_CLKSEL,PWM Clock Select Register" bitfld.long 0x4 12.--14. "CLKSEL3,Timer 3 Clock Source Selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "CLKSEL2,Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CLKSEL1,Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "CLKSEL0,Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)" "0,1,2,3,4,5,6,7" line.long 0x8 "PWM_CTL,PWM Control Register" bitfld.long 0x8 27. "CH3MOD,PWM-Timer 3 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY3 to be cleared." "0: One-Shot Mode,1: Continuous Mode" bitfld.long 0x8 26. "CH3INV,PWM-Timer 3 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 24. "CH3EN,PWM-Timer 3 Enable/Disable Start Run" "0: PWM-Timer 3 Running Stopped,1: PWM-Timer 3 Start Run Enabled" bitfld.long 0x8 19. "CH2MOD,PWM-Timer 2 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY2 be cleared." "0: One-Shot Mode,1: Continuous Mode" newline bitfld.long 0x8 18. "CH2INV,PWM-Timer 2 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 16. "CH2EN,PWM-Timer 2 Enable/Disable Start Run" "0: PWM-Timer 2 Running Stopped,1: PWM-Timer 2 Start Run Enabled" newline bitfld.long 0x8 11. "CH1MOD,PWM-Timer 1 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY1 to be cleared." "0: One-Shot Mode,1: Continuous Mode" bitfld.long 0x8 10. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 8. "CH1EN,PWM-Timer 1 Enable/Disable Start Run" "0: PWM-Timer 1 Running Stopped,1: PWM-Timer 1 Start Run Enabled" bitfld.long 0x8 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair." "0: Disabled,1: Enabled" newline bitfld.long 0x8 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair." "0: Disabled,1: Enabled" bitfld.long 0x8 3. "CH0MOD,PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit it will cause CN and CM of PWM0_DUTY0 to be cleared." "0: One-Shot Mode,1: Continuous Mode" newline bitfld.long 0x8 2. "CH0INV,PWM-Timer 0 Output Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON" bitfld.long 0x8 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run" "0: PWM-Timer 0 Running Stopped,1: PWM-Timer 0 Start Run Enabled" line.long 0xC "PWM_INTEN,PWM Interrupt Enable Register" bitfld.long 0xC 3. "TMIE3,PWM Timer 3 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 2. "TMIE2,PWM Timer 2 Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 1. "TMIE1,PWM Timer 1 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 0. "TMIE0,PWM Timer 0 Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x10 "PWM_INTSTS,PWM Interrupt Indication Register" bitfld.long 0x10 8. "PresSyncFlag,Prescale Synchronize Flag\nNote: software should check this flag when writing Prescale if this flag is set and user ignore this flag and change Prescale the Prescale may be wrong for one prescale cycle" "0: Prescale has been synchronized to ECLK domain,1: Prescale is synchronizing to ECLK domain" bitfld.long 0x10 7. "Duty3Syncflag,Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3 if this flag is set and user ignore this flag and change duty3 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty3 has been synchronized to ECLK domain,1: Duty3 is synchronizing to ECLK domain" newline bitfld.long 0x10 6. "Duty2Syncflag,Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2 if this flag is set and user ignore this flag and change duty2 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty2 has been synchronized to ECLK domain,1: Duty2 is synchronizing to ECLK domain" bitfld.long 0x10 5. "Duty1Syncflag,Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1 if this flag is set and user ignore this flag and change duty1 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty1 has been synchronized to ECLK domain,1: Duty1 is synchronizing to ECLK domain" newline bitfld.long 0x10 4. "Duty0Syncflag,Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0 if this flag is set and user ignore this flag and change duty0 the corresponding CNR and CMR may be wrong for one duty cycle" "0: Duty0 has been synchronized to ECLK domain,1: Duty0 is synchronizing to ECLK domain" bitfld.long 0x10 3. "TMINT3,PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 2. "TMINT2,PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero software can clear this bit by writing a one to it." "0,1" bitfld.long 0x10 1. "TMINT1,PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero software can clear this bit by writing a one to it." "0,1" newline bitfld.long 0x10 0. "TMINT0,PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero software can clear this bit by writing a one to it." "0,1" line.long 0x14 "PWM_OE,PWM Output Enable for PWM0~PWM3" bitfld.long 0x14 3. "CH3_OE,PWM CH3 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH3 output to pin Disabled,1: PWM CH3 output to pin Enabled" bitfld.long 0x14 2. "CH2_OE,PWM CH2 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH2 output to pin Disabled,1: PWM CH2 output to pin Enabled" newline bitfld.long 0x14 1. "CH1_OE,PWM CH1 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH1 output to pin Disabled,1: PWM CH1 output to pin Enabled" bitfld.long 0x14 0. "CH0_OE,PWM CH0 Output Enable Register\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)" "0: PWM CH0 output to pin Disabled,1: PWM CH0 output to pin Enabled" group.long 0x1C++0x3 line.long 0x0 "PWM_DUTY0,PWM Counter/Comparator Register 0" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x20++0x3 line.long 0x0 "PWM_DATA0,PWM Data Register 0" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x28++0x3 line.long 0x0 "PWM_DUTY1,PWM Counter/Comparator Register 1" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x2C++0x3 line.long 0x0 "PWM_DATA1,PWM Data Register 1" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x34++0x3 line.long 0x0 "PWM_DUTY2,PWM Counter/Comparator Register 2" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x38++0x3 line.long 0x0 "PWM_DATA2,PWM Data Register 2" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x40++0x3 line.long 0x0 "PWM_DUTY3,PWM Counter/Comparator Register 3" hexmask.long.word 0x0 16.--31. 1. "CM,PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle." hexmask.long.word 0x0 0.--15. 1. "CN,PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle." rgroup.long 0x44++0x3 line.long 0x0 "PWM_DATA3,PWM Data Register 3" bitfld.long 0x0 31. "sync,Indicate that CNR value is sync to PWM counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel" "0: CNR value is sync to PWM counter,1: CNR value is not sync to PWM counter" hexmask.long.word 0x0 16.--30. 1. "PWMx_DATAy30_16,PWM Data Register \nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter\nNotes:This will be valid only for the corresponding cascade enable .bit is set" newline hexmask.long.word 0x0 0.--15. 1. "PWMx_DATAy15_0,PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter." group.long 0x54++0xB line.long 0x0 "PWM_CAPCTL,Capture Control Register" bitfld.long 0x0 31. "CAPRELOADFEN3,Reload CNR3 when CH3 falling capture Event Comes" "0: Falling capture reload for CH3 Disabled,1: Falling capture reload for CH3 Enabled" bitfld.long 0x0 30. "CAPRELOADREN3,Reload CNR3 when CH3 Rising Capture Event Comes" "0: Rising capture reload for CH3 Disabled,1: Rising capture reload for CH3 Enabled" newline bitfld.long 0x0 29. "CH23CASK,Cascade channel 2 and channel 3 PWM counter for capturing usage" "0,1" bitfld.long 0x0 28. "CH2RFORDER," "0: PWM_CFL2 is the first captured data to memory,1: PWM_CRL2 is the first captured data to memory" newline bitfld.long 0x0 26. "CAPCH3PADEN,Capture Input Enable Register" "0: OFF,1: ON" bitfld.long 0x0 25. "CAPCH3EN,Capture Channel 3 transition Enable/Disable\nWhen Enabled Capture latched the PMW-timer and saved to PWM_CRL3 (Rising latch) and PWM_CFL3 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL3 and PWM_CFL3 and disable Channel 3.." "0: Capture function on channel 3 Disabled,1: Capture function on channel 3 Enabled" newline bitfld.long 0x0 24. "INV3,Channel 3 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 23. "CAPRELOADFEN2,Reload CNR2 when CH2 capture failing event coming" "0: Failing capture reload for CH2 Disabled,1: Failing capture reload for CH2 Enabled" newline bitfld.long 0x0 22. "CAPRELOADREN2,Reload CNR2 when CH2 capture rising event coming" "0: Rising capture reload for CH2 Disabled,1: Rising capture reload for CH2 Enabled" bitfld.long 0x0 20.--21. "PDMACAPMOD2,Select CRL2 or CFL2 for PDMA Transfer" "0,1,2,3" newline bitfld.long 0x0 19. "CH2PDMAEN,Channel 2 PDMA Enable" "0: Channel 2 PDMA function Disabled,1: Channel 2 PDMA function Enabled for the channel.." bitfld.long 0x0 18. "CAPCH2PADEN,Capture Input Enable Register" "0: OFF,1: ON" newline bitfld.long 0x0 17. "CAPCH2EN,Capture Channel 2 transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWM_CRL2 (Rising latch) and PWM_CFL2 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL2 and PWM_CFL2 and disable Channel.." "0: Capture function on channel 2 Disabled,1: Capture function on channel 2 Enabled" bitfld.long 0x0 16. "INV2,Channel 2 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." newline bitfld.long 0x0 15. "CAPRELOADFEN1,Reload CNR1 when CH1 capture falling event coming" "0: Capture falling reload for CH1 Disabled,1: Capture falling reload for CH1 Enabled" bitfld.long 0x0 14. "CAPRELOADREN1,Reload CNR1 when CH1 Capture Rising Event Comes" "0: Rising capture reload for CH1 Disabled,1: Rising capture reload for CH1 Enabled" newline bitfld.long 0x0 13. "CH01CASK,Cascade channel 0 and channel 1 PWM timer for capturing usage" "0,1" bitfld.long 0x0 12. "CH0RFORDER," "0: PWM_CFL0 is the first captured data to memory,1: PWM_CRL0 is the first captured data to memory" newline bitfld.long 0x0 10. "CAPCH1PADEN,Capture Input Enable Register" "0: OFF,1: ON" bitfld.long 0x0 9. "CAPCH1EN,Capture Channel 1 transition Enable/Disable\nWhen Enabled Capture latched the PMW-counter and saved to PWM_CRL1 (Rising latch) and PWM_CFL1 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL1 and PWM_CFL1 and disable Channel 1.." "0: Capture function on channel 1 Disabled,1: Capture function on channel 1 Enabled" newline bitfld.long 0x0 8. "INV1,Channel 1 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." bitfld.long 0x0 7. "CAPRELOADFEN0,Reload CNR0 when CH0 Capture Falling Event Comes" "0: Falling capture reload for CH0 Disabled,1: Falling capture reload for CH0 Enabled" newline bitfld.long 0x0 6. "CAPRELOADREN0,Reload CNR0 when CH0 Capture Rising Event Comes" "0: Rising capture reload for CH0 Disabled,1: Rising capture reload for CH0 Enabled" bitfld.long 0x0 4.--5. "PDMACAPMOD0,Select CRL0 or CFL0 for PDMA Transfer" "0,1,2,3" newline bitfld.long 0x0 3. "CH0PDMAEN,Channel 0 PDMA Enable" "0: Channel 0 PDMA function Disabled,1: Channel 0 PDMA function Enabled for the channel.." bitfld.long 0x0 2. "CAPCH0PADEN,Capture Input Enable Register" "0: OFF,1: ON" newline bitfld.long 0x0 1. "CAPCH0EN,Capture Channel 0 transition Enable/Disable\nWhen Enabled Capture latched the PWM-timer value and saved to PWM_CRL0 (Rising latch) and PWM_CFL0 (Falling latch).\nWhen Disabled Capture does not update PWM_CRL0 and PWM_CFL0 and disable Channel.." "0: Capture function on channel 0 Disabled,1: Capture function on channel 0 Enabled" bitfld.long 0x0 0. "INV0,Channel 0 Inverter ON/OFF" "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." line.long 0x4 "PWM_CAPINTEN,Capture interrupt enable Register" bitfld.long 0x4 25. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 24. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 3 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 17. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 16. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 2 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 9. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 8. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable \nWhen Enabled if Capture detects Channel 1 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" newline bitfld.long 0x4 1. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 0 has falling transition Capture issues an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled" bitfld.long 0x4 0. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled if Capture detects Channel 0 has rising transition Capture issues an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled" line.long 0x8 "PWM_CAPINTSTS,Capture Interrupt Indication Register" bitfld.long 0x8 28. "CAPOVF3,Capture Falling Flag Over Run for Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 bit 26 of PWM_CAPINTSTS" "0,1" bitfld.long 0x8 27. "CAPOVR3,Capture Rising Flag Over Run for Channel 3\nThis flag indicate CRL3update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 bit 25 of PWM_CAPINTSTS" "0,1" newline bitfld.long 0x8 26. "CFLI3,PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 25. "CRLI3,PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 24. "CAPIF3,Capture3 Interrupt Indication Flag" "0,1" bitfld.long 0x8 20. "CAPOVF2,Capture Falling Flag Over Run for Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 bit 18 of PWM_CAPINTSTS" "0,1" newline bitfld.long 0x8 19. "CAPOVR2,Capture Rising Flag Over Run for Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 bit 17 of PWM_CAPINTSTS" "0,1" bitfld.long 0x8 18. "CFLI2,PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 17. "CRLI2,PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 16. "CAPIF2,Capture2 Interrupt Indication Flag" "0,1" newline bitfld.long 0x8 12. "CAPOVF1,Capture Falling Flag Over Run for Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 bit 10 of PWM_CAPINTSTS" "0,1" bitfld.long 0x8 11. "CAPOVR1,Capture Rising Flag Over Run for Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 bit 9 of PWM_CAPINTSTS" "0,1" newline bitfld.long 0x8 10. "CFLI1,PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition PWM0_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 9. "CRLI1,PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition PWM0_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 8. "CAPIF1,Capture1 Interrupt Indication Flag" "0,1" bitfld.long 0x8 4. "CAPOVF0,Capture Falling Flag Over Run for Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set." "0,1" newline bitfld.long 0x8 3. "CAPOVR0,Capture Rising Flag Over Run for Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 bit 1 of PWM_CAPINTSTS." "0,1" bitfld.long 0x8 2. "CFLRI0,PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" newline bitfld.long 0x8 1. "CRLI0,PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing 1 to it." "0,1" bitfld.long 0x8 0. "CAPIF0,Capture0 Interrupt Indication Flag" "0,1" rgroup.long 0x60++0x27 line.long 0x0 "PWM_CRL0,Capture Rising Latch Register (Channel 0)" hexmask.long.word 0x0 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x0 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x4 "PWM_CFL0,Capture Falling Latch Register (Channel 0)" hexmask.long.word 0x4 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x4 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x8 "PWM_CRL1,Capture Rising Latch Register (Channel 1)" hexmask.long.word 0x8 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x8 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0xC "PWM_CFL1,Capture Falling Latch Register (Channel 1)" hexmask.long.word 0xC 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0xC 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x10 "PWM_CRL2,Capture Rising Latch Register (Channel 2)" hexmask.long.word 0x10 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x10 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x14 "PWM_CFL2,Capture Falling Latch Register (Channel 2)" hexmask.long.word 0x14 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x14 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x18 "PWM_CRL3,Capture Rising Latch Register (Channel 3)" hexmask.long.word 0x18 16.--31. 1. "CRL31_16,Upper Half Word of 32-bit Capture Data when Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CRL0 and CRL2 are also extend to 32 bit " hexmask.long.word 0x18 0.--15. 1. "CRL15_0,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition." line.long 0x1C "PWM_CFL3,Capture Falling Latch Register (Channel 3)" hexmask.long.word 0x1C 16.--31. 1. "CFL31_16,Upper Half Word of 32-bit Capture Data When Cascade Enabled\nWhen cascade is enabled for capture channel 0 2 the original 16 bit counter extend to 32 bit and capture result CFL0 and CFL2 are also extend to 32 bit " hexmask.long.word 0x1C 0.--15. 1. "CFL15_0,Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition." line.long 0x20 "PWM_PDMACH0,PDMA channel 0 captured data" hexmask.long.byte 0x20 24.--31. 1. "Captureddata31_24,PDMACH0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the 4th byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 16.--23. 1. "Captureddata23_16,PDMACH0\nWhen CH01CASK is disabled this byte is 0\nWhen CH01CASK is enabled It is the third byte of 32 bit capturing data for channel 0" newline hexmask.long.byte 0x20 8.--15. 1. "Captureddata15_8,PDMACH0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the second byte of 32 bit capturing data for channel 0" hexmask.long.byte 0x20 0.--7. 1. "Captureddata7_0,PDMACH0\nWhen CH01CASK is disabled it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled It is the for the first byte of 32 bit capturing data for channel 0" line.long 0x24 "PWM_PDMACH2,PDMA channel 2 captured data" hexmask.long.byte 0x24 24.--31. 1. "Captureddata31_24,PDMACH0\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the 4th byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 16.--23. 1. "Captureddata23_16,PDMACH0\nWhen CH23CASK is disabled this byte is 0\nWhen CH23CASK is enabled It is the third byte of 32 bit capturing data for channel 2" newline hexmask.long.byte 0x24 8.--15. 1. "Captureddata15_8,PDMACH0\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the second byte of 32 bit capturing data for channel 2" hexmask.long.byte 0x24 0.--7. 1. "Captureddata7_0,PDMACH0\nWhen CH23CASK is disabled it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled It is the for the first byte of 32 bit capturing data for channel 2" endif tree.end tree.end tree "RTC (Real Time Clock)" base ad:0x40008000 group.long 0x0++0x23 line.long 0x0 "RTC_INIR,RTC Initiation Register" sif (cpuis("NANO1*AN")) hexmask.long 0x0 0.--31. 1. "INIR,RTC Initiation (Write Only)\nWhen RTC block is powered on RTC is at reset state. User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357 the RTC will be in un-reset state.." endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 0. "ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state" newline endif sif (cpuis("NANO1*BN")) hexmask.long 0x0 0.--31. 1. "INIR,RTC Initiation (Write Only)\nWhen RTC block is powered on RTC is at reset state. User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357 the RTC will be in un-reset state.." endif line.long 0x4 "RTC_AER,RTC Access Enable Register" rbitfld.long 0x4 16. "ENF,RTC Register Access Enable Flag (Read Only)\n" "0: RTC register read/write disable,1: RTC register read/write enable" sif (cpuis("NANO1*AN")) hexmask.long.word 0x4 0.--15. 1. "AER,RTC Register Access Enable Password (Write Only)\n" newline endif sif (cpuis("NANO1*BN")) hexmask.long.word 0x4 0.--15. 1. "AER,RTC Register Access Enable Password (Write Only)" endif line.long 0x8 "RTC_FCR,RTC Frequency Compensation Register" hexmask.long.byte 0x8 8.--11. 1. "INTEGER,Integer Part\n" hexmask.long.byte 0x8 0.--5. 1. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number." line.long 0xC "RTC_TLR,Time Loading Register" bitfld.long 0xC 20.--21. "_10HR,10 Hour Time Digit (0~2)" "0,1,2,3" hexmask.long.byte 0xC 16.--19. 1. "_1HR,1 Hour Time Digit (0~9)" newline bitfld.long 0xC 12.--14. "_10MIN,10 Min Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "_1MIN,1 Min Time Digit (0~9)" newline bitfld.long 0xC 4.--6. "_10SEC,10 Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "_1SEC,1 Sec Time Digit (0~9)" line.long 0x10 "RTC_CLR,Calendar Loading Register" hexmask.long.byte 0x10 20.--23. 1. "_10YEAR,10 Year Calendar Digit (0~9)" hexmask.long.byte 0x10 16.--19. 1. "_1YEAR,1 Year Calendar Digit (0~9)" newline bitfld.long 0x10 12. "_10MON,10 Month Calendar Digit (0~1)" "0,1" hexmask.long.byte 0x10 8.--11. 1. "_1MON,1 Month Calendar Digit (0~9)" newline bitfld.long 0x10 4.--5. "_10DAY,10 Day Calendar Digit (0~3)" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "_1DAY,1 Day Calendar Digit (0~9)" line.long 0x14 "RTC_TSSR,Time Scale Selection Register" bitfld.long 0x14 0. "_24hr_12hr,24-Hour / 12-Hour Mode Selection\n" "0: select 12-hour time scale with AM and PM..,1: select 24-hour time scale" line.long 0x18 "RTC_DWR,Day of the Week Register" bitfld.long 0x18 0.--2. "DWR,Day Of The Week Register \n" "0,1,2,3,4,5,6,7" line.long 0x1C "RTC_TAR,Time Alarm Register" bitfld.long 0x1C 20.--21. "_10HR,10 Hour Time Digit of Alarm Setting (0~2)" "0,1,2,3" hexmask.long.byte 0x1C 16.--19. 1. "_1HR,1 Hour Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 12.--14. "_10MIN,10 Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--11. 1. "_1MIN,1 Min Time Digit of Alarm Setting (0~9)" newline bitfld.long 0x1C 4.--6. "_10SEC,10 Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--3. 1. "_1SEC,1 Sec Time Digit of Alarm Setting (0~9)" line.long 0x20 "RTC_CAR,Calendar Alarm Register" hexmask.long.byte 0x20 20.--23. 1. "_10YEAR,10 Year Calendar Digit of Alarm Setting (0~9)" hexmask.long.byte 0x20 16.--19. 1. "_1YEAR,1 Year Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 12. "_10MON,10 Month Calendar Digit of Alarm Setting (0~1)" "0,1" hexmask.long.byte 0x20 8.--11. 1. "_1MON,1 Month Calendar Digit of Alarm Setting (0~9)" newline bitfld.long 0x20 4.--5. "_10DAY,10 Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "_1DAY,1 Day Calendar Digit of Alarm Setting (0~9)" rgroup.long 0x24++0x3 line.long 0x0 "RTC_LIR,RTC Leap Year Indication Register" bitfld.long 0x0 0. "LIR,Leap Year Indication REGISTER (Read Only)\n" "0: This year is not a leap year,1: This year is leap year" group.long 0x28++0xB line.long 0x0 "RTC_RIER,RTC Interrupt Enable Register" bitfld.long 0x0 2. "SNOOPIER,Snooper Pin Event Detection Interrupt Enable\n" "0: Snooper Pin Event Detection Interrupt is disabled,1: Snooper Pin Event Detection Interrupt is enabled" bitfld.long 0x0 1. "TIER,Time Tick Interrupt And Wake-Up By Tick Enable\n" "0: RTC Time Tick Interrupt is disabled,1: RTC Time Tick Interrupt is enabled" newline bitfld.long 0x0 0. "AIER,Alarm Interrupt Enable\n" "0: RTC Alarm Interrupt is disabled,1: RTC Alarm Interrupt is enabled" line.long 0x4 "RTC_RIIR,RTC Interrupt Indicator Register" bitfld.long 0x4 2. "SNOOPIS,Snooper Pin Event Detection Interrupt Status\nWhen SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin this flag will be set. While this bit is set and SNOOPIER is also high RTC will generate an interrupt to CPU.\nWrite.." "0: Snooper pin event defined by SNOOPEDGE never..,1: Snooper pin event defined by SNOOPEDGE detected" bitfld.long 0x4 1. "TIS,RTC Time Tick Interrupt Status\nRTC unit will set TIF to high periodically in the period selected by TTR(RTC_TTR[2:0]). When this bit is set and TIER is also high RTC will generate an interrupt to CPU.\nThis bit is software clear by writing '1' to.." "0: Indicates RCT Time Tick Interrupt condition..,1: Indicates RTC Time Tick Interrupt is requested" newline bitfld.long 0x4 0. "AIS,RTC Alarm Interrupt Status\nRTC unit will set AIF to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR. When this bit is set and AIER is also high RTC will generate an interrupt to CPU.\nThis bit is.." "0: Indicates RCT Alarm Interrupt condition never..,1: Indicates RTC Alarm Interrupt is requested if.." line.long 0x8 "RTC_TTR,RTC Time Tick Register" bitfld.long 0x8 3. "TWKE,RTC Timer Wake-Up CPU Function Enable Bit\nIf TWKE is set before CPU enters power-down mode when a RTC Time Tick CPU will be wakened up by RTC unit.\nNote: Tick timer setting follows the TTR description." "0: Time Tick wake-up CPU function Disabled,1: Wake-up function Enabled so that CPU can be.." bitfld.long 0x8 0.--2. "TTR,Time Tick Register\n" "0,1,2,3,4,5,6,7" group.long 0x3C++0x53 line.long 0x0 "RTC_SPRCTL,RTC Spare Functional Control Register" bitfld.long 0x0 7. "SPRRDY,SPR Register Ready\nThis bit indicates if the registers SPR0 ~ SPR19 are ready to read.\nAfter CPU writing registers SPR0 ~ SPR19 polling this bit to check if SP0 ~ SPR19 are updated done is necessary.\nThis it is a read only bit and any write to.." "0: SPR0 ~ SPR19 updating is in progress,1: SPR0 ~ SPR19 are updated done and ready to read" bitfld.long 0x0 1. "SNOOPEDGE,Snooper Active Edge Selection\nThis bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers.\n" "0: Rising edge of snooper pin generates snooper pin..,1: Falling edge of snooper pin generates snooper.." newline bitfld.long 0x0 0. "SNOOPEN,Snooper Pin Event Detection Enable\nThis bit enables the snooper pin event detection.\nWhen this bit is set high and an event defined by SNOOPEDGE detected the 20 spare registers will be cleared to '0' by hardware automatically. And the SNOOPIF.." "0: Snooper pin event detection function Disabled,1: Snooper pin event detection function Enabled" line.long 0x4 "RTC_SPR0,RTC Spare Register 0" hexmask.long 0x4 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x8 "RTC_SPR1,RTC Spare Register 1" hexmask.long 0x8 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0xC "RTC_SPR2,RTC Spare Register 2" hexmask.long 0xC 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x10 "RTC_SPR3,RTC Spare Register 3" hexmask.long 0x10 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x14 "RTC_SPR4,RTC Spare Register 4" hexmask.long 0x14 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x18 "RTC_SPR5,RTC Spare Register 5" hexmask.long 0x18 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x1C "RTC_SPR6,RTC Spare Register 6" hexmask.long 0x1C 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x20 "RTC_SPR7,RTC Spare Register 7" hexmask.long 0x20 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x24 "RTC_SPR8,RTC Spare Register 8" hexmask.long 0x24 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x28 "RTC_SPR9,RTC Spare Register 9" hexmask.long 0x28 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x2C "RTC_SPR10,RTC Spare Register 10" hexmask.long 0x2C 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x30 "RTC_SPR11,RTC Spare Register 11" hexmask.long 0x30 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x34 "RTC_SPR12,RTC Spare Register 12" hexmask.long 0x34 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x38 "RTC_SPR13,RTC Spare Register 13" hexmask.long 0x38 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x3C "RTC_SPR14,RTC Spare Register 14" hexmask.long 0x3C 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x40 "RTC_SPR15,RTC Spare Register 15" hexmask.long 0x40 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x44 "RTC_SPR16,RTC Spare Register 16" hexmask.long 0x44 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x48 "RTC_SPR17,RTC Spare Register 17" hexmask.long 0x48 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x4C "RTC_SPR18,RTC Spare Register 18" hexmask.long 0x4C 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." line.long 0x50 "RTC_SPR19,RTC Spare Register 19" hexmask.long 0x50 0.--31. 1. "SPARE,SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected." tree.end tree "SC (Smart Card Host Interface)" base ad:0x0 tree "SC0" base ad:0x40190000 rgroup.long 0x0++0x3 line.long 0x0 "SC_RBR,SC Receiving Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "RBR,Receiving Buffer \nBy reading RBR the SC will return an 8-bit received data." wgroup.long 0x0++0x3 line.long 0x0 "SC_THR,SC Transmit Holding Register." hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Buffer\nBy writing data to THR the SC will send out an 8-bit data.\nNote: If SC_CEN (SC_CTL[0]) is not enabled THR cannot be programmed." group.long 0x4++0x17 line.long 0x0 "SC_CTL,SC Control Register." sif (cpuis("NANO1*AN")) bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n" "0: De-bounce sample card insert once per 384 (128 *..,1: De-bounce sample card insert once per 192 (64 *..,?,?" bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection \n" "0: All internal timer function Disabled,1: Internal 24-bit timer Enabled. Software can..,?,?" newline bitfld.long 0x0 6.--7. "RX_FTRI_LEV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV the RDA_IF will be set (if RDA_IEN (IER[0]) is enabled an interrupt will be generated).\n" "0: INTR_RDA Trigger Level with 01 byte,1: INTR_RDA Trigger Level with 02 bytes,?,?" bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection\nNote: If AUTO_CON_EN (SC_CTL[3]) enabled this fields are ignored." "0: Direct convention,1: Reserved,?,?" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-Bounce Select Register" "0,1,2,3" endif bitfld.long 0x0 23. "TX_ERETRY_EN,TX Error Retry Enable Control\nThis bit enables transmitter retry function when parity error has occurred.\n" "0: TX error retry function Disabled,1: TX error retry function Enabled" newline bitfld.long 0x0 20.--22. "TX_ERETRY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field.." "?,1: The real retry number is TX_ERETRY + 1,2: This field cannot be changed when TX_ERETRY_EN..,?,?,?,?,?" bitfld.long 0x0 19. "RX_ERETRY_EN,RX Error Retry Enable Control\n" "0: RX error retry function Disabled,1: RX error retry function Enabled" newline bitfld.long 0x0 16.--18. "RX_ERETRY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field cannot.." "?,1: The real retry number is RX_ERETRY + 1,2: This field cannot be changed when RX_ERETRY_EN..,?,?,?,?,?" bitfld.long 0x0 15. "SLEN,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU" newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection" "0,1,2,3" endif hexmask.long.byte 0x0 8.--12. 1. "BGT,Block Guard Time (BGT)\n\nIn RX mode software can enable RX_BGT_EN (SC_ALTCTL[12]) to detect the first coming character timing. If the incoming data timing less than BGT an interrupt will be generated.\nNote: The real block guard time is BGT + 1." newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 6.--7. "RX_FTRI_LEV,RX Buffer Trigger Level" "0,1,2,3" bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection" "0,1,2,3" newline endif bitfld.long 0x0 3. "AUTO_CON_EN,Auto Convention Enable Control\n" "0: Auto-convention Disabled,1: Auto-convention Enabled. When hardware receives.." bitfld.long 0x0 2. "DIS_TX,TX Transition Disable Control\n" "0: The transceiver Enabled,1: The transceiver Disabled" newline bitfld.long 0x0 1. "DIS_RX,RX Transition Disable Control\nNote: If AUTO_CON_EN (SC_CTL[3]) is enabled these fields must be ignored." "0: The receiver Enabled,1: The receiver Disabled" bitfld.long 0x0 0. "SC_CEN,SC Engine Enable Control\nSet this bit to 1 to enable SC operation. If this bit is cleared SC will force all transition to IDLE state" "0,1" line.long 0x4 "SC_ALTCTL,SC Alternate Control Register." sif (cpuis("NANO1*AN")) bitfld.long 0x4 16. "OUTSEL,Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode\n" "0: Quasi mode,1: Open-drain mode" endif rbitfld.long 0x4 15. "TMR2_ATV,Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n" "0: Timer2 is not active,1: Timer2 is active" newline rbitfld.long 0x4 14. "TMR1_ATV,Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n" "0: Timer1 is not active,1: Timer1 is active" rbitfld.long 0x4 13. "TMR0_ATV,Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n" "0: Timer0 is not active,1: Timer0 is active" newline bitfld.long 0x4 12. "RX_BGT_EN,Receiver Block Guard Time Function Enable Control\n" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled" bitfld.long 0x4 8.--9. "INIT_SEL,Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in 5.14.4.1.\nWarm-reset: refer to Warm-Reset Sequence.." "0,1,2,3" newline bitfld.long 0x4 7. "TMR2_SEN,Internal Timer2 Start Enable Control\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill.." "0: Stop counting,1: Start counting" bitfld.long 0x4 6. "TMR1_SEN,Internal Timer1 Start Enable Control\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill.." "0: Stop counting,1: Start counting" newline bitfld.long 0x4 5. "TMR0_SEN,Internal Timer0 Start Enable Control\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill.." "0: Stop counting,1: Start counting" bitfld.long 0x4 4. "WARST_EN,Warm Reset Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be.." "0: No effect,1: When the warm reset sequence completed" newline bitfld.long 0x4 3. "ACT_EN,Activation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be set.." "0: No effect,1: When the activation sequence completed" bitfld.long 0x4 2. "DACT_EN,Deactivation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will.." "0: No effect,1: When the deactivation sequence completed" newline bitfld.long 0x4 1. "RX_RST,Rx Software Reset\nWhen RX_RST (SC_ALTCTL[1]) is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers" bitfld.long 0x4 0. "TX_RST,TX Software Reset\nWhen TX_RST (SC_ALTCTL[0]) is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers" line.long 0x8 "SC_EGTR,SC Extend Guard Time Register." hexmask.long.byte 0x8 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT." line.long 0xC "SC_RFTMR,SC Receive Buffer Time-out Register." hexmask.long.word 0xC 0.--8. 1. "RFTM,SC Receiver Buffer Time-Out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Fill all 0 to this field indicates to disable this function." line.long 0x10 "SC_ETUCR,SC ETU Control Register." bitfld.long 0x10 15. "COMPEN_EN,Compensation Mode Enable Control\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and n-1 clock cycles where n is the value to be written into the ETU_RDIV .\n" "0: Compensation function Disabled,1: Compensation function Enabled" hexmask.long.word 0x10 0.--11. 1. "ETU_RDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field but this field must be greater than 0x004." line.long 0x14 "SC_IER,SC Interrupt Enable Control Register." sif (cpuis("NANO1*BN")) bitfld.long 0x14 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and (n-1) clock cycles where n is the value to be written into the ETU_RDIV register." "0: Compensation function Disabled,1: Compensation function Enabled" endif bitfld.long 0x14 10. "ACON_ERR_IE,Auto Convention Error Interrupt Enable Control \nThis field is used for auto-convention error interrupt enable.\n" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled" newline bitfld.long 0x14 9. "RTMR_IE,Receiver Buffer Time-Out Interrupt Enable Control \nThis field is used for receiver buffer time-out interrupt enable.\n" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled" bitfld.long 0x14 8. "INIT_IE,Initial End Interrupt Enable Control\n" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled" newline bitfld.long 0x14 7. "CD_IE,Card Detect Interrupt Enable Control\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F (SC_SR[12]) \n" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled" bitfld.long 0x14 6. "BGT_IE,Block Guard Time Interrupt Enable Control\nThis field is used for block guard time interrupt enable.\n" "0: Block guard time Disabled,1: Block guard time Enabled" newline bitfld.long 0x14 5. "TMR2_IE,Timer2 Interrupt Enable Control\nThis field is used for TMR2 interrupt enable.\n" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled" bitfld.long 0x14 4. "TMR1_IE,Timer1 Interrupt Enable Control\nThis field is used to enable the TMR1 interrupt.\n" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled" newline bitfld.long 0x14 3. "TMR0_IE,Timer0 Interrupt Enable Control\nThis field is used to enable the TMR0 interrupt.\n" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled" bitfld.long 0x14 2. "TERR_IE,Transfer Error Interrupt Enable Control\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]) frame error RX_EFR_F (SC_SR[5]) parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled" newline bitfld.long 0x14 1. "TBE_IE,Transmit Buffer Empty Interrupt Enable Control\nThis field is used for transmit buffer empty interrupt enable.\n" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled" bitfld.long 0x14 0. "RDA_IE,Receive Data Reach Interrupt Enable Control\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled" rgroup.long 0x1C++0x3 line.long 0x0 "SC_ISR,SC Interrupt Status Register." bitfld.long 0x0 10. "ACON_ERR_IS,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F this bit will be set.\nNote: This bit is read only but it can be cleared.." "0,1" bitfld.long 0x0 9. "RTMR_IS,Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1" newline bitfld.long 0x0 8. "INIT_IS,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN (SC_ALTCTL[3])) deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only .." "0,1" bitfld.long 0x0 7. "CD_IS,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F (SC_SR[11]).\nNote: This field is the status flag of CD_INS_F (SC_SR[12]) .." "0,1" newline bitfld.long 0x0 6. "BGT_IS,\n" "0,1" bitfld.long 0x0 5. "TMR2_IS,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 4. "TMR1_IS,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" bitfld.long 0x0 3. "TMR0_IS,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 2. "TERR_IS,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]) frame error RX_EFR_F.." "0,1" bitfld.long 0x0 1. "TBE_IS,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1" newline bitfld.long 0x0 0. "RDA_IS,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV.." "0,1" group.long 0x20++0x17 line.long 0x0 "SC_TRSR,SC Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0x0 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\n" "0: This bit is cleared automatically when TX..,1: This bit is set by hardware when TX transfer is.." rbitfld.long 0x0 30. "TX_OVER_REERR,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline rbitfld.long 0x0 29. "TX_REERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU." "?,1: This bit is read only" rbitfld.long 0x0 24.--25. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3" newline rbitfld.long 0x0 22. "RX_OVER_REERR,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries.." "?,1: This bit is read only" rbitfld.long 0x0 21. "RX_REERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "?,1: This bit is read only" newline rbitfld.long 0x0 16.--17. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F (SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU .." "0,1,2,3" rbitfld.long 0x0 13. "CD_PIN_F,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: The SC_CD pin state at low,1: The SC_CD pin state at high" newline rbitfld.long 0x0 12. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: The card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" rbitfld.long 0x0 11. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.\nThis bit is cleared automatically when TX transfer is finished and the STOP bit (include guard.." "0,1" rbitfld.long 0x0 30. "TX_OVER_ERETRY,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x0 29. "TX_ERETRY_F,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and can not generate any interrupt to CPU." "?,1: This bit is read only" endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 24.--26. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3,4,5,6,7" newline endif rbitfld.long 0x0 23. "RX_ATV,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1" sif (cpuis("NANO1*BN")) rbitfld.long 0x0 22. "RX_OVER_ERETRY,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU enables receiver retries.." "?,1: This bit is read only" newline rbitfld.long 0x0 21. "RX_ERETRY_F,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and can not generate any interrupt.." "?,1: This bit is read only" endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 16.--18. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F increases one. When one byte of RX buffer is read by CPU RX_POINT_F decreases.." "0,1,2,3,4,5,6,7" newline endif rbitfld.long 0x0 10. "TX_FULL_F,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1" rbitfld.long 0x0 9. "TX_EMPTY_F,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data.." "0,1" newline rbitfld.long 0x0 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to SC_THR will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" rbitfld.long 0x0 6. "RX_EBR_F,Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + data bits.." "?,1: This bit is read only" newline rbitfld.long 0x0 5. "RX_EFR_F,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic 0). \nNote1: This.." "?,1: This bit is read only" rbitfld.long 0x0 4. "RX_EPA_F,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver.." "?,1: This bit is read only" newline rbitfld.long 0x0 2. "RX_FULL_F,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1" rbitfld.long 0x0 1. "RX_EMPTY_F,Receiver Buffer Empty Status Flag (Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU hardware sets this bit high. It will be cleared when SC receives any new data." "0,1" newline rbitfld.long 0x0 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing.." "0,1" line.long 0x4 "SC_PINCSR,SC Pin Control State Register." rbitfld.long 0x4 16. "SC_DATA_I_ST,SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_I\n" "0: The SC_DATA_I pin is low,1: The SC_DATA_I pin is high" bitfld.long 0x4 10. "CD_LEV,Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine enable" "0: When hardware detects the card detect pin from..,1: When hardware detects the card detect pin from.." newline bitfld.long 0x4 9. "SC_DATA_O,SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically. So don't.." "0: Drive SC_DATA_O pin to low,1: Drive SC_DATA_O pin to high" rbitfld.long 0x4 8. "SC_OEN_ST,SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n" "0: The SC_DATA_OEN pin state at low,1: The SC_DATA_OEN pin state at high" newline bitfld.long 0x4 7. "ADAC_CD_EN,Auto Deactivation When Card Removal\nNote: When the card is removal hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an interrupt INT_INIT to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.." bitfld.long 0x4 6. "CLK_KEEP,SC Clock Enable Control \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running" newline sif (cpuis("NANO1*BN")) bitfld.long 0x4 5. "CLK_STOP_LEV,SC Clock Stop Level\nThis field indicates the clock polarity control in clock stop mode." "0: SC_CLK stopped in low level,1: SC_CLK stopped in high level" endif rbitfld.long 0x4 4. "CD_PIN_ST,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: SC_CD pin state at low,1: SC_CD pin state at high" newline rbitfld.long 0x4 3. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" rbitfld.long 0x4 2. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" newline bitfld.long 0x4 1. "SC_RST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.." bitfld.long 0x4 0. "POW_EN,SC_POW_EN Pin Signal\nSoftware can set POW_EN and POW_INV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin.." "0: SC_PWR pin status is low,1: SC_PWR pin status is high" line.long 0x8 "SC_TMR0,SC Internal Timer Control Register 0." hexmask.long.byte 0x8 24.--27. 1. "MODE,Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection." hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values." line.long 0xC "SC_TMR1,SC Internal Timer Control Register 1." hexmask.long.byte 0xC 24.--27. 1. "MODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection." hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values." line.long 0x10 "SC_TMR2,SC Internal Timer Control Register 2." hexmask.long.byte 0x10 24.--27. 1. "MODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection" hexmask.long.byte 0x10 0.--7. 1. "CNT,Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values." line.long 0x14 "SC_UACTL,SC UART Mode Control Register." bitfld.long 0x14 7. "OPE,Odd Parity Enable Control\nNote: This bit has effect only when PBDIS bit is '0'." "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or check.." bitfld.long 0x14 6. "PBDIS,Parity Bit Disable Control\nNote: In smart card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).." newline sif (cpuis("NANO1*AN")) bitfld.long 0x14 4.--5. "DATA_LEN,Data Length\nNote: In smart card mode this DATA_LEN must be '00'" "0: Character Data Length is 8 bits,1: Character Data Length is 7 bits,?,?" endif sif (cpuis("NANO1*BN")) bitfld.long 0x14 4.--5. "DATA_LEN,Data Length" "0,1,2,3" newline endif bitfld.long 0x14 0. "UA_MODE_EN,UART Mode Enable Control\nNote3: When UART is enabled hardware will generate a reset to reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode" rgroup.long 0x38++0x7 line.long 0x0 "SC_TDRA,SC Timer Current Data Register A." hexmask.long.tbyte 0x0 0.--23. 1. "TDR0,Timer0 Current Data Value (Read Only)\nThis field indicates the current count values of Timer0." line.long 0x4 "SC_TDRB,SC Timer Current Data Register B." hexmask.long.byte 0x4 8.--15. 1. "TDR2,Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of Timer2." hexmask.long.byte 0x4 0.--7. 1. "TDR1,Timer1 Current Data Value (Read Only)\nThis field indicates the current count values of Timer1." tree.end tree "SC1" base ad:0x401B0000 rgroup.long 0x0++0x3 line.long 0x0 "SC_RBR,SC Receiving Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "RBR,Receiving Buffer \nBy reading RBR the SC will return an 8-bit received data." wgroup.long 0x0++0x3 line.long 0x0 "SC_THR,SC Transmit Holding Register." hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Buffer\nBy writing data to THR the SC will send out an 8-bit data.\nNote: If SC_CEN (SC_CTL[0]) is not enabled THR cannot be programmed." group.long 0x4++0x17 line.long 0x0 "SC_CTL,SC Control Register." sif (cpuis("NANO1*AN")) bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n" "0: De-bounce sample card insert once per 384 (128 *..,1: De-bounce sample card insert once per 192 (64 *..,?,?" bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection \n" "0: All internal timer function Disabled,1: Internal 24-bit timer Enabled. Software can..,?,?" newline bitfld.long 0x0 6.--7. "RX_FTRI_LEV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV the RDA_IF will be set (if RDA_IEN (IER[0]) is enabled an interrupt will be generated).\n" "0: INTR_RDA Trigger Level with 01 byte,1: INTR_RDA Trigger Level with 02 bytes,?,?" bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection\nNote: If AUTO_CON_EN (SC_CTL[3]) enabled this fields are ignored." "0: Direct convention,1: Reserved,?,?" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-Bounce Select Register" "0,1,2,3" endif bitfld.long 0x0 23. "TX_ERETRY_EN,TX Error Retry Enable Control\nThis bit enables transmitter retry function when parity error has occurred.\n" "0: TX error retry function Disabled,1: TX error retry function Enabled" newline bitfld.long 0x0 20.--22. "TX_ERETRY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field.." "?,1: The real retry number is TX_ERETRY + 1,2: This field cannot be changed when TX_ERETRY_EN..,?,?,?,?,?" bitfld.long 0x0 19. "RX_ERETRY_EN,RX Error Retry Enable Control\n" "0: RX error retry function Disabled,1: RX error retry function Enabled" newline bitfld.long 0x0 16.--18. "RX_ERETRY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field cannot.." "?,1: The real retry number is RX_ERETRY + 1,2: This field cannot be changed when RX_ERETRY_EN..,?,?,?,?,?" bitfld.long 0x0 15. "SLEN,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU" newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection" "0,1,2,3" endif hexmask.long.byte 0x0 8.--12. 1. "BGT,Block Guard Time (BGT)\n\nIn RX mode software can enable RX_BGT_EN (SC_ALTCTL[12]) to detect the first coming character timing. If the incoming data timing less than BGT an interrupt will be generated.\nNote: The real block guard time is BGT + 1." newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 6.--7. "RX_FTRI_LEV,RX Buffer Trigger Level" "0,1,2,3" bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection" "0,1,2,3" newline endif bitfld.long 0x0 3. "AUTO_CON_EN,Auto Convention Enable Control\n" "0: Auto-convention Disabled,1: Auto-convention Enabled. When hardware receives.." bitfld.long 0x0 2. "DIS_TX,TX Transition Disable Control\n" "0: The transceiver Enabled,1: The transceiver Disabled" newline bitfld.long 0x0 1. "DIS_RX,RX Transition Disable Control\nNote: If AUTO_CON_EN (SC_CTL[3]) is enabled these fields must be ignored." "0: The receiver Enabled,1: The receiver Disabled" bitfld.long 0x0 0. "SC_CEN,SC Engine Enable Control\nSet this bit to 1 to enable SC operation. If this bit is cleared SC will force all transition to IDLE state" "0,1" line.long 0x4 "SC_ALTCTL,SC Alternate Control Register." sif (cpuis("NANO1*AN")) bitfld.long 0x4 16. "OUTSEL,Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode\n" "0: Quasi mode,1: Open-drain mode" endif rbitfld.long 0x4 15. "TMR2_ATV,Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n" "0: Timer2 is not active,1: Timer2 is active" newline rbitfld.long 0x4 14. "TMR1_ATV,Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n" "0: Timer1 is not active,1: Timer1 is active" rbitfld.long 0x4 13. "TMR0_ATV,Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n" "0: Timer0 is not active,1: Timer0 is active" newline bitfld.long 0x4 12. "RX_BGT_EN,Receiver Block Guard Time Function Enable Control\n" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled" bitfld.long 0x4 8.--9. "INIT_SEL,Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in 5.14.4.1.\nWarm-reset: refer to Warm-Reset Sequence.." "0,1,2,3" newline bitfld.long 0x4 7. "TMR2_SEN,Internal Timer2 Start Enable Control\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill.." "0: Stop counting,1: Start counting" bitfld.long 0x4 6. "TMR1_SEN,Internal Timer1 Start Enable Control\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill.." "0: Stop counting,1: Start counting" newline bitfld.long 0x4 5. "TMR0_SEN,Internal Timer0 Start Enable Control\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill.." "0: Stop counting,1: Start counting" bitfld.long 0x4 4. "WARST_EN,Warm Reset Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be.." "0: No effect,1: When the warm reset sequence completed" newline bitfld.long 0x4 3. "ACT_EN,Activation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be set.." "0: No effect,1: When the activation sequence completed" bitfld.long 0x4 2. "DACT_EN,Deactivation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will.." "0: No effect,1: When the deactivation sequence completed" newline bitfld.long 0x4 1. "RX_RST,Rx Software Reset\nWhen RX_RST (SC_ALTCTL[1]) is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers" bitfld.long 0x4 0. "TX_RST,TX Software Reset\nWhen TX_RST (SC_ALTCTL[0]) is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers" line.long 0x8 "SC_EGTR,SC Extend Guard Time Register." hexmask.long.byte 0x8 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT." line.long 0xC "SC_RFTMR,SC Receive Buffer Time-out Register." hexmask.long.word 0xC 0.--8. 1. "RFTM,SC Receiver Buffer Time-Out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Fill all 0 to this field indicates to disable this function." line.long 0x10 "SC_ETUCR,SC ETU Control Register." bitfld.long 0x10 15. "COMPEN_EN,Compensation Mode Enable Control\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and n-1 clock cycles where n is the value to be written into the ETU_RDIV .\n" "0: Compensation function Disabled,1: Compensation function Enabled" hexmask.long.word 0x10 0.--11. 1. "ETU_RDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field but this field must be greater than 0x004." line.long 0x14 "SC_IER,SC Interrupt Enable Control Register." sif (cpuis("NANO1*BN")) bitfld.long 0x14 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and (n-1) clock cycles where n is the value to be written into the ETU_RDIV register." "0: Compensation function Disabled,1: Compensation function Enabled" endif bitfld.long 0x14 10. "ACON_ERR_IE,Auto Convention Error Interrupt Enable Control \nThis field is used for auto-convention error interrupt enable.\n" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled" newline bitfld.long 0x14 9. "RTMR_IE,Receiver Buffer Time-Out Interrupt Enable Control \nThis field is used for receiver buffer time-out interrupt enable.\n" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled" bitfld.long 0x14 8. "INIT_IE,Initial End Interrupt Enable Control\n" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled" newline bitfld.long 0x14 7. "CD_IE,Card Detect Interrupt Enable Control\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F (SC_SR[12]) \n" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled" bitfld.long 0x14 6. "BGT_IE,Block Guard Time Interrupt Enable Control\nThis field is used for block guard time interrupt enable.\n" "0: Block guard time Disabled,1: Block guard time Enabled" newline bitfld.long 0x14 5. "TMR2_IE,Timer2 Interrupt Enable Control\nThis field is used for TMR2 interrupt enable.\n" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled" bitfld.long 0x14 4. "TMR1_IE,Timer1 Interrupt Enable Control\nThis field is used to enable the TMR1 interrupt.\n" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled" newline bitfld.long 0x14 3. "TMR0_IE,Timer0 Interrupt Enable Control\nThis field is used to enable the TMR0 interrupt.\n" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled" bitfld.long 0x14 2. "TERR_IE,Transfer Error Interrupt Enable Control\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]) frame error RX_EFR_F (SC_SR[5]) parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled" newline bitfld.long 0x14 1. "TBE_IE,Transmit Buffer Empty Interrupt Enable Control\nThis field is used for transmit buffer empty interrupt enable.\n" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled" bitfld.long 0x14 0. "RDA_IE,Receive Data Reach Interrupt Enable Control\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled" rgroup.long 0x1C++0x3 line.long 0x0 "SC_ISR,SC Interrupt Status Register." bitfld.long 0x0 10. "ACON_ERR_IS,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F this bit will be set.\nNote: This bit is read only but it can be cleared.." "0,1" bitfld.long 0x0 9. "RTMR_IS,Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1" newline bitfld.long 0x0 8. "INIT_IS,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN (SC_ALTCTL[3])) deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only .." "0,1" bitfld.long 0x0 7. "CD_IS,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F (SC_SR[11]).\nNote: This field is the status flag of CD_INS_F (SC_SR[12]) .." "0,1" newline bitfld.long 0x0 6. "BGT_IS,\n" "0,1" bitfld.long 0x0 5. "TMR2_IS,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 4. "TMR1_IS,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" bitfld.long 0x0 3. "TMR0_IS,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline bitfld.long 0x0 2. "TERR_IS,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]) frame error RX_EFR_F.." "0,1" bitfld.long 0x0 1. "TBE_IS,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1" newline bitfld.long 0x0 0. "RDA_IS,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV.." "0,1" group.long 0x20++0x17 line.long 0x0 "SC_TRSR,SC Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0x0 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\n" "0: This bit is cleared automatically when TX..,1: This bit is set by hardware when TX transfer is.." rbitfld.long 0x0 30. "TX_OVER_REERR,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" newline rbitfld.long 0x0 29. "TX_REERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU." "?,1: This bit is read only" rbitfld.long 0x0 24.--25. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3" newline rbitfld.long 0x0 22. "RX_OVER_REERR,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries.." "?,1: This bit is read only" rbitfld.long 0x0 21. "RX_REERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "?,1: This bit is read only" newline rbitfld.long 0x0 16.--17. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F (SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU .." "0,1,2,3" rbitfld.long 0x0 13. "CD_PIN_F,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: The SC_CD pin state at low,1: The SC_CD pin state at high" newline rbitfld.long 0x0 12. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: The card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" rbitfld.long 0x0 11. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.\nThis bit is cleared automatically when TX transfer is finished and the STOP bit (include guard.." "0,1" rbitfld.long 0x0 30. "TX_OVER_ERETRY,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x0 29. "TX_ERETRY_F,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and can not generate any interrupt to CPU." "?,1: This bit is read only" endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 24.--26. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3,4,5,6,7" newline endif rbitfld.long 0x0 23. "RX_ATV,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1" sif (cpuis("NANO1*BN")) rbitfld.long 0x0 22. "RX_OVER_ERETRY,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU enables receiver retries.." "?,1: This bit is read only" newline rbitfld.long 0x0 21. "RX_ERETRY_F,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and can not generate any interrupt.." "?,1: This bit is read only" endif sif (cpuis("NANO1*BN")) rbitfld.long 0x0 16.--18. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F increases one. When one byte of RX buffer is read by CPU RX_POINT_F decreases.." "0,1,2,3,4,5,6,7" newline endif rbitfld.long 0x0 10. "TX_FULL_F,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1" rbitfld.long 0x0 9. "TX_EMPTY_F,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data.." "0,1" newline rbitfld.long 0x0 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to SC_THR will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing 1 to it." "0,1" rbitfld.long 0x0 6. "RX_EBR_F,Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + data bits.." "?,1: This bit is read only" newline rbitfld.long 0x0 5. "RX_EFR_F,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic 0). \nNote1: This.." "?,1: This bit is read only" rbitfld.long 0x0 4. "RX_EPA_F,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver.." "?,1: This bit is read only" newline rbitfld.long 0x0 2. "RX_FULL_F,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1" rbitfld.long 0x0 1. "RX_EMPTY_F,Receiver Buffer Empty Status Flag (Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU hardware sets this bit high. It will be cleared when SC receives any new data." "0,1" newline rbitfld.long 0x0 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing.." "0,1" line.long 0x4 "SC_PINCSR,SC Pin Control State Register." rbitfld.long 0x4 16. "SC_DATA_I_ST,SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_I\n" "0: The SC_DATA_I pin is low,1: The SC_DATA_I pin is high" bitfld.long 0x4 10. "CD_LEV,Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine enable" "0: When hardware detects the card detect pin from..,1: When hardware detects the card detect pin from.." newline bitfld.long 0x4 9. "SC_DATA_O,SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically. So don't.." "0: Drive SC_DATA_O pin to low,1: Drive SC_DATA_O pin to high" rbitfld.long 0x4 8. "SC_OEN_ST,SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n" "0: The SC_DATA_OEN pin state at low,1: The SC_DATA_OEN pin state at high" newline bitfld.long 0x4 7. "ADAC_CD_EN,Auto Deactivation When Card Removal\nNote: When the card is removal hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an interrupt INT_INIT to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.." bitfld.long 0x4 6. "CLK_KEEP,SC Clock Enable Control \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running" newline sif (cpuis("NANO1*BN")) bitfld.long 0x4 5. "CLK_STOP_LEV,SC Clock Stop Level\nThis field indicates the clock polarity control in clock stop mode." "0: SC_CLK stopped in low level,1: SC_CLK stopped in high level" endif rbitfld.long 0x4 4. "CD_PIN_ST,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: SC_CD pin state at low,1: SC_CD pin state at high" newline rbitfld.long 0x4 3. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" rbitfld.long 0x4 2. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only" newline bitfld.long 0x4 1. "SC_RST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.." bitfld.long 0x4 0. "POW_EN,SC_POW_EN Pin Signal\nSoftware can set POW_EN and POW_INV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin.." "0: SC_PWR pin status is low,1: SC_PWR pin status is high" line.long 0x8 "SC_TMR0,SC Internal Timer Control Register 0." hexmask.long.byte 0x8 24.--27. 1. "MODE,Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection." hexmask.long.tbyte 0x8 0.--23. 1. "CNT,Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values." line.long 0xC "SC_TMR1,SC Internal Timer Control Register 1." hexmask.long.byte 0xC 24.--27. 1. "MODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection." hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values." line.long 0x10 "SC_TMR2,SC Internal Timer Control Register 2." hexmask.long.byte 0x10 24.--27. 1. "MODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection" hexmask.long.byte 0x10 0.--7. 1. "CNT,Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values." line.long 0x14 "SC_UACTL,SC UART Mode Control Register." bitfld.long 0x14 7. "OPE,Odd Parity Enable Control\nNote: This bit has effect only when PBDIS bit is '0'." "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or check.." bitfld.long 0x14 6. "PBDIS,Parity Bit Disable Control\nNote: In smart card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).." newline sif (cpuis("NANO1*AN")) bitfld.long 0x14 4.--5. "DATA_LEN,Data Length\nNote: In smart card mode this DATA_LEN must be '00'" "0: Character Data Length is 8 bits,1: Character Data Length is 7 bits,?,?" endif sif (cpuis("NANO1*BN")) bitfld.long 0x14 4.--5. "DATA_LEN,Data Length" "0,1,2,3" newline endif bitfld.long 0x14 0. "UA_MODE_EN,UART Mode Enable Control\nNote3: When UART is enabled hardware will generate a reset to reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode" rgroup.long 0x38++0x7 line.long 0x0 "SC_TDRA,SC Timer Current Data Register A." hexmask.long.tbyte 0x0 0.--23. 1. "TDR0,Timer0 Current Data Value (Read Only)\nThis field indicates the current count values of Timer0." line.long 0x4 "SC_TDRB,SC Timer Current Data Register B." hexmask.long.byte 0x4 8.--15. 1. "TDR2,Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of Timer2." hexmask.long.byte 0x4 0.--7. 1. "TDR1,Timer1 Current Data Value (Read Only)\nThis field indicates the current count values of Timer1." tree.end sif (cpuis("NANO1*BN")) tree "SC2" base ad:0x401C0000 rgroup.long 0x0++0x3 line.long 0x0 "SC_RBR,SC Receiving Buffer Register (Read Only)." hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register\nBy reading this register the SC will return an 8-bit received data." wgroup.long 0x0++0x3 line.long 0x0 "SC_THR,SC Transmit Holding Register." hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the SC will send out an 8-bit data.\nNote: If SC_CTL [SC_CEN] not enabled this register can not be programmed." group.long 0x4++0x17 line.long 0x0 "SC_CTL,SC Control Register." bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-Bounce Select Register" "0,1,2,3" bitfld.long 0x0 23. "TX_ERETRY_EN,TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: User must fill TX_ERETRY value before enabling this bit." "0: TX error retry function Disabled,1: TX error retry function Enabled" newline bitfld.long 0x0 20.--22. "TX_ERETRY,TX Error Retry Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field can.." "?,1: The real retry number is TX_ERETRY + 1,2: This field can not be changed when TX_ERETRY_EN..,?,?,?,?,?" bitfld.long 0x0 19. "RX_ERETRY_EN,RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill RX_ERETRY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled" newline bitfld.long 0x0 16.--18. "RX_ERETRY,RX Error Retry Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This field.." "?,1: The real maximum retry number is RX_ERETRY + 1,2: This field can not be changed when RX_ERETRY_EN..,?,?,?,?,?" bitfld.long 0x0 15. "SLEN,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2." "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU" newline bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection" "0,1,2,3" hexmask.long.byte 0x0 8.--12. 1. "BGT,Block Guard Time (BGT)\nIn TX mode hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming.." newline bitfld.long 0x0 6.--7. "RX_FTRI_LEV,RX Buffer Trigger Level" "0,1,2,3" bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection" "0,1,2,3" newline bitfld.long 0x0 3. "AUTO_CON_EN,Auto Convention Enable" "0: Auto-convention Disabled,1: Auto-convention Enabled. When hardware receives.." bitfld.long 0x0 2. "DIS_TX,TX Transition Disable" "0: Transceiver Enabled,1: Transceiver Disabled" newline bitfld.long 0x0 1. "DIS_RX,RX Transition Disable" "0: Receiver Enabled,1: Receiver Disabled" bitfld.long 0x0 0. "SC_CEN,SC Engine Enable\nSet this bit to '1' to enable SC operation. If this bit is cleared SC will force all transition to IDLE state." "0,1" line.long 0x4 "SC_ALTCTL,SC Alternate Control Register." rbitfld.long 0x4 15. "TMR2_ATV,Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2." "0: Timer2 is not active,1: Timer2 is active" rbitfld.long 0x4 14. "TMR1_ATV,Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1." "0: Timer1 is not active,1: Timer1 is active" newline rbitfld.long 0x4 13. "TMR0_ATV,Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0." "0: Timer0 is not active,1: Timer0 is active" bitfld.long 0x4 12. "RX_BGT_EN,Receiver Block Guard Time Function Enable" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled" newline bitfld.long 0x4 8.--9. "INIT_SEL,Initial Timing Selection" "0,1,2,3" bitfld.long 0x4 7. "TMR2_SEN,Internal Timer2 Start Enable\nThis bit enables Timer2 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared by TX_RST and RX_RST. So don't fill this bit TX_RST and RX_RST at the.." "0: Stops counting,1: Starts counting" newline bitfld.long 0x4 6. "TMR1_SEN,Internal Timer1 Start Enable\nThis bit enables Timer '1' to start counting. Software can fill 0 to stop it and set '1' to reload and count.\nNote3: This field will be cleared by TX_RST and RX_RST so don't fill this bit TX_RST and RX_RST at.." "0: Stops counting,1: Starts counting" bitfld.long 0x4 5. "TMR0_SEN,Internal Timer0 Start Enable\nThis bit enables Timer0 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared by TX_RST and RX_RST. So don't fill this bit TX_RST and RX_RST at the.." "0: Stops counting,1: Starts counting" newline bitfld.long 0x4 4. "WARST_EN,Warm Reset Sequence Generator Enable\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: When the warm reset sequence completed" bitfld.long 0x4 3. "ACT_EN,Activation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to.." "0: No effect,1: When the activation sequence completed" newline bitfld.long 0x4 2. "DACT_EN,Deactivation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: When the deactivation sequence completed" bitfld.long 0x4 1. "RX_RST,RX Software Reset\nWhen RX_RST is set all the bytes in the receiver buffer and RX internal state machine will be cleared.\nNote: This bit will be auto cleared and needs at least 3 SC engine clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" newline bitfld.long 0x4 0. "TX_RST,TX Software Reset\nWhen TX_RST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and needs at least 3 SC engine clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" line.long 0x8 "SC_EGTR,SC Extend Guard Time Register." hexmask.long.byte 0x8 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU based and the real extended guard time is EGT." line.long 0xC "SC_RFTMR,SC Receive Buffer Time-Out Register." hexmask.long.word 0xC 0.--8. 1. "RFTM,SC Receiver Buffer Time-Out Register (ETU Based)\nThe time-out counter resets and starts counting whenever the RX buffer received a new data word. Once the counter decrease to '1' and no new data is received or CPU does not read data by reading.." line.long 0x10 "SC_ETUCR,SC ETU Control Register." bitfld.long 0x10 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and (n-1) clock cycles where n is the value to be written into the ETU_RDIV register." "0: Compensation function Disabled,1: Compensation function Enabled" hexmask.long.word 0x10 0.--11. 1. "ETU_RDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field but this field must be greater than 0x04.\nNote2: Software can configure this field but if the error rate is.." line.long 0x14 "SC_IER,SC Interrupt Enable Register." bitfld.long 0x14 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and (n-1) clock cycles where n is the value to be written into the ETU_RDIV register." "0: Compensation function Disabled,1: Compensation function Enabled" bitfld.long 0x14 10. "ACON_ERR_IE,Auto convention Error Interrupt Enable \nThis field is used for auto convention error interrupt enable." "0: INT_ACON_ERR Disabled,1: INT_ACON_ERR Enabled" newline bitfld.long 0x14 9. "RTMR_IE,Receiver Buffer Time-Out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable." "0: INT_RTMR Disabled,1: INT_RTMR Enabled" bitfld.long 0x14 8. "INIT_IE,Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable." "0: INT_INIT Disabled,1: INT_INIT Enabled" newline bitfld.long 0x14 7. "CD_IE,Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL]." "0: INT_CD Disabled,1: INT_CD Enabled" bitfld.long 0x14 6. "BGT_IE,Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable." "0: INT_BGT Disabled,1: INT_BGT Enabled" newline bitfld.long 0x14 5. "TMR2_IE,Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable." "0: INT_TMR2 Disabled,1: INT_TMR2 Enabled" bitfld.long 0x14 4. "TMR1_IE,Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable." "0: INT_TMR1 Disabled,1: INT_TMR1 Enabled" newline bitfld.long 0x14 3. "TMR0_IE,Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable." "0: INT_TMR0 Disabled,1: INT_TMR0 Enabled" bitfld.long 0x14 2. "TERR_IE,Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity error (RX_EPA_F) receiver.." "0: INT_TERR Disabled,1: INT_TERR Enabled" newline bitfld.long 0x14 1. "TBE_IE,Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable." "0: INT_THRE Disabled,1: INT_THRE Enabled" bitfld.long 0x14 0. "RDA_IE,Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable." "0: INT_RDR Disabled,1: INT_RDR Enabled" rgroup.long 0x1C++0x7 line.long 0x0 "SC_ISR,SC Interrupt Status Register." bitfld.long 0x0 10. "ACON_ERR_IS,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F this bit will be set.\nNote: This bit is read only but can be cleared by.." "0,1" bitfld.long 0x0 9. "RTMR_IS,Receiver buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1" newline bitfld.long 0x0 8. "INIT_IS,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.\nNote: This bit is read only but it.." "0,1" bitfld.long 0x0 7. "CD_IS,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].\nNote: This field is the status flag of SC_PINCSR [CD_INS_F].." "0,1" newline bitfld.long 0x0 6. "BGT_IS,Block Guard Time Interrupt Status Flag (Read Only)\nThis field is used for block guard time interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" bitfld.long 0x0 5. "TMR2_IS,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x0 4. "TMR1_IS,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" bitfld.long 0x0 3. "TMR0_IS,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x0 2. "TERR_IS,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity error.." "0,1" bitfld.long 0x0 1. "TBE_IS,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag. This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag; The TX_EMPTY_F will be set when the last.." "0,1" newline bitfld.long 0x0 0. "RDA_IS,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If.." "0,1" line.long 0x4 "SC_TRSR,SC Transfer Status Register." bitfld.long 0x4 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.\nThis bit is cleared automatically when TX transfer is finished and the STOP bit (include guard.." "0,1" bitfld.long 0x4 30. "TX_OVER_ERETRY,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline bitfld.long 0x4 29. "TX_ERETRY_F,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and can not generate any interrupt to CPU." "?,1: This bit is read only" bitfld.long 0x4 24.--26. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 23. "RX_ATV,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1" bitfld.long 0x4 22. "RX_OVER_ERETRY,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU enables receiver retries.." "?,1: This bit is read only" newline bitfld.long 0x4 21. "RX_ERETRY_F,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and can not generate any interrupt.." "?,1: This bit is read only" bitfld.long 0x4 16.--18. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F increases one. When one byte of RX buffer is read by CPU RX_POINT_F decreases.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10. "TX_FULL_F,Transmit buffer Full Status flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1" bitfld.long 0x4 9. "TX_EMPTY_F,Transmit buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data.." "0,1" newline bitfld.long 0x4 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: The additional write data will be ignored." "?,1: This bit is read only" bitfld.long 0x4 6. "RX_EBR_F,Receiver Break Error Status Flag (Read Only)\nThis bit is set to a logic '1' whenever the received data input (RX) held in the 'spacing state' (logic '0') is longer than a full word transmission time (that is the total time of 'start bit' +.." "?,1: This bit is read only" newline bitfld.long 0x4 5. "RX_EFR_F,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic '1' whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic '0'). \nNote1:.." "?,1: This bit is read only" bitfld.long 0x4 4. "RX_EPA_F,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic '1' whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU sets.." "?,1: This bit is read only" newline bitfld.long 0x4 2. "RX_FULL_F,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1" bitfld.long 0x4 1. "RX_EMPTY_F,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of RX buffer has been read by CPU hardware sets this bit high. It will be cleared when SC receives any new data." "0,1" newline bitfld.long 0x4 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than RX Buffer (SC_RBR) size 4 bytes of SC this bit will be set.\nNote1: This bit is read only but it can be.." "?,1: This bit is read only" group.long 0x24++0x13 line.long 0x0 "SC_PINCSR,SC Pin Control State Register." rbitfld.long 0x0 16. "SC_DATA_I_ST,SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_I" "0: The SC_DATA_I pin is low,1: The SC_DATA_I pin is high" bitfld.long 0x0 10. "CD_LEV,Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine enable" "0: When hardware detects the card detect pin from..,1: When hardware detects the card detect pin from.." newline bitfld.long 0x0 9. "SC_DATA_O,Output of SC Data Pin \nThis bit is the pin status of SC data output but user can drive this pin to high or low by setting this bit.\nNote: When SC is at activation warm re set or deactivation mode this bit will be changed automatically." "0: Drive SC data output pin to low,1: Drive SC data output pin to high" rbitfld.long 0x0 8. "SC_OEN_ST,SC Data Pin Output Enable Status (Read Only)" "0: SC data output enable pin status is at low,1: SC data output enable pin status is at high" newline bitfld.long 0x0 7. "ADAC_CD_EN,Auto Deactivation When Card Removal\nNote1: When the card is removal hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an interrupt INT_INIT to CPU." "0: Auto deactivation Disabled when hardware..,1: When the card is removal" bitfld.long 0x0 6. "CLK_KEEP,SC Clock Enable \nNote: When operation at activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field When operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running" newline bitfld.long 0x0 5. "CLK_STOP_LEV,SC Clock Stop Level\nThis field indicates the clock polarity control in clock stop mode." "0: SC_CLK stopped in low level,1: SC_CLK stopped in high level" rbitfld.long 0x0 4. "CD_PIN_ST,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD" "0: SC_CD pin state at low,1: SC_CD pin state at high" newline rbitfld.long 0x0 3. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CTL [SC_CEN] set." "0: No effect,1: This bit is read only" rbitfld.long 0x0 2. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CTL [SC_CEN] set." "0: No effect,1: This bit is read only" newline bitfld.long 0x0 1. "SC_RST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nNote: When operation at activation warm reset or deactivation mode this bit will be changed automatically. So don't fill.." "0: Drive SC_RST pin to low,1: Drive SC_RST pin to high" bitfld.long 0x0 0. "POW_EN,SC_POW_EN Pin Signal\nThis bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit.\nNote: When operation at activation warm reset or deactivation mode this bit will be changed automatically. So.." "0: Drive SC_POW_EN pin to low,1: Drive SC_POW_EN pin to high" line.long 0x4 "SC_TMR0,SC Internal Timer Control Register 0." hexmask.long.byte 0x4 24.--27. 1. "MODE,Timer 0 Operation Mode Selection" hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value Register (ETU Base)\nThis field indicates the internal timer operation values." line.long 0x8 "SC_TMR1,SC Internal Timer Control Register 1." hexmask.long.byte 0x8 24.--27. 1. "MODE,Timer 1 Operation Mode Selection" hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value Register (ETU Base)\nThis field indicates the internal timer operation values." line.long 0xC "SC_TMR2,SC Internal Timer Control Register 2." hexmask.long.byte 0xC 24.--27. 1. "MODE,Timer 2 Operation Mode Selection" hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value Register (ETU Base)\nThis field indicates the internal timer operation values." line.long 0x10 "SC_UACTL,SC UART Mode Control Register." bitfld.long 0x10 7. "OPE,Odd Parity Enable\nNote: This bit has effect only when PBDIS bit is '0'." "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or check.." bitfld.long 0x10 6. "PBDIS,Parity Bit Disable\nNote: In Smart Card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).." newline bitfld.long 0x10 4.--5. "DATA_LEN,Data Length" "0,1,2,3" bitfld.long 0x10 0. "UA_MODE_EN,UART Mode Enable\nNote1: When operating in UART mode user must set SCx_CTL [CON_SEL] and SCx_CTL [AUTO_CON_EN] to '0'.\nNote2: When operating in smart card mode user must set SCx_UACTL [7:0] register to '0'.\nNote3: When UART is enabled .." "0: Smart Card mode,1: When operating in UART mode" rgroup.long 0x38++0x7 line.long 0x0 "SC_TDRA,SC Timer Current Data Register A." hexmask.long.tbyte 0x0 0.--23. 1. "TDR0,Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0." line.long 0x4 "SC_TDRB,SC Timer Current Data Register B." hexmask.long.byte 0x4 8.--15. 1. "TDR2,Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2." hexmask.long.byte 0x4 0.--7. 1. "TDR1,Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1." tree.end endif tree.end tree "SCS (System Controllers Space)" base ad:0xE000E000 group.long 0x10++0xB line.long 0x0 "SYST_CTL,SysTick Control and Status" bitfld.long 0x0 16. "COUNTFLAG,Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\n COUNTFLAG is set by a count transition from 1 to 0.\n COUNTFLAG is cleared on read or by a write to the Current Value register." "0,1" bitfld.long 0x0 2. "CLKSRC," "0: Clock Source is (optional) external reference..,1: Core clock used for SysTick If no external clock.." newline bitfld.long 0x0 1. "TICKINT," "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.." bitfld.long 0x0 0. "ENABLE," "0: The counter is Disabled,1: The counter will operate in a multi-shot manner" line.long 0x4 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,The value to load into the Current Value register when the counter reaches 0." line.long 0x8 "SYST_CVR,SysTick Current Value" hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current Counter Value \nThis is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported.." group.long 0x100++0x3 line.long 0x0 "NVIC_ISER,IRQ0~IRQ31 Set-enable Control Register" hexmask.long 0x0 0.--31. 1. "SETENA,Enable one or more interrupts within a group of 32. Each Bit Represents An Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47) \nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with.." group.long 0x180++0x3 line.long 0x0 "NVIC_ICER,IRQ0~IRQ31 Clear-enable Control Register" hexmask.long 0x0 0.--31. 1. "CLRENA,Disable one or more interrupts within a group of 32. Each Bit Represents An Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47) \nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with.." group.long 0x200++0x3 line.long 0x0 "NVIC_ISPR,IRQ0~IRQ31 Set-pending Control Register" hexmask.long 0x0 0.--31. 1. "SETPEND,Writing 1 To A Bit To Set Pending State Of The Associated Interrupt Under Software Control Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current.." group.long 0x280++0x3 line.long 0x0 "NVIC_ICPR,IRQ0~IRQ31 Clear-pending Control Register" hexmask.long 0x0 0.--31. 1. "CLRPEND,Writing 1 To A Bit To Remove The Pending State Of Associated Interrupt Under Software Control Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the.." group.long 0x400++0x1F line.long 0x0 "NVIC_IPR0,IRQ0~IRQ3 Priority Control Register" bitfld.long 0x0 30.--31. "PRI_3,Priority Of IRQ3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x0 22.--23. "PRI_2,Priority Of IRQ2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x0 14.--15. "PRI_1,Priority Of IRQ1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x0 6.--7. "PRI_0,Priority Of IRQ0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x4 "NVIC_IPR1,IRQ4~IRQ7 Priority Control Register" bitfld.long 0x4 30.--31. "PRI_7,Priority Of IRQ7\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_6,Priority Of IRQ6\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x4 14.--15. "PRI_5,Priority Of IRQ5\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 6.--7. "PRI_4,Priority Of IRQ4\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x8 "NVIC_IPR2,IRQ8~IRQ11 Priority Control Register" bitfld.long 0x8 30.--31. "PRI_11,Priority Of IRQ11\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x8 22.--23. "PRI_10,Priority Of IRQ10\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x8 14.--15. "PRI_9,Priority Of IRQ9\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x8 6.--7. "PRI_8,Priority Of IRQ8\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0xC "NVIC_IPR3,IRQ12~IRQ15 Priority Control Register" bitfld.long 0xC 30.--31. "PRI_15,Priority Of IRQ15\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0xC 22.--23. "PRI_14,Priority Of IRQ14\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0xC 14.--15. "PRI_13,Priority Of IRQ13\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0xC 6.--7. "PRI_12,Priority Of IRQ12\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x10 "NVIC_IPR4,IRQ16~IRQ19 Priority Control Register" bitfld.long 0x10 30.--31. "PRI_19,Priority Of IRQ19\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x10 22.--23. "PRI_18,Priority Of IRQ18\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x10 14.--15. "PRI_17,Priority Of IRQ17\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x10 6.--7. "PRI_16,Priority Of IRQ16\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x14 "NVIC_IPR5,IRQ20~IRQ23 Priority Control Register" bitfld.long 0x14 30.--31. "PRI_23,Priority Of IRQ23\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x14 22.--23. "PRI_22,Priority Of IRQ22\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x14 14.--15. "PRI_21,Priority Of IRQ21\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x14 6.--7. "PRI_20,Priority Of IRQ20\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x18 "NVIC_IPR6,IRQ24~IRQ27 Priority Control Register" bitfld.long 0x18 30.--31. "PRI_27,Priority Of IRQ27\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x18 22.--23. "PRI_26,Priority Of IRQ26\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x18 14.--15. "PRI_25,Priority Of IRQ25\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x18 6.--7. "PRI_24,Priority Of IRQ24\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x1C "NVIC_IPR7,IRQ28~IRQ31 Priority Control Register" bitfld.long 0x1C 30.--31. "PRI_31,Priority Of IRQ31\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x1C 22.--23. "PRI_30,Priority Of IRQ30\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" newline bitfld.long 0x1C 14.--15. "PRI_29,Priority Of IRQ29\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x1C 6.--7. "PRI_28,Priority Of IRQ28\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" rgroup.long 0xD00++0x3 line.long 0x0 "CPUID,CPUID Base Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER," hexmask.long.byte 0x0 16.--19. 1. "PART,Reads as 0xC for ARMv6-M parts" newline hexmask.long.word 0x0 4.--15. 1. "PARTNO,Reads as 0xC20." hexmask.long.byte 0x0 0.--3. 1. "REVISION,Reads as 0x0" group.long 0xD04++0x3 line.long 0x0 "ICSR,Interrupt Control State Register" bitfld.long 0x0 31. "NMIPENDSET,Setting This Bit Will Activate An NMI\nSince NMI is the highest priority exception it will activate as soon as it is registered. Reads back with current state (1 if Pending 0 if not)." "0,1" bitfld.long 0x0 28. "PENDSVSET,Set A Pending PendSV Interrupt\nThis is normally used to request a context switch. Reads back with current state (1 if Pending 0 if not)." "0,1" newline bitfld.long 0x0 27. "PENDSVCLR,Write 1 to clear a pending PendSV interrupt." "0,1" bitfld.long 0x0 26. "PENDSTSET,Set A Pending SysTick Reads back with current state (1 if Pending 0 if not)." "0,1" newline bitfld.long 0x0 25. "PENDSTCLR,Write 1 to clear a pending SysTick." "0,1" bitfld.long 0x0 23. "ISRPREEMPT,If set a pending exception will be serviced on exit from the debug halt state." "0,1" newline bitfld.long 0x0 22. "ISRPENDING,Indicates if an external configurable (NVIC generated) interrupt is pending." "0,1" hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Indicates The Exception Number For The Highest Priority Pending Exception\nThe pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero.." newline hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,If value of VECTACTIVE 1: the exception number for the current executing exception." sif (cpuis("NANO1*AN")) group.long 0xD0C++0x3 line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,When write this register this field should be 0x05FA otherwise the write action will be unpredictable." bitfld.long 0x0 2. "SYSRESETREQ,Writing This Bit 1 Will Cause A Reset Signal To Be Asserted To The Chip To Indicate A Reset Is Requested\nThe bit is a write only bit and self-clears as part of the reset sequence." "0,1" newline bitfld.long 0x0 1. "VECTCLRACTIVE,Set This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the.." "0,1" endif group.long 0xD10++0x3 line.long 0x0 "SCR,System Control Register" bitfld.long 0x0 4. "SEVONPEND,When enabled interrupt transitions from Inactive to Pending are included in the list of wake-up events for the WFE instruction." "0,1" bitfld.long 0x0 2. "SLEEPDEEP,A qualifying hint that indicates waking from sleep might take longer." "0,1" newline bitfld.long 0x0 1. "SLEEPONEXIT,When Set To 1 The Core Can Enter A Sleep State On An Exception Return To Thread Mode This is the mode and exception level entered at reset the base level of execution." "0,1" group.long 0xD1C++0x7 line.long 0x0 "SHPR2,System Handler Priority Register 2" bitfld.long 0x0 30.--31. "PRI_11,Priority Of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" line.long 0x4 "SHPR3,System Handler Priority Register 3" bitfld.long 0x4 30.--31. "PRI_15,Priority Of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_14,Priority Of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3" tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI0" base ad:0x40030000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKEUP_EN,Wake-Up Enable\nNote: When the system enters the power-down mode the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up this bit must be clear by user.." "0: Wake-up function Disabled when the system enters..,1: Wake-up function Enabled" sif (cpuis("NANO1*BN")) bitfld.long 0x0 29. "DUAL_IO_EN,Dual IO Mode Enable" "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" newline bitfld.long 0x0 28. "DUAL_IO_DIR,Dual IO Mode Direction" "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function" endif bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable\nNote: Refer to Variable Serial Clock Frequency section." "0: The serial clock output frequency is fixed and..,1: The serial clock output frequency is variable." newline bitfld.long 0x0 22. "TWOB,2 Data Channel Transfer Mode Active\nNote: When enabling TWOB the setting of TX_NUM must be programmed as 00." "0: 2data channel transfer mode Disabled,1: 2data channel transfer mode Enabled" bitfld.long 0x0 21. "FIFOM,FIFO Mode Enable\nNote: Refer to Dual FIFO Mode section." "0: FIFO mode Disabled (in Normal mode),1: FIFO mode Enabled" newline sif (cpuis("NANO1*AN")) bitfld.long 0x0 19.--20. "REORDER,Reorder Mode Selection\nNote: The suspend interval is defined in SP_CYCLE" "0: Disable both byte reorder and suspend functions,1: Enable byte reorder function and insert a byte..,?,?" bitfld.long 0x0 8.--9. "TX_NUM,Number Of Transmit/Receive Transaction\n" "0,1,2,3" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable" "0,1" endif bitfld.long 0x0 18. "SLAVE,Slave Mode Indication\nNote: Refer to Slave Selection section" "0: SPI controller is set as Master mode,1: SPI controller is set as Slave mode" newline bitfld.long 0x0 17. "INTEN,Interrupt Enable\n" "0: SPI Interrupt Disabled,1: SPI Interrupt Enabled" hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\n" newline bitfld.long 0x0 11. "CLKP,Clock Polarity\nNote: Refer to Clock Parity section." "0: The default level of SPICLK is low,1: The default level of SPICLK is high" bitfld.long 0x0 10. "LSB,Send LSB First\nNote: Refer to LSB First section." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\n" bitfld.long 0x0 2. "TX_NEG,Transmit At Negative Edge\nNote: Refer to Edge Condition section." "0: The transmitted data output is changed at the..,1: The transmitted data output is changed at the.." newline bitfld.long 0x0 1. "RX_NEG,Receive At Negative Edge\nNote: Refer to Edge Condition section." "0: The received data is latched at the rising edge..,1: The received data is latched at the falling edge.." bitfld.long 0x0 0. "GO_BUSY,Go And Busy Status\nDuring the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically.\nNote 1: All registers should be set before writing '1' to the GO_BUSY bit in the SPI_CTL.." "0: Writing this bit '0' to stop data transfer if..,1: All registers should be set before writing '1'.." line.long 0x4 "SPI_STATUS,SPI Status Register" sif (cpuis("NANO1*BN")) hexmask.long.byte 0x4 20.--23. 1. "TX_FIFO_CNT,Data counts in TX FIFO (Read Only)" hexmask.long.byte 0x4 16.--19. 1. "RX_FIFO_CNT,Data counts in RX FIFO (Read Only)" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 12. "TIME_OUT_STS,TIMEOUT Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: There is not timeout event on the received buffer,1: RX fifo is not empty and there is not be read.." endif sif (cpuis("NANO1*BN")) rbitfld.long 0x4 10. "TXINT_STS,TX FIFO Threshold Interrupt Status (Read Only)" "0: TX valid data counts bigger than TXTHRESHOLD,1: TX valid data counts small or equal than.." newline bitfld.long 0x4 9. "RX_OVER_RUN,RX FIFO Over Run Status\nIf SPI receives data when RX FIFO is full this bit will set to 1 and the received data will dropped.\nNote: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x4 8. "RXINT_STS,RX FIFO Threshold Interrupt Status (Read Only)" "0: RX valid data counts small or equal than..,1: RX valid data counts bigger than RXTHRESHOLD" newline endif bitfld.long 0x4 7. "INTSTS,Interrupt Status\nNote: This bit is read only but can be cleared by writing '1' to this bit." "0: Transfer is not finished yet,1: Transfer is done. The interrupt is requested.." bitfld.long 0x4 6. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to indicate that the transfer has started in Slave mode with no slave select.\n" "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline bitfld.long 0x4 4. "LTRIG_FLAG,Level Trigger Flag (INTERNAL ONLY)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is read only" "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." bitfld.long 0x4 3. "TX_FULL,Transmitted Dual FIFO_FULL Status\n" "0: Transmitted data FIFO is not full in the dual..,1: Transmitted data FIFO is full in the dual FIFO.." newline bitfld.long 0x4 2. "TX_EMPTY,Transmitted Dual FIFO_EMPTY Status\n" "0: Transmitted data FIFO is not empty in the dual..,1: Transmitted data FIFO is empty in the dual FIFO.." bitfld.long 0x4 1. "RX_FULL,Received Dual FIFO_FULL Status\n" "0: Received data FIFO is not full in dual FIFO mode,1: Received data FIFO is full in the dual FIFO mode" newline bitfld.long 0x4 0. "RX_EMPTY,Received Dual FIFO_EMPTY Status\n" "0: Received data FIFO is not empty in the dual FIFO..,1: Received data FIFO is empty in the dual FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" sif (cpuis("NANO1*AN")) hexmask.long.word 0x8 16.--31. 1. "DIVIDER2,Clock Divider 2 Register \nThe value is the 2nd 2nd frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/" hexmask.long.word 0x8 0.--15. 1. "DIVIDER1,Clock Divider 1 Register \nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/\n\nNote 1: The DIVIDER1 can be set as 0. If the.." newline endif sif (cpuis("NANO1*BN")) hexmask.long.byte 0x8 16.--23. 1. "DIVIDER2,Clock Divider 2 Register \nThe value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:" endif sif (cpuis("NANO1*BN")) hexmask.long.byte 0x8 0.--7. 1. "DIVIDER1,Clock Divider 1 Register \nThe value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation: \nWhere\n is the SPI engine clock.." endif line.long 0xC "SPI_SSR,SPI Slave Select Register" sif (cpuis("NANO1*BN")) bitfld.long 0xC 16. "SS_INT_OPT,Slave Select Interrupt Option \nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." endif bitfld.long 0xC 9. "SSTA_INTEN,Slave Start Interrupt Enable\nNote : Refer to No Slave Select Mode." "0: Transfer start interrupt Disabled in no slave..,1: Transaction start interrupt Enabled in no slave.." newline sif (cpuis("NANO1*AN")) bitfld.long 0xC 8. "SLV_ABORT,Abort In Slave Mode With No Slave Selected\nNote 1:Refer to No Slave Select Mode.\nNote 2: It is auto clear to '0' by hardware when the abort event is active." "0: No force the slave abort,1: Refer to No Slave Select Mode" bitfld.long 0xC 0.--1. "SSR,Slave Select Active Register (Master Only)\nIf AUTOSS bit (SPI_SSR[3]) is cleared writing '1' to SSR[0] bit sets the SPISS[0] line to an active state and writing '0' sets the line back to inactive state.( the same as SSR[1] for SPISS[1])\nNote 1:.." "0: Both SPISS[1] and SPISS[0] are inactive,1: This interface can only drive one device/slave..,2: SPISS[0] is also defined as device/slave select..,?" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0xC 8. "SLV_ABORT,Abort in Slave Mode with No Slave Selected\nIn normal operation there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial.." "0,1" endif bitfld.long 0xC 5. "NOSLVSEL,No Slave Selected In Slave Mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote 1: Refer to No Slave.." "0: The controller is 4-wire bi-direction interface,1: Refer to No Slave Select Mode" newline bitfld.long 0xC 4. "SS_LTRIG,Slave Select Level Trigger\n" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection (Master Only)\n" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPISS[1:0] signals are.." newline bitfld.long 0xC 2. "SS_LVL,Slave Select Active Level\nIt defines the active level of device/slave select signals (SPISS[1:0]).\n" "0: The SPISS slave select signal is active Low,1: The SPISS slave select signal is active High" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" sif (cpuis("NANO1*AN")) hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1 the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit.." endif sif (cpuis("NANO1*BN")) hexmask.long 0x0 0.--31. 1. "RDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RX_EMPTY SPI_STATUS[0] to check if there is any more received data or not. \nNote: These registers are read only." endif line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" sif (cpuis("NANO1*AN")) hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1 the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit.." endif sif (cpuis("NANO1*BN")) hexmask.long 0x4 0.--31. 1. "RDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RX_EMPTY SPI_STATUS[0] to check if there is any more received data or not. \nNote: These registers are read only." endif wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TDATA,Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if TX_BIT_LEN is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TDATA,Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if TX_BIT_LEN is set.." group.long 0x34++0x3 line.long 0x0 "SPI_VARCLK,SPI Variable Clock Pattern Flag Register" hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK.\n" sif (cpuis("NANO1*AN")) group.long 0x38++0x7 line.long 0x0 "SPI_PDMA,SPI PDMA Control Register" bitfld.long 0x0 2. "PDMA_RST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state. \nNote: It is auto cleared to '0' after the reset function done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RX_DMA_EN,Receiver PDMA Enable (PDMA Reads SPI Data To Memory)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Hardware will clear this bit to 0 automatically after PDMA transfer done.\nNote 3: In Slave mode and the FIFO bit is.." "0: Receiver PDMA function Disabled,1: Refer to DMA section for more detail information" newline bitfld.long 0x0 0. "TX_DMA_EN,Transmit PDMA Enable (PDMA Writes Data To SPI)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB.." "0: Transmit PDMA function Disabled,1: Refer to DMA section for more detail information" line.long 0x4 "SPI_FFCLR,SPI FIFO Counter Clear Control Register" bitfld.long 0x4 1. "TX_CLR,Transmitting FIFO Counter Clear\nNote: This bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting.." "0: No clear the transmitted FIFO,1: Clear the transmitted FIFO" bitfld.long 0x4 0. "RX_CLR,Receiving FIFO Counter Clear\nNote: This bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After.." "0: No clear the received FIFO,1: Clear the received FIFO" endif sif (cpuis("NANO1*BN")) group.long 0x38++0x7 line.long 0x0 "SPI_DMA,SPI DMA Control Register" bitfld.long 0x0 2. "PDMA_RST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state. \nNote: it is auto cleared to '0' after the reset function done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RX_DMA_EN,Receiving PDMA Enable(PDMA Reads SPI Data to Memory)\nSet this bit to '1' will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when there is data written into the received buffer or the status.." "0,1" newline bitfld.long 0x0 0. "TX_DMA_EN,Transmit PDMA Enable (PDMA Writes Data to SPI)\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data remember not to set GO_BUSY bit of.." "0,1" line.long 0x4 "SPI_FFCTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\n3-bit register value from 0 ~7.\n If TX valid data counts small or equal than TXTHRESHOLD TXINT_STS will set to 1 else TXINT_STS will set to 0." "?,?,?,3: bit register,?,?,?,?" bitfld.long 0x4 24.--26. "RX_THRESHOLD,Received FIFO Threshold\n3-bits register value from 0 ~7.\n If RX valid data counts large than RXTHRESHOLD RXINT_STS will set to 1 else RXINT_STS will set to 0." "?,?,?,3: bits register,?,?,?,?" newline bitfld.long 0x4 7. "TIMEOUT_EN,RX Read timeout function enable" "0: RX read Timeout function Disabled,1: RX read Timeout function Enabled" bitfld.long 0x4 4. "RXOVINT_EN,RX FIFO Over Run Interrupt Enable" "0: RX FIFO over run interrupt Disabled,1: RX FIFO over run interrupt Enabled" newline bitfld.long 0x4 3. "TXINT_EN,TX Threshold Interrupt Enable" "0: Tx threshold interrupt Disabled,1: TX threshold interrupt Enable" bitfld.long 0x4 2. "RXINT_EN,RX Threshold Interrupt Enable" "0: Rx threshold interrupt Disabled,1: RX threshold interrupt Enable" newline bitfld.long 0x4 1. "TX_CLR,Transmitting FIFO Counter Clear\nThis bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0,1" bitfld.long 0x4 0. "RX_CLR,Receiving FIFO Counter Clear\nThis bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0,1" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" endif tree.end tree "SPI1" base ad:0x40130000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKEUP_EN,Wake-Up Enable\nNote: When the system enters the power-down mode the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up this bit must be clear by user.." "0: Wake-up function Disabled when the system enters..,1: Wake-up function Enabled" sif (cpuis("NANO1*BN")) bitfld.long 0x0 29. "DUAL_IO_EN,Dual IO Mode Enable" "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" newline bitfld.long 0x0 28. "DUAL_IO_DIR,Dual IO Mode Direction" "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function" endif bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable\nNote: Refer to Variable Serial Clock Frequency section." "0: The serial clock output frequency is fixed and..,1: The serial clock output frequency is variable." newline bitfld.long 0x0 22. "TWOB,2 Data Channel Transfer Mode Active\nNote: When enabling TWOB the setting of TX_NUM must be programmed as 00." "0: 2data channel transfer mode Disabled,1: 2data channel transfer mode Enabled" bitfld.long 0x0 21. "FIFOM,FIFO Mode Enable\nNote: Refer to Dual FIFO Mode section." "0: FIFO mode Disabled (in Normal mode),1: FIFO mode Enabled" newline sif (cpuis("NANO1*AN")) bitfld.long 0x0 19.--20. "REORDER,Reorder Mode Selection\nNote: The suspend interval is defined in SP_CYCLE" "0: Disable both byte reorder and suspend functions,1: Enable byte reorder function and insert a byte..,?,?" bitfld.long 0x0 8.--9. "TX_NUM,Number Of Transmit/Receive Transaction\n" "0,1,2,3" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable" "0,1" endif bitfld.long 0x0 18. "SLAVE,Slave Mode Indication\nNote: Refer to Slave Selection section" "0: SPI controller is set as Master mode,1: SPI controller is set as Slave mode" newline bitfld.long 0x0 17. "INTEN,Interrupt Enable\n" "0: SPI Interrupt Disabled,1: SPI Interrupt Enabled" hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\n" newline bitfld.long 0x0 11. "CLKP,Clock Polarity\nNote: Refer to Clock Parity section." "0: The default level of SPICLK is low,1: The default level of SPICLK is high" bitfld.long 0x0 10. "LSB,Send LSB First\nNote: Refer to LSB First section." "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\n" bitfld.long 0x0 2. "TX_NEG,Transmit At Negative Edge\nNote: Refer to Edge Condition section." "0: The transmitted data output is changed at the..,1: The transmitted data output is changed at the.." newline bitfld.long 0x0 1. "RX_NEG,Receive At Negative Edge\nNote: Refer to Edge Condition section." "0: The received data is latched at the rising edge..,1: The received data is latched at the falling edge.." bitfld.long 0x0 0. "GO_BUSY,Go And Busy Status\nDuring the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically.\nNote 1: All registers should be set before writing '1' to the GO_BUSY bit in the SPI_CTL.." "0: Writing this bit '0' to stop data transfer if..,1: All registers should be set before writing '1'.." line.long 0x4 "SPI_STATUS,SPI Status Register" sif (cpuis("NANO1*BN")) hexmask.long.byte 0x4 20.--23. 1. "TX_FIFO_CNT,Data counts in TX FIFO (Read Only)" hexmask.long.byte 0x4 16.--19. 1. "RX_FIFO_CNT,Data counts in RX FIFO (Read Only)" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 12. "TIME_OUT_STS,TIMEOUT Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: There is not timeout event on the received buffer,1: RX fifo is not empty and there is not be read.." endif sif (cpuis("NANO1*BN")) rbitfld.long 0x4 10. "TXINT_STS,TX FIFO Threshold Interrupt Status (Read Only)" "0: TX valid data counts bigger than TXTHRESHOLD,1: TX valid data counts small or equal than.." newline bitfld.long 0x4 9. "RX_OVER_RUN,RX FIFO Over Run Status\nIf SPI receives data when RX FIFO is full this bit will set to 1 and the received data will dropped.\nNote: This bit will be cleared by writing 1 to itself." "0,1" rbitfld.long 0x4 8. "RXINT_STS,RX FIFO Threshold Interrupt Status (Read Only)" "0: RX valid data counts small or equal than..,1: RX valid data counts bigger than RXTHRESHOLD" newline endif bitfld.long 0x4 7. "INTSTS,Interrupt Status\nNote: This bit is read only but can be cleared by writing '1' to this bit." "0: Transfer is not finished yet,1: Transfer is done. The interrupt is requested.." bitfld.long 0x4 6. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to indicate that the transfer has started in Slave mode with no slave select.\n" "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline bitfld.long 0x4 4. "LTRIG_FLAG,Level Trigger Flag (INTERNAL ONLY)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is read only" "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." bitfld.long 0x4 3. "TX_FULL,Transmitted Dual FIFO_FULL Status\n" "0: Transmitted data FIFO is not full in the dual..,1: Transmitted data FIFO is full in the dual FIFO.." newline bitfld.long 0x4 2. "TX_EMPTY,Transmitted Dual FIFO_EMPTY Status\n" "0: Transmitted data FIFO is not empty in the dual..,1: Transmitted data FIFO is empty in the dual FIFO.." bitfld.long 0x4 1. "RX_FULL,Received Dual FIFO_FULL Status\n" "0: Received data FIFO is not full in dual FIFO mode,1: Received data FIFO is full in the dual FIFO mode" newline bitfld.long 0x4 0. "RX_EMPTY,Received Dual FIFO_EMPTY Status\n" "0: Received data FIFO is not empty in the dual FIFO..,1: Received data FIFO is empty in the dual FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" sif (cpuis("NANO1*AN")) hexmask.long.word 0x8 16.--31. 1. "DIVIDER2,Clock Divider 2 Register \nThe value is the 2nd 2nd frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/" hexmask.long.word 0x8 0.--15. 1. "DIVIDER1,Clock Divider 1 Register \nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/\n\nNote 1: The DIVIDER1 can be set as 0. If the.." newline endif sif (cpuis("NANO1*BN")) hexmask.long.byte 0x8 16.--23. 1. "DIVIDER2,Clock Divider 2 Register \nThe value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:" endif sif (cpuis("NANO1*BN")) hexmask.long.byte 0x8 0.--7. 1. "DIVIDER1,Clock Divider 1 Register \nThe value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation: \nWhere\n is the SPI engine clock.." endif line.long 0xC "SPI_SSR,SPI Slave Select Register" sif (cpuis("NANO1*BN")) bitfld.long 0xC 16. "SS_INT_OPT,Slave Select Interrupt Option \nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." endif bitfld.long 0xC 9. "SSTA_INTEN,Slave Start Interrupt Enable\nNote : Refer to No Slave Select Mode." "0: Transfer start interrupt Disabled in no slave..,1: Transaction start interrupt Enabled in no slave.." newline sif (cpuis("NANO1*AN")) bitfld.long 0xC 8. "SLV_ABORT,Abort In Slave Mode With No Slave Selected\nNote 1:Refer to No Slave Select Mode.\nNote 2: It is auto clear to '0' by hardware when the abort event is active." "0: No force the slave abort,1: Refer to No Slave Select Mode" bitfld.long 0xC 0.--1. "SSR,Slave Select Active Register (Master Only)\nIf AUTOSS bit (SPI_SSR[3]) is cleared writing '1' to SSR[0] bit sets the SPISS[0] line to an active state and writing '0' sets the line back to inactive state.( the same as SSR[1] for SPISS[1])\nNote 1:.." "0: Both SPISS[1] and SPISS[0] are inactive,1: This interface can only drive one device/slave..,2: SPISS[0] is also defined as device/slave select..,?" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0xC 8. "SLV_ABORT,Abort in Slave Mode with No Slave Selected\nIn normal operation there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial.." "0,1" endif bitfld.long 0xC 5. "NOSLVSEL,No Slave Selected In Slave Mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote 1: Refer to No Slave.." "0: The controller is 4-wire bi-direction interface,1: Refer to No Slave Select Mode" newline bitfld.long 0xC 4. "SS_LTRIG,Slave Select Level Trigger\n" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection (Master Only)\n" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPISS[1:0] signals are.." newline bitfld.long 0xC 2. "SS_LVL,Slave Select Active Level\nIt defines the active level of device/slave select signals (SPISS[1:0]).\n" "0: The SPISS slave select signal is active Low,1: The SPISS slave select signal is active High" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" sif (cpuis("NANO1*AN")) hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1 the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit.." endif sif (cpuis("NANO1*BN")) hexmask.long 0x0 0.--31. 1. "RDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RX_EMPTY SPI_STATUS[0] to check if there is any more received data or not. \nNote: These registers are read only." endif line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" sif (cpuis("NANO1*AN")) hexmask.long 0x4 0.--31. 1. "RXDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1 the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit.." endif sif (cpuis("NANO1*BN")) hexmask.long 0x4 0.--31. 1. "RDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RX_EMPTY SPI_STATUS[0] to check if there is any more received data or not. \nNote: These registers are read only." endif wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TDATA,Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if TX_BIT_LEN is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TDATA,Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if TX_BIT_LEN is set.." group.long 0x34++0x3 line.long 0x0 "SPI_VARCLK,SPI Variable Clock Pattern Flag Register" hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK.\n" sif (cpuis("NANO1*AN")) group.long 0x38++0x7 line.long 0x0 "SPI_PDMA,SPI PDMA Control Register" bitfld.long 0x0 2. "PDMA_RST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state. \nNote: It is auto cleared to '0' after the reset function done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RX_DMA_EN,Receiver PDMA Enable (PDMA Reads SPI Data To Memory)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Hardware will clear this bit to 0 automatically after PDMA transfer done.\nNote 3: In Slave mode and the FIFO bit is.." "0: Receiver PDMA function Disabled,1: Refer to DMA section for more detail information" newline bitfld.long 0x0 0. "TX_DMA_EN,Transmit PDMA Enable (PDMA Writes Data To SPI)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB.." "0: Transmit PDMA function Disabled,1: Refer to DMA section for more detail information" line.long 0x4 "SPI_FFCLR,SPI FIFO Counter Clear Control Register" bitfld.long 0x4 1. "TX_CLR,Transmitting FIFO Counter Clear\nNote: This bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting.." "0: No clear the transmitted FIFO,1: Clear the transmitted FIFO" bitfld.long 0x4 0. "RX_CLR,Receiving FIFO Counter Clear\nNote: This bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After.." "0: No clear the received FIFO,1: Clear the received FIFO" endif sif (cpuis("NANO1*BN")) group.long 0x38++0x7 line.long 0x0 "SPI_DMA,SPI DMA Control Register" bitfld.long 0x0 2. "PDMA_RST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state. \nNote: it is auto cleared to '0' after the reset function done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" bitfld.long 0x0 1. "RX_DMA_EN,Receiving PDMA Enable(PDMA Reads SPI Data to Memory)\nSet this bit to '1' will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when there is data written into the received buffer or the status.." "0,1" newline bitfld.long 0x0 0. "TX_DMA_EN,Transmit PDMA Enable (PDMA Writes Data to SPI)\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data remember not to set GO_BUSY bit of.." "0,1" line.long 0x4 "SPI_FFCTL,SPI FIFO Control Register" bitfld.long 0x4 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\n3-bit register value from 0 ~7.\n If TX valid data counts small or equal than TXTHRESHOLD TXINT_STS will set to 1 else TXINT_STS will set to 0." "?,?,?,3: bit register,?,?,?,?" bitfld.long 0x4 24.--26. "RX_THRESHOLD,Received FIFO Threshold\n3-bits register value from 0 ~7.\n If RX valid data counts large than RXTHRESHOLD RXINT_STS will set to 1 else RXINT_STS will set to 0." "?,?,?,3: bits register,?,?,?,?" newline bitfld.long 0x4 7. "TIMEOUT_EN,RX Read timeout function enable" "0: RX read Timeout function Disabled,1: RX read Timeout function Enabled" bitfld.long 0x4 4. "RXOVINT_EN,RX FIFO Over Run Interrupt Enable" "0: RX FIFO over run interrupt Disabled,1: RX FIFO over run interrupt Enabled" newline bitfld.long 0x4 3. "TXINT_EN,TX Threshold Interrupt Enable" "0: Tx threshold interrupt Disabled,1: TX threshold interrupt Enable" bitfld.long 0x4 2. "RXINT_EN,RX Threshold Interrupt Enable" "0: Rx threshold interrupt Disabled,1: RX threshold interrupt Enable" newline bitfld.long 0x4 1. "TX_CLR,Transmitting FIFO Counter Clear\nThis bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0,1" bitfld.long 0x4 0. "RX_CLR,Receiving FIFO Counter Clear\nThis bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0,1" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" endif tree.end sif (cpuis("NANO1*BN")) tree "SPI2" base ad:0x400D0000 group.long 0x0++0xF line.long 0x0 "SPI_CTL,SPI Control Register" bitfld.long 0x0 31. "WKEUP_EN,Wake-Up Enable\nWhen the system enters Power-down mode the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up this bit must be cleared by user to.." "0: Wake-up function Disabled when the system enters..,1: Wake-up function Enabled" newline bitfld.long 0x0 29. "DUAL_IO_EN,Dual IO Mode Enable" "0: Dual I/O Mode function Disabled,1: Dual I/O Mode function Enabled" newline bitfld.long 0x0 28. "DUAL_IO_DIR,Dual IO Mode Direction" "0: Date read in the Dual I/O Mode function,1: Data write in the Dual I/O Mode function" newline bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: The serial clock output frequency is fixed and..,1: The serial clock output frequency is variable." newline bitfld.long 0x0 22. "TWOB,2-bit Transfer Mode Active\nNote that when enabling TWOB the serial transmitted 2-bits data are from SPI_TX1/0 and the received 2-bits data input are put into SPI_RX1/0." "0: 2-bit transfer mode Disabled,1: 2-bit transfer mode Enabled" newline bitfld.long 0x0 21. "FIFOM,FIFO Mode Enable\nNote: \nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set '1' automatically after the data was written into the 8-depth FIFO." "0: Normal mode,1: FIFO mode" newline bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable" "0,1" newline bitfld.long 0x0 18. "SLAVE,Slave Mode" "0: SPI controller set as Master mode,1: SPI controller set as Slave mode" newline bitfld.long 0x0 17. "INTEN,Interrupt Enable" "0: SPI Interrupt Disabled,1: SPI Interrupt Enabled" newline hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nIf the Variable Clock function is enabled the minimum period of suspend interval (the transmit data in FIFO buffer is not empty) between the successive transaction is (6.5 + SP_CYCLE) * SPICLK clock cycle." newline bitfld.long 0x0 11. "CLKP,Clock Polarity" "0: The default level of SCLK is low in idle state,1: The default level of SCLK is high in idle state" newline bitfld.long 0x0 10. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI_TX0/1 is sent first to.." newline hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length" newline bitfld.long 0x0 2. "TX_NEG,Transmit At Negative Edge" "0: The transmitted data output is changed on the..,1: The transmitted data output is changed on the.." newline bitfld.long 0x0 1. "RX_NEG,Receive At Negative Edge" "0: The received data is latched on the rising edge..,1: The received data is latched on the falling edge.." newline bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of '1'. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI.." "0: Writing this bit '0' will stop data transfer if..,1: In Master mode writing '1' to this bit will.." line.long 0x4 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x4 20.--23. 1. "TX_FIFO_CNT,Data counts in TX FIFO (Read Only)" newline hexmask.long.byte 0x4 16.--19. 1. "RX_FIFO_CNT,Data counts in RX FIFO (Read Only)" newline bitfld.long 0x4 12. "TIME_OUT_STS,TIMEOUT Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: There is not timeout event on the received buffer,1: RX fifo is not empty and there is not be read.." newline rbitfld.long 0x4 10. "TXINT_STS,TX FIFO Threshold Interrupt Status (Read Only)" "0: TX valid data counts bigger than TXTHRESHOLD,1: TX valid data counts small or equal than.." newline bitfld.long 0x4 9. "RX_OVER_RUN,RX FIFO Over Run Status\nIf SPI receives data when RX FIFO is full this bit will set to 1 and the received data will dropped.\nNote: This bit will be cleared by writing 1 to itself." "0,1" newline rbitfld.long 0x4 8. "RXINT_STS,RX FIFO Threshold Interrupt Status (Read Only)" "0: RX valid data counts small or equal than..,1: RX valid data counts bigger than RXTHRESHOLD" newline bitfld.long 0x4 7. "INTSTS,Interrupt Status\nNote: This bit is read only but can be cleared by writing '1' to this bit." "0: Transfer is not finished yet,1: Transfer is done. The interrupt is requested.." newline bitfld.long 0x4 6. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave mode with no slave select." "0: Slave started transfer no active,1: Transfer has started in Slave mode with no slave.." newline bitfld.long 0x4 4. "LTRIG_FLAG,Level Trigger Accomplish Flag (INTERNAL ONLY)\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GO_BUSY.." "0: The transferred bit length of one transaction..,1: The transferred bit length meets the specified.." newline bitfld.long 0x4 3. "TX_FULL,Transmitted FIFO_FULL Status" "0: Transmitted data FIFO is not full in the dual..,1: Transmitted data FIFO is full in the dual FIFO.." newline bitfld.long 0x4 2. "TX_EMPTY,Transmitted FIFO_EMPTY Status" "0: Transmitted data FIFO is not empty in the dual..,1: Transmitted data FIFO is empty in the dual FIFO.." newline bitfld.long 0x4 1. "RX_FULL,Received FIFO_FULL Status" "0: Received data FIFO is not full in dual FIFO mode,1: Received data FIFO is full in the dual FIFO mode" newline bitfld.long 0x4 0. "RX_EMPTY,Received FIFO_EMPTY Status" "0: Received data FIFO is not empty in the dual FIFO..,1: Received data FIFO is empty in the dual FIFO mode" line.long 0x8 "SPI_CLKDIV,SPI Clock Divider Register" hexmask.long.byte 0x8 16.--23. 1. "DIVIDER2,Clock Divider 2 Register \nThe value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation:" newline hexmask.long.byte 0x8 0.--7. 1. "DIVIDER1,Clock Divider 1 Register \nThe value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. The desired frequency is obtained according to the following equation: \nWhere\n is the SPI engine clock.." line.long 0xC "SPI_SSR,SPI Slave Select Register" bitfld.long 0xC 16. "SS_INT_OPT,Slave Select Interrupt Option \nIt is used to enable the interrupt when the transfer has done in slave mode." "0: No any interrupt even there is slave select..,1: There is interrupt event when the slave select.." newline bitfld.long 0xC 9. "SSTA_INTEN,Slave Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave mode with no slave select. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the.." "0: Tansfer start interrupt Disabled,1: Transaction start interrupt Enabled. It is.." newline bitfld.long 0xC 8. "SLV_ABORT,Abort in Slave Mode with No Slave Selected\nIn normal operation there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial.." "0,1" newline bitfld.long 0xC 5. "NOSLVSEL,No Slave Selected in Slave Mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK SPI_MISO and SPI_MOSI when it is set as a slave device.\nNote: In no slave select.." "0: The controller is 4-wire bi-direction interface,1: The controller is 3-wire bi-direction interface.." newline bitfld.long 0xC 4. "SS_LTRIG,Slave Select Level Trigger" "0: The input slave select signal is edge-trigger,1: The slave select signal will be level-trigger." newline bitfld.long 0xC 3. "AUTOSS,Automatic Slave Selection (Master Only)" "0: If this bit is set as '0' slave select signals..,1: If this bit is set as '1' SPISS[1:0] signals are.." newline bitfld.long 0xC 2. "SS_LVL,Slave Select Active Level\nIt defines the active level of device/slave select signal (SPISS[1:0])." "0: The SPI_SS slave select signal is active Low,1: The SPI_SS slave select signal is active High" newline bitfld.long 0xC 0.--1. "SSR,Slave Select Active Register (Master Only)\nIf AUTOSS bit is cleared writing '1' to SSR[0] bit sets the SPISS[0] line to an active state and writing '0' sets the line back to inactive state.(the same as SSR[1] for SPISS[1])\nIf AUTOSS bit is set .." "0,1,2,3" rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,SPI Receive Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "RDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RX_EMPTY SPI_STATUS[0] to check if there is any more received data or not. \nNote: These registers are read only." line.long 0x4 "SPI_RX1,SPI Receive Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "RDATA,Receive Data FIFO Register\nThe received data can be read on it. If the FIFO bit is set as 1 the user also checks the RX_EMPTY SPI_STATUS[0] to check if there is any more received data or not. \nNote: These registers are read only." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,SPI Transmit Data FIFO Register 0" hexmask.long 0x0 0.--31. 1. "TDATA,Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if TX_BIT_LEN is set.." line.long 0x4 "SPI_TX1,SPI Transmit Data FIFO Register 1" hexmask.long 0x4 0.--31. 1. "TDATA,Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example if TX_BIT_LEN is set.." group.long 0x34++0xB line.long 0x0 "SPI_VARCLK,SPI Variable Clock Pattern Flag Register" hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK. If the bit pattern of VARCLK is '0' the output frequency of SPICLK is according the value of DIVIDER1. If the bit patterns of VARCLK are '1' the output.." line.long 0x4 "SPI_DMA,SPI DMA Control Register" bitfld.long 0x4 2. "PDMA_RST,PDMA Reset\nIt is used to reset the SPI PDMA function into default state. \nNote: it is auto cleared to '0' after the reset function done." "0: After reset PDMA function or in normal operation,1: Reset PDMA function" newline bitfld.long 0x4 1. "RX_DMA_EN,Receiving PDMA Enable(PDMA Reads SPI Data to Memory)\nSet this bit to '1' will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when there is data written into the received buffer or the status.." "0,1" newline bitfld.long 0x4 0. "TX_DMA_EN,Transmit PDMA Enable (PDMA Writes Data to SPI)\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data remember not to set GO_BUSY bit of.." "0,1" line.long 0x8 "SPI_FFCTL,SPI FIFO Control Register" bitfld.long 0x8 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\n3-bit register value from 0 ~7.\n If TX valid data counts small or equal than TXTHRESHOLD TXINT_STS will set to 1 else TXINT_STS will set to 0." "?,?,?,3: bit register,?,?,?,?" newline bitfld.long 0x8 24.--26. "RX_THRESHOLD,Received FIFO Threshold\n3-bits register value from 0 ~7.\n If RX valid data counts large than RXTHRESHOLD RXINT_STS will set to 1 else RXINT_STS will set to 0." "?,?,?,3: bits register,?,?,?,?" newline bitfld.long 0x8 7. "TIMEOUT_EN,RX Read timeout function enable" "0: RX read Timeout function Disabled,1: RX read Timeout function Enabled" newline bitfld.long 0x8 4. "RXOVINT_EN,RX FIFO Over Run Interrupt Enable" "0: RX FIFO over run interrupt Disabled,1: RX FIFO over run interrupt Enabled" newline bitfld.long 0x8 3. "TXINT_EN,TX Threshold Interrupt Enable" "0: Tx threshold interrupt Disabled,1: TX threshold interrupt Enable" newline bitfld.long 0x8 2. "RXINT_EN,RX Threshold Interrupt Enable" "0: Rx threshold interrupt Disabled,1: RX threshold interrupt Enable" newline bitfld.long 0x8 1. "TX_CLR,Transmitting FIFO Counter Clear\nThis bit is used to clear the transmit counter in FIFO Mode. This bit can be written '1' to clear the transmitting counter and this bit will be cleared to '0' automatically after clearing transmitting counter." "0,1" newline bitfld.long 0x8 0. "RX_CLR,Receiving FIFO Counter Clear\nThis bit is used to clear the receiver counter in FIFO Mode. This bit can be written '1' to clear the receiver counter and this bit will be cleared to '0' automatically after clearing receiving counter. After the.." "0,1" group.long 0x50++0x3 line.long 0x0 "SPI_INTERNAL,SPI INTERNAL Register" tree.end endif tree.end tree "TMR (Timer Controller)" base ad:0x0 tree "TMR0" base ad:0x40010000 sif (cpuis("NANO1*AN")) group.long 0x0++0x17 line.long 0x0 "TMR0_CTL,Timer 0 Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx +1 will be in.." "0: Inter-timer trigger mode is disabled,1: Inter-timer trigger mode is enabled" bitfld.long 0x0 22. "TCAP_DEB_EN,TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,TCapture Pin Edge Detect Selection\n" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: Transition on TCapture pin is used as timer..,1: Transition on TCapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,TCapture Pin Functional Enable\nThis bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN (TMRx_CTL[24]) is set the TCAP_EN will be forced to.." "0: The transition on TCapture pin is ignored,1: The transition on TCapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n" "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]) the 24-bit.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is.." "0: TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and..,1: TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA.." newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS Or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS.." bitfld.long 0x0 8. "ADC_TEEN,TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller will.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]).." newline rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n" "0: Timer is not active,1: Timer is in active" bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable\n" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." bitfld.long 0x0 2. "WAKE_EN,Wake-Up Enable\nWhen WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set the timer controller will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0.\nNote: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR0_PRECNT,Timer 0 Pre-scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-Scale Counter\n" line.long 0x8 "TMR0_CMPR,Timer 0 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is.." line.long 0xC "TMR0_IER,Timer 0 Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE.." "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNOTE: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR0_ISR,Timer 0 Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down.." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high and the transition of external pin matches the TCAP_EDGE.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this.." "0,1" line.long 0x14 "TMR0_DR,Timer 0 Data Register" hexmask.long.tbyte 0x14 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." rgroup.long 0x18++0x3 line.long 0x0 "TMR0_TCAP,Timer 0 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set TCAP_MODE (TMRx_CTL[17]) is 0 TCAP_CNT_MOD (TMRx_CTL[20]) is 0 and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting the value of 24-bit up-counting.." endif sif (cpuis("NANO1*BN")) group.long 0x0++0x13 line.long 0x0 "TMR_CTL,Timer x Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if Inter-timer Trigger mode is enabled.\nIf Inter-timer Trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx+1 will be in.." "0: Inter-timer trigger mode Disabled,1: Inter-timer trigger mode Enabled" bitfld.long 0x0 22. "CAP_DEB_EN,Tcapture Pin De-bounce Enable\nWhen CAP_DEB_EN is set the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by MODE_SEL field." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,Tcapture Pin Edge Detect Selection" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,Tcapture Pin Function Mode Selection\nThis bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: The transition on Tcapture pin is used as timer..,1: The transition on Tcapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,Tcapture Pin Functional Enable\nThis bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN is set the TCAP_EN will be forced to low and the.." "0: The transition on Tcapture pin is ignored,1: The transition on Tcapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1." "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE the 24-bit up-counting timer.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA DAC and ADC while TMR_IS or TCAP_IS is set.\nIf this bit is low and TMR_IS is set timer will generate an internal trigger event to PDMA DAC or.." "0: TMR_IS is used to trigger PDMA DAC and ADC,1: TCAP_IS is used to trigger PDMA DAC and ADC" newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to PDMA.." "0: TMR_IS or TCAP_IS trigger PDMA Disabled,1: TMR_IS or TCAP_IS trigger PDMA Enabled" bitfld.long 0x0 9. "DAC_TEEN,TMR_IS or TCAP_IS Trigger DAC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger DAC.\nWhen DAC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to DAC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger DAC Disabled,1: TMR_IS or TCAP_IS trigger DAC Enabled" newline bitfld.long 0x0 8. "ADC_TEEN,TMR_IS or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger ADC.\nWhen ADC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to ADC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger ADC Disabled,1: TMR_IS or TCAP_IS trigger ADC Enabled" rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select" "0,1,2,3" bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." newline bitfld.long 0x0 2. "WAKE_EN,Wake-up Enable\nWhen WAKE_EN is set and the TMR_IS or TCAP_IS is set the timer controller will generate a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_CTL [TMR_EN] to 0.\nNote: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." newline bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR_PRECNT,Timer x Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-scale Counter" line.long 0x8 "TMR_CMPR,Timer x Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled." line.long 0xC "TMR_IER,Timer x Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNote: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting" "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNote: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR_ISR,Timer x Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged and drop the new.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN is set high and the transition of external pin matches the TCAP_EDGE setting. Write 1 to.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to 0.\nIf this bit.." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "TMR_DR,Timer x Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." line.long 0x4 "TMR_TCAP,Timer x Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN is set TCAP_MODE is 0 and the transition of external pin matches the TCAP_EDGE setting the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. User can read this register for the.." endif rgroup.long 0x200++0x17 line.long 0x0 "GPA_SHADOW,GPIO Port A Pin Value Shadow Register" bitfld.long 0x0 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" newline bitfld.long 0x0 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x0 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" line.long 0x4 "GPB_SHADOW,GPIO Port B Pin Value Shadow Register" bitfld.long 0x4 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" newline bitfld.long 0x4 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x4 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" line.long 0x8 "GPC_SHADOW,GPIO Port C Pin Value Shadow Register" bitfld.long 0x8 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" newline bitfld.long 0x8 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x8 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" line.long 0xC "GPD_SHADOW,GPIO Port D Pin Value Shadow Register" bitfld.long 0xC 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" newline bitfld.long 0xC 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0xC 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" line.long 0x10 "GPE_SHADOW,GPIO Port E Pin Value Shadow Register" bitfld.long 0x10 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" newline bitfld.long 0x10 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x10 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" line.long 0x14 "GPF_SHADOW,GPIO Port F Pin Value Shadow Register" bitfld.long 0x14 15. "PIN15,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 14. "PIN14,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 13. "PIN13,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 12. "PIN12,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 11. "PIN11,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 10. "PIN10,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 9. "PIN9,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 8. "PIN8,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 7. "PIN7,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 6. "PIN6,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 5. "PIN5,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 4. "PIN4,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 3. "PIN3,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 2. "PIN2,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" newline bitfld.long 0x14 1. "PIN1,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" bitfld.long 0x14 0. "PIN0,GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW bits [15:9] are reserved." "0,1" tree.end tree "TMR1" base ad:0x40010100 sif (cpuis("NANO1*AN")) group.long 0x0++0x17 line.long 0x0 "TMR1_CTL,Timer 1 Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx +1 will be in.." "0: Inter-timer trigger mode is disabled,1: Inter-timer trigger mode is enabled" bitfld.long 0x0 22. "TCAP_DEB_EN,TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,TCapture Pin Edge Detect Selection\n" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: Transition on TCapture pin is used as timer..,1: Transition on TCapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,TCapture Pin Functional Enable\nThis bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN (TMRx_CTL[24]) is set the TCAP_EN will be forced to.." "0: The transition on TCapture pin is ignored,1: The transition on TCapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n" "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]) the 24-bit.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is.." "0: TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and..,1: TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA.." newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS Or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS.." bitfld.long 0x0 8. "ADC_TEEN,TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller will.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]).." newline rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n" "0: Timer is not active,1: Timer is in active" bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable\n" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." bitfld.long 0x0 2. "WAKE_EN,Wake-Up Enable\nWhen WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set the timer controller will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0.\nNote: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR1_PRECNT,Timer 1 Pre-scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-Scale Counter\n" line.long 0x8 "TMR1_CMPR,Timer 1 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is.." line.long 0xC "TMR1_IER,Timer 1 Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE.." "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNOTE: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR1_ISR,Timer 1 Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down.." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high and the transition of external pin matches the TCAP_EDGE.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this.." "0,1" line.long 0x14 "TMR1_DR,Timer 1 Data Register" hexmask.long.tbyte 0x14 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." rgroup.long 0x18++0x3 line.long 0x0 "TMR1_TCAP,Timer 1 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set TCAP_MODE (TMRx_CTL[17]) is 0 TCAP_CNT_MOD (TMRx_CTL[20]) is 0 and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting the value of 24-bit up-counting.." endif sif (cpuis("NANO1*BN")) group.long 0x0++0x13 line.long 0x0 "TMR_CTL,Timer x Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if Inter-timer Trigger mode is enabled.\nIf Inter-timer Trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx+1 will be in.." "0: Inter-timer trigger mode Disabled,1: Inter-timer trigger mode Enabled" bitfld.long 0x0 22. "CAP_DEB_EN,Tcapture Pin De-bounce Enable\nWhen CAP_DEB_EN is set the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by MODE_SEL field." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,Tcapture Pin Edge Detect Selection" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,Tcapture Pin Function Mode Selection\nThis bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: The transition on Tcapture pin is used as timer..,1: The transition on Tcapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,Tcapture Pin Functional Enable\nThis bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN is set the TCAP_EN will be forced to low and the.." "0: The transition on Tcapture pin is ignored,1: The transition on Tcapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1." "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE the 24-bit up-counting timer.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA DAC and ADC while TMR_IS or TCAP_IS is set.\nIf this bit is low and TMR_IS is set timer will generate an internal trigger event to PDMA DAC or.." "0: TMR_IS is used to trigger PDMA DAC and ADC,1: TCAP_IS is used to trigger PDMA DAC and ADC" newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to PDMA.." "0: TMR_IS or TCAP_IS trigger PDMA Disabled,1: TMR_IS or TCAP_IS trigger PDMA Enabled" bitfld.long 0x0 9. "DAC_TEEN,TMR_IS or TCAP_IS Trigger DAC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger DAC.\nWhen DAC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to DAC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger DAC Disabled,1: TMR_IS or TCAP_IS trigger DAC Enabled" newline bitfld.long 0x0 8. "ADC_TEEN,TMR_IS or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger ADC.\nWhen ADC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to ADC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger ADC Disabled,1: TMR_IS or TCAP_IS trigger ADC Enabled" rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select" "0,1,2,3" bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." newline bitfld.long 0x0 2. "WAKE_EN,Wake-up Enable\nWhen WAKE_EN is set and the TMR_IS or TCAP_IS is set the timer controller will generate a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_CTL [TMR_EN] to 0.\nNote: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." newline bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR_PRECNT,Timer x Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-scale Counter" line.long 0x8 "TMR_CMPR,Timer x Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled." line.long 0xC "TMR_IER,Timer x Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNote: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting" "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNote: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR_ISR,Timer x Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged and drop the new.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN is set high and the transition of external pin matches the TCAP_EDGE setting. Write 1 to.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to 0.\nIf this bit.." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "TMR_DR,Timer x Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." line.long 0x4 "TMR_TCAP,Timer x Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN is set TCAP_MODE is 0 and the transition of external pin matches the TCAP_EDGE setting the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. User can read this register for the.." endif tree.end tree "TMR2" base ad:0x40110000 sif (cpuis("NANO1*AN")) group.long 0x0++0x17 line.long 0x0 "TMR2_CTL,Timer 2 Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx +1 will be in.." "0: Inter-timer trigger mode is disabled,1: Inter-timer trigger mode is enabled" bitfld.long 0x0 22. "TCAP_DEB_EN,TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,TCapture Pin Edge Detect Selection\n" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: Transition on TCapture pin is used as timer..,1: Transition on TCapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,TCapture Pin Functional Enable\nThis bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN (TMRx_CTL[24]) is set the TCAP_EN will be forced to.." "0: The transition on TCapture pin is ignored,1: The transition on TCapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n" "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]) the 24-bit.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is.." "0: TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and..,1: TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA.." newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS Or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS.." bitfld.long 0x0 8. "ADC_TEEN,TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller will.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]).." newline rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n" "0: Timer is not active,1: Timer is in active" bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable\n" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." bitfld.long 0x0 2. "WAKE_EN,Wake-Up Enable\nWhen WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set the timer controller will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0.\nNote: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR2_PRECNT,Timer 2 Pre-scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-Scale Counter\n" line.long 0x8 "TMR2_CMPR,Timer 2 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is.." line.long 0xC "TMR2_IER,Timer 2 Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE.." "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNOTE: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR2_ISR,Timer 2 Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down.." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high and the transition of external pin matches the TCAP_EDGE.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this.." "0,1" line.long 0x14 "TMR2_DR,Timer 2 Data Register" hexmask.long.tbyte 0x14 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." rgroup.long 0x18++0x3 line.long 0x0 "TMR2_TCAP,Timer 2 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set TCAP_MODE (TMRx_CTL[17]) is 0 TCAP_CNT_MOD (TMRx_CTL[20]) is 0 and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting the value of 24-bit up-counting.." endif sif (cpuis("NANO1*BN")) group.long 0x0++0x13 line.long 0x0 "TMR_CTL,Timer x Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if Inter-timer Trigger mode is enabled.\nIf Inter-timer Trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx+1 will be in.." "0: Inter-timer trigger mode Disabled,1: Inter-timer trigger mode Enabled" bitfld.long 0x0 22. "CAP_DEB_EN,Tcapture Pin De-bounce Enable\nWhen CAP_DEB_EN is set the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by MODE_SEL field." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,Tcapture Pin Edge Detect Selection" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,Tcapture Pin Function Mode Selection\nThis bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: The transition on Tcapture pin is used as timer..,1: The transition on Tcapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,Tcapture Pin Functional Enable\nThis bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN is set the TCAP_EN will be forced to low and the.." "0: The transition on Tcapture pin is ignored,1: The transition on Tcapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1." "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE the 24-bit up-counting timer.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA DAC and ADC while TMR_IS or TCAP_IS is set.\nIf this bit is low and TMR_IS is set timer will generate an internal trigger event to PDMA DAC or.." "0: TMR_IS is used to trigger PDMA DAC and ADC,1: TCAP_IS is used to trigger PDMA DAC and ADC" newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to PDMA.." "0: TMR_IS or TCAP_IS trigger PDMA Disabled,1: TMR_IS or TCAP_IS trigger PDMA Enabled" bitfld.long 0x0 9. "DAC_TEEN,TMR_IS or TCAP_IS Trigger DAC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger DAC.\nWhen DAC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to DAC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger DAC Disabled,1: TMR_IS or TCAP_IS trigger DAC Enabled" newline bitfld.long 0x0 8. "ADC_TEEN,TMR_IS or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger ADC.\nWhen ADC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to ADC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger ADC Disabled,1: TMR_IS or TCAP_IS trigger ADC Enabled" rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select" "0,1,2,3" bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." newline bitfld.long 0x0 2. "WAKE_EN,Wake-up Enable\nWhen WAKE_EN is set and the TMR_IS or TCAP_IS is set the timer controller will generate a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_CTL [TMR_EN] to 0.\nNote: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." newline bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR_PRECNT,Timer x Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-scale Counter" line.long 0x8 "TMR_CMPR,Timer x Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled." line.long 0xC "TMR_IER,Timer x Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNote: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting" "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNote: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR_ISR,Timer x Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged and drop the new.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN is set high and the transition of external pin matches the TCAP_EDGE setting. Write 1 to.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to 0.\nIf this bit.." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "TMR_DR,Timer x Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." line.long 0x4 "TMR_TCAP,Timer x Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN is set TCAP_MODE is 0 and the transition of external pin matches the TCAP_EDGE setting the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. User can read this register for the.." endif tree.end tree "TMR3" base ad:0x40110100 sif (cpuis("NANO1*AN")) group.long 0x0++0x17 line.long 0x0 "TMR3_CTL,Timer 3 Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx +1 will be in.." "0: Inter-timer trigger mode is disabled,1: Inter-timer trigger mode is enabled" bitfld.long 0x0 22. "TCAP_DEB_EN,TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by.." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,TCapture Pin Edge Detect Selection\n" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: Transition on TCapture pin is used as timer..,1: Transition on TCapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,TCapture Pin Functional Enable\nThis bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN (TMRx_CTL[24]) is set the TCAP_EN will be forced to.." "0: The transition on TCapture pin is ignored,1: The transition on TCapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n" "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]) the 24-bit.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is.." "0: TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and..,1: TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA.." newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS Or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS.." bitfld.long 0x0 8. "ADC_TEEN,TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low the timer controller will.." "0: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])..,1: TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]).." newline rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n" "0: Timer is not active,1: Timer is in active" bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select\n" "0,1,2,3" newline bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable\n" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." bitfld.long 0x0 2. "WAKE_EN,Wake-Up Enable\nWhen WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set the timer controller will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable" newline bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0.\nNote: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR3_PRECNT,Timer 3 Pre-scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-Scale Counter\n" line.long 0x8 "TMR3_CMPR,Timer 3 Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is.." line.long 0xC "TMR3_IER,Timer 3 Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE.." "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNOTE: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR3_ISR,Timer 3 Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down.." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high and the transition of external pin matches the TCAP_EDGE.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this.." "0,1" line.long 0x14 "TMR3_DR,Timer 3 Data Register" hexmask.long.tbyte 0x14 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." rgroup.long 0x18++0x3 line.long 0x0 "TMR3_TCAP,Timer 3 Capture Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set TCAP_MODE (TMRx_CTL[17]) is 0 TCAP_CNT_MOD (TMRx_CTL[20]) is 0 and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting the value of 24-bit up-counting.." endif sif (cpuis("NANO1*BN")) group.long 0x0++0x13 line.long 0x0 "TMR_CTL,Timer x Control Register" bitfld.long 0x0 24. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if Inter-timer Trigger mode is enabled.\nIf Inter-timer Trigger mode is enabled the TMRx will be in counter mode and counting with external Clock Source or event. And TMRx+1 will be in.." "0: Inter-timer trigger mode Disabled,1: Inter-timer trigger mode Enabled" bitfld.long 0x0 22. "CAP_DEB_EN,Tcapture Pin De-bounce Enable\nWhen CAP_DEB_EN is set the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" newline bitfld.long 0x0 20. "CAP_CNT_MOD,Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.\nIf this bit is 0 the free-counting mode the behavior of 24-bit up-counting timer is defined by MODE_SEL field." "0: Capture with free-counting timer mode,1: Capture with trigger-counting timer mode" bitfld.long 0x0 18.--19. "TCAP_EDGE,Tcapture Pin Edge Detect Selection" "0,1,2,3" newline bitfld.long 0x0 17. "TCAP_MODE,Tcapture Pin Function Mode Selection\nThis bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL if INTR_TRG_EN is set the TCAP_MODE will be forced to low." "0: The transition on Tcapture pin is used as timer..,1: The transition on Tcapture pin is used as timer.." bitfld.long 0x0 16. "TCAP_EN,Tcapture Pin Functional Enable\nThis bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function.\nNote: For TMRx_CTL if INTR_TRG_EN is set the TCAP_EN will be forced to low and the.." "0: The transition on Tcapture pin is ignored,1: The transition on Tcapture pin will result in.." newline bitfld.long 0x0 14. "EVNT_DEB_EN,External Event De-bounce Enable\nWhen EVNT_DEB_EN is set the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by.." "0: De-bounce circuit Disabled,1: De-bounce circuit Enabled" bitfld.long 0x0 13. "EVENT_EDGE,Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1." "0: A falling edge of external event enabling the..,1: A rising edge of external event enabling the.." newline bitfld.long 0x0 12. "EVENT_EN,Event Counting Mode Enable\nWhen EVENT_EN is set the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE the 24-bit up-counting timer.." "0: Timer counting is not controlled by external..,1: Timer counting is controlled by external event pin" bitfld.long 0x0 11. "CAP_TRG_EN,TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA DAC and ADC while TMR_IS or TCAP_IS is set.\nIf this bit is low and TMR_IS is set timer will generate an internal trigger event to PDMA DAC or.." "0: TMR_IS is used to trigger PDMA DAC and ADC,1: TCAP_IS is used to trigger PDMA DAC and ADC" newline bitfld.long 0x0 10. "PDMA_TEEN,TMR_IS or TCAP_IS Trigger PDMA Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger PDMA.\nWhen PDMA_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to PDMA.." "0: TMR_IS or TCAP_IS trigger PDMA Disabled,1: TMR_IS or TCAP_IS trigger PDMA Enabled" bitfld.long 0x0 9. "DAC_TEEN,TMR_IS or TCAP_IS Trigger DAC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger DAC.\nWhen DAC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to DAC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger DAC Disabled,1: TMR_IS or TCAP_IS trigger DAC Enabled" newline bitfld.long 0x0 8. "ADC_TEEN,TMR_IS or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS or TCAP_IS could trigger ADC.\nWhen ADC_TEEN is set TMR_IS is set and the CAP_TRG_EN is low the timer controller will generate an internal trigger event to ADC controller.\nWhen.." "0: TMR_IS or TCAP_IS trigger ADC Disabled,1: TMR_IS or TCAP_IS trigger ADC Enabled" rbitfld.long 0x0 7. "TMR_ACT,Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer." "0: Timer is not active,1: Timer is in active" newline bitfld.long 0x0 4.--5. "MODE_SEL,Timer Operating Mode Select" "0,1,2,3" bitfld.long 0x0 3. "DBGACK_EN,ICE Debug Mode Acknowledge Ineffective Enable" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement is ineffective.." newline bitfld.long 0x0 2. "WAKE_EN,Wake-up Enable\nWhen WAKE_EN is set and the TMR_IS or TCAP_IS is set the timer controller will generate a wake-up trigger event to CPU." "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled" bitfld.long 0x0 1. "SW_RST,Software Reset\nSet this bit will reset the timer counter pre-scale counter and also force TMR_CTL [TMR_EN] to 0.\nNote: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.." newline bitfld.long 0x0 0. "TMR_EN,Timer Counter Enable Bit" "0: Stops/Suspends counting,1: Starts counting" line.long 0x4 "TMR_PRECNT,Timer x Pre-Scale Counter Register" hexmask.long.byte 0x4 0.--7. 1. "PRESCALE_CNT,Pre-scale Counter" line.long 0x8 "TMR_CMPR,Timer x Compare Register" hexmask.long.tbyte 0x8 0.--23. 1. "TMR_CMP,Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled." line.long 0xC "TMR_IER,Timer x Interrupt Enable Register" bitfld.long 0xC 1. "TCAP_IE,Timer Capture Function Interrupt Enable\nNote: If timer external pin function interrupt is enabled the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting" "0: Timer External Pin Function Interrupt Disabled,1: Timer External Pin Function Interrupt Enabled" bitfld.long 0xC 0. "TMR_IE,Timer Interrupt Enable\nNote: If timer interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled" line.long 0x10 "TMR_ISR,Timer x Interrupt Status Register" bitfld.long 0x10 5. "NCAP_DET_STS,New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.\nIf the above condition occurred the Timer will keep register TMRx_CAP unchanged and drop the new.." "0: New incoming capture event didn't detect before..,1: New incoming capture event detected before CPU.." bitfld.long 0x10 4. "TMR_Wake_STS,Timer Wake-up Status\nIf timer causes CPU wakes up from power-down mode this bit will be set to high. It must be cleared by software with a write 1 to this bit." "0: Timer does not cause system wake-up,1: Wakes system up from power-down mode by Timer.." newline bitfld.long 0x10 1. "TCAP_IS,Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN is set high and the transition of external pin matches the TCAP_EDGE setting. Write 1 to.." "0,1" bitfld.long 0x10 0. "TMR_IS,Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to 0.\nIf this bit.." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "TMR_DR,Timer x Data Register" hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value." line.long 0x4 "TMR_TCAP,Timer x Capture Data Register" hexmask.long.tbyte 0x4 0.--23. 1. "CAP,Timer Capture Data Register\nWhen TCAP_EN is set TCAP_MODE is 0 and the transition of external pin matches the TCAP_EDGE setting the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. User can read this register for the.." endif tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x0 tree "UART0" base ad:0x40050000 rgroup.long 0x0++0x3 line.long 0x0 "UART_RBR,UART Receive Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register\nBy reading this register the UART will return an 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,UART Transmit Holding Register." hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART will send out an 8-bit data through the TX pin (LSB first)." group.long 0x4++0x23 line.long 0x0 "UART_CTL,UART Control Register." bitfld.long 0x0 12. "ABAUD_EN,Auto-Baud Rate Detect Enable\nNote: When the auto-baud rate detect operation finishes hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x0 9. "WAKE_DATA_EN,Incoming Data Wake-Up Function Enable \nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system Disabled,1: Incoming data wake-up function Enabled when the.." newline sif (cpuis("NANO1*AN")) bitfld.long 0x0 8. "WAKE_CTS_EN,CTSn Wake-Up Function Enable \n" "0: CTSn wake-up system function Disabled 1 =..,?" newline bitfld.long 0x0 5. "AUTO_CTS_EN,CTSn Auto-Flow Control Enable \n" "?,1: CTSn auto-flow control Enabled" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 8. "WAKE_CTS_EN,CTSn Wake-Up Function Enable" "0: CTSn wake-up system function Disabled,1: Wake-up function Enabled when the system is in.." newline endif bitfld.long 0x0 7. "DMA_TX_EN,TX DMA Enable \nNote: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]) Frame Error Flag.." "0: TX PDMA service function Enabled,1: TX PDMA service function Disabled" newline bitfld.long 0x0 6. "DMA_RX_EN,RX DMA Enable \nNote: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]) Frame Error Flag.." "0: RX PDMA service function Enabled,1: RX PDMA service function Disabled" newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 5. "AUTO_CTS_EN,CTSn Auto-Flow Control Enable \nNote: When CTSn auto-flow is enabled the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted)." "0: CTSn auto-flow control. Disabled,1: CTSn auto-flow control Enabled" newline endif bitfld.long 0x0 4. "AUTO_RTS_EN,RTSn Auto-Flow Control Enable \nWhen RTSn auto-flow is enabled if the number of bytes in the RX-FIFO equals the RTS_TRI_LEV (UART_TLCTL[13:12]) the UART will reassert RTSn signal.\n" "0: RTSn auto-flow control. Disabled,1: RTSn auto-flow control Enabled" newline bitfld.long 0x0 3. "TX_DIS,Transfer Disable Register\n" "0: Transfer Enabled,1: Transfer Disabled" newline bitfld.long 0x0 2. "RX_DIS,Receiver Disable Register\nNote1: In RS-485 NMM mode user can setting this bit to receive data or not that before detect address byte.\nNote2: In RS-485 NMM mode this bit will be setting to '1' automatically.\nNote3: In RS-485 AAD mode and LIN.." "0: Receiver Enabled,1: In RS-485 NMM mode" newline bitfld.long 0x0 1. "TX_RST,TX Software Reset\nWhen TX_RST is set all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART engine clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x0 0. "RX_RST,RX Software Reset\nWhen RX_RST is set all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x4 "UART_TLCTL,UART Transfer Line Control Register." sif (cpuis("NANO1*AN")) bitfld.long 0x4 12.--13. "RTS_TRI_LEV,RTSn Trigger Level (For Auto-Flow Control Use)\nNote: This field is used for auto RTSn flow control." "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,?,?" newline bitfld.long 0x4 8.--9. "RFITL,RX-FIFO Interrupt (INT_RDA) Trigger Level \nWhen the number of bytes in the receiving FIFO equals to the RFITL then the RDA_IF will be set (if RDA_IEN (IER [0]) is enabled an interrupt will be generated)\nNote: When operating in IrDA mode or.." "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,?,?" newline bitfld.long 0x4 6. "BCB,Break Control Bit \nWhen this bit is set to logic '1' the serial data output (TX) is forced to the Spacing State (logic '0'). This bit acts only on TX pin and has no effect on the transmitter logic.\n" "0: Break control Disabled,1: Break control Enabled" newline bitfld.long 0x4 3. "PBE,Parity Bit Enable\n" "0: Parity bit is not generated (transmitting data)..,?" newline bitfld.long 0x4 0.--1. "DATA_LEN,Data Length\n" "0: Word length is 5-bit,1: Word length is 6-bit,?,?" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 12.--13. "RTS_TRI_LEV,RTSn Trigger Level (For Auto-flow Control Use)" "0,1,2,3" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 8.--9. "RFITL,RX-FIFO Interrupt (INT_RDA) Trigger Level" "0,1,2,3" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 6. "BCB,Break Control Bit \nWhen this bit is set to logic '1' the serial data output (TX) is forced to the Spacing State (logic '0'). This bit acts only on TX pin and has no effect on the transmitter logic." "0,1" newline endif bitfld.long 0x4 5. "SPE,Stick Parity Enable \nStick Parity Enable Control\nNote1: When bits PBE EPE and SPE are set the parity bit is transmitted and checked as '0'. When PBE and SPE are set and EPE is cleared the parity bit is transmitted and checked as '1'. \nNote2:.." "0: Stick parity Disabled,1: When bits PBE" newline bitfld.long 0x4 4. "EPE,Even Parity Enable\nNote: This bit has effect only when PBE bit (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or check..,1: Even number of logic 1's are transmitted or.." newline sif (cpuis("NANO1*BN")) bitfld.long 0x4 3. "PBE,Parity Bit Enable" "0: Parity bit is not generated (transmitting data)..,1: Parity bit is generated or checked bet'een the.." newline endif bitfld.long 0x4 2. "NSB,Number Of STOP Bit Length\n" "0: 1 ' STOP bit' is generated in the transmitted data,1: 1.5 'STOP bit' is generated in the transmitted.." line.long 0x8 "UART_IER,UART Interrupt Enable Register." bitfld.long 0x8 8. "LIN_IE,LIN Interrupt Enable\n" "0: INT_LIN Disable,1: INT_LIN Enabled" newline bitfld.long 0x8 7. "ABAUD_IE,Auto-Baud Rate Interrupt Enable\n" "0: INT_ABAUD Disable,1: INT_ABAUD Enabled" newline bitfld.long 0x8 6. "WAKE_IE,Wake-Up Interrupt Enable\n" "0: INT_WAKE Disable,1: INT_WAKE Enabled" newline bitfld.long 0x8 5. "BUF_ERR_IE,Buffer Error Interrupt Enable\n" "0: INT_BUT_ERR Disable,1: INT_BUF_ERR Enabled" newline bitfld.long 0x8 4. "RTO_IE,RX Time-Out Interrupt Enable\n" "0: INT_TOUT Disable,1: INT_TOUT Enabled" newline bitfld.long 0x8 3. "MODEM_IE,Modem Status Interrupt Enable \n" "0: INT_MOS Disable,1: INT_MOS Enabled" newline bitfld.long 0x8 2. "RLS_IE,Receive Line Status Interrupt Enable \n" "0: INT_RLS Disable,1: INT_RLS Enabled" newline bitfld.long 0x8 1. "THRE_IE,Transmit Holding Register Empty Interrupt Enable\n" "0: INT_THRE Disable,1: INT_THRE Enabled" newline bitfld.long 0x8 0. "RDA_IE,Receive Data Available Interrupt Enable\n" "0: INT_RDA Disable,1: INT_RDA Enabled" line.long 0xC "UART_ISR,UART Interrupt Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0xC 8. "LIN_IS,LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted RX header received or the SIN does not equal SOUT and if LIN_IE (IER [8]) is set then the LIN interrupt will be generated. \nNote1: This bit is read only .." "0: No LIN interrupt is generated,1: This bit is read only" newline rbitfld.long 0xC 7. "ABAUD_IS,Auto-Baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (IER [7]) is set then the auto-baud rate interrupt will be.." "0: No Auto-Baud Rate interrupt is generated,1: This bit is read only" newline bitfld.long 0xC 6. "WAKE_IS,Wake-Up Interrupt Status Flag\nThis bit is set in Power-down mode the receiver received data or CTSn signal. If WAKE_IE (IER [6]) is set then the wake-up interrupt will be generated.\nNote: This bit can be cleared by it by writing '1' to it." "0: No Wake-Up interrupt is generated,1: Wake-Up interrupt is generated" newline rbitfld.long 0xC 5. "BUF_ERR_IS,Buffer Error Interrupt Status Flag (Read Only)\nThis bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set the transfer maybe not correct. If BUF_ER_IEN (IER [5]) is set then the buffer error interrupt will be.." "0: No Buffer error interrupt is generated,1: This bit is read only" newline rbitfld.long 0xC 4. "RTO_IS,RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If Tout_IEN (IER [4]) is set then the tout interrupt will be generated." "0: No RX Time-Out interrupt is generated,1: RX Time-Out interrupt is generated" newline rbitfld.long 0xC 3. "MODEM_IS,MODEM Interrupt Status Flag (Read Only) \nNote: This bit is read only but can be cleared by it by writing '1' to DCT_F (UART_MCSR [18])." "0: No MODEM interrupt is generated,1: MODEM interrupt is generated" newline rbitfld.long 0xC 2. "RLS_IS,Receive Line Interrupt Status Flag (Read Only)\nThis bit is set when the RX received data has parity error (PE_F (UART_FSR[4])) framing error (FE_F (UART_FSR[5])) break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F.." "0: No Receive Line interrupt is generated,1: This bit is read only" newline rbitfld.long 0xC 1. "THRE_IS,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If THRE_IEN (IER [1]) is set that the THRE interrupt will be generated.\nNote: This bit is.." "0: No Transmit Holding register empty interrupt is..,1: Transmit Holding register empty interrupt.." newline rbitfld.long 0xC 0. "RDA_IS,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (IER [0]) is set then the RDA interrupt will be generated. \nNote: This bit is read only and it.." "0: No Receive Data available interrupt is generated,1: Receive Data available interrupt is generated" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0xC 8. "LIN_IS,LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted RX header received or the SIN does not equal SOUT and if IER [LIN_IE] is set then the LIN interrupt will be generated. \nNote1: This bit is read only but.." "?,1: This bit is read only" newline rbitfld.long 0xC 7. "ABAUD_IS,Auto-Baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if IER [ABAUD_IE] is set then the auto-baud rate interrupt will be.." "?,1: This bit is read only" newline rbitfld.long 0xC 6. "WAKE_IS,Wake-Up Interrupt Status Flag (Read Only)\nThis bit is set in Power-down mode the receiver received data or CTSn signal. If IER [WAKE_IE] is set then the wake-up interrupt will be generated.\nNote: This bit is read only but can be cleared by.." "0,1" newline rbitfld.long 0xC 5. "BUF_ERR_IS,Buffer Error Interrupt Status Flag (Read Only)\nThis bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set the transfer maybe not correct. If IER [BUF_ER_IEN] is set then the buffer error interrupt will be generated.\nNote1:.." "?,1: This bit is read only" newline rbitfld.long 0xC 4. "RTO_IS,RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If IER [Tout_IEN] is set then the tout interrupt will be generated. \nNote:.." "0,1" newline rbitfld.long 0xC 3. "MODEM_IS,MODEM Interrupt Status Flag (Read Only) \nNote: This bit is read only but can be cleared by it by writing '1' to UART_MCSR [DCT_F]." "0,1" newline rbitfld.long 0xC 2. "RLS_IS,Receive Line Interrupt Status Flag (Read Only).\nThis bit is set when the RX received data has parity error (UART_FSR [PE_F]) framing error (UART_FSR [FE_F]) break error (UART_FSR [BI_F]) or RS-485 detect address byte (UART_TRSR.." "?,1: This bit is read only" newline rbitfld.long 0xC 1. "THRE_IS,Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If IER [THRE_IEN] is set that the THRE interrupt will be generated.\nNote: This bit is read.." "0,1" endif line.long 0x10 "UART_TRSR,UART Transfer Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0x10 8. "LIN_RX_SYNC_ERR_F,LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic '1' when LIN received incorrect SYNC field. \nUser can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register.\nNote: This bit is read only but can be cleared by.." "0: No LIN Rx sync error is generated,1: LIN Rx sync error is generated" newline bitfld.long 0x10 5. "BIT_ERR_F,Bit Error Detect Status Flag\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F will be set.\nWhen occur bit error hardware will generate an.." "0: No Bit error interrupt is generated,1: Bit error interrupt is generated" newline bitfld.long 0x10 4. "LIN_RX_F,LIN RX Interrupt Flag\nThis bit is set to logic '1' when received LIN header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' and it can be choose by setting LIN_HEAD_SEL.." "0: No LIN Rx interrupt is generated,1: LIN Rx interrupt is generated" newline bitfld.long 0x10 3. "LIN_TX_F,LIN TX Interrupt Flag\nThis bit is set to logic '1' when LIN transmitted header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' it can be choose by setting LIN_HEAD_SEL.." "0: No LIN Tx interrupt is generated,1: LIN Tx interrupt is generated" newline bitfld.long 0x10 2. "ABAUD_TOUT_F,Auto-Baud Rate Time-Out Interrupt\nThis bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: No Auto-Baud Rate Time-Out interrupt is generated,1: Auto-Baud Rate Time-Out interrupt is generated" newline bitfld.long 0x10 1. "ABAUD_F,Auto-Baud Rate Interrupt\nThis bit is set to logic '1' when auto-baud rate detect function finished.\nNote: This bit can be cleared by writing '1' to it." "0: No Auto- Baud Rate interrupt is generated,1: Auto-Baud Rate interrupt is generated" newline bitfld.long 0x10 0. "RS_485_ADDET_F,RS-485 Address Byte Detection Status Flag\nNote1: This field is used for RS-485 mode.\nNote2: This bit can be cleared by writing '1' to it." "0: No RS-485 address detection interrupt is generated,1: This field is used for RS-485 mode" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x10 8. "LIN_RX_SYNC_ERR_F,LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic '1' when LIN received incorrect SYNC field. \nUser can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register.\nIf the field includes 'break field + sync field' and.." "0,1" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x10 5. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state is not equal to the output pin (SOUT) state BIT_ERR_F will be set.\nWhen occur bit error hardware will.." "?,1: This bit is read only" newline rbitfld.long 0x10 4. "LIN_RX_F,LIN RX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when received LIN header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' and it can be choose by setting UART_ALT_CTL.." "0,1" newline rbitfld.long 0x10 3. "LIN_TX_F,LIN TX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when LIN transmitted header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' it can be choose by setting.." "0,1" newline rbitfld.long 0x10 2. "ABAUD_TOUT_F,Auto-Baud Rate Time-Out Interrupt (Read Only)\nThis bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x10 1. "ABAUD_F,Auto-Baud Rate Interrupt (Read Only)\nThis bit is set to logic '1' when auto-baud rate detect function finished.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x10 0. "RS_485_ADDET_F,RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 mode.\nNote2: This bit is read only but can be cleared by writing '1' to it." "?,1: This field is used for RS-485 mode" endif line.long 0x14 "UART_FSR,UART FIFO Status Register." hexmask.long.byte 0x14 24.--28. 1. "TX_POINTER_F,TX-FIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register TX_POINTER_F.." newline hexmask.long.byte 0x14 16.--20. 1. "RX_POINTER_F,RX-FIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU RX_POINTER_F decreases one." newline sif (cpuis("NANO1*AN")) rbitfld.long 0x14 11. "TE_F,Transmitter Empty Status Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. \nThis bit is cleared automatically when TX FIFO is not empty or the last byte transmission.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline rbitfld.long 0x14 10. "TX_FULL_F,Transmitter FIFO Full (Read Only)\nThis bit indicates TX-FIFO full or not.\nThis bit is set when TX_POINTER_F is equal to 16 otherwise is cleared by hardware.\n" "0: TX FIFO is not full,1: TX FIFO is full" newline rbitfld.long 0x14 9. "TX_EMPTY_F,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX-FIFO empty or not.\nWhen the last byte of TX-FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline bitfld.long 0x14 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag\nIf TX-FIFO (UART_THR) is full an additional write to UART_THR will cause this bit to logic '1'. \nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline bitfld.long 0x14 6. "BI_F,Break Status Flag\nThis bit is set to a logic '1' whenever the received data input(RX) is held in the 'spacing state' (logic '0') for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).." "0: No Break interrupt is generated,1: Break interrupt is generated" newline bitfld.long 0x14 5. "FE_F,Framing Error Status Flag\nThis bit is set to logic '1' whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic '0') and it is reset whenever the CPU.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x14 4. "PE_F,Parity Error State Status Flag\nThis bit is set to logic '1' whenever the received character does not have a valid 'parity bit' and it is reset whenever the CPU writes '1' to this bit.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" newline rbitfld.long 0x14 2. "RX_FULL_F,Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16 otherwise is cleared by hardware.\n" "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x14 1. "RX_EMPTY_F,Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data.\n" "0: RX FIFO is not empty,1: RX FIFO is empty" newline bitfld.long 0x14 0. "RX_OVER_F,RX Overflow Error Status Flag \nThis bit is set when RX-FIFO overflow.\nIf the number of bytes of received data is greater than RX-FIFO (UART_RBR) size 16 bytes of UART0/UART1 this bit will be set.\nNote: This bit can be cleared by writing.." "0: RX FIFO is not overflow,1: RX FIFO is overflow" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x14 11. "TE_F,Transmitter Empty Status Flag (Read Only)\nBit is set by hardware when TX is inactive. (TX shift register does not have data)\nBit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not.." "0,1" newline rbitfld.long 0x14 10. "TX_FULL_F,Transmitter FIFO Full (Read Only)\nThis bit indicates TX-FIFO full or not.\nThis bit is set when TX_POINTER_F is equal to 16 otherwise is cleared by hardware." "0,1" newline rbitfld.long 0x14 9. "TX_EMPTY_F,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX-FIFO empty or not.\nWhen the last byte of TX-FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0,1" newline rbitfld.long 0x14 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX-FIFO (UART_THR) is full an additional write to UART_THR will cause this bit to logic '1'. \nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x14 6. "BI_F,Break Status Flag (Read Only)\nThis bit is set to a logic '1' whenever the received data input(RX) is held in the 'spacing state' (logic '0') for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity.." "0,1" newline rbitfld.long 0x14 5. "FE_F,Framing Error Status Flag (Read Only)\nThis bit is set to logic '1' whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic '0') and it is reset.." "0,1" newline rbitfld.long 0x14 4. "PE_F,Parity Error State Status Flag (Read Only)\nThis bit is set to logic '1' whenever the received character does not have a valid 'parity bit' and it is reset whenever the CPU writes '1' to this bit.\nNote: This bit is read only but it can be cleared.." "0,1" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x14 2. "RX_FULL_F,Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16 otherwise is cleared by hardware." "0,1" newline rbitfld.long 0x14 1. "RX_EMPTY_F,Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1" newline rbitfld.long 0x14 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX-FIFO overflow.\nIf the number of bytes of received data is greater than RX-FIFO (UART_RBR) size 16 bytes of UART0/UART1 this bit will be set.\nNote: This bit is read only .." "0,1" endif line.long 0x18 "UART_MCSR,UART Modem Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0x18 18. "DCT_F,Detect CTSn State Change Status Flag (Read Only)\nThis bit is set whenever CTSn input has change state and it will generate Modem interrupt to CPU when Modem_IEN (UART_IER [3]).\nNote: This bit is read only but it can be cleared by writing '1' to.." "0: CTS input has not change state,1: CTS input has change state" newline rbitfld.long 0x18 17. "CTS_ST,CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.\n" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline rbitfld.long 0x18 1. "RTS_ST,RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.\n" "0: RTS pin input is low level voltage logic state,1: RTS pin input is high level voltage logic state" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x18 18. "DCT_F,Detect CTSn State Change Status Flag (Read Only)\nThis bit is set whenever CTSn input has change state and it will generate Modem interrupt to CPU when UART_IER [Modem_IEN].\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x18 17. "CTS_ST,CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn." "0,1" newline endif bitfld.long 0x18 16. "LEV_CTS,CTSn Trigger Level\n" "0: Low level triggered,1: High level triggered" newline sif (cpuis("NANO1*BN")) rbitfld.long 0x18 1. "RTS_ST,RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn." "0,1" newline endif bitfld.long 0x18 0. "LEV_RTS,RTSn Trigger Level \n" "0: low level triggered,1: high level triggered" line.long 0x1C "UART_TMCTL,UART Time-out Control Register." hexmask.long.byte 0x1C 16.--23. 1. "DLY,TX Delay Time Value\nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n \nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real delay value is DLY.\nNote3: The.." newline hexmask.long.word 0x1C 0.--8. 1. "TOIC,Time-Out Comparator\nThe time-out counter resets and starts counting whenever the RX-FIFO receives a new data word. \nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real time-out value is TOIC + 1.\nNote3: The.." line.long 0x20 "UART_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x20 31. "DIV_16_EN,Divider 16 Enable\nNote: In IrDA mode this bit must disable." "0: The equation of baud rate is UART_CLK / [ (BRD+1)],1: The equation of baud rate is UART_CLK / [16 *.." newline hexmask.long.word 0x20 0.--15. 1. "BRD,Baud Rate Divider \n" group.long 0x30++0x3 line.long 0x0 "UART_IRCR,UART IrDA Control Register." bitfld.long 0x0 6. "INV_RX,INV_RX\n" "0: RX input signal no inversion,1: RX input signal inversion" newline bitfld.long 0x0 5. "INV_TX,INV_TX\n" "0: TX output signal no inversion,1: TX output signal inversion" newline bitfld.long 0x0 1. "TX_SELECT,TX_SELECT\n" "0: Select IrDA receiver,1: Select IrDA transmitter" sif (cpuis("NANO1*AN")) group.long 0x34++0x3 line.long 0x0 "UART_ALT_CTL,UART Alternate Control State Register." hexmask.long.byte 0x0 24.--31. 1. "ADDR_PID_MATCH,Address / PID Match Value Register\nWhen in the RS-485 Function Mode this field contains the RS-485 address match values.\nWhen in the LIN Function mode this field contains the LIN protected identifier field software fills ID0~ID5.." bitfld.long 0x0 19. "RS_485_ADD_EN,RS-485 Address Detection Enable\nThis bit is used to enable RS-485 hardware address detection mode.\n" "0: Address detection mode Disabled,1: Address detection mode Enabled.Note: This field.." newline bitfld.long 0x0 18. "RS_485_AUD,RS-485 Auto Direction Mode (RS-485 AUD Mode)\n" "0: RS-485 Auto Direction mode (AUD) Disabled,1: RS-485 Auto Direction mode (AUD) Enabled.Note:.." bitfld.long 0x0 17. "RS_485_AAD,RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\n" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0x0 16. "RS_485_NMM,RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\n" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0x0 8. "BIT_ERR_EN,Bit Error Detect Enable\n" "0: Bit error detection Disabled,1: Bit error detection Enabled.Note: In LIN.." newline bitfld.long 0x0 7. "LIN_TX_EN,LIN TX Header Trigger Enable\nNote2: If user wants to receive transmit data it recommended to enable LIN_RX_EN bit." "0: LIN TX Header Trigger Disabled,1: LIN TX Header Trigger Enabled.Note1: This bit.." bitfld.long 0x0 6. "LIN_RX_EN,LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL) the controller will generator a interrupt to CPU (INT_LIN)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x0 4.--5. "LIN_HEAD_SEL,LIN Header Selection\n" "0: The LIN header includes 'break field',1: The LIN header includes 'break field + sync field',?,?" bitfld.long 0x0 0.--2. "LIN_TX_BCNT,LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8." "?,?,?,3: bit LIN TX break field count,?,?,?,?" endif sif (cpuis("NANO1*BN")) group.long 0x34++0x3 line.long 0x0 "UART_ALT_CSR,UART Alternate Control State Register." hexmask.long.byte 0x0 24.--31. 1. "ADDR_PID_MATCH,Address / PID Match Value Register\nThis field contains the RS-485 address match values in RS-485 Function mode.\nThis field contains the LIN protected identifier field n LIN Function mode software fills ID0~ID5 (ADDR_PID_MATCH [5:0]) .." bitfld.long 0x0 19. "RS_485_ADD_EN,RS-485 Address Detection Enable\nNote: This field is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0x0 18. "RS_485_AUD,RS-485 Auto Direction Mode (RS-485 AUD Mode)\nNote: It can be active in RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction mode (AUD) Disabled,1: RS-485 Auto Direction mode (AUD) Enabled" bitfld.long 0x0 17. "RS_485_AAD,RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\nNote: It can't be active in RS-485_NMM Operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0x0 16. "RS_485_NMM,RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\nNote: It can't be active in RS-485_AAD Operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0x0 8. "Bit_ERR_EN,Bit Error Detect Enable\nNote: In LIN function mode when bit error occurs hardware will generate an interrupt to CPU (INT_LIN)." "0: Bit error detection function Disabled,1: Bit error detection Enabled" newline bitfld.long 0x0 7. "LIN_TX_EN,LIN TX Header Trigger Enable\nNote1: When TX header field (break field or break and sync field or break sync and PID field) transfer operation finished this bit will be cleared automatically and generate a interrupt to CPU (INT_LIN).\nNote2:.." "0: LIN TX Header Trigger Disabled,1: When TX header field" bitfld.long 0x0 6. "LIN_RX_EN,LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL) the controller will generator a interrupt to CPU (INT_LIN)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x0 4.--5. "LIN_HEAD_SEL,LIN Header Selection\n" "0,1,2,3" bitfld.long 0x0 0.--2. "LIN_TX_BCNT,LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8." "?,?,?,3: bit LIN TX break field count,?,?,?,?" endif group.long 0x38++0x3 line.long 0x0 "UART_FUN_SEL,UART Function Select Register." sif (cpuis("NANO1*AN")) bitfld.long 0x0 0.--1. "FUN_SEL,Function Select Enable\n" "0: UART function mode,1: LIN function mode,?,?" endif tree.end tree "UART1" base ad:0x40150000 rgroup.long 0x0++0x3 line.long 0x0 "UART_RBR,UART Receive Buffer Register." hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register\nBy reading this register the UART will return an 8-bit data received from RX pin (LSB first)." wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,UART Transmit Holding Register." hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART will send out an 8-bit data through the TX pin (LSB first)." group.long 0x4++0x23 line.long 0x0 "UART_CTL,UART Control Register." bitfld.long 0x0 12. "ABAUD_EN,Auto-Baud Rate Detect Enable\nNote: When the auto-baud rate detect operation finishes hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" newline bitfld.long 0x0 9. "WAKE_DATA_EN,Incoming Data Wake-Up Function Enable \nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system Disabled,1: Incoming data wake-up function Enabled when the.." newline sif (cpuis("NANO1*AN")) bitfld.long 0x0 8. "WAKE_CTS_EN,CTSn Wake-Up Function Enable \n" "0: CTSn wake-up system function Disabled 1 =..,?" newline bitfld.long 0x0 5. "AUTO_CTS_EN,CTSn Auto-Flow Control Enable \n" "?,1: CTSn auto-flow control Enabled" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x0 8. "WAKE_CTS_EN,CTSn Wake-Up Function Enable" "0: CTSn wake-up system function Disabled,1: Wake-up function Enabled when the system is in.." newline endif bitfld.long 0x0 7. "DMA_TX_EN,TX DMA Enable \nNote: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]) Frame Error Flag.." "0: TX PDMA service function Enabled,1: TX PDMA service function Disabled" newline bitfld.long 0x0 6. "DMA_RX_EN,RX DMA Enable \nNote: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]) Frame Error Flag.." "0: RX PDMA service function Enabled,1: RX PDMA service function Disabled" newline sif (cpuis("NANO1*BN")) bitfld.long 0x0 5. "AUTO_CTS_EN,CTSn Auto-Flow Control Enable \nNote: When CTSn auto-flow is enabled the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted)." "0: CTSn auto-flow control. Disabled,1: CTSn auto-flow control Enabled" newline endif bitfld.long 0x0 4. "AUTO_RTS_EN,RTSn Auto-Flow Control Enable \nWhen RTSn auto-flow is enabled if the number of bytes in the RX-FIFO equals the RTS_TRI_LEV (UART_TLCTL[13:12]) the UART will reassert RTSn signal.\n" "0: RTSn auto-flow control. Disabled,1: RTSn auto-flow control Enabled" newline bitfld.long 0x0 3. "TX_DIS,Transfer Disable Register\n" "0: Transfer Enabled,1: Transfer Disabled" newline bitfld.long 0x0 2. "RX_DIS,Receiver Disable Register\nNote1: In RS-485 NMM mode user can setting this bit to receive data or not that before detect address byte.\nNote2: In RS-485 NMM mode this bit will be setting to '1' automatically.\nNote3: In RS-485 AAD mode and LIN.." "0: Receiver Enabled,1: In RS-485 NMM mode" newline bitfld.long 0x0 1. "TX_RST,TX Software Reset\nWhen TX_RST is set all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART engine clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers" newline bitfld.long 0x0 0. "RX_RST,RX Software Reset\nWhen RX_RST is set all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers" line.long 0x4 "UART_TLCTL,UART Transfer Line Control Register." sif (cpuis("NANO1*AN")) bitfld.long 0x4 12.--13. "RTS_TRI_LEV,RTSn Trigger Level (For Auto-Flow Control Use)\nNote: This field is used for auto RTSn flow control." "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,?,?" newline bitfld.long 0x4 8.--9. "RFITL,RX-FIFO Interrupt (INT_RDA) Trigger Level \nWhen the number of bytes in the receiving FIFO equals to the RFITL then the RDA_IF will be set (if RDA_IEN (IER [0]) is enabled an interrupt will be generated)\nNote: When operating in IrDA mode or.." "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,?,?" newline bitfld.long 0x4 6. "BCB,Break Control Bit \nWhen this bit is set to logic '1' the serial data output (TX) is forced to the Spacing State (logic '0'). This bit acts only on TX pin and has no effect on the transmitter logic.\n" "0: Break control Disabled,1: Break control Enabled" newline bitfld.long 0x4 3. "PBE,Parity Bit Enable\n" "0: Parity bit is not generated (transmitting data)..,?" newline bitfld.long 0x4 0.--1. "DATA_LEN,Data Length\n" "0: Word length is 5-bit,1: Word length is 6-bit,?,?" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 12.--13. "RTS_TRI_LEV,RTSn Trigger Level (For Auto-flow Control Use)" "0,1,2,3" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 8.--9. "RFITL,RX-FIFO Interrupt (INT_RDA) Trigger Level" "0,1,2,3" newline endif sif (cpuis("NANO1*BN")) bitfld.long 0x4 6. "BCB,Break Control Bit \nWhen this bit is set to logic '1' the serial data output (TX) is forced to the Spacing State (logic '0'). This bit acts only on TX pin and has no effect on the transmitter logic." "0,1" newline endif bitfld.long 0x4 5. "SPE,Stick Parity Enable \nStick Parity Enable Control\nNote1: When bits PBE EPE and SPE are set the parity bit is transmitted and checked as '0'. When PBE and SPE are set and EPE is cleared the parity bit is transmitted and checked as '1'. \nNote2:.." "0: Stick parity Disabled,1: When bits PBE" newline bitfld.long 0x4 4. "EPE,Even Parity Enable\nNote: This bit has effect only when PBE bit (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or check..,1: Even number of logic 1's are transmitted or.." newline sif (cpuis("NANO1*BN")) bitfld.long 0x4 3. "PBE,Parity Bit Enable" "0: Parity bit is not generated (transmitting data)..,1: Parity bit is generated or checked bet'een the.." newline endif bitfld.long 0x4 2. "NSB,Number Of STOP Bit Length\n" "0: 1 ' STOP bit' is generated in the transmitted data,1: 1.5 'STOP bit' is generated in the transmitted.." line.long 0x8 "UART_IER,UART Interrupt Enable Register." bitfld.long 0x8 8. "LIN_IE,LIN Interrupt Enable\n" "0: INT_LIN Disable,1: INT_LIN Enabled" newline bitfld.long 0x8 7. "ABAUD_IE,Auto-Baud Rate Interrupt Enable\n" "0: INT_ABAUD Disable,1: INT_ABAUD Enabled" newline bitfld.long 0x8 6. "WAKE_IE,Wake-Up Interrupt Enable\n" "0: INT_WAKE Disable,1: INT_WAKE Enabled" newline bitfld.long 0x8 5. "BUF_ERR_IE,Buffer Error Interrupt Enable\n" "0: INT_BUT_ERR Disable,1: INT_BUF_ERR Enabled" newline bitfld.long 0x8 4. "RTO_IE,RX Time-Out Interrupt Enable\n" "0: INT_TOUT Disable,1: INT_TOUT Enabled" newline bitfld.long 0x8 3. "MODEM_IE,Modem Status Interrupt Enable \n" "0: INT_MOS Disable,1: INT_MOS Enabled" newline bitfld.long 0x8 2. "RLS_IE,Receive Line Status Interrupt Enable \n" "0: INT_RLS Disable,1: INT_RLS Enabled" newline bitfld.long 0x8 1. "THRE_IE,Transmit Holding Register Empty Interrupt Enable\n" "0: INT_THRE Disable,1: INT_THRE Enabled" newline bitfld.long 0x8 0. "RDA_IE,Receive Data Available Interrupt Enable\n" "0: INT_RDA Disable,1: INT_RDA Enabled" line.long 0xC "UART_ISR,UART Interrupt Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0xC 8. "LIN_IS,LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted RX header received or the SIN does not equal SOUT and if LIN_IE (IER [8]) is set then the LIN interrupt will be generated. \nNote1: This bit is read only .." "0: No LIN interrupt is generated,1: This bit is read only" newline rbitfld.long 0xC 7. "ABAUD_IS,Auto-Baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (IER [7]) is set then the auto-baud rate interrupt will be.." "0: No Auto-Baud Rate interrupt is generated,1: This bit is read only" newline bitfld.long 0xC 6. "WAKE_IS,Wake-Up Interrupt Status Flag\nThis bit is set in Power-down mode the receiver received data or CTSn signal. If WAKE_IE (IER [6]) is set then the wake-up interrupt will be generated.\nNote: This bit can be cleared by it by writing '1' to it." "0: No Wake-Up interrupt is generated,1: Wake-Up interrupt is generated" newline rbitfld.long 0xC 5. "BUF_ERR_IS,Buffer Error Interrupt Status Flag (Read Only)\nThis bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set the transfer maybe not correct. If BUF_ER_IEN (IER [5]) is set then the buffer error interrupt will be.." "0: No Buffer error interrupt is generated,1: This bit is read only" newline rbitfld.long 0xC 4. "RTO_IS,RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If Tout_IEN (IER [4]) is set then the tout interrupt will be generated." "0: No RX Time-Out interrupt is generated,1: RX Time-Out interrupt is generated" newline rbitfld.long 0xC 3. "MODEM_IS,MODEM Interrupt Status Flag (Read Only) \nNote: This bit is read only but can be cleared by it by writing '1' to DCT_F (UART_MCSR [18])." "0: No MODEM interrupt is generated,1: MODEM interrupt is generated" newline rbitfld.long 0xC 2. "RLS_IS,Receive Line Interrupt Status Flag (Read Only)\nThis bit is set when the RX received data has parity error (PE_F (UART_FSR[4])) framing error (FE_F (UART_FSR[5])) break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F.." "0: No Receive Line interrupt is generated,1: This bit is read only" newline rbitfld.long 0xC 1. "THRE_IS,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If THRE_IEN (IER [1]) is set that the THRE interrupt will be generated.\nNote: This bit is.." "0: No Transmit Holding register empty interrupt is..,1: Transmit Holding register empty interrupt.." newline rbitfld.long 0xC 0. "RDA_IS,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (IER [0]) is set then the RDA interrupt will be generated. \nNote: This bit is read only and it.." "0: No Receive Data available interrupt is generated,1: Receive Data available interrupt is generated" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0xC 8. "LIN_IS,LIN Interrupt Status Flag (Read Only)\nThis bit is set when the LIN TX header transmitted RX header received or the SIN does not equal SOUT and if IER [LIN_IE] is set then the LIN interrupt will be generated. \nNote1: This bit is read only but.." "?,1: This bit is read only" newline rbitfld.long 0xC 7. "ABAUD_IS,Auto-Baud Rate Interrupt Status Flag (Read Only)\nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if IER [ABAUD_IE] is set then the auto-baud rate interrupt will be.." "?,1: This bit is read only" newline rbitfld.long 0xC 6. "WAKE_IS,Wake-Up Interrupt Status Flag (Read Only)\nThis bit is set in Power-down mode the receiver received data or CTSn signal. If IER [WAKE_IE] is set then the wake-up interrupt will be generated.\nNote: This bit is read only but can be cleared by.." "0,1" newline rbitfld.long 0xC 5. "BUF_ERR_IS,Buffer Error Interrupt Status Flag (Read Only)\nThis bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set the transfer maybe not correct. If IER [BUF_ER_IEN] is set then the buffer error interrupt will be generated.\nNote1:.." "?,1: This bit is read only" newline rbitfld.long 0xC 4. "RTO_IS,RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If IER [Tout_IEN] is set then the tout interrupt will be generated. \nNote:.." "0,1" newline rbitfld.long 0xC 3. "MODEM_IS,MODEM Interrupt Status Flag (Read Only) \nNote: This bit is read only but can be cleared by it by writing '1' to UART_MCSR [DCT_F]." "0,1" newline rbitfld.long 0xC 2. "RLS_IS,Receive Line Interrupt Status Flag (Read Only).\nThis bit is set when the RX received data has parity error (UART_FSR [PE_F]) framing error (UART_FSR [FE_F]) break error (UART_FSR [BI_F]) or RS-485 detect address byte (UART_TRSR.." "?,1: This bit is read only" newline rbitfld.long 0xC 1. "THRE_IS,Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If IER [THRE_IEN] is set that the THRE interrupt will be generated.\nNote: This bit is read.." "0,1" endif line.long 0x10 "UART_TRSR,UART Transfer Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0x10 8. "LIN_RX_SYNC_ERR_F,LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic '1' when LIN received incorrect SYNC field. \nUser can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register.\nNote: This bit is read only but can be cleared by.." "0: No LIN Rx sync error is generated,1: LIN Rx sync error is generated" newline bitfld.long 0x10 5. "BIT_ERR_F,Bit Error Detect Status Flag\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F will be set.\nWhen occur bit error hardware will generate an.." "0: No Bit error interrupt is generated,1: Bit error interrupt is generated" newline bitfld.long 0x10 4. "LIN_RX_F,LIN RX Interrupt Flag\nThis bit is set to logic '1' when received LIN header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' and it can be choose by setting LIN_HEAD_SEL.." "0: No LIN Rx interrupt is generated,1: LIN Rx interrupt is generated" newline bitfld.long 0x10 3. "LIN_TX_F,LIN TX Interrupt Flag\nThis bit is set to logic '1' when LIN transmitted header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' it can be choose by setting LIN_HEAD_SEL.." "0: No LIN Tx interrupt is generated,1: LIN Tx interrupt is generated" newline bitfld.long 0x10 2. "ABAUD_TOUT_F,Auto-Baud Rate Time-Out Interrupt\nThis bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: No Auto-Baud Rate Time-Out interrupt is generated,1: Auto-Baud Rate Time-Out interrupt is generated" newline bitfld.long 0x10 1. "ABAUD_F,Auto-Baud Rate Interrupt\nThis bit is set to logic '1' when auto-baud rate detect function finished.\nNote: This bit can be cleared by writing '1' to it." "0: No Auto- Baud Rate interrupt is generated,1: Auto-Baud Rate interrupt is generated" newline bitfld.long 0x10 0. "RS_485_ADDET_F,RS-485 Address Byte Detection Status Flag\nNote1: This field is used for RS-485 mode.\nNote2: This bit can be cleared by writing '1' to it." "0: No RS-485 address detection interrupt is generated,1: This field is used for RS-485 mode" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x10 8. "LIN_RX_SYNC_ERR_F,LIN RX SYNC Error Flag (Read Only)\nThis bit is set to logic '1' when LIN received incorrect SYNC field. \nUser can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register.\nIf the field includes 'break field + sync field' and.." "0,1" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x10 5. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state is not equal to the output pin (SOUT) state BIT_ERR_F will be set.\nWhen occur bit error hardware will.." "?,1: This bit is read only" newline rbitfld.long 0x10 4. "LIN_RX_F,LIN RX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when received LIN header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' and it can be choose by setting UART_ALT_CTL.." "0,1" newline rbitfld.long 0x10 3. "LIN_TX_F,LIN TX Interrupt Flag (Read Only)\nThis bit is set to logic '1' when LIN transmitted header field. The header may be 'break field' or 'break field + sync field' or 'break field + sync field + PID field' it can be choose by setting.." "0,1" newline rbitfld.long 0x10 2. "ABAUD_TOUT_F,Auto-Baud Rate Time-Out Interrupt (Read Only)\nThis bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x10 1. "ABAUD_F,Auto-Baud Rate Interrupt (Read Only)\nThis bit is set to logic '1' when auto-baud rate detect function finished.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x10 0. "RS_485_ADDET_F,RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 mode.\nNote2: This bit is read only but can be cleared by writing '1' to it." "?,1: This field is used for RS-485 mode" endif line.long 0x14 "UART_FSR,UART FIFO Status Register." hexmask.long.byte 0x14 24.--28. 1. "TX_POINTER_F,TX-FIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register TX_POINTER_F.." newline hexmask.long.byte 0x14 16.--20. 1. "RX_POINTER_F,RX-FIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU RX_POINTER_F decreases one." newline sif (cpuis("NANO1*AN")) rbitfld.long 0x14 11. "TE_F,Transmitter Empty Status Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. \nThis bit is cleared automatically when TX FIFO is not empty or the last byte transmission.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline rbitfld.long 0x14 10. "TX_FULL_F,Transmitter FIFO Full (Read Only)\nThis bit indicates TX-FIFO full or not.\nThis bit is set when TX_POINTER_F is equal to 16 otherwise is cleared by hardware.\n" "0: TX FIFO is not full,1: TX FIFO is full" newline rbitfld.long 0x14 9. "TX_EMPTY_F,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX-FIFO empty or not.\nWhen the last byte of TX-FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0: TX FIFO is not empty,1: TX FIFO is empty" newline bitfld.long 0x14 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag\nIf TX-FIFO (UART_THR) is full an additional write to UART_THR will cause this bit to logic '1'. \nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline bitfld.long 0x14 6. "BI_F,Break Status Flag\nThis bit is set to a logic '1' whenever the received data input(RX) is held in the 'spacing state' (logic '0') for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).." "0: No Break interrupt is generated,1: Break interrupt is generated" newline bitfld.long 0x14 5. "FE_F,Framing Error Status Flag\nThis bit is set to logic '1' whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic '0') and it is reset whenever the CPU.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x14 4. "PE_F,Parity Error State Status Flag\nThis bit is set to logic '1' whenever the received character does not have a valid 'parity bit' and it is reset whenever the CPU writes '1' to this bit.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated" newline rbitfld.long 0x14 2. "RX_FULL_F,Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16 otherwise is cleared by hardware.\n" "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x14 1. "RX_EMPTY_F,Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data.\n" "0: RX FIFO is not empty,1: RX FIFO is empty" newline bitfld.long 0x14 0. "RX_OVER_F,RX Overflow Error Status Flag \nThis bit is set when RX-FIFO overflow.\nIf the number of bytes of received data is greater than RX-FIFO (UART_RBR) size 16 bytes of UART0/UART1 this bit will be set.\nNote: This bit can be cleared by writing.." "0: RX FIFO is not overflow,1: RX FIFO is overflow" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x14 11. "TE_F,Transmitter Empty Status Flag (Read Only)\nBit is set by hardware when TX is inactive. (TX shift register does not have data)\nBit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not.." "0,1" newline rbitfld.long 0x14 10. "TX_FULL_F,Transmitter FIFO Full (Read Only)\nThis bit indicates TX-FIFO full or not.\nThis bit is set when TX_POINTER_F is equal to 16 otherwise is cleared by hardware." "0,1" newline rbitfld.long 0x14 9. "TX_EMPTY_F,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX-FIFO empty or not.\nWhen the last byte of TX-FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR.." "0,1" newline rbitfld.long 0x14 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX-FIFO (UART_THR) is full an additional write to UART_THR will cause this bit to logic '1'. \nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x14 6. "BI_F,Break Status Flag (Read Only)\nThis bit is set to a logic '1' whenever the received data input(RX) is held in the 'spacing state' (logic '0') for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity.." "0,1" newline rbitfld.long 0x14 5. "FE_F,Framing Error Status Flag (Read Only)\nThis bit is set to logic '1' whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic '0') and it is reset.." "0,1" newline rbitfld.long 0x14 4. "PE_F,Parity Error State Status Flag (Read Only)\nThis bit is set to logic '1' whenever the received character does not have a valid 'parity bit' and it is reset whenever the CPU writes '1' to this bit.\nNote: This bit is read only but it can be cleared.." "0,1" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x14 2. "RX_FULL_F,Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16 otherwise is cleared by hardware." "0,1" newline rbitfld.long 0x14 1. "RX_EMPTY_F,Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1" newline rbitfld.long 0x14 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX-FIFO overflow.\nIf the number of bytes of received data is greater than RX-FIFO (UART_RBR) size 16 bytes of UART0/UART1 this bit will be set.\nNote: This bit is read only .." "0,1" endif line.long 0x18 "UART_MCSR,UART Modem Status Register." sif (cpuis("NANO1*AN")) rbitfld.long 0x18 18. "DCT_F,Detect CTSn State Change Status Flag (Read Only)\nThis bit is set whenever CTSn input has change state and it will generate Modem interrupt to CPU when Modem_IEN (UART_IER [3]).\nNote: This bit is read only but it can be cleared by writing '1' to.." "0: CTS input has not change state,1: CTS input has change state" newline rbitfld.long 0x18 17. "CTS_ST,CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.\n" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state" newline rbitfld.long 0x18 1. "RTS_ST,RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.\n" "0: RTS pin input is low level voltage logic state,1: RTS pin input is high level voltage logic state" newline endif sif (cpuis("NANO1*BN")) rbitfld.long 0x18 18. "DCT_F,Detect CTSn State Change Status Flag (Read Only)\nThis bit is set whenever CTSn input has change state and it will generate Modem interrupt to CPU when UART_IER [Modem_IEN].\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1" newline rbitfld.long 0x18 17. "CTS_ST,CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn." "0,1" newline endif bitfld.long 0x18 16. "LEV_CTS,CTSn Trigger Level\n" "0: Low level triggered,1: High level triggered" newline sif (cpuis("NANO1*BN")) rbitfld.long 0x18 1. "RTS_ST,RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn." "0,1" newline endif bitfld.long 0x18 0. "LEV_RTS,RTSn Trigger Level \n" "0: low level triggered,1: high level triggered" line.long 0x1C "UART_TMCTL,UART Time-out Control Register." hexmask.long.byte 0x1C 16.--23. 1. "DLY,TX Delay Time Value\nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n \nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real delay value is DLY.\nNote3: The.." newline hexmask.long.word 0x1C 0.--8. 1. "TOIC,Time-Out Comparator\nThe time-out counter resets and starts counting whenever the RX-FIFO receives a new data word. \nNote1: Fill all '0' to this field indicates to disable this function.\nNote2: The real time-out value is TOIC + 1.\nNote3: The.." line.long 0x20 "UART_BAUD,UART Baud Rate Divisor Register" bitfld.long 0x20 31. "DIV_16_EN,Divider 16 Enable\nNote: In IrDA mode this bit must disable." "0: The equation of baud rate is UART_CLK / [ (BRD+1)],1: The equation of baud rate is UART_CLK / [16 *.." newline hexmask.long.word 0x20 0.--15. 1. "BRD,Baud Rate Divider \n" group.long 0x30++0x3 line.long 0x0 "UART_IRCR,UART IrDA Control Register." bitfld.long 0x0 6. "INV_RX,INV_RX\n" "0: RX input signal no inversion,1: RX input signal inversion" newline bitfld.long 0x0 5. "INV_TX,INV_TX\n" "0: TX output signal no inversion,1: TX output signal inversion" newline bitfld.long 0x0 1. "TX_SELECT,TX_SELECT\n" "0: Select IrDA receiver,1: Select IrDA transmitter" sif (cpuis("NANO1*AN")) group.long 0x34++0x3 line.long 0x0 "UART_ALT_CTL,UART Alternate Control State Register." hexmask.long.byte 0x0 24.--31. 1. "ADDR_PID_MATCH,Address / PID Match Value Register\nWhen in the RS-485 Function Mode this field contains the RS-485 address match values.\nWhen in the LIN Function mode this field contains the LIN protected identifier field software fills ID0~ID5.." bitfld.long 0x0 19. "RS_485_ADD_EN,RS-485 Address Detection Enable\nThis bit is used to enable RS-485 hardware address detection mode.\n" "0: Address detection mode Disabled,1: Address detection mode Enabled.Note: This field.." newline bitfld.long 0x0 18. "RS_485_AUD,RS-485 Auto Direction Mode (RS-485 AUD Mode)\n" "0: RS-485 Auto Direction mode (AUD) Disabled,1: RS-485 Auto Direction mode (AUD) Enabled.Note:.." bitfld.long 0x0 17. "RS_485_AAD,RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\n" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0x0 16. "RS_485_NMM,RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\n" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0x0 8. "BIT_ERR_EN,Bit Error Detect Enable\n" "0: Bit error detection Disabled,1: Bit error detection Enabled.Note: In LIN.." newline bitfld.long 0x0 7. "LIN_TX_EN,LIN TX Header Trigger Enable\nNote2: If user wants to receive transmit data it recommended to enable LIN_RX_EN bit." "0: LIN TX Header Trigger Disabled,1: LIN TX Header Trigger Enabled.Note1: This bit.." bitfld.long 0x0 6. "LIN_RX_EN,LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL) the controller will generator a interrupt to CPU (INT_LIN)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x0 4.--5. "LIN_HEAD_SEL,LIN Header Selection\n" "0: The LIN header includes 'break field',1: The LIN header includes 'break field + sync field',?,?" bitfld.long 0x0 0.--2. "LIN_TX_BCNT,LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8." "?,?,?,3: bit LIN TX break field count,?,?,?,?" endif sif (cpuis("NANO1*BN")) group.long 0x34++0x3 line.long 0x0 "UART_ALT_CSR,UART Alternate Control State Register." hexmask.long.byte 0x0 24.--31. 1. "ADDR_PID_MATCH,Address / PID Match Value Register\nThis field contains the RS-485 address match values in RS-485 Function mode.\nThis field contains the LIN protected identifier field n LIN Function mode software fills ID0~ID5 (ADDR_PID_MATCH [5:0]) .." bitfld.long 0x0 19. "RS_485_ADD_EN,RS-485 Address Detection Enable\nNote: This field is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled" newline bitfld.long 0x0 18. "RS_485_AUD,RS-485 Auto Direction Mode (RS-485 AUD Mode)\nNote: It can be active in RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction mode (AUD) Disabled,1: RS-485 Auto Direction mode (AUD) Enabled" bitfld.long 0x0 17. "RS_485_AAD,RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\nNote: It can't be active in RS-485_NMM Operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." newline bitfld.long 0x0 16. "RS_485_NMM,RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\nNote: It can't be active in RS-485_AAD Operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." bitfld.long 0x0 8. "Bit_ERR_EN,Bit Error Detect Enable\nNote: In LIN function mode when bit error occurs hardware will generate an interrupt to CPU (INT_LIN)." "0: Bit error detection function Disabled,1: Bit error detection Enabled" newline bitfld.long 0x0 7. "LIN_TX_EN,LIN TX Header Trigger Enable\nNote1: When TX header field (break field or break and sync field or break sync and PID field) transfer operation finished this bit will be cleared automatically and generate a interrupt to CPU (INT_LIN).\nNote2:.." "0: LIN TX Header Trigger Disabled,1: When TX header field" bitfld.long 0x0 6. "LIN_RX_EN,LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL) the controller will generator a interrupt to CPU (INT_LIN)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x0 4.--5. "LIN_HEAD_SEL,LIN Header Selection\n" "0,1,2,3" bitfld.long 0x0 0.--2. "LIN_TX_BCNT,LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8." "?,?,?,3: bit LIN TX break field count,?,?,?,?" endif group.long 0x38++0x3 line.long 0x0 "UART_FUN_SEL,UART Function Select Register." sif (cpuis("NANO1*AN")) bitfld.long 0x0 0.--1. "FUN_SEL,Function Select Enable\n" "0: UART function mode,1: LIN function mode,?,?" endif tree.end tree.end tree "USB (Universal Serial Bus)" base ad:0x40060000 group.long 0x0++0x3 line.long 0x0 "USB_CTL,USB Control Register" bitfld.long 0x0 9. "WAKEUP_EN,Wake-Up Function Enable\n" "0: USB wake-up function Disabled,1: USB wake-up function Enabled" bitfld.long 0x0 8. "RWAKEUP,Remote Wake-Up\n" "0: Don't force USB bus to K state,1: Force USB bus to K (USB_DP low USB_DM: high).." newline bitfld.long 0x0 4. "DRVSE0,Force USB PHY Transceiver To Drive SE0 (Single Ended Zero)\nThe Single Ended Zero is present when both lines (USB_DP USB_DM) are being pulled low.\nThe default value is '1'." "0: None,1: Force USB PHY transceiver to drive SE0" bitfld.long 0x0 3. "DPPU_EN,Pull-Up Resistor On USB_DP Enable\n" "0: Disabled the pull-up resistor in USB_DP bus,1: Pull-up resistor in USB_DP bus will be active" newline bitfld.long 0x0 2. "PWRDB,Power Down PHY Transceiver Low Active\n" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver" bitfld.long 0x0 1. "PHY_EN,PHY Transceiver Enable\n" "0: PHY transceiver Disabled,1: PHY transceiver Enabled" newline bitfld.long 0x0 0. "USB_EN,USB Function Enable\n" "0: USB Disabled,1: USB Enabled" rgroup.long 0x4++0x3 line.long 0x0 "USB_BUSSTS,USB Bus Status Register" bitfld.long 0x0 4. "FLDET,Device Floating Detection\n" "0: The controller didn't attach into the USB,1: When the controller is attached into the USB.." bitfld.long 0x0 3. "TIMEOUT,Time Out Flag\n" "?,1: Bus no any response more than 18 bits time. It.." newline bitfld.long 0x0 2. "RESUME,Resume Status\n" "?,1: Resume from suspend. It is read only" bitfld.long 0x0 1. "SUSPEND,Suspend Status \n" "?,1: Bus idle more than 3mS either cable is plugged.." newline bitfld.long 0x0 0. "USBRST,USB Reset Status \n" "?,1: Bus reset when SE0 (single-ended 0) more than.." group.long 0x8++0xB line.long 0x0 "USB_INTEN,Interrupt Enable Register" bitfld.long 0x0 3. "WAKEUP_IE,USB Wake-Up Interrupt Enable\n" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" bitfld.long 0x0 2. "FLDET_IE,Floating Detect Interrupt Enable\n" "0: Floating detect Interrupt Disabled,1: Floating detect Interrupt Enabled" newline bitfld.long 0x0 1. "USBEVT_IE,USB Event Interrupt Enable\n" "0: USB event interrupt Disabled,1: USB event interrupt Enabled" bitfld.long 0x0 0. "BUSEVT_IE,Bus Event Interrupt Enable\n" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled" line.long 0x4 "USB_INTSTS,Interrupt Event Status Register" bitfld.long 0x4 31. "SETUP,Setup Event Status \n" "0: No Setup event,1: Setup event occurred cleared by write '1' to.." sif (cpuis("NANO1*BN")) bitfld.long 0x4 23. "EPEVT7,USB Event Status on EP7" "0: No event occurred in Endpoint 7,1: USB event occurred on Endpoint 7 check.." newline bitfld.long 0x4 22. "EPEVT6,USB Event Status on EP6" "0: No event occurred in Endpoint 6,1: USB event occurred on Endpoint 6 check.." endif bitfld.long 0x4 21. "EPEVT5,USB Event Status On EP5\n" "0: No event occurred in Endpoint 5,1: USB event occurred on Endpoint 5 check.." newline bitfld.long 0x4 20. "EPEVT4,USB Event Status On EP4\n" "0: No event occurred in Endpoint 4,1: USB event occurred on Endpoint 4 check.." bitfld.long 0x4 19. "EPEVT3,USB Event Status On EP3\n" "0: No event occurred in Endpoint 3,1: USB event occurred on Endpoint 3 check.." newline bitfld.long 0x4 18. "EPEVT2,USB Event Status On EP2\n" "0: No event occurred in Endpoint 2,1: USB event occurred on Endpoint 2 check.." bitfld.long 0x4 17. "EPEVT1,USB Event Status On EP1\n" "0: No event occurred in Endpoint 1,1: USB event occurred on Endpoint 1 check.." newline bitfld.long 0x4 16. "EPEVT0,USB Event Status On EP0\n" "0: No event occurred in Endpoint 0,1: USB event occurred on Endpoint 0 check.." bitfld.long 0x4 3. "WKEUP_STS,Wake-Up Interrupt Status\n" "0: No wake-up event is occurred,1: Wake-up event occurred cleared by write 1 to.." newline bitfld.long 0x4 2. "FLD_STS,Floating Interrupt Status\n" "0: There is not attached event in the USB,1: There is attached event in the USB and it is.." bitfld.long 0x4 1. "USB_STS,USB Interrupt Status\nThe USB event means that there is Setup Token IN token OUT ACK ISO IN or ISO OUT event in the bus. This bit is used to indicate that there is one of events in the bus.\n" "0: No USB event is occurred,1: USB event occurred check EPSTS0~5[3:0] in.." newline bitfld.long 0x4 0. "BUS_STS,BUS Interrupt Status\nThe BUS event means there is bus suspense or bus resume in the bus. This bit is used to indicate that there is one of events in the bus.\n" "0: No BUS event is occurred,1: BUS event occurred; check USB_BUSSTS [3:0] to.." line.long 0x8 "USB_FADDR,Device Function Address Register" hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB device's function address" rgroup.long 0x14++0x3 line.long 0x0 "USB_EPSTS,Endpoint Status Register" hexmask.long.byte 0x0 28.--31. 1. "EPSTS5,Endpoint 5 Bus Status\n" hexmask.long.byte 0x0 24.--27. 1. "EPSTS4,Endpoint 4 Bus Status\n" newline hexmask.long.byte 0x0 20.--23. 1. "EPSTS3,Endpoint 3 Bus Status\n" hexmask.long.byte 0x0 16.--19. 1. "EPSTS2,Endpoint 2 Bus Status\n" newline hexmask.long.byte 0x0 12.--15. 1. "EPSTS1,Endpoint 1 Bus Status\n" hexmask.long.byte 0x0 8.--11. 1. "EPSTS0,Endpoint 0 Bus Status\n" newline bitfld.long 0x0 7. "OVERRUN,Overrun\nIt means the received data is over the maximum payload number or not.\n" "0: No overrun,1: Out Data more than the Max Payload in MXPLD.." group.long 0x18++0x3 line.long 0x0 "USB_BUFSEG,Setup Token Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG," sif (cpuis("NANO1*BN")) rgroup.long 0x1C++0x3 line.long 0x0 "USB_EPSTS2,Endpoint Bus Status" bitfld.long 0x0 4.--6. "EPSTS7,Endpoint 7 Bus Status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "EPSTS6,Endpoint 6 Bus Status" "0,1,2,3,4,5,6,7" group.long 0x80++0xB line.long 0x0 "USB_BUFSEG6,Endpoint 6 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD6,Endpoint 6 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG6,Endpoint 6 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0x90++0xB line.long 0x0 "USB_BUFSEG7,Endpoint 7 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD7,Endpoint 7 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG7,Endpoint 7 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0xA0++0x3 line.long 0x0 "USB_BIST,USB Buffer Self Test Control Register" endif group.long 0x20++0xB line.long 0x0 "USB_BUFSEG0,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD0,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG0,Endpoint 0 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response\n" "0: Disabled the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response\n" "0: Disabled to the device to clear the STALL..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0x30++0xB line.long 0x0 "USB_BUFSEG1,Endpoint 1 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD1,Endpoint 1 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG1,Endpoint 1 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response\n" "0: Disabled the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response\n" "0: Disabled to the device to clear the STALL..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0x40++0xB line.long 0x0 "USB_BUFSEG2,Endpoint 2 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD2,Endpoint 2 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG2,Endpoint 2 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response\n" "0: Disabled the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response\n" "0: Disabled to the device to clear the STALL..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0x50++0xB line.long 0x0 "USB_BUFSEG3,Endpoint 3 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD3,Endpoint 3 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG3,Endpoint 3 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response\n" "0: Disabled the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response\n" "0: Disabled to the device to clear the STALL..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0x60++0xB line.long 0x0 "USB_BUFSEG4,Endpoint 4 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD4,Endpoint 4 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG4,Endpoint 4 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response\n" "0: Disabled the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response\n" "0: Disabled to the device to clear the STALL..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0x70++0xB line.long 0x0 "USB_BUFSEG5,Endpoint 5 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description." line.long 0x4 "USB_MXPLD5,Endpoint 5 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nIt is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or.." line.long 0x8 "USB_CFG5,Endpoint 5 Configuration Register" bitfld.long 0x8 9. "SSTALL,Set STALL Response\n" "0: Disabled the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x8 8. "CSTALL,Clear STALL Response\n" "0: Disabled to the device to clear the STALL..,1: Clear the device to response STALL handshake in.." newline bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens the user shall take care of it to confirm the right.." "0: DATA0 PID,1: DATA1 PID" bitfld.long 0x8 5.--6. "EPMODE,Endpoint Mode\n" "0,1,2,3" newline bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0,1" hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" group.long 0xA4++0x3 line.long 0x0 "USB_PDMA,USB PDMA Control Register" bitfld.long 0x0 3. "PDMA_RST,PDMA Reset\nIt is used to reset the USB PDMA function into default state. \nNote: it is auto clear to 0 after the reset function done." "0: No Reset PDMA Reset Disable,1: Reset the PDMA function in this controller" bitfld.long 0x0 2. "BYTEM,CPU Access USB SRAM Size Mode Select\n" "0: Word Mode: The size of the transfer from CPU to..,1: Byte Mode: The size of the transfer from CPU to.." newline bitfld.long 0x0 1. "PDMA_TRG,Active PDMA Function\nThis bit will be automatically cleared after PDMA transfer done." "0: The PDMA function is not active,1: The PDMA function in USB is active" bitfld.long 0x0 0. "PDMA_RW,PDMA_RW\n" "0: The PDMA will read data from memory to USB buffer,1: The PDMA will read data from USB buffer to memory" tree.end tree "VDMA (Video Direct Memory Access)" base ad:0x0 sif (cpuis("NANO1*AN")) tree "DMA_GCR" base ad:0x50008F00 group.long 0x0++0xB line.long 0x0 "DMA_GCRCSR,DMA Global Control Register" bitfld.long 0x0 12. "CLK4_EN,DMA Controller Channel 4 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "CLK3_EN,DMA Controller Channel 3 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "CLK2_EN,DMA Controller Channel 2 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x0 9. "CLK1_EN,DMA Controller Channel 1 Clock Enable Control\n" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "CLK0_EN,DMA Controller Channel 0 Clock Enable Control\n" "0: Disabled,1: Enabled" line.long 0x4 "DMA_DSSR0,DMA Service Selection Control Register 0" hexmask.long.byte 0x4 24.--28. 1. "CH3_SEL,Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by CH3_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL." hexmask.long.byte 0x4 16.--20. 1. "CH2_SEL,Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by CH2_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL." hexmask.long.byte 0x4 8.--12. 1. "CH1_SEL,Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral by setting CH1_SEL.\n" line.long 0x8 "DMA_DSSR1,DMA Service Selection Control Register 1" hexmask.long.byte 0x8 0.--4. 1. "CH4_SEL,Channel 4 Selection \nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral by setting CH4_SEL.\n" rgroup.long 0xC++0x3 line.long 0x0 "DMA_GCRISR,DMA Global Interrupt Status Register" bitfld.long 0x0 4. "INTR4,Interrupt Status Of Channel 4 (Read Only)\nThis bit is the Interrupt status of DMA channel 4." "0,1" bitfld.long 0x0 3. "INTR3,Interrupt Status Of Channel 3 (Read Only)\nThis bit is the Interrupt status of DMA channel 3." "0,1" bitfld.long 0x0 2. "INTR2,Interrupt Status Of Channel 2 (Read Only)\nThis bit is the Interrupt status of DMA channel 2." "0,1" bitfld.long 0x0 1. "INTR1,Interrupt Status Of Channel 1 (Read Only)\nThis bit is the Interrupt status of DMA channel 1." "0,1" bitfld.long 0x0 0. "INTR0,Interrupt Status Of Channel 0 (Read Only)\nThis bit is the Interrupt status of DMA channel 0." "0,1" tree.end tree "PDMA_CH1" base ad:0x50008100 group.long 0x0++0xF line.long 0x0 "PDMA_CSR,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Control\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TO_EN,Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero the TO_IS will be set.\n" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Control\nSetting this bit to '1' enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1" line.long 0x4 "PDMA_SAR,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n" rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CBCR,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address)." group.long 0x20++0xB line.long 0x0 "PDMA_IER,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable Control\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable Control\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable Control\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Control\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag\n" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received ERROR response or not if bus master received occur it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TCR,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts.." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer." tree.end tree "PDMA_CH2" base ad:0x50008200 group.long 0x0++0xF line.long 0x0 "PDMA_CSR,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Control\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TO_EN,Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero the TO_IS will be set.\n" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Control\nSetting this bit to '1' enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1" line.long 0x4 "PDMA_SAR,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n" rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CBCR,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address)." group.long 0x20++0xB line.long 0x0 "PDMA_IER,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable Control\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable Control\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable Control\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Control\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag\n" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received ERROR response or not if bus master received occur it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TCR,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts.." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer." tree.end tree "PDMA_CH3" base ad:0x50008300 group.long 0x0++0xF line.long 0x0 "PDMA_CSR,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Control\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TO_EN,Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero the TO_IS will be set.\n" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Control\nSetting this bit to '1' enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1" line.long 0x4 "PDMA_SAR,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n" rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CBCR,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address)." group.long 0x20++0xB line.long 0x0 "PDMA_IER,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable Control\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable Control\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable Control\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Control\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag\n" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received ERROR response or not if bus master received occur it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TCR,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts.." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer." tree.end tree "PDMA_CH4" base ad:0x50008400 group.long 0x0++0xF line.long 0x0 "PDMA_CSR,PDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Control\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. User must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled" bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?" newline bitfld.long 0x0 12. "TO_EN,Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero the TO_IS will be set.\n" "0: PDMA internal counter Disabled,1: PDMA internal counter Enabled" bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer Destination address is incremented..,1: Reserved,?,?" newline bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer Source address is incremented..,1: Reserved,?,?" bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?" newline bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and pointers." bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable Control\nSetting this bit to '1' enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1" line.long 0x4 "PDMA_SAR,PDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment." line.long 0x8 "PDMA_DAR,PDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment" line.long 0xC "PDMA_BCR,PDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n" rgroup.long 0x14++0xB line.long 0x0 "PDMA_CSAR,PDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred." line.long 0x4 "PDMA_CDAR,PDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred." line.long 0x8 "PDMA_CBCR,PDMA Current Transfer Byte Count Register" hexmask.long.tbyte 0x8 0.--23. 1. "PDMA_CBCR,PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address)." group.long 0x20++0xB line.long 0x0 "PDMA_IER,PDMA Interrupt Enable Register" bitfld.long 0x0 6. "TO_IE,Time-Out Interrupt Enable Control\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled" hexmask.long.byte 0x0 2.--5. 1. "WRA_BCR_IE,Wrap Around Byte Count Interrupt Enable Control\n" newline bitfld.long 0x0 1. "TD_IE,PDMA Transfer Done Interrupt Enable Control\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Control\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "PDMA_ISR,PDMA Interrupt Status Register" bitfld.long 0x4 6. "TO_IS,Time-Out Interrupt Status Flag\nThis flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.\nNote: This bit is cleared by writing '1' to it." "0: No time-out flag,1: Time-out flag" hexmask.long.byte 0x4 2.--5. 1. "WRA_BCR_IS,Wrap Around Transfer Byte Count Interrupt Status Flag\n" newline bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that PDMA has finished all transfer. \nNote: This bit is cleared by writing '1' to it." "0: Not finished yet,1: Done" bitfld.long 0x4 0. "TABORT_IS,PDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received ERROR response or not if bus master received occur it means that target abort is happened. PDMA.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" line.long 0x8 "PDMA_TCR,PDMA Timer Counter Setting Register" hexmask.long.word 0x8 0.--15. 1. "PDMA_TCR,PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts.." rgroup.long 0x80++0x3 line.long 0x0 "PDMA_BUF,PDMA Internal Buffer FIFO" hexmask.long 0x0 0.--31. 1. "PDMA_BUF,PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer." tree.end endif tree "VDMA" base ad:0x50008000 group.long 0x0++0xF line.long 0x0 "VDMA_CSR,VDMA Control Register" bitfld.long 0x0 23. "TRIG_EN,Trigger Enable Control\nNote: When VDMA transfer is completed this bit will be cleared automatically.\nIf the bus error occurs all VDMA transfer will be stopped. User must reset all VDMA channel and then trigger again." "0: No effect,1: VDMA data read or write transfer Enabled" bitfld.long 0x0 11. "DIR_SEL,Transfer Source/Destination Address Direction Selection\n" "0: Transfer address is incremented successively,1: Transfer address is decremented successively" newline bitfld.long 0x0 10. "STRIDE_EN,Stride Mode Enable Control\n" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled" bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and pointers." newline bitfld.long 0x0 0. "VDMACEN,VDMA Channel Enable Control\nSetting this bit to '1' enables VDMA's operation. If this bit is cleared VDMA will ignore all VDMA request and force Bus Master into IDLE state.\nNote: SW_RST will clear this bit." "0,1" line.long 0x4 "VDMA_SAR,VDMA Source Address Register" hexmask.long 0x4 0.--31. 1. "VDMA_SAR,VDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of VDMA." line.long 0x8 "VDMA_DAR,VDMA Destination Address Register" hexmask.long 0x8 0.--31. 1. "VDMA_DAR,VDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of VDMA." line.long 0xC "VDMA_BCR,VDMA Transfer Byte Count Register" hexmask.long.word 0xC 0.--15. 1. "VDMA_BCR,VDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count number of VDMA.\n" rgroup.long 0x14++0xB line.long 0x0 "VDMA_CSAR,VDMA Current Source Address Register" hexmask.long 0x0 0.--31. 1. "VDMA_CSAR,VDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the VDMA transfer just occurred." line.long 0x4 "VDMA_CDAR,VDMA Current Destination Address Register" hexmask.long 0x4 0.--31. 1. "VDMA_CDAR,VDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the VDMA transfer just occurred." line.long 0x8 "VDMA_CBCR,VDMA Current Transfer Byte Count Register" hexmask.long.word 0x8 0.--15. 1. "VDMA_CBCR,VDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of VDMA." group.long 0x20++0x7 line.long 0x0 "VDMA_IER,VDMA Interrupt Enable Register" bitfld.long 0x0 1. "TD_IE,VDMA Transfer Done Interrupt Enable Control\n" "0: Iinterrupt generator Disabled during VDMA..,1: Interrupt generator Enabled during VDMA transfer.." bitfld.long 0x0 0. "TABORT_IE,VDMA Read/Write Target Abort Interrupt Enable Control\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.." line.long 0x4 "VDMA_ISR,VDMA Interrupt Status Register" bitfld.long 0x4 1. "TD_IS,Transfer Done Interrupt Status Flag\nThis bit indicates that VDMA has finished all transfer. \n" "0: Not finished yet,1: Done. Note: This bit is cleared by writing '1'.." bitfld.long 0x4 0. "TABORT_IS,VDMA Read/Write Target Abort Interrupt Status Flag\nNote1: This bit is cleared by writing '1' to it.\nNote2: This bit indicates bus master received ERROR response or not if bus master received occur it means that target abort is happened. VDMA.." "0: No bus ERROR response received,1: This bit is cleared by writing '1' to it" group.long 0x2C++0x7 line.long 0x0 "VDMA_SASOCR,VDMA Source Address Stride Offset Register" hexmask.long.word 0x0 16.--31. 1. "STBC,VDMA Stride Transfer Byte Count\nThe 16-bit register defines the stride transfer byte count of each row." hexmask.long.word 0x0 0.--15. 1. "SASTOBL,VDMA Source Address Stride Offset Byte Length\nThe 16-bit register defines the source address stride transfer offset count of each row." line.long 0x4 "VDMA_DASOCR,VDMA Destination Address Stride Offset Register" hexmask.long.word 0x4 0.--15. 1. "DASTOBL,VDMA Destination Address Stride Offset Byte Length\nThe 16-bit register defines the destination address stride transfer offset count of each row." rgroup.long 0x80++0x7 line.long 0x0 "VDMA_BUF0,VDMA Internal Buffer FIFO 0" hexmask.long 0x0 0.--31. 1. "VDMA_BUF0,VDMA Internal Buffer FIFO 0 (Read Only)\nVDMA channel has its own 2 words internal buffer." line.long 0x4 "VDMA_BUF1,VDMA Internal Buffer FIFO 1" hexmask.long 0x4 0.--31. 1. "VDMA_BUF1,VDMA Internal Buffer FIFO 1 (Read Only)\nVDMA channel has its own 2 words internal buffer." tree.end tree.end tree "WDT (Watchdog Timer)" base ad:0x40004000 group.long 0x0++0xB line.long 0x0 "WDT_CTL,Watchdog Timer Control Register" sif (cpuis("NANO1*BN")) bitfld.long 0x0 8.--9. "WTRDSEL,Watchdog Timer Reset Delay Select" "0,1,2,3" endif bitfld.long 0x0 4.--6. "WTIS,Watchdog Timer Interval Selection (Write Protect)\nPlease refer to open lock sequence to program it.\nThe three bits select the time-out interval for the Watchdog timer. This count is free running counter.\nPlease refer to Table 5.191 Watchdog.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "WTE,Watchdog Timer Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\n" "0: Watchdog timer Disabled (this action will reset..,1: Watchdog timer Enabled" bitfld.long 0x0 2. "WTWKE,Watchdog Timer Wake-Up Function Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\n" "0: Watchdog timer Wake-up CPU function Disabled,1: Wake-up function Enabled so that Watchdog timer.." newline bitfld.long 0x0 1. "WTRE,Watchdog Timer Reset Function Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will enable the Watchdog timer reset function.\n" "0: Watchdog timer reset function Disabled,1: Watchdog timer reset function Enabled" bitfld.long 0x0 0. "WTR,Clear Watchdog Timer (Write Protect)\nPlease refer to open lock sequence to program it.\nSet this bit will clear the Watchdog timer. \nNote: This bit will auto clear after few clock cycle" "0: No effect,1: Reset the contents of the Watchdog timer" line.long 0x4 "WDT_IER,Watchdog Timer Interrupt Enable Register" bitfld.long 0x4 0. "WDT_IE,Watchdog Timer Interrupt Enable Control\n" "0: Watchdog timer interrupt Disabled,1: Watchdog timer interrupt Enabled" line.long 0x8 "WDT_ISR,Watchdog Timer Interrupt Status Register" sif (cpuis("NANO1*AN")) rbitfld.long 0x8 2. "WDT_WAKE_IS,Watchdog Timer Wake-Up Status (Read Only)\nIf Watchdog timer causes system to wake up from power-down mode this bit will be set to high. It must be cleared by software with a write '1' to this bit.\nNote1: When system in power-down mode and.." "0: Watchdog timer does not cause system wake-up,1: When system in power-down mode and watchdog.." rbitfld.long 0x8 1. "WDT_RST_IS,Watchdog Timer Reset Status (Read Only)\nWhen the Watchdog timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing '1'.." "0: Watchdog timer reset does not occur,1: Watchdog timer reset occurs" newline rbitfld.long 0x8 0. "WDT_IS,Watchdog Timer Interrupt Status (Read Only)\nIf the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled then this bit.." "0: Watchdog timer interrupt does not occur,1: Watchdog timer interrupt occurs" endif sif (cpuis("NANO1*BN")) bitfld.long 0x8 2. "WDT_WAKE_IS,Watchdog Timer Wake-up Status \nIf Watchdog timer causes system to wake up from power-down mode this bit will be set to high. It must be cleared by software with a write '1' to this bit.\nNote1: When system in power-down mode and watchdog.." "0: Watchdog timer does not cause system wake-up,1: When system in power-down mode and watchdog.." newline bitfld.long 0x8 1. "WDT_RST_IS,Watchdog Timer Reset Status \nWhen the Watchdog timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing '1' to it. If.." "0: Watchdog timer reset did not occur,1: Watchdog timer reset occurs" bitfld.long 0x8 0. "WDT_IS,Watchdog Timer Interrupt Status \nIf the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled then this bit indicates.." "0: Watchdog timer interrupt did not occur,1: Watchdog timer interrupt occurs" endif tree.end AUTOINDENT.OFF