; -------------------------------------------------------------------------------- ; @Title: N572 On-Chip Peripherals ; @Props: Released ; @Author: NEJ ; @Changelog: 2023-04-07 NEJ ; 2023-11-08 NEJ ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: Generated (TRACE32, build: 164352.), based on: ; N572F065_fixed_v3.svd (Ver. 1.0), N572F072_v3_fixed.svd (Ver. 1.0) ; @Core: Cortex-M0 ; @Chip: N572F065, N572F072, N572P072 ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pern572.per 16971 2023-11-09 16:09:22Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ADC (Analog to Digital Converter)" base ad:0x400E0000 rgroup.long 0x0++0x1F line.long 0x0 "ADC_DAT0,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x0 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x0 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x0 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x0 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x0 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x0 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0x4 "ADC_DAT1,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x4 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x4 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x4 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x4 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x4 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x4 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0x8 "ADC_DAT2,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x8 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x8 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x8 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x8 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x8 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x8 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0xC "ADC_DAT3,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0xC 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0xC 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0xC 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0xC 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0xC 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0xC 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0x10 "ADC_DAT4,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x10 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x10 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x10 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x10 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x10 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x10 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0x14 "ADC_DAT5,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x14 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x14 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x14 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x14 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x14 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x14 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0x18 "ADC_DAT6,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x18 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x18 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x18 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x18 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x18 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x18 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." line.long 0x1C "ADC_DAT7,A/D Data Register for the channel defined in CHSEQ0" sif (cpuis("N572F065")) rbitfld.long 0x1C 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid" rbitfld.long 0x1C 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) rbitfld.long 0x1C 17. "VALID,Valid Flag. 1: Data in RSLT are valid.. 0: Data in RSLT are not valid.. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read." "0: Data in RSLT are not valid,1: Data in RSLT are valid" rbitfld.long 0x1C 16. "OV,Over Run Flag. 1: Data in RSLT are overwritten.. 0: Data in RSLT are recent conversion result.. If converted data in RSLT have not been read before new conversion result is loaded to this register OVERRUN is set to 1. It is cleared by hardware after.." "0: Data in RSLT are recent conversion result,1: Data in RSLT are overwritten" newline endif hexmask.long.byte 0x1C 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]." hexmask.long.word 0x1C 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit." group.long 0x20++0x13 line.long 0x0 "ADC_CTL,A/D Control Register" sif (cpuis("N572F065")) bitfld.long 0x0 12. "ADCFM,Data Format Of ADC Conversion Result." "0: Unsigned,1: 2'Complemet" bitfld.long 0x0 11. "SWTRG,A/D Conversion Start. Note: SWTRG bit can be set to 1 from three sources: software write and external pin STADC. SWTRG is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In.." "0: Conversion is stopped and A/D converter enters..,1: Start conversion" newline bitfld.long 0x0 6.--7. "HWTRGCOND,Trigger Condition. These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.." "0: Low level,1: High level,?,?" bitfld.long 0x0 2.--3. "OPMODE,A/D Converter Operation Mode. When changing the operation mode software should disable SWTRG bit firstly." "0: Single conversion,1: Reserved,?,?" newline bitfld.long 0x0 1. "ADCIE,A/D Interrupt Enable. A/D conversion end interrupt request is generated if ADCIE bit is set to 1." "0: Disable A/D interrupt function,1: Enable A/D interrupt function" bitfld.long 0x0 0. "ADCEN,A/D Converter Enable. Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption." "0: Disable,1: Enable" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 12. "ADCFM,Data Format Of ADC Conversion Result. 1: 2'Complemet. 0: Unsigned" "0: Unsigned,?" bitfld.long 0x0 11. "SWTRG,A/D software Conversion Start. 1: Conversion start.. 0: Conversion stopped and A/D converter enter idle state.. SWTRG bit can be set to 1 from three sources: software write and external pin STADC. SWTRG is cleared to 0 by hardware automatically at.." "0: Conversion stopped and A/D converter enter idle..,1: Conversion start" newline endif bitfld.long 0x0 8. "HWTRGEN,Trigger Enable. Enable or disable triggering of A/D conversion by external STADC pin.." "0: Disable,1: Enable" sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 6.--7. "HWTRGCOND,Trigger Condition. These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.. 00: Low level. 01: High level. 10:.." "0: Low level,1: High level,?,?" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 2.--3. "OPMODE,A/D Converter Operation Mode. 00: Single conversion. 01: Reserved. 10: Single-cycle scan. 11: Continuous scan. When changing the operation mode software should disable SWTRG bit firstly." "0: Single conversion,1: Reserved,?,?" bitfld.long 0x0 1. "ADCIE,A/D Interrupt Enable. 1: Enable A/D interrupt function. 0: Disable A/D interrupt function. A/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: Disable A/D interrupt function,1: Enable A/D interrupt function" endif line.long 0x4 "ADC_CHSEQ,A/D Channel Sequence Register" hexmask.long.byte 0x4 28.--31. 1. "CHSEQ7,Select Channel N As The 8th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." hexmask.long.byte 0x4 24.--27. 1. "CHSEQ6,Select Channel N As The 7th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." newline hexmask.long.byte 0x4 20.--23. 1. "CHSEQ5,Select Channel N As The 6th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." hexmask.long.byte 0x4 16.--19. 1. "CHSEQ4,Select Channel N As The 5th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." newline hexmask.long.byte 0x4 12.--15. 1. "CHSEQ3,Select Channel N As The 4th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." hexmask.long.byte 0x4 8.--11. 1. "CHSEQ2,Select Channel N As The 3rd Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." newline hexmask.long.byte 0x4 4.--7. 1. "CHSEQ1,Select Channel N As The 2nd Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0." sif (cpuis("N572F065")) hexmask.long.byte 0x4 0.--3. 1. "CHSEQ0,Select Channel N As The 1st Conversion In Scan Sequence." endif line.long 0x8 "ADC_CMP0,A/D Compare Register 0" hexmask.long.word 0x8 16.--27. 1. "CMPDAT,Compare Data. The 12 bits data are used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.. The data format.." hexmask.long.byte 0x8 8.--11. 1. "CMPMCNT,Compare Match Count. When the specified A/D channel analog conversion result matches the comparing condition the internal match counter will increase 1. When the internal counter achieves the setting (CMPMCNT+1) hardware will set the ADCMPF bit." newline sif (cpuis("N572F065")) bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection." "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?" bitfld.long 0x8 2. "CMPCOND,Compare Condition." "0: ADCMPFx bit is set if conversion result is less..,1: ADCMPFx bit is set if conversion result is.." newline bitfld.long 0x8 1. "ADCMPIE,Compare Interrupt Enable. When converted data in RESULT is less (or greater) than the compare data CMPDAT[11:0] ADCMPF bit is asserted. If ADCMPIE is set to 1 a compare interrupt request is generated." "0: Disable,1: Enable" bitfld.long 0x8 0. "ADCMPEN,Compare Enable. Set this bit to 1 to enable the comparison CMPDAT[11:0] with specified channel conversion result when converted data is loaded into ADC_DAT register." "0: Disable compare,1: Enable compare" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection. 000: Channel 0 conversion result is selected to be compared.. 001: Channel 1 conversion result is selected to be compared.. 010: Channel 2 conversion result is selected to be compared.. 011: Channel 3 conversion result is.." "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?" bitfld.long 0x8 2. "CMPCOND,Compare Condition. 1: CMPFx bit is set if conversion result is greater or equal to CMPD . 0: CMPFx bit is set if conversion result is less than CMPD." "0: CMPFx bit is set if conversion result is less..,1: CMPFx bit is set if conversion result is greater.." newline bitfld.long 0x8 1. "ADCMPIE,Compare Interrupt Enable. 1: Enable. 0: Disable. When converted data in RSLT is less (or greater) than the compare data CMPD CMPF bit is asserted. If CMPIE is set to 1 a compare interrupt request is generated." "0: Disable,1: Enable" endif line.long 0xC "ADC_CMP1,A/D Compare Register 0" hexmask.long.word 0xC 16.--27. 1. "CMPDAT,Compare Data. The 12 bits data are used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.. The data format.." hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count. When the specified A/D channel analog conversion result matches the comparing condition the internal match counter will increase 1. When the internal counter achieves the setting (CMPMCNT+1) hardware will set the ADCMPF bit." newline sif (cpuis("N572F065")) bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection." "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?" bitfld.long 0xC 2. "CMPCOND,Compare Condition." "0: ADCMPFx bit is set if conversion result is less..,1: ADCMPFx bit is set if conversion result is.." newline bitfld.long 0xC 1. "ADCMPIE,Compare Interrupt Enable. When converted data in RESULT is less (or greater) than the compare data CMPDAT[11:0] ADCMPF bit is asserted. If ADCMPIE is set to 1 a compare interrupt request is generated." "0: Disable,1: Enable" bitfld.long 0xC 0. "ADCMPEN,Compare Enable. Set this bit to 1 to enable the comparison CMPDAT[11:0] with specified channel conversion result when converted data is loaded into ADC_DAT register." "0: Disable compare,1: Enable compare" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection. 000: Channel 0 conversion result is selected to be compared.. 001: Channel 1 conversion result is selected to be compared.. 010: Channel 2 conversion result is selected to be compared.. 011: Channel 3 conversion result is.." "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?" bitfld.long 0xC 2. "CMPCOND,Compare Condition. 1: CMPFx bit is set if conversion result is greater or equal to CMPD . 0: CMPFx bit is set if conversion result is less than CMPD." "0: CMPFx bit is set if conversion result is less..,1: CMPFx bit is set if conversion result is greater.." newline bitfld.long 0xC 1. "ADCMPIE,Compare Interrupt Enable. 1: Enable. 0: Disable. When converted data in RSLT is less (or greater) than the compare data CMPD CMPF bit is asserted. If CMPIE is set to 1 a compare interrupt request is generated." "0: Disable,1: Enable" endif line.long 0x10 "ADC_STATUS,A/D Status Register" hexmask.long.byte 0x10 16.--23. 1. "OV,Over Run Flag. It is a mirror to OV bit in ADC_DATn." hexmask.long.byte 0x10 8.--15. 1. "VALID,Data Valid Flag. It is a mirror of VALID bit in ADC_DATn." newline bitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel. It is read only." "0,1,2,3,4,5,6,7" newline sif (cpuis("N572F065")) bitfld.long 0x10 3. "BUSY,BUSY/IDLE. This bit is mirror of SWTRG bit in ADC_CTL.. It is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline bitfld.long 0x10 2. "ADCMPF1,Compare Flag. When the selected channel A/D conversion result meets setting conditions in ADC_CMP1 then this bit is set to 1. And it is cleared by write 1.." "0: Converted result RESULT in ADC_DAT does not meet..,1: Converted result RESULT in ADC_DAT meets.." bitfld.long 0x10 1. "ADCMPF0,Compare Flag. When the selected channel A/D conversion result meets setting conditions in ADC_CMP0 then this bit is set to 1. And it is cleared by write 1.." "0: Converted result RESULT in ADC_DAT does not meet..,1: Converted result RESULT in ADC_DAT meets.." newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x10 3. "BUSY,BUSY/IDLE. 1: A/D converter is busy at conversion.. 0: A/D converter is in idle state.. This bit is mirror of SWTRG bit in ADC_CTL.. It is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion" bitfld.long 0x10 2. "ADCMPF1,Compare Flag. When the selected channel A/D conversion result meets setting conditions in ADCMPR1 then this bit is set to 1. And it is cleared by write 1.. 1: Converted result RSLT in ADCDR meets ADCMPR1 setting . 0: Converted result RSLT in.." "0: Converted result RSLT in ADCDR does not meet..,1: Converted result RSLT in ADCDR meets ADCMPR1.." newline bitfld.long 0x10 1. "ADCMPF0,Compare Flag. When the selected channel A/D conversion result meets setting conditions in ADCMPR0 then this bit is set to 1. And it is cleared by write 1.. 1: Converted result RSLT in ADCDR meets ADCMPR0 setting . 0: Converted result RSLT in.." "0: Converted result RSLT in ADCDR does not meet..,1: Converted result RSLT in ADCDR meets ADCMPR0.." endif bitfld.long 0x10 0. "ADIF,A/D Conversion End Flag. A status flag that indicates the end of A/D conversion.. ADIF is set to 1 under the following two conditions:. When A/D conversion ends in single mode . When A/D conversion ends on all channels specified by channel sequence.." "0,1" sif (cpuis("N572F065")) group.long 0x34++0x3 line.long 0x0 "ADC_CAL,A/D Calibration Register" rbitfld.long 0x0 1. "CALDONE,Calibration is Done (read only). When 0 is written to CALEN bit CALDONE bit is cleared by hardware immediately and be set to 1 after 96 ADC clocks. It is a read only bit." "0: A/D converter has not been calibrated or..,1: A/D converter self-calibration is done" bitfld.long 0x0 0. "CALEN,Self-Calibration Enable. Software can set this bit to 1 enables A/D converter to do self-calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable.." "0: Disable self-calibration,1: Enable self-calibration" endif group.long 0x3C++0x3 line.long 0x0 "ADC_PGCTL,ADC Pre-amplifier Gain Control Register" sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.byte 0x0 24.--28. 1. "PAG_I,Gain Setting Bits For The First Stage Of Pre-Amp. 00000: 20 dB . 00001: 21 dB . 00010: 22 dB . 00011: 23 dB . :. 10100: 40 dB.. Others: equivalent with '00000'." bitfld.long 0x0 23. "APPS,ADC And Pre-Amplifier Power Source Selection. 0: Internal regulator is disabled and AVDD is selected as power source.. 1: Internal regulator is enabled and regulator output is selected as power source.. The input of internal regulator is from AVDD.." "0: Internal regulator is disabled,1: Internal regulator is enabled" newline bitfld.long 0x0 22. "MICE,MIC_BIAS Output Enable. 0: MIC_BIAS output is disabled (tri-state).. 1: MIC_BIAS output is enabled its output is 0.85 time the voltage of AVDD." "0: MIC_BIAS output is disabled,1: MIC_BIAS output is enabled" endif sif (cpuis("N572F065")) bitfld.long 0x0 11.--12. "PAG_I,Gain Setting Bits for the First Stage Of Pre-Amp." "0: -6 dB,1: 0 dB,?,?" newline hexmask.long.byte 0x0 6.--10. 1. "OS,Configuration for Pre-Amp OP Offset Bias Compensation Voltage. There are 32 levels and 2mV per level @ 5V condition." hexmask.long.byte 0x0 1.--5. 1. "PAG_II,Gain Setting Bits for the Second Stage Of Pre-Amp." newline bitfld.long 0x0 0. "OPMUTE,Mute Control of First Stage Pre-Amp for Offset Bias Calibration. When this bit is set as '1' two input end of first stage pre-amp will be shorted and feedback resistor of this stage will be shorted.." "0: open,1: short" endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x0 8.--16. 1. "OS,Configuration For Pre-Amp OP Offset Bias Compensation Voltage. There are 512 levels and 0.25mV per level @ 5V condition.. The compensation is available only when FWU of MIBSCR register is 2'b11." newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 1.--2. "PAG_II,Gain Setting Bits For The Second Stage Of Pre-Amp. 00: 0 dB . 01: 10 dB . 10: 20 dB . 11: 30 dB." "0,1,2,3" endif sif (cpuis("N572F072")||cpuis("N572P072")) group.long 0x40++0x3 line.long 0x0 "ADC_MIBSCTL,MIC bias and PGC Control Register" bitfld.long 0x0 4.--5. "CTRS,AVDD/2 Accelerating. 00: R~10K. 01: R~40K. 10: R~200K. 11: R~600K" "0: R~10K,1: R~40K,?,?" bitfld.long 0x0 0.--1. "FWU,Fast Wake Up For RC. 00: 8K (Twu<100ms). set 00 at initial then 11 after 80ms. 01: 40K. 10: 200K. 11: 400K (Normal path)" "0,1,2,3" endif tree.end sif (cpuis("N572F065")) base ad:0x400C0000 elif (cpuis("N572F072")||cpuis("N572P072")) base ad:0x50008000 endif tree "APU (Audio Processing Unit)" group.long 0x0++0x7 line.long 0x0 "APU_CTL,APU Control Register" bitfld.long 0x0 13. "DACGN,DAC Output Current Control. This bit is effective only when BPPAM is '1'." "0: 3mA,1: 5mA" bitfld.long 0x0 9. "BPPAM,Bypass Power Amplifier DAC Output To Pin. Note: User must set BPPAM to '0' to use SPK+ and SPK- as the power amplifier outputs." "0: SPK+ and SPK- are power amplifier outputs,1: No output at SPK-. This setting is for testing.." newline bitfld.long 0x0 8. "DACE,DAC Enable." "0: Disable DAC function,1: Enable DAC function" bitfld.long 0x0 7. "PAMPE,Power Amplifier Enable." "0: Disable PA function,1: Enable PA function" newline bitfld.long 0x0 6. "APUIE,APU Interrupt Enable." "0: Disable the APU threshold interrupt,1: Enable the APU threshold interrupt" bitfld.long 0x0 5. "APUIS,APU Interrupt Status. This flag is set by hardware when APU threshold is met. Software can clear this bit by writing a zero to it." "0: APU threshold interrupt does not occur,1: APU threshold interrupt occur" newline bitfld.long 0x0 0.--2. "TSHD,APU Interrupt Threshold." "0: Buffer 0 is read out by APU,1: Buffer 1 is read out by APU,?,?,?,?,?,?" line.long 0x4 "APU_VM,APU Volume Control Register" bitfld.long 0x4 0.--2. "VOLUM,APU Volume Adjustment." "0: 0 dB,1: -3 dB,?,?,?,?,?,?" group.long 0xC++0x23 line.long 0x0 "APU_CH1DAT0,APU Channel 1 Data Buffer Register" sif (cpuis("N572F065")) hexmask.long.word 0x0 0.--12. 1. "PCM1,PCM Data Of Channel 1 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x0 0.--15. 1. "PCM,PCM Data Of Channel 1 . This field contains 16-bit PCM data that are one of the Mixer input.. User needs to take care of the effective bit of PCM because the H/W mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement." endif line.long 0x4 "APU_CH0DAT0,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x4 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x4 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0x8 "APU_CH0DAT1,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x8 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x8 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0xC "APU_CH0DAT2,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0xC 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0xC 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0x10 "APU_CH0DAT3,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x10 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x10 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0x14 "APU_CH0DAT4,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x14 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x14 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0x18 "APU_CH0DAT5,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x18 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x18 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0x1C "APU_CH0DAT6,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x1C 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x1C 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif line.long 0x20 "APU_CH0DAT7,APU Channel 0 Data Buffer Register 0" sif (cpuis("N572F065")) hexmask.long.word 0x20 0.--12. 1. "PCM,PCM Data Of Channel 0 . This field contains 13 bits PCM data that is one of the mixer input.. The data format of PCM is 2'complement." endif sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.word 0x20 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to Mixer APU H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is.." endif tree.end tree "CFG (User Configuration)" base ad:0x300000 group.long 0x0++0x3 line.long 0x0 "CONFIG,User Configuration Memory" bitfld.long 0x0 31. "CWDTEN,Watchdog Enable." "0: Watchdog is disabled after power on,1: Watchdog is enabled after power on" sif (cpuis("N572F065")) bitfld.long 0x0 28. "CKF,Clock Filter Enable." "0: Disable clock filter,1: Enable clock filter" newline bitfld.long 0x0 24.--26. "CFOSC,Power-on Clock Source Selection." "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 23. "CVDEN,Voltage Detector Enable." "0: Enable Voltage Detector after power on,1: Disable Voltage Detector after power on" newline bitfld.long 0x0 21. "CVDTV,Voltage Detector Threshold Voltage Selection." "0,1" sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 6.--7. "CSPI0_CT,Coarse Timing Control for SPI0 Data Receiving After Power On. These bits are used to adjust receiving clock for latching serial-in data correctly in high speed transmission mode. ." "0: Receiving data clock is same as the SPI0_CLK,1: Receiving data clock is delayed 2 half SPI0_CLK..,?,?" newline bitfld.long 0x0 4.--5. "CSPI0_FT,Fine Timing Control for SPI0 Data Receiving After Power On. The delay timing selected by CSPI0_CT can be further tuned finely by CSPI0_FT. . Note: The extra delay is implemented by delay chains. The accuracy of delay time would base on process.." "0: Receiving data clock has extra 7.5nS delay,1: Receiving data clock has extra 5.0nS delay,?,?" endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 2. "PRTB,Protection On 8K Bytes Flash. This bit is effective only for the part of 72KB flash. ." "0: ISP function only can operate on the 64KB Flash..,1: ISP function can operate on the whole 72KB Flash.." newline endif bitfld.long 0x0 1. "LOCK,Security Lock. When flash data is locked (1) only device ID CONFIG can be read by Writer and ICP thru serial debug interface. Other data are locked as 0xFFFFFFFF.(2) ISP can read data anywhere regardless of LOCK bit value. (3) SWD interface cannot.." "0: Flash data are locked,1: Flash data are not locked" tree.end tree "CLK (Clock Controller)" base ad:0x50000200 group.long 0x0++0xB line.long 0x0 "CLK_PWRCTL,System Power Control Register" bitfld.long 0x0 8. "PD_WAIT_CPU,This Bit Controls The Power Down Entry Condition. Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit.. The following is a brief description of PD_WAIT_CPU bit.." "0: Chip is at normal mode. Note that PWR_DOWN..,1: Chip waits to enter power-down mode" bitfld.long 0x0 7. "PWR_DOWN,System Power Down Active Or Enable Bit." "0: Chip operates at normal mode,1: Chip is standing by power-down entry condition" newline bitfld.long 0x0 6. "WINT_STS,Chip Power Down Wake Up Status Flag. Set by 'power down wake up' it indicates that resume from power down mode. . The flag is set if the GPIO USB WDT or RTC wakeup.. Note: Write 1 to clear the bit." "0,1" bitfld.long 0x0 5. "WINT_EN,Enable Interrupt When Wake Up From Power Down Mode." "0: Disable,1: Enable. The interrupt will occur when MCU wakes.." newline bitfld.long 0x0 4. "WU_DLY,Enable The Wake Up Delay Counter. When the chip wakes up from idle mode the clock control will delay some clock cycles to wait the 12MHz (or 6MHz) crystal or the internal 24MHz oscillator clock stable. ." "0: Disable the clock cycles delay,1: Enable the clock cycles delay. The delay is 4096.." newline sif (cpuis("N572F065")) bitfld.long 0x0 3. "VOUTX_PD,Driving Out 3.0V (Through VOUTX Pad) LDO Control." "0: 3.0V LDO (VOUTX) is enabled,1: 3.0V LDO (VOUTX) is disabled" newline bitfld.long 0x0 2. "OSC24M_EN,Internal 24MHz Oscillator Control. After reset this bit is '1'.." "0: 24MHz oscillation is disabled,1: 24MHz Oscillation is enabled" bitfld.long 0x0 0. "XTL12M_EN,External 12MHz (or 6MHz) Crystal Oscillator Control. This bit is set by the combination logic of flash controller user configuration register CONFIG[26:24] after power on.." "0: 12MHz (or 6MHz) crystal oscillation is disabled,1: 12MHz (or 6MHz) crystal oscillation is enabled" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 3. "LDO30_PD,Driving Out 3.0V (Through LDO30E Pad) LDO Control. After reset this bit is '1'.." "0: 3.0V LDO (LDO30) is enabled,1: 3.0V LDO (LDO30) is disabled" bitfld.long 0x0 2. "OSC48M_EN,Internal 48MHz RC Oscillator Control. After reset this bit is '1'. ." "0: 48MHz oscillation is disabled,1: 48MHz oscillation is enabled" newline endif bitfld.long 0x0 1. "XTL32K_EN,External 32.768KHz Crystal Control. After reset this bit is '0'.." "0: 32.768KHz Crystal is disabled,1: 32.768KHz Crystal is enabled" line.long 0x4 "CLK_AHBCLK,AHB Device Clock Enable Control Register" sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x4 3. "APUCKEN,APU Clock Enable Control." "0: To disable the APU engine clock,1: To enable the APU engine clock" endif bitfld.long 0x4 2. "ISPCKEN,Flash ISP Engine Clock Enable Control." "0: To disable the Flash ISP engine clock,1: To enable the Flash ISP engine clock" line.long 0x8 "CLK_APBCLK,APB Device Clock Enable Control Register" sif (cpuis("N572F065")) bitfld.long 0x8 30. "APU_EN,APU Clock Enable Control." "0: To disable the APU engine clock,1: To enable the APU engine clock" bitfld.long 0x8 27. "USBD_EN,USB FS Device Controller Clock Enable Control." "0: Disable,1: Enable" newline endif bitfld.long 0x8 28. "ADC_EN,Audio Analog-Digital-Converter (ADC) Clock Enable Control." "0: Disable,1: Enable" bitfld.long 0x8 20. "PWM_EN,PWM Block Clock Enable Control." "0: Disable,1: Enable" newline bitfld.long 0x8 13. "SPI1_EN,SPI1 Clock Enable Control." "0: Disable,1: Enable" bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable Control." "0: Disable,1: Enable" newline bitfld.long 0x8 5. "TMRF_EN,TimerF Clock Enable Control." "0: Disable,1: Enable" bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable Control." "0: Disable,1: Enable" newline bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable Control." "0: Disable,1: Enable" bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable Control." "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RTC_EN,Real-Time-Clock APB Interface Clock Control. This bit is used to control the RTC APB clock only. The RTC engine clock source is from the 32.768KHz crystal.." "0: Disable,1: Enable" bitfld.long 0x8 0. "WDT_EN,Watchdog Clock Enable Control. This bit is the protected bit. To program this bit needs an open lock sequence write '59h' '16h' '88h' to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.. The.." "0: Disable,1: Enable" group.long 0x10++0xB line.long 0x0 "CLK_CLKSEL0,Clock Source Select Control Register 0" sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 3.--5. "STCLKSEL,MCU Cortex_M0 SysTick Clock Source Select." "0: Clock source from HCLK/2,1: Clock source from XTL_32K.. Clock source from..,?,?,?,?,?,?" endif sif (cpuis("N572F065")) bitfld.long 0x0 0.--2. "HCLKSEL,HCLK clock source select.. Note:. 1. Before clock switch the related clock sources (pre-select and new-select) must be turned on.. 2. The 3-bit default value is reloaded with the value of CFOSC (CONFIG[26:24]) in user configuration register in.." "0: clock source from external 32KHz crystal clock,1: clock source from external 12MHz (or 6MHz)..,?,3: bit default value is reloaded with the value of..,?,?,?,?" endif line.long 0x4 "CLK_CLKSEL1,Clock Source Select Control Register 1" bitfld.long 0x4 28.--29. "PWMSEL,PWM Timer Clock Source Select ." "0: Clock source from HCLK,1: Clock source from external 32KHz crystal clock,?,?" sif (cpuis("N572F065")) bitfld.long 0x4 20.--22. "TMRFSEL,TimerF Clock Source Select." "0: Clock source from external 32KHz crystal clock /..,1: Clock source from external 32KHz crystal clock /..,?,?,?,?,?,?" newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x4 20.--22. "TMRFSEL,TimerF Clock Source Select." "0: Clock source from external XTL_32K/32,1: Clock source from external XTL_32K/(4x32),?,?,?,?,?,?" newline endif bitfld.long 0x4 16.--18. "TMR2SEL,Timer2 Clock Source Select." "0: Clock source from HCLK,1: Clock source from external 32KHz crystal clock.,?,?,?,?,?,?" newline bitfld.long 0x4 12.--14. "TMR1SEL,Timer1 Clock Source Select." "0: Clock source from HCLK,1: Clock source from external 32KHz crystal clock.,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "TMR0SEL,Timer0 Clock Source Select." "0: Clock source from HCLK,1: Clock source from external 32KHz crystal clock.,?,?,?,?,?,?" newline sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x4 4.--5. "SPI0SEL,SPI0 Clock Source Select." "0: Clock source from HCLK,1: Clock source from PLL2_FOUT.. Clock source from..,?,?" endif bitfld.long 0x4 2.--3. "ADCSEL,ADC Clock Source Select." "0: Clock source from PLL2 clock,1: Clock source from external 12MHz (or 6MHz)..,?,?" newline bitfld.long 0x4 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect) . These bits are protected bits. To program these bits needs an open lock sequence write '59h' '16h' '88h' to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address.." "0: Clock source from HCLK/2048 clock,1: Clock source from external 32KHz crystal clock,?,?" line.long 0x8 "CLK_CLKDIV,Clock Divider Number Register" hexmask.long.byte 0x8 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source. The ADC clock must meet the constraint: ADCLK ( HCKL/2" hexmask.long.byte 0x8 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source." group.long 0x20++0x3 line.long 0x0 "CLK_PLLCON,PLL Control Register" tree.end tree "FMC (Flash Memory Controller)" base ad:0x5000C000 group.long 0x0++0x13 line.long 0x0 "FMC_ISPCTL,ISP Control Register" bitfld.long 0x0 12.--14. "ET,Flash Page Erase Time." "0: 20 ms (default),1: 25 ms,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "PT,Flash Program Time." "0: 40 (s (default),1: 45 (s,?,?,?,?,?,?" bitfld.long 0x0 6. "ISPFF,ISP Fail Flag. This bit is set by hardware when a triggered ISP meets any of the following conditions:. MCU writes (or erase) to Flash when EWEN is '0'.. Destination address is illegal such as over an available range.. . Write 1 to clear." "0,1" bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable. When enabled ISP functions can access the CONFIG address space and modify device configuration area." "0: Disable,1: Enable" newline bitfld.long 0x0 1. "EWEN,Enable Erase/Write Of ISP Function." "0: Disable erase/write,1: Enable erase/write" bitfld.long 0x0 0. "ISPEN,ISP Enable." "0: Disable ISP function,1: Enable ISP function" line.long 0x4 "FMC_ISPADDR,ISP Address Register" hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address Register. This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32-bit word only consequently ISPADDR [1:0] must be 00b for correct ISP operation. . N572F064 equips with an.." line.long 0x8 "FMC_ISPDAT,ISP Data Register" hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data Register. Write data to this register before an ISP program operation.. Read data from this register after an ISP read operation" line.long 0xC "FMC_ISPCMD,ISP Command Register" hexmask.long.byte 0xC 0.--5. 1. "CMD,ISP Command . Operation Mode : CMD. -------------------- -------. Standby : 0x3X. Read CID : 0x0B. Read DID : 0x0C. Flash Page Erase : 0x22. Flash Program : 0x21. Flash Read.." line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register" bitfld.long 0x10 0. "ISPGO,ISP Start Trigger. Write 1 to start ISP operation. This bit will be cleared to 0 by hardware automatically when ISP operation is finished.." "0: ISP operation is finished,1: ISP is ongoing" sif (cpuis("N572F065")) group.long 0x18++0x3 line.long 0x0 "FMC_FAT,Flash Access Time Control Register" endif tree.end tree "GPIO (General Purpose I/Os)" base ad:0x50004000 group.long 0x0++0xF line.long 0x0 "PA_MODE,GPIO PA Pin I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" line.long 0x4 "PA_DINOFF,GPIO PA Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 30. "DINOFF14,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 28. "DINOFF12,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 26. "DINOFF10,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 24. "DINOFF8,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 22. "DINOFF6,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 20. "DINOFF4,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 18. "DINOFF2,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 16. "DINOFF0,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." line.long 0x8 "PA_DOUT,GPIO PA Data Output Value" hexmask.long.word 0x8 0.--15. 1. "DOUT,Port [A/B] Pin[N] Output Value. Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output open-drain or quasi-bidirectional mode.." line.long 0xC "PA_DATMSK,GPIO PA Data Output Write Mask" hexmask.long.word 0xC 0.--15. 1. "DATMSK,Port [A/B] Pin[N] Data Output Write Mask. These bits are used to protect the corresponding register of Px_DOUT[n]. When set the DATMSK[n] to '1' the corresponding Px_DOUT[n] bit is writing protected. ." rgroup.long 0x10++0x3 line.long 0x0 "PA_PIN,GPIO PA Pin Value" hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin[N] Pin Values. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." group.long 0x18++0xB line.long 0x0 "PA_INTTYPE,GPIO PA Interrupt Trigger Type" hexmask.long.word 0x0 0.--15. 1. "TYPE,Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control. TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered the input source is sampled by one HCLK.." line.long 0x4 "PA_INTEN,GPIO PA Interrupt Enable" bitfld.long 0x4 31. "RHIEN15,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 30. "RHIEN14,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 29. "RHIEN13,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 28. "RHIEN12,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 27. "RHIEN11,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 26. "RHIEN10,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 25. "RHIEN9,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 24. "RHIEN8,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 23. "RHIEN7,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 22. "RHIEN6,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 21. "RHIEN5,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 20. "RHIEN4,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 19. "RHIEN3,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 18. "RHIEN2,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 17. "RHIEN1,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 16. "RHIEN0,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 15. "FLIEN15,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 14. "FLIEN14,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 13. "FLIEN13,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 12. "FLIEN12,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 11. "FLIEN11,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 10. "FLIEN10,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 9. "FLIEN9,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 8. "FLIEN8,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 7. "FLIEN7,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 6. "FLIEN6,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 5. "FLIEN5,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 4. "FLIEN4,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 3. "FLIEN3,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 2. "FLIEN2,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 1. "FLIEN1,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 0. "FLIEN0,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" line.long 0x8 "PA_INTSRC,GPIO PA Interrupt Source Flag" hexmask.long.word 0x8 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag. Read operation:." group.long 0x40++0xF line.long 0x0 "PB_MODE,GPIO PA Pin I/O Mode Control" bitfld.long 0x0 30.--31. "MODE15,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 28.--29. "MODE14,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 26.--27. "MODE13,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 24.--25. "MODE12,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 22.--23. "MODE11,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 20.--21. "MODE10,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 18.--19. "MODE9,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 16.--17. "MODE8,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 14.--15. "MODE7,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 12.--13. "MODE6,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 10.--11. "MODE5,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 8.--9. "MODE4,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 6.--7. "MODE3,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 4.--5. "MODE2,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" newline bitfld.long 0x0 2.--3. "MODE1,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" bitfld.long 0x0 0.--1. "MODE0,Port [A/B] Pin[N] I/O Mode Control . Determine each I/O type of GPIO Px pins." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?" line.long 0x4 "PB_DINOFF,GPIO PA Digital Input Path Disable Control" bitfld.long 0x4 31. "DINOFF15,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 30. "DINOFF14,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 29. "DINOFF13,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 28. "DINOFF12,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 27. "DINOFF11,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 26. "DINOFF10,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 25. "DINOFF9,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 24. "DINOFF8,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 23. "DINOFF7,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 22. "DINOFF6,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 21. "DINOFF5,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 20. "DINOFF4,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 19. "DINOFF3,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 18. "DINOFF2,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." newline bitfld.long 0x4 17. "DINOFF1,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." bitfld.long 0x4 16. "DINOFF0,Port [A/B] Pin[N] Digital Input Path Disable Control." "0: Px.n Digital input path Enable (Default),1: Px.n Digital input path Disable (digital input.." line.long 0x8 "PB_DOUT,GPIO PA Data Output Value" hexmask.long.word 0x8 0.--15. 1. "DOUT,Port [A/B] Pin[N] Output Value. Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output open-drain or quasi-bidirectional mode.." line.long 0xC "PB_DATMSK,GPIO PA Data Output Write Mask" hexmask.long.word 0xC 0.--15. 1. "DATMSK,Port [A/B] Pin[N] Data Output Write Mask. These bits are used to protect the corresponding register of Px_DOUT[n]. When set the DATMSK[n] to '1' the corresponding Px_DOUT[n] bit is writing protected. ." rgroup.long 0x50++0x3 line.long 0x0 "PB_PIN,GPIO PA Pin Value" hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin[N] Pin Values. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." group.long 0x58++0xB line.long 0x0 "PB_INTTYPE,GPIO PA Interrupt Trigger Type" hexmask.long.word 0x0 0.--15. 1. "TYPE,Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control. TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered the input source is sampled by one HCLK.." line.long 0x4 "PB_INTEN,GPIO PA Interrupt Enable" bitfld.long 0x4 31. "RHIEN15,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 30. "RHIEN14,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 29. "RHIEN13,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 28. "RHIEN12,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 27. "RHIEN11,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 26. "RHIEN10,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 25. "RHIEN9,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 24. "RHIEN8,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 23. "RHIEN7,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 22. "RHIEN6,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 21. "RHIEN5,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 20. "RHIEN4,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 19. "RHIEN3,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 18. "RHIEN2,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 17. "RHIEN1,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." bitfld.long 0x4 16. "RHIEN0,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.." newline bitfld.long 0x4 15. "FLIEN15,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 14. "FLIEN14,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 13. "FLIEN13,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 12. "FLIEN12,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 11. "FLIEN11,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 10. "FLIEN10,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 9. "FLIEN9,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 8. "FLIEN8,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 7. "FLIEN7,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 6. "FLIEN6,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 5. "FLIEN5,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 4. "FLIEN4,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 3. "FLIEN3,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 2. "FLIEN2,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" newline bitfld.long 0x4 1. "FLIEN1,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" bitfld.long 0x4 0. "FLIEN0,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt" line.long 0x8 "PB_INTSRC,GPIO PA Interrupt Source Flag" hexmask.long.word 0x8 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag. Read operation:." tree.end tree "INT (Interrupt Multiplexer)" base ad:0x50000300 rgroup.long 0x0++0xF line.long 0x0 "IRQ0_SRC,IRQ0 (WDT) Interrupt Source Identity Register" bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: WDT_INT" "0: WDT_INT,?,?,?,?,?,?,?" line.long 0x4 "IRQ1_SRC,IRQ1 (APU) Interrupt Source Identity Register" bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: APU_INT" "0: APU_INT,?,?,?,?,?,?,?" line.long 0x8 "IRQ2_SRC,IRQ2 (ADC) Interrupt Source Identity Register" bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: ADC_INT" "0: ADC_INT,?,?,?,?,?,?,?" line.long 0xC "IRQ3_SRC,IRQ3 (EXINT) Interrupt Source Identity Register" bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: External interrupt" "0: External interrupt,?,?,?,?,?,?,?" sif (cpuis("N572F065")) rgroup.long 0x10++0x3 line.long 0x0 "IRQ4_SRC,IRQ4 (USBD) Interrupt Source Identity Register" bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: USBD_INT" "0: USBD_INT,?,?,?,?,?,?,?" endif rgroup.long 0x14++0x27 line.long 0x0 "IRQ5_SRC,IRQ5 (Timer0) Interrupt Source Identity Register" bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: Timer0_INT" "0: Timer0_INT,?,?,?,?,?,?,?" line.long 0x4 "IRQ6_SRC,IRQ6 (Timer1) Interrupt Source Identity Register" bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: Timer1_INT" "0: Timer1_INT,?,?,?,?,?,?,?" line.long 0x8 "IRQ7_SRC,IRQ7 (Timer2) Interrupt Source Identity Register" bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: Timer2_INT" "0: Timer2_INT,?,?,?,?,?,?,?" line.long 0xC "IRQ8_SRC,IRQ8 (GPA/B) Interrupt Source Identity Register" bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: GPB_INT. Bit0: GPA_INT" "0: GPA_INT,1: GPB_INT,?,?,?,?,?,?" line.long 0x10 "IRQ9_SRC,IRQ9 (SPI0) Interrupt Source Identity Register" bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: SPI0_INT" "0: SPI0_INT,?,?,?,?,?,?,?" line.long 0x14 "IRQ10_SRC,IRQ10 (PWM) Interrupt Source Identity Register" bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: PWM_INT" "0: PWM_INT,?,?,?,?,?,?,?" line.long 0x18 "IRQ11_SRC,IRQ11 (SPI1) Interrupt Source Identity Register" bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: SPI1_INT" "0: SPI1_INT,?,?,?,?,?,?,?" line.long 0x1C "IRQ12_SRC,IRQ12 (TimerF) Interrupt Source Identity Register" bitfld.long 0x1C 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: TimerF_INT" "0: TimerF_INT,?,?,?,?,?,?,?" line.long 0x20 "IRQ13_SRC,IRQ13 (RTC) Interrupt Source Identity Register" bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: RTC_INT" "0: RTC_INT,?,?,?,?,?,?,?" line.long 0x24 "IRQ14_SRC,IRQ14 (PWRWU) Interrupt Source Identity Register" bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: PWRWU_INT" "0: PWRWU_INT,?,?,?,?,?,?,?" group.long 0x80++0x7 line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register" bitfld.long 0x0 7. "IRQ_TM,IRQ Test Mode. This bit is the protected bit. To program this bit needs an open lock sequence write '59h' '16h' '88h' to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.." "0: The interrupt register MCU_IRQ operates in..,1: All the interrupts from peripheral to MCU are.." hexmask.long.byte 0x0 0.--3. 1. "NMI_SEL,NMI Source Interrupt Select. The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[15:0].. The NMI_SEL bit is used to select the NMI interrupt source.. Note: IRQ15 is reserved in N572F064_F065" line.long 0x4 "MCU_IRQ,MCU IRQ Number Identify Register" hexmask.long.word 0x4 0.--15. 1. "MCU_IRQ,MCU IRQ Source Test Mode. The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0 the normal mode and test mode.. When.." tree.end tree "PWM (PWM Generator and Capture Timer)" base ad:0x40040000 group.long 0x0++0x13 line.long 0x0 "PWM_CLKPSC,PWM Prescaler Register" hexmask.long.byte 0x0 24.--31. 1. "DZI1,Dead Zone Interval Register 1. These 8 bits determine dead zone length.. The unit time of dead zone length is that from clock selector." hexmask.long.byte 0x0 16.--23. 1. "DZI0,Dead Zone Interval Register 0. These 8 bits determine dead zone length.. The unit time of dead zone length is that from clock selector." newline hexmask.long.byte 0x0 0.--7. 1. "CLKPSC,Clock Prescaler For PWM Timer. Clock input is divided by (CLKPSC + 1) ." line.long 0x4 "PWM_CLKDIV,PWM Clock Select Register" sif (cpuis("N572F065")) bitfld.long 0x4 0.--2. "CLKDIV,PWM Timer Clock Source Selection. Value : Input clock divided by. 000 : 2. 001 : 4. 010 : 8. 011 : 16. 1xx : 1" "0,1,2,3,4,5,6,7" endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x4 0.--2. "CLKDIV0,PWM Timer Clock Source Selection. Value : Input clock divided by. 000 : 2. 001 : 4. 010 : 8. 011 :.." "0,1,2,3,4,5,6,7" endif line.long 0x8 "PWM_CTL,PWM Control Register" bitfld.long 0x8 5. "DTEN1,Dead-Zone 1 Generator Enable/Disable." "0: Disable,1: Enable" bitfld.long 0x8 4. "DTEN0,Dead-Zone 0 Generator Enable/Disable." "0: Disable,1: Enable" newline bitfld.long 0x8 3. "CNTMODE,PWM-Timer Auto-Reload/One-Shot Mode." "0: One-Shot Mode,1: Auto-reload Mode" bitfld.long 0x8 2. "PINV,PWM-Timer Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON" newline bitfld.long 0x8 0. "CNTEN,PWM-Timer Enable." "0: Stop PWM-Timer Running,1: Enable PWM-Timer" line.long 0xC "PWM_PERIOD,PWM Period Register" hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value. PERIOD determines the PWM period.." line.long 0x10 "PWM_CMPDAT0,PWM Comparator Register 0" hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle." rgroup.long 0x14++0x3 line.long 0x0 "PWM_CNT,PWM Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Register. Reports the current value of the 16-bit down counter." group.long 0x1C++0x3 line.long 0x0 "PWM_CMPDAT1,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle." group.long 0x28++0x3 line.long 0x0 "PWM_CMPDAT2,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle." group.long 0x34++0x3 line.long 0x0 "PWM_CMPDAT3,PWM Comparator Register 0" hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle." group.long 0x40++0x7 line.long 0x0 "PWM_INTEN,PWM Interrupt Enable Register" bitfld.long 0x0 0. "PIEN,PWM Timer Interrupt Enable." "0: Disable,1: Enable" line.long 0x4 "PWM_INTSTS,PWM Interrupt Flag Register" bitfld.long 0x4 0. "PIF,PWM Timer Interrupt Flag. Flag is set by hardware when PWM down counter reaches zero software can clear this bit by writing '1' to it." "0,1" group.long 0x50++0x3 line.long 0x0 "PWM_CAPCTL,Capture Control Register" bitfld.long 0x0 7. "CFLIF,PWM_FCAPDAT Latched Indicator Bit. When input channel has a falling transition PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1" bitfld.long 0x0 6. "CRLIF,PWM_RCAPDAT Latched Indicator Bit. When input channel has a rising transition PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1" newline bitfld.long 0x0 4. "CAPIF,Capture Interrupt Indication Flag. Note:If this bit is '1' PWM counter will not be reloaded when next capture interrupt occurs." "0,1" bitfld.long 0x0 3. "CAPEN,Capture Channel Input Transition Enable/Disable. When enabled Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.. When disabled Capture function is inactive as is.." "0: Disable capture function,1: Enable capture function" newline bitfld.long 0x0 2. "CFLIEN,Falling Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt" bitfld.long 0x0 1. "CRLIEN,Rising Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt" newline bitfld.long 0x0 0. "CAPINV,Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.." rgroup.long 0x58++0x7 line.long 0x0 "PWM_RCAPDAT,Capture Rising Latch Register" hexmask.long.word 0x0 0.--15. 1. "RCAPDAT,Capture Rising Latch Register. In Capture mode this register is latched with the value of the PWM counter on a rising edge of the input signal." line.long 0x4 "PWM_FCAPDAT,Capture Falling Latch Register" hexmask.long.word 0x4 0.--15. 1. "FCAPDAT,Capture Falling Latch Register. In Capture mode this register is latched with the value of the PWM counter on a falling edge of the input signal." group.long 0x7C++0x3 line.long 0x0 "PWM_PCEN,PWM Output and Capture Input Enable Register" bitfld.long 0x0 8. "CAPINEN,Capture Input Enable Register." "0: OFF (PB.12 pin input disconnected from Capture..,1: ON (PB.12 pin if in PWM alternative function.." bitfld.long 0x0 3. "POEN3,PWM3 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPB_MFP Error! Reference source not found.)" "0: Disable PWM3 output to pin,1: Enable PWM3 output to pin" newline bitfld.long 0x0 2. "POEN2,PWM2 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Error! Reference source not found.)" "0: Disable PWM2 output to pin,1: Enable PWM2 output to pin" bitfld.long 0x0 1. "POEN1,PWM1 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Error! Reference source not found.)" "0: Disable PWM1 output to pin,1: Enable PWM1 output to pin" newline bitfld.long 0x0 0. "POEN0,PWM0 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Error! Reference source not found.)" "0: Disable PWM0 output to pin,1: Enable PWM0 output to pin" tree.end tree "RTC (Real Time Clock)" base ad:0x40008000 group.long 0x0++0x3 line.long 0x0 "RTC_CTL,RTC Control Register" bitfld.long 0x0 3.--4. "RTIS,RTC Timer Interval Select. These two bits select the timeout interval for the RTC. ." "0: Time-out frequency is 0.25Hz,1: Time-out frequency is 2Hz,?,?" bitfld.long 0x0 2. "RTCE,RTC Enable." "0: Disable RTC function,1: Enable RTC function" bitfld.long 0x0 1. "RTIE,RTC Interrupt Enable." "0: Disable the RTC interrupt,1: Enable the RTC interrupt" bitfld.long 0x0 0. "RTIF,RTC Interrupt Flag. If the RTC interrupt is enabled then the hardware will set this bit to indicate that the RTC interrupt has occurred. If the RTC interrupt is not enabled then this bit indicates that a timeout period has elapsed.. Note: This bit.." "0: RTC interrupt does not occur,1: RTC interrupt occurs" tree.end tree "SCS (System Controllable Space)" base ad:0xE000E000 sif (cpuis("N572F072")||cpuis("N572P072")) group.long 0x10++0xB line.long 0x0 "SYST_CSR,SysTick Control and Status Register" bitfld.long 0x0 16. "COUNTFLAG,System Tick Count Flag. Returns 1 if timer counted to 0 since last time this register was read.." "0: Cleared on read or by a write to the Current..,1: Set by a count transition from 1 to 0" bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection. If no external clock provided this bit will read as 1 and ignore writes." "0: clock source is (optional) external reference..,1: core clock used for SysTick" newline bitfld.long 0x0 1. "TICKINT,Enables SYST Exception Request." "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause SysTick exception.." bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled ." "0: The counter is disabled,1: The counter will operate in a multi-shot manner" line.long 0x4 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value. Value to load into the Current Value register when the counter reaches 0.. To generate a multi-shot timer with a period of N processor clock cycles use a RELOAD value of N-1. For example if the SysTick interrupt is.." line.long 0x8 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Counter Value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0." endif group.long 0x100++0x3 line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ15 Set-Enable Control Register" hexmask.long.word 0x0 0.--15. 1. "SETENA,Interrupt Set-Enable Bit. The NVIC_ISER register enables interrupts and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. . Write Operation: ." group.long 0x180++0x3 line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ15 Clear-Enable Control Register" hexmask.long.word 0x0 0.--15. 1. "CLRENA,Interrupt Clear-Enable Bit. The NVIC_ICER register disables interrupts and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. . Write Operation: ." group.long 0x200++0x3 line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ15 Set-Pending Control Register" hexmask.long.word 0x0 0.--15. 1. "SETPEND,Interrupt Set-Pending Bit. The NVIC_ISPR register forces interrupts into the pending state and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. . Write Operation: ." group.long 0x280++0x3 line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ15 Clear-Pending Control Register" hexmask.long.word 0x0 0.--15. 1. "CLRPEND,Interrupt Clear-Pending Bit. The NVIC_ICPR register removes the pending state of associated interrupts and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. Write.." group.long 0x400++0xF line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register" bitfld.long 0x0 30.--31. "PRI_3,Priority Of IRQ3. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x0 22.--23. "PRI_2,Priority Of IRQ2. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x0 14.--15. "PRI_1,Priority Of IRQ1. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x0 6.--7. "PRI_0,Priority Of IRQ0. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register" bitfld.long 0x4 30.--31. "PRI_7,Priority Of IRQ7. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x4 22.--23. "PRI_6,Priority Of IRQ6. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x4 14.--15. "PRI_5,Priority Of IRQ5. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x4 6.--7. "PRI_4,Priority Of IRQ4. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register" bitfld.long 0x8 30.--31. "PRI_11,Priority Of IRQ11. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x8 22.--23. "PRI_10,Priority Of IRQ10. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x8 14.--15. "PRI_9,Priority Of IRQ9. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0x8 6.--7. "PRI_8,Priority Of IRQ8. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register" bitfld.long 0xC 30.--31. "PRI_15,Priority Of IRQ15. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0xC 22.--23. "PRI_14,Priority Of IRQ14. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0xC 14.--15. "PRI_13,Priority Of IRQ13. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" bitfld.long 0xC 6.--7. "PRI_12,Priority Of IRQ12. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3" tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI0" base ad:0x40030000 group.long 0x0++0xB line.long 0x0 "SPI_CTL,Control and Status Register" sif (cpuis("N572F065")) bitfld.long 0x0 20. "REORDER,BYTE ENDIAN." "0: Disable the BYTE ENDIAN,1: Enable the BYTE ENDIAN. Only the 16 24 and 32.." bitfld.long 0x0 17. "UNIT_INTEN,Unit Transfer Interrupt Enable." "0: Disable SPI Unit Transfer Interrupt,1: Enable SPI Unit Transfer Interrupt to CPU" newline bitfld.long 0x0 16. "UNIT_INTSTS,Unit Transfer Interrupt Status. Note: This bit is read only but can be cleared by writing 1 to this bit." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Mode Only). (SUSPITV+2)* SPI_SCLKn clock cycles . Note: SUSPITV cannot be '0' for SPI0." newline hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Transmit Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.." endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 20. "BYTE_ENDIAN,BYTE ENDIAN." "0: Disable the BYTE ENDIAN,1: Enable the BYTE ENDIAN. Only the 16 24 and 32.." newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 18. "SLAVE,Master/Slave Mode Select. This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit." "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "SPIIE,Interrupt Enable." "0: Disable SPI interrupt,1: Enable SPI interrupt" newline bitfld.long 0x0 16. "SPIIF,Interrupt Flag. NOTE: This bit is read only but can be cleared by writing 1 to this bit." "0: It indicates that the transfer does not finish yet,1: It indicates that the transfer is done. The.." hexmask.long.byte 0x0 12.--15. 1. "SLEEP,Suspend Interval (Master Mode Only). (SLEEP+2)* SPI_SCLKn.. Note: SLEEP cannot be '0' for SPI0." newline endif bitfld.long 0x0 11. "CLKP,Clock Polarity." "0: SPI_SCLKn idle low,1: SPI_SCLKn idle high" bitfld.long 0x0 10. "LSB,Send LSB First." "0: The MSB is transmitted/received first (which bit..,1: The LSB (SPI_TXn[0]) is sent first to SPI_MOSIn.." newline bitfld.long 0x0 8.--9. "TX_NUM,Transmit/Receive Numbers. This field specifies how many transmit/receive numbers should be executed in one transfer.." "0: Only one transmit/receive will be executed in..,1: Two successive transmit/receive will be executed..,?,?" sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.." newline endif newline bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge." "0: The output on SPI_MOSIn is changed on the rising..,1: The output on SPI_MOSIn is changed on the.." bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge." "0: The input on SPI_MISOn is latched on the rising..,1: The input on SPI_MISOn is latched on the falling.." newline bitfld.long 0x0 0. "GO_BUSY,Go And Busy Status. NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress writing to any register of the SPI core has no effect." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit starts the transfer. This.." line.long 0x4 "SPI_CLKDIV,Clock Divider Register" hexmask.long.word 0x4 0.--15. 1. "DIVIDER,Clock Divider Register . The value in this field is the frequency divider of the system clock PCLK to generate the serial clock on the output (SPICLK).The desired frequency is obtained according to the following equation:. /. NOTE: Suggest.." line.long 0x8 "SPI_SSCTL,Slave Select Register" sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Flag (Slave Mode Only). When the SS_LTRIG bit is set in slave mode this bit can be read to indicate the received bit number meets the requirement or not.. . Note 1: This bit is READ only.. Note 2: This bit exists in SPI1 only." "0: One of the received number and the received bit..,1: This bit is READ only" bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger (Slave Mode Only). . Note 1: This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit." "0: The input slave select signal is edge-trigger.,1: This bit exists in SPI1 only" newline bitfld.long 0x8 3. "ASS,Automatic Slave Select (Master Mode Only)." "0: Slave select signal (SPI_SSBx0/SPI_SSBx1) is..,1: Slave select signal (SPI_SSBx0/SPI_SSBx1) is.." endif sif (cpuis("N572F065")) bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select." "0: Slave select signal (SPI_SSBx0/SPI_SSBx1) is..,1: Slave select signal (SPI_SSBx0/SPI_SSBx1) is.." newline bitfld.long 0x8 0.--1. "SS,Slave Select Pin Control (Master Mode Only). If AUTOSS bit is 0 . SPIn_SSBx0 and SPIn_SSBx1 output are determined by SS[0] and SS[1] respectively. ." "0: Any bit location of this field forces the pin to..,1: Any bit location of this field forces the proper..,?,?" endif bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level. It defines the active level of device/slave select signal.." "0: The SPI_SSBx0/SPI_SSBx1 slave select signal is..,1: The SPI_SSBx0/SPI_SSBx1 slave select signal is.." newline sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x8 0.--1. "SSPC,Slave Select Pin Control (Master Mode Only). If ASS bit is 0 SPI_SSBx0 and SPI_SSBx1 output are determined by SSPC[0] and SSPC[1] respectively. Writing 1 to any bit location of this field forces the proper SPI_SSBx0/SPI_SSBx1 pin to an active state.." "0,1,2,3" endif rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops." line.long 0x4 "SPI_RX1,Data Receive Register 0" hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register. Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. Note: The SPI_RXn and SPI_TXn registers share the same flip-flops which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two.." line.long 0x4 "SPI_TX1,Data Transmit Register 0" hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register. Note: The SPI_RXn and SPI_TXn registers share the same flip-flops which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two.." sif (cpuis("N572F072")||cpuis("N572P072")) group.long 0x30++0x3 line.long 0x0 "SPI0_RCLK,SPI0 Receive Timing Control Register" bitfld.long 0x0 2.--3. "SPI0_CTIM,Coarse Timing Control For SPI0 Data Receiving. Setting these bits can adjust receiving clock for latching serial-in data correctly in high speed transmission mode. ." "0: Receiving data clock of SPI0 is same as the..,1: Receiving data clock of SPI0 is delayed 2 half..,?,?" bitfld.long 0x0 0.--1. "SPI0_FTIM,Fine Timing Control For SPI0 Data Receiving. The delay timing selected by SPI0_CTIM can be further tuned finely by SPI0_FTIM. ." "0: Receiving data clock of SPI0 has extra 7.5nS delay,1: Receiving data clock of SPI0 has extra 5.0nS..,?,?" endif tree.end tree "SPI1" base ad:0x40034000 group.long 0x0++0xB line.long 0x0 "SPI_CTL,Control and Status Register" sif (cpuis("N572F065")) bitfld.long 0x0 20. "REORDER,BYTE ENDIAN." "0: Disable the BYTE ENDIAN,1: Enable the BYTE ENDIAN. Only the 16 24 and 32.." bitfld.long 0x0 17. "UNIT_INTEN,Unit Transfer Interrupt Enable." "0: Disable SPI Unit Transfer Interrupt,1: Enable SPI Unit Transfer Interrupt to CPU" newline bitfld.long 0x0 16. "UNIT_INTSTS,Unit Transfer Interrupt Status. Note: This bit is read only but can be cleared by writing 1 to this bit." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer" hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Mode Only). (SUSPITV+2)* SPI_SCLKn clock cycles . Note: SUSPITV cannot be '0' for SPI0." newline hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Transmit Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.." endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 20. "BYTE_ENDIAN,BYTE ENDIAN." "0: Disable the BYTE ENDIAN,1: Enable the BYTE ENDIAN. Only the 16 24 and 32.." newline endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 18. "SLAVE,Master/Slave Mode Select. This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit." "0: Master mode,1: Slave mode" bitfld.long 0x0 17. "SPIIE,Interrupt Enable." "0: Disable SPI interrupt,1: Enable SPI interrupt" newline bitfld.long 0x0 16. "SPIIF,Interrupt Flag. NOTE: This bit is read only but can be cleared by writing 1 to this bit." "0: It indicates that the transfer does not finish yet,1: It indicates that the transfer is done. The.." hexmask.long.byte 0x0 12.--15. 1. "SLEEP,Suspend Interval (Master Mode Only). (SLEEP+2)* SPI_SCLKn.. Note: SLEEP cannot be '0' for SPI0." newline endif bitfld.long 0x0 11. "CLKP,Clock Polarity." "0: SPI_SCLKn idle low,1: SPI_SCLKn idle high" bitfld.long 0x0 10. "LSB,Send LSB First." "0: The MSB is transmitted/received first (which bit..,1: The LSB (SPI_TXn[0]) is sent first to SPI_MOSIn.." newline bitfld.long 0x0 8.--9. "TX_NUM,Transmit/Receive Numbers. This field specifies how many transmit/receive numbers should be executed in one transfer.." "0: Only one transmit/receive will be executed in..,1: Two successive transmit/receive will be executed..,?,?" sif (cpuis("N572F072")||cpuis("N572P072")) hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.." newline endif newline bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge." "0: The output on SPI_MOSIn is changed on the rising..,1: The output on SPI_MOSIn is changed on the.." bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge." "0: The input on SPI_MISOn is latched on the rising..,1: The input on SPI_MISOn is latched on the falling.." newline bitfld.long 0x0 0. "GO_BUSY,Go And Busy Status. NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress writing to any register of the SPI core has no effect." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit starts the transfer. This.." line.long 0x4 "SPI_CLKDIV,Clock Divider Register" hexmask.long.word 0x4 0.--15. 1. "DIVIDER,Clock Divider Register . The value in this field is the frequency divider of the system clock PCLK to generate the serial clock on the output (SPICLK).The desired frequency is obtained according to the following equation:. /. NOTE: Suggest.." line.long 0x8 "SPI_SSCTL,Slave Select Register" sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Flag (Slave Mode Only). When the SS_LTRIG bit is set in slave mode this bit can be read to indicate the received bit number meets the requirement or not.. . Note 1: This bit is READ only.. Note 2: This bit exists in SPI1 only." "0: One of the received number and the received bit..,1: This bit is READ only" bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger (Slave Mode Only). . Note 1: This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit." "0: The input slave select signal is edge-trigger.,1: This bit exists in SPI1 only" newline bitfld.long 0x8 3. "ASS,Automatic Slave Select (Master Mode Only)." "0: Slave select signal (SPI_SSBx0/SPI_SSBx1) is..,1: Slave select signal (SPI_SSBx0/SPI_SSBx1) is.." endif sif (cpuis("N572F065")) bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select." "0: Slave select signal (SPI_SSBx0/SPI_SSBx1) is..,1: Slave select signal (SPI_SSBx0/SPI_SSBx1) is.." newline bitfld.long 0x8 0.--1. "SS,Slave Select Pin Control (Master Mode Only). If AUTOSS bit is 0 . SPIn_SSBx0 and SPIn_SSBx1 output are determined by SS[0] and SS[1] respectively. ." "0: Any bit location of this field forces the pin to..,1: Any bit location of this field forces the proper..,?,?" endif bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level. It defines the active level of device/slave select signal.." "0: The SPI_SSBx0/SPI_SSBx1 slave select signal is..,1: The SPI_SSBx0/SPI_SSBx1 slave select signal is.." newline sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x8 0.--1. "SSPC,Slave Select Pin Control (Master Mode Only). If ASS bit is 0 SPI_SSBx0 and SPI_SSBx1 output are determined by SSPC[0] and SSPC[1] respectively. Writing 1 to any bit location of this field forces the proper SPI_SSBx0/SPI_SSBx1 pin to an active state.." "0,1,2,3" endif rgroup.long 0x10++0x7 line.long 0x0 "SPI_RX0,Data Receive Register 0" hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops." line.long 0x4 "SPI_RX1,Data Receive Register 0" hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register. Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops." wgroup.long 0x20++0x7 line.long 0x0 "SPI_TX0,Data Transmit Register 0" hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. Note: The SPI_RXn and SPI_TXn registers share the same flip-flops which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two.." line.long 0x4 "SPI_TX1,Data Transmit Register 0" hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register. Note: The SPI_RXn and SPI_TXn registers share the same flip-flops which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two.." tree.end tree.end tree "SYS (System Control Registers)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "SYS_PDID,Product Identifier Register" hexmask.long 0x0 0.--31. 1. "PDID,Product Identifier. Chip identifier (part number) for N572F064 series." group.long 0x4++0xB line.long 0x0 "SYS_RSTSTS,System Reset Source Register" bitfld.long 0x0 6. "PMURSTF,Reset Source From PMU. The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from PMU,1: The PMU has issued the reset signal to reset the.." sif (cpuis("N572F065")) bitfld.long 0x0 5. "MCURF,MCU Reset Flag . The MCURF flag is set by the 'reset signal' from the MCU Cortex_M0 module to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from MCU,1: The MCU Cortex_M0 had issued the reset signal to.." endif newline bitfld.long 0x0 3. "LVRF,LVR Reset Flag . The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. . Note: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.." bitfld.long 0x0 2. "WDTRF,Reset Source From WDG. The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.. Note: Write 1 to clear this bit to 0." "0: No reset from Watch-Dog,1: The Watch-Dog module issued the reset signal to.." newline bitfld.long 0x0 1. "PINRF,nRESET Pin Reset Flag . The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. . Note: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.." bitfld.long 0x0 0. "PORF,POR Reset Flag . The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller to indicate the previous reset source. . Note: Write 1 to clear this bit to 0." "0: No reset from POR,1: Power-on Reset (POR) Controller had issued the.." line.long 0x4 "SYS_IPRST0,IP Reset Control Resister0" bitfld.long 0x4 3. "RAMWS,Wait State Control For CPU Access RAM ." "0: 1 HCLK clock wait-state,1: zero wait-state" bitfld.long 0x4 2. "CPUWS,CPU Wait-State Control For Flash Memory Access. Note: that CPUWS cannot be set as '1' when CPU runs the program to do Flash ISP operation." "0: 1 HCLK clock wait-state,1: zero wait-state" newline bitfld.long 0x4 1. "CPURST,CPU Kernel One Shot Reset. Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC) this bit will automatically return to '0' after the 2 clock cycles." "0: Normal,1: Reset CPU" bitfld.long 0x4 0. "CHIPRST,CHIP One Shot Reset. Set this bit will reset the whole chip this bit will automatically return to '0' after 2 clock cycles.. The CHIPRST is almost the same as the POR reset all the chip modules are reset but the chip settings from flash are not.." "0: Normal,1: Reset CHIP" line.long 0x8 "SYS_IPRST1,IP Reset Control Resister1" bitfld.long 0x8 28. "ADCRST,ADC Controller Reset ." "0: Normal Operation,1: IP reset" sif (cpuis("N572F065")) bitfld.long 0x8 27. "USBDRST,USB Device Controller Reset." "0: Normal operation,1: IP reset" endif newline bitfld.long 0x8 20. "PWMRST,PWM Controller Reset." "0: Normal Operation,1: IP reset" bitfld.long 0x8 13. "SPI1RST,SPI1 Controller Reset." "0: Normal Operation,1: IP reset" newline bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset." "0: Normal Operation,1: IP reset" bitfld.long 0x8 6. "TMRFRST,TimerF Controller Reset." "0: Normal operation,1: IP reset" newline bitfld.long 0x8 5. "APURST,APU Controller Reset." "0: Normal operation,1: IP reset" bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset." "0: Normal operation,1: IP reset" newline bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset." "0: Normal Operation,1: IP reset" bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset." "0: Normal Operation,1: IP reset" newline bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset." "0: Normal operation,1: IP reset" group.long 0x18++0x7 line.long 0x0 "SYS_BODCTL,Brown-Out Detector Control Register" bitfld.long 0x0 7. "LVR_EN,Low Voltage Reset (LVR) Enable (Protected Bit). The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.." "0: Disable LVR function,1: Enable LVR function - After enable the bit the.." bitfld.long 0x0 6. "BOD_OUT,The Status For Brown-Out Detector Output It's a read only bit.." "0: The detected voltage is lower than BOD_VL..,1: The detected voltage is higher than BOD_VL setting" newline sif (cpuis("N572F065")) bitfld.long 0x0 1. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Initiate & Protected Bit). The default value is set by flash controller user configuration register CONFIG[21].." "0: Threshold voltage is 2.7V,1: Threshold voltage is 3.0V" endif sif (cpuis("N572F072")||cpuis("N572P072")) bitfld.long 0x0 1. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Initiate & Protected Bit)." "0,1" newline endif bitfld.long 0x0 0. "BOD_EN,Brown-Out Detector Enable (Initiated & Protected Bit)." "0: Brown-Out Detector function is disabled,1: Brown-Out Detector function is enabled" line.long 0x4 "SYS_PORCTL,Power-On-Reset Controller Register" hexmask.long.word 0x4 0.--15. 1. "POROFF,Power-On Reset Enable Bit (Write Protect) . When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.." group.long 0x30++0x7 line.long 0x0 "SYS_GPA_MFP,GPIO PA Multiple Alternate Functions and Input Type Control Register" hexmask.long.word 0x0 16.--31. 1. "PAnTYPEn," bitfld.long 0x0 15. "PA15MFP," "0: The GPIOA-15 is selected to the pin PA.15,1: ADC input channel 7" newline bitfld.long 0x0 14. "PA14MFP," "0: The GPIOA-14 is selected to the pin PA.14,1: ADC input channel 6" bitfld.long 0x0 13. "PA13MFP," "0: The GPIOA-13 is selected to the pin PA.13,1: ADC input channel 5" newline bitfld.long 0x0 12. "PA12MFP," "0: The GPIOA-12 is selected to the pin PA.12,1: ADC input channel 4" bitfld.long 0x0 11. "PA11MFP," "0: The GPIOA-11 is selected to the pin PA.11,1: ADC input channel 3" newline bitfld.long 0x0 10. "PA10MFP," "0: The GPIOA-10 is selected to the pin PA.10,1: ADC input channel 2" bitfld.long 0x0 9. "PA9MFP," "0: The GPIOA-9 is selected to the pin PA.9,1: ADC input channel 1" newline bitfld.long 0x0 8. "PA8MFP," "0: The GPIOA-8 is selected to the pin PA.8,1: ADC input channel 0" bitfld.long 0x0 7. "PA7MFP," "0: The GPIOA-7 is selected to the pin PA.7,1: ADC input external trigger input" newline bitfld.long 0x0 6. "PA6MFP," "0: The GPIOA-6 is selected to the pin PA.6,1: External interrupt input" bitfld.long 0x0 5. "PA5MFP," "0: The GPIOA-5 is selected to the pin PA.5,1: Timer0 counter external input" newline bitfld.long 0x0 4. "PA4MFP," "0: The GPIOA-4 is selected to the pin PA.4,1: SPI0 data output" bitfld.long 0x0 3. "PA3MFP," "0: The GPIOA-3 is selected to the pin PA.3,1: SPI0 data input" newline bitfld.long 0x0 2. "PA2MFP," "0: The GPIOA-2 is selected to the pin PA.2,1: SPI0 clock output" bitfld.long 0x0 1. "PA1MFP," "0: The GPIOA-1 is selected to the pin PA.1,1: SPI0 1st chip select output" newline bitfld.long 0x0 0. "PA0MFP," "0: The GPIOA-0 is selected to the pin PA.0,1: SPI0 2nd chip select output" line.long 0x4 "SYS_GPB_MFP,GPIO PB Multiple Alternate Functions and Input Type Control Register" hexmask.long.word 0x4 16.--31. 1. "PBnTYPEn," bitfld.long 0x4 15. "PB15MFP," "0: The GPIOB-15 is selected to the pin PB.15,1: Timer2 counter external input" newline bitfld.long 0x4 14. "PB14MFP," "0: The GPIOB-14 is selected to the pin PB.14,1: Timer1 counter external input" bitfld.long 0x4 13. "PB13MFP," "0: The GPIOB-13 is selected to the pin PB.13,1: IR carrier output" newline bitfld.long 0x4 12. "PB12MFP," "0: The GPIOB-12 is selected to the pin PB.12,1: PWM timer capture input" bitfld.long 0x4 11. "PB11MFP," "0: The GPIOB-11 is selected to the pin PB.11,1: PWM output pin 3" newline bitfld.long 0x4 10. "PB10MFP," "0: The GPIOB-10 is selected to the pin PB.10,1: PWM output pin 2" bitfld.long 0x4 9. "PB9MFP," "0: The GPIOB-9 is selected to the pin PB.9,1: PWM output pin 1" newline bitfld.long 0x4 8. "PB8MFP," "0: The GPIOB-8 is selected to the pin PB.8,1: PWM output pin 0" bitfld.long 0x4 4. "PB4MFP," "0: The GPIOB-4 is selected to the pin PB.4,1: SPI1 data output/input" newline bitfld.long 0x4 3. "PB3MFP," "0: The GPIOB-3 is selected to the pin PB.3,1: SPI1 data input/output" bitfld.long 0x4 2. "PB2MFP," "0: The GPIOB-2 is selected to the pin PB.2,1: SPI1 clock output/input" newline bitfld.long 0x4 1. "PB1MFP," "0: The GPIOB-1 is selected to the pin PB.1,1: SPI1 1st chip select output or slave select input" bitfld.long 0x4 0. "PB0MFP," "0: The GPIOB-0 is selected to the pin PB.0,1: SPI1 2nd chip select output" sif (cpuis("N572F072")||cpuis("N572P072")) group.long 0x38++0x3 line.long 0x0 "SYS_GPA_HS,PA.4 ~ PA.0 High Speed Transition Control Register" hexmask.long.byte 0x0 16.--20. 1. "GPRB,Five general purpose R/W register bits." hexmask.long.byte 0x0 0.--4. 1. "GPA_HS," endif group.long 0x100++0x3 line.long 0x0 "SYS_REGLCTL,Register Lock Control Register" rbitfld.long 0x0 0. "REGLCTL,Protected Register Lock/Unlock Index (Read Only). SPI0_RCLK - address 0x4003_0030. FMC_ISPCTL - address 0x5000_C000 (Flash ISP Control register). WDT_CTL - address 0x4000_4000. FATCON - address 0x5000_C018" "0: Protected registers are locked. Any write to the..,1: Protected registers are unlocked" hexmask.long.byte 0x0 0.--7. 1. "SYS_REGLCTL,Register Lock Control Code (Write Only) . Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.." tree.end tree "TMR (Timer Controller)" base ad:0x40010000 group.long 0x0++0x7 line.long 0x0 "TIMER0_CTL,Timer0 Control and Status Register" bitfld.long 0x0 31. "Reserved,Reserved." "0,1" bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt" bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The Timer is operating in the one-shot mode. The..,1: The Timer is operating in the periodic mode. The..,?,?" newline bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the Timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 16-bit.." rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of Timer.." "0: Timer is not active,1: Timer is active" newline hexmask.long.byte 0x0 0.--7. 1. "PSC,Timer Clock Prescaler." line.long 0x4 "TIMER0_CMP,Timer0 Compare Register" hexmask.long.word 0x4 0.--15. 1. "CMPDAT,Timer Comparison Value. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. Note 2: No matter CNTEN is 0 or 1 whenever software writes a new value into this register TIMER will restart counting by using this new value.." rgroup.long 0x8++0x7 line.long 0x0 "TIMER0_INTSTS,Timer0 Interrupt Status Register" bitfld.long 0x0 0. "TIF,Timer Interrupt Flag (Read Only). This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself." "0: No effect,1: CNT (TIMERx_CNT[15:0]) value matches the CMPDAT.." line.long 0x4 "TIMER0_CNT,Timer0 Data Register" hexmask.long.word 0x4 0.--15. 1. "CNT,Timer Data Register. User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1 " group.long 0x20++0x7 line.long 0x0 "TIMER1_CTL,Timer0 Control and Status Register" bitfld.long 0x0 31. "Reserved,Reserved." "0,1" bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt" bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The Timer is operating in the one-shot mode. The..,1: The Timer is operating in the periodic mode. The..,?,?" newline bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the Timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 16-bit.." rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of Timer.." "0: Timer is not active,1: Timer is active" newline hexmask.long.byte 0x0 0.--7. 1. "PSC,Timer Clock Prescaler." line.long 0x4 "TIMER1_CMP,Timer0 Compare Register" hexmask.long.word 0x4 0.--15. 1. "CMPDAT,Timer Comparison Value. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. Note 2: No matter CNTEN is 0 or 1 whenever software writes a new value into this register TIMER will restart counting by using this new value.." rgroup.long 0x28++0x7 line.long 0x0 "TIMER1_INTSTS,Timer0 Interrupt Status Register" bitfld.long 0x0 0. "TIF,Timer Interrupt Flag (Read Only). This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself." "0: No effect,1: CNT (TIMERx_CNT[15:0]) value matches the CMPDAT.." line.long 0x4 "TIMER1_CNT,Timer0 Data Register" hexmask.long.word 0x4 0.--15. 1. "CNT,Timer Data Register. User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1 " group.long 0x30++0x7 line.long 0x0 "TIMERF_INTSTS,TimerF Interrupt Status Register" bitfld.long 0x0 1. "TFIE,TimerF Interrupt Enable." "0: Disable TimerF Interrupt,1: Enable TimerF Interrupt" bitfld.long 0x0 0. "TFIF,TimerF Interrupt Flag. This bit indicates the interrupt status of TimerF.. TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit.." "0: It indicates that TimerF does not time out yet,1: It indicates that TimerF time out. The interrupt.." line.long 0x4 "IR_CTL,IR Carrier Output Control Register" group.long 0x40++0x7 line.long 0x0 "TIMER2_CTL,Timer0 Control and Status Register" bitfld.long 0x0 31. "Reserved,Reserved." "0,1" bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stop/Suspend counting,1: Start counting" newline bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt" bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The Timer is operating in the one-shot mode. The..,1: The Timer is operating in the periodic mode. The..,?,?" newline bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the Timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 16-bit.." rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of Timer.." "0: Timer is not active,1: Timer is active" newline hexmask.long.byte 0x0 0.--7. 1. "PSC,Timer Clock Prescaler." line.long 0x4 "TIMER2_CMP,Timer0 Compare Register" hexmask.long.word 0x4 0.--15. 1. "CMPDAT,Timer Comparison Value. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. Note 2: No matter CNTEN is 0 or 1 whenever software writes a new value into this register TIMER will restart counting by using this new value.." rgroup.long 0x48++0x7 line.long 0x0 "TIMER2_INTSTS,Timer0 Interrupt Status Register" bitfld.long 0x0 0. "TIF,Timer Interrupt Flag (Read Only). This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself." "0: No effect,1: CNT (TIMERx_CNT[15:0]) value matches the CMPDAT.." line.long 0x4 "TIMER2_CNT,Timer0 Data Register" hexmask.long.word 0x4 0.--15. 1. "CNT,Timer Data Register. User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1 " tree.end sif (cpuis("N572F065")) tree "USBD (USB Device Controller)" base ad:0x40060000 group.long 0x0++0xB line.long 0x0 "USBD_INTEN,USB Device Interrupt Enable Register" bitfld.long 0x0 15. "INNAKEN,Active NAK Function And Its Status In IN Token ." "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS.." bitfld.long 0x0 8. "WKEN,Wake-Up Function Enable Bit ." "0: USB wake-up function Disabled,1: USB wake-up function Enabled" newline bitfld.long 0x0 3. "NEVWKIEN,USB No-Event-Wake-Up Interrupt Enable Bit ." "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled" bitfld.long 0x0 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit ." "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled" newline bitfld.long 0x0 1. "USBIEN,USB Event Interrupt Enable Bit ." "0: USB event interrupt Disabled,1: USB event interrupt Enabled" bitfld.long 0x0 0. "BUSIEN,Bus Event Interrupt Enable Bit ." "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled" line.long 0x4 "USBD_INTSTS,USB Device Interrupt Event Status Register" bitfld.long 0x4 31. "SETUP,Setup Event Status ." "0: No Setup event,1: Setup event occurred cleared by write 1 to.." bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status ." "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.." newline bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status ." "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.." bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status . USBD_INTSTS[1]." "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.." newline bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status ." "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.." bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status ." "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.." newline bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status ." "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.." bitfld.long 0x4 3. "NEVWKIF,No-Event-Wake-Up Interrupt Status ." "0: NEVWK event does not occur,1: No-event-wake-up event occurred cleared by write.." newline bitfld.long 0x4 2. "VBDETIF,VBUS Detection Interrupt Status ." "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.." bitfld.long 0x4 1. "USBIF,USB Event Interrupt Status . The USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus. ." "0: No USB event occurred,1: USB event occurred check EPSTS0~5[2:0] to know.." newline bitfld.long 0x4 0. "BUSIF,BUS Interrupt Status . The BUS event means that there is one of the suspense or the resume function in the bus. ." "0: No BUS event occurred,1: Bus event occurred; check USBD_ATTR[3:0] to know.." line.long 0x8 "USBD_FADDR,USB Device Function Address Register" hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB Device Function Address" rgroup.long 0xC++0x3 line.long 0x0 "USBD_EPSTS,USB Device Endpoint Status Register" bitfld.long 0x0 23.--25. "EPSTS5,Endpoint 5 Status . These bits are used to indicate the current status of this endpoint." "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 20.--22. "EPSTS4,Endpoint 4 Status . These bits are used to indicate the current status of this endpoint." "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 17.--19. "EPSTS3,Endpoint 3 Status . These bits are used to indicate the current status of this endpoint." "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 14.--16. "EPSTS2,Endpoint 2 Status . These bits are used to indicate the current status of this endpoint." "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 11.--13. "EPSTS1,Endpoint 1 Status . These bits are used to indicate the current status of this endpoint." "0: In ACK,1: In NAK,?,?,?,?,?,?" bitfld.long 0x0 8.--10. "EPSTS0,Endpoint 0 Status . These bits are used to indicate the current status of this endpoint." "0: In ACK,1: In NAK,?,?,?,?,?,?" newline bitfld.long 0x0 7. "OV,Overrun . It indicates that the received data is over the maximum payload number or not. ." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.." bitfld.long 0x0 4.--6. "STS," "0: In ACK,1: In NAK,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "EPT,Endpoint number" group.long 0x10++0x3 line.long 0x0 "USBD_ATTR,USB Device Bus Status and Attribution Register" bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection." "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.." bitfld.long 0x0 9. "PDB,Power Down USB-IP Related Power and Control." "0: Enable power down,1: Disable power down" newline bitfld.long 0x0 8. "DPPUEN,Pull-Up Resistor On USB_DP Enable Bit." "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active" bitfld.long 0x0 7. "USBEN,USB Controller Enable Bit." "0: USB Controller Disabled,1: USB Controller Enabled" newline bitfld.long 0x0 5. "RWAKEUP,Remote Wake-Up." "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).." bitfld.long 0x0 4. "PHYEN,PHY Transceiver Function Enable Bit ." "0: PHY transceiver function Disabled. The PHY means..,1: PHY transceiver function Enabled" newline bitfld.long 0x0 3. "TOUT,Time-Out Status. Note: This bit is read only." "0: No time-out,1: No Bus response more than 18 bits time" bitfld.long 0x0 2. "RESUME,Resume Status. Note: This bit is read only." "0: No bus resume,1: Resume from suspend" newline bitfld.long 0x0 1. "SUSPEND,Suspend Status. Note: This bit is read only." "0: Bus no suspend,1: Bus idle more than 3ms either cable is plugged.." bitfld.long 0x0 0. "USBRST,USB Reset Status. Note: This bit is read only." "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.." rgroup.long 0x14++0x3 line.long 0x0 "USBD_VBUSDET,USB Device VBUS Detection Register" bitfld.long 0x0 0. "VBUSDET,Device VBUS Detection . Note: This bit is read only." "0: Controller is not attached to the USB host,1: Controller is attached to the USB host" group.long 0x18++0x3 line.long 0x0 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "STBUFSEG,SETUP Token Buffer Segmentation . It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is . USBD_SRAM address + {STBUFSEG[8:3] 3'b000} . Note: It is used for.." group.long 0x20++0x5F line.long 0x0 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + { BUFSEG[8:3] 3'b000}. Refer to the section.." line.long 0x4 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload . Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x8 "USBD_CFG0,Endpoint 0 Configuration Register" bitfld.long 0x8 9. "CSTALL,Clear STALL Response ." "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x8 7. "DSQSYNC,Data Sequence Synchronization . Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x8 5.--6. "STATE,Endpoint STATE ." "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint . This bit is used to set the endpoint as Isochronous endpoint no handshake. ." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x8 0.--3. 1. "EPNUM,Endpoint Number . These bits are used to define the endpoint number of the current endpoint" line.long 0xC "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0xC 1. "SSTALL,Set STALL ." "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0xC 0. "CLRRDY,Clear Ready . When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x10 "USBD_BUFSEG1,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x10 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + { BUFSEG[8:3] 3'b000}. Refer to the section.." line.long 0x14 "USBD_MXPLD1,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x14 0.--8. 1. "MXPLD,Maximal Payload . Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x18 "USBD_CFG1,Endpoint 0 Configuration Register" bitfld.long 0x18 9. "CSTALL,Clear STALL Response ." "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x18 7. "DSQSYNC,Data Sequence Synchronization . Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x18 5.--6. "STATE,Endpoint STATE ." "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint . This bit is used to set the endpoint as Isochronous endpoint no handshake. ." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x18 0.--3. 1. "EPNUM,Endpoint Number . These bits are used to define the endpoint number of the current endpoint" line.long 0x1C "USBD_CFGP1,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x1C 1. "SSTALL,Set STALL ." "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x1C 0. "CLRRDY,Clear Ready . When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x20 "USBD_BUFSEG2,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x20 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + { BUFSEG[8:3] 3'b000}. Refer to the section.." line.long 0x24 "USBD_MXPLD2,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x24 0.--8. 1. "MXPLD,Maximal Payload . Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x28 "USBD_CFG2,Endpoint 0 Configuration Register" bitfld.long 0x28 9. "CSTALL,Clear STALL Response ." "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x28 7. "DSQSYNC,Data Sequence Synchronization . Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x28 5.--6. "STATE,Endpoint STATE ." "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint . This bit is used to set the endpoint as Isochronous endpoint no handshake. ." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x28 0.--3. 1. "EPNUM,Endpoint Number . These bits are used to define the endpoint number of the current endpoint" line.long 0x2C "USBD_CFGP2,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x2C 1. "SSTALL,Set STALL ." "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x2C 0. "CLRRDY,Clear Ready . When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x30 "USBD_BUFSEG3,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x30 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + { BUFSEG[8:3] 3'b000}. Refer to the section.." line.long 0x34 "USBD_MXPLD3,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x34 0.--8. 1. "MXPLD,Maximal Payload . Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x38 "USBD_CFG3,Endpoint 0 Configuration Register" bitfld.long 0x38 9. "CSTALL,Clear STALL Response ." "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x38 7. "DSQSYNC,Data Sequence Synchronization . Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x38 5.--6. "STATE,Endpoint STATE ." "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint . This bit is used to set the endpoint as Isochronous endpoint no handshake. ." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x38 0.--3. 1. "EPNUM,Endpoint Number . These bits are used to define the endpoint number of the current endpoint" line.long 0x3C "USBD_CFGP3,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x3C 1. "SSTALL,Set STALL ." "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x3C 0. "CLRRDY,Clear Ready . When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x40 "USBD_BUFSEG4,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x40 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + { BUFSEG[8:3] 3'b000}. Refer to the section.." line.long 0x44 "USBD_MXPLD4,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x44 0.--8. 1. "MXPLD,Maximal Payload . Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x48 "USBD_CFG4,Endpoint 0 Configuration Register" bitfld.long 0x48 9. "CSTALL,Clear STALL Response ." "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x48 7. "DSQSYNC,Data Sequence Synchronization . Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x48 5.--6. "STATE,Endpoint STATE ." "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint . This bit is used to set the endpoint as Isochronous endpoint no handshake. ." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x48 0.--3. 1. "EPNUM,Endpoint Number . These bits are used to define the endpoint number of the current endpoint" line.long 0x4C "USBD_CFGP4,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x4C 1. "SSTALL,Set STALL ." "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x4C 0. "CLRRDY,Clear Ready . When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" line.long 0x50 "USBD_BUFSEG5,Endpoint 0 Buffer Segmentation Register" hexmask.long.byte 0x50 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + { BUFSEG[8:3] 3'b000}. Refer to the section.." line.long 0x54 "USBD_MXPLD5,Endpoint 0 Maximal Payload Register" hexmask.long.word 0x54 0.--8. 1. "MXPLD,Maximal Payload . Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.." line.long 0x58 "USBD_CFG5,Endpoint 0 Configuration Register" bitfld.long 0x58 9. "CSTALL,Clear STALL Response ." "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.." bitfld.long 0x58 7. "DSQSYNC,Data Sequence Synchronization . Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID" newline bitfld.long 0x58 5.--6. "STATE,Endpoint STATE ." "0: Endpoint is Disabled,1: Out endpoint,?,?" bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint . This bit is used to set the endpoint as Isochronous endpoint no handshake. ." "0: No Isochronous endpoint,1: Isochronous endpoint" newline hexmask.long.byte 0x58 0.--3. 1. "EPNUM,Endpoint Number . These bits are used to define the endpoint number of the current endpoint" line.long 0x5C "USBD_CFGP5,Endpoint 0 Set Stall and Clear In/Out Ready Control Register" bitfld.long 0x5C 1. "SSTALL,Set STALL ." "0: Disable the device to response STALL,1: Set the device to respond STALL automatically" bitfld.long 0x5C 0. "CLRRDY,Clear Ready . When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1" group.long 0x90++0x3 line.long 0x0 "USBD_SE0,USB Device Drive SE0 Control Register" bitfld.long 0x0 0. "SE0,Drive Single Ended Zero In USB Bus . The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. ." "0: Normal operation,1: Force USB PHY transceiver to drive SE0" group.long 0xA0++0x3 line.long 0x0 "USBD_BIST,USB Buffer Self-test Register" bitfld.long 0x0 2. "BISTFAIL,BIST Fail. The BISTFAIL indicates if the BIST test fails or succeeds. If the BISTFAIL is low at the end the embedded SRAM pass the BIST test otherwise it is faulty. The BISTFAIL will be high once the BIST detects the error and remains high.." "0,1" bitfld.long 0x0 1. "FINISH,BIST Operation Finish. It indicates the end of the BIST operation. When BIST controller finishes all operations this bit will be set high.. This bit is a write clear field. Write 1 to this field clears the content and write 0 has no effect.." "0,1" newline bitfld.long 0x0 0. "BISTEN,BIST mode enable." "0: BIST is disabled or completed (automatically..,1: BIST is enabled; begin to perform BIST on.." tree.end endif tree "WDT (Watchdog Timer)" base ad:0x40004000 group.long 0x0++0x3 line.long 0x0 "WDT_CTL,Watchdog Timer Control Register" bitfld.long 0x0 8.--10. "TOUTSEL,Watchdog Timer Interval Select. These three bits select the timeout interval for the Watchdog timer a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset. . The WDT interrupt timeout is given by:. Where WDT_CLK is.." "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?,?,?,?,?,?" bitfld.long 0x0 7. "WDTEN,Watchdog Timer Enable." "0: Disable the WDT(Watchdog timer) (This action..,1: Enable the WDT(Watchdog timer)" newline bitfld.long 0x0 6. "INTEN,Watchdog Time-Out Interrupt Enable." "0: Disable the WDT time-out interrupt,1: Enable the WDT time-out interrupt" bitfld.long 0x0 5. "WKF,WDT Time-Out Wake-Up Flag. If WDT causes CPU wake up from sleep or power-down mode this bit will be set to high.. Note: This bit is cleared by writing 1 to it." "0: WDT does not cause CPU wake-up,1: CPU wakes up from sleep or power-down mode by.." newline bitfld.long 0x0 4. "WKEN,WDT Time-Out Wake-Up Function Control. If this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will generate a wake-up.." "0: Enable the Wakeup function that WDT timeout can..,1: Disable WDT Wakeup CPU function" bitfld.long 0x0 3. "IF,Watchdog Timer Interrupt Flag. If the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled then this bit indicates that a.." "0: Watchdog timer interrupt has not occurred,1: Watchdog timer interrupt has occurred" newline bitfld.long 0x0 2. "RSTF,Watchdog Timer Reset Flag. When the Watchdog timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is.." "0: Watchdog timer reset has not occurred,1: Watchdog timer reset has occurred" bitfld.long 0x0 1. "RSTEN,Watchdog Timer Reset Enable. Setting this bit will enable the Watchdog timer reset function.. Note: This function cannot work with XTL32-based clock source." "0: Disable Watchdog timer reset function,1: Enable Watchdog timer reset function" newline bitfld.long 0x0 0. "RSTCNT,Clear Watchdog Timer . Set this bit will clear the Watchdog timer. . Note: This bit will auto clear after few clock cycles" "0: Writing 0 to this bit has no effect,1: Reset the contents of the Watchdog timer" tree.end AUTOINDENT.OFF