; -------------------------------------------------------------------------------- ; @Title: MWCT101X On-Chip Peripherals ; @Props: Released ; @Author: RAB, PAK, DLI ; @Changelog: 2019-07-12 RAB ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: MWCT101XSFRM.pdf (Rev. 0, 2017-05) ; MWCT101XSFRM_2.pdf (Rev. 2, 2018-12) ; @Core: Cortex-M4 ; @Chip: MWCT1014S, MWCT1015S, MWCT1016S ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permwct101x.per 17736 2024-04-08 09:26:07Z kwisniewski $ sif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif config 16. 8. tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 8. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration Register" bitfld.word 0x00 7. " ASC[7] ,Bus slave connection to AXBS input port 7" "Absent,Present" bitfld.word 0x00 6. " [6] ,Bus slave connection to AXBS input port 6" "Absent,Present" bitfld.word 0x00 5. " [5] ,Bus slave connection to AXBS input port 5" "Absent,Present" bitfld.word 0x00 4. " [4] ,Bus slave connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x00 3. " [3] ,Bus slave connection to AXBS input port 3" "Absent,Present" bitfld.word 0x00 2. " [2] ,Bus slave connection to AXBS input port 2" "Absent,Present" bitfld.word 0x00 1. " [1] ,Bus slave connection to AXBS input port 1" "Absent,Present" bitfld.word 0x00 0. " [0] ,Bus slave connection to AXBS input port 0" "Absent,Present" line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration Register" bitfld.word 0x02 7. " AMC[7] ,Bus master connection to AXBS input port 7" "Absent,Present" bitfld.word 0x02 6. " [6] ,Bus master connection to AXBS input port 6" "Absent,Present" bitfld.word 0x02 5. " [5] ,Bus master connection to AXBS input port 5" "Absent,Present" bitfld.word 0x02 4. " [4] ,Bus master connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x02 3. " [3] ,Bus master connection to AXBS input port 3" "Absent,Present" bitfld.word 0x02 2. " [2] ,Bus master connection to AXBS input port 2" "Absent,Present" bitfld.word 0x02 1. " [1] ,Bus master connection to AXBS input port 1" "Absent,Present" bitfld.word 0x02 0. " [0] ,Bus master connection to AXBS input port 0" "Absent,Present" group.long 0x0C++0x07 line.long 0x00 "CPCR,Core Platform Control Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Fixed priority,Fixed priority" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected" bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Fixed priority,Fixed priority" newline bitfld.long 0x00 9. " CBRR ,Crossbar round-robin arbitration enable" "Fixed-priority,Round-robin" rbitfld.long 0x00 6. " PBRIDGE_IDLE ,Peripheral bridge idle" "Busy,Idle" rbitfld.long 0x00 4. " FMC_PF_IDLE ,Flash memory controller program flash idle" "Busy,Idle" rbitfld.long 0x00 3. " AXBS_HLTD ,AXBS halted" "Not halted,Halted" newline rbitfld.long 0x00 2. " AXBS_HLT_REQ ,AXBS halt request" "Not requested,Requested" rbitfld.long 0x00 0.--1. " HLT_FSM_ST ,AXBS halt state machine status" "Waiting for request,Waiting for platform idle,Platform stalled,?..." line.long 0x04 "ISCR,Interrupt Status And Control Register" bitfld.long 0x04 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" rbitfld.long 0x04 15. " FIDC ,FPU input denormal interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 12. " FIXC ,FPU inexact interrupt status" "No interrupt,Interrupt" newline rbitfld.long 0x04 11. " FUFC ,FPU underflow interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 10. " FOFC ,FPU overflow interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 9. " FDZC ,FPU divide-by-zero interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 8. " FIOC ,FPU invalid operation interrupt status" "No interrupt,Interrupt" group.long 0x30++0x03 line.long 0x00 "PID,Process ID Register" hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID and M1_PID for MPU" group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Wakeup" rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "No,Yes" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" if (((per.l(ad:0xE0080000+0x400))&0x10000)==0x10000) group.long 0x400++0x03 line.long 0x00 "LMDR0,Local Memory Descriptor Register0" rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid" rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..." newline rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..." bitfld.long 0x00 16. " LOCK ,Lock bit" "Read/write,Read only" rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,?..." sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 1. " CF0[1] ,Control field 0 - ECC enable read check" "Disabled,Enabled" rbitfld.long 0x00 0. " CF0[0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "LMDR0,Local Memory Descriptor Register0" rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid" rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..." newline rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..." bitfld.long 0x00 16. " LOCK ,Lock bit" "Read/write,Read only" rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,?..." sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled" endif newline bitfld.long 0x00 1. " CF0[1] ,Control field 0 - ECC enable read check" "Disabled,Enabled" bitfld.long 0x00 0. " CF0[0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled" endif if (((per.l(ad:0xE0080000+0x404))&0x10000)==0x10000) group.long 0x404++0x03 line.long 0x00 "LMDR1,Local Memory Descriptor Register1" rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid" rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..." newline rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..." bitfld.long 0x00 16. " LOCK ,Lock bit" "Read/write,Read only" rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,?..." sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 1. " CF0[1] ,Control field 0 - ECC enable read check" "Disabled,Enabled" rbitfld.long 0x00 0. " CF0[0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled" else group.long 0x404++0x03 line.long 0x00 "LMDR1,Local Memory Descriptor Register1" rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid" rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..." newline rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..." bitfld.long 0x00 16. " LOCK ,Lock bit" "Read/write,Read only" rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,?..." sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled" endif newline bitfld.long 0x00 1. " CF0[1] ,Control field 0 - ECC enable read check" "Disabled,Enabled" bitfld.long 0x00 0. " CF0[0] ,Control field 0 - ECC enable write generation" "Disabled,Enabled" endif group.long 0x408++0x03 line.long 0x00 "LMDR2,Local Memory Descriptor Register2" rbitfld.long 0x00 31. " V ,Local memory valid" "Invalid,Valid" rbitfld.long 0x00 28. " LMSZH ,LMEM size hole" "Disabled,Enabled" sif cpuis("S32MTV") rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" ",,,4KB,?..." textfld " " else rbitfld.long 0x00 24.--27. " LMSZ ,LMEM size" "No LMEM,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" endif rbitfld.long 0x00 20.--23. " WY ,Level 1 cache ways" "No cache,,2-way,,4-way,?..." newline rbitfld.long 0x00 17.--19. " DPW ,LMEM data path width" ",,32-bit,64-bit,?..." bitfld.long 0x00 16. " LOCK ,Lock bit" "Read/write,Read only" sif cpuis("S32MTV") rbitfld.long 0x00 13.--15. " MT ,Memory type" ",,PC Cache,?..." else rbitfld.long 0x00 13.--15. " MT ,Memory type" "SRAM_L,SRAM_U,?..." textfld " " endif bitfld.long 0x00 7. " CF1[3] ,Control field 1 - PC parity fault enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CF1[1] ,Control field 1 - PC parity miss enable" "Disabled,Enabled" group.long 0x480++0x03 line.long 0x00 "LMPECR,LMEM Parity And ECC Control Register" bitfld.long 0x00 20. " ECPR ,Enable cache parity reporting" "Disabled,Enabled" bitfld.long 0x00 8. " ER1BR ,Enable RAM ECC 1 bit reporting" "Disabled,Enabled" bitfld.long 0x00 0. " ERNCR ,Enable RAM ECC noncorrectable reporting" "Disabled,Enabled" group.long 0x488++0x03 line.long 0x00 "LMPEIR,LMEM Parity And ECC Interrupt Register" rbitfld.long 0x00 31. " V ,Valid bit" "Invalid,Valid" rbitfld.long 0x00 24.--28. " PEELOC ,Parity or ECC error location" "SRAM_L non-correctable ECC,SRAM_U non-correctable ECC,,,,,,,SRAM_L 1-bit correctable ECC,SRAM_U 1-bit correctable ECC,,,,,PC tag parity,PC data parity,?..." sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") eventfld.long 0x00 21. "PE[21] ,Parity error - PC data parity" "No error,Error" eventfld.long 0x00 20. " [20] ,Parity error - PC tag parity" "No error,Error" else eventfld.long 0x00 21. "PE[5] ,Parity error - PC data parity" "No error,Error" eventfld.long 0x00 20. " [4] ,Parity error - PC tag parity" "No error,Error" endif newline eventfld.long 0x00 9. " E1B[1] ,ECC 1-bit error - SRAM_U" "No error,Error" eventfld.long 0x00 8. " [0] ,ECC 1-bit error - SRAM_L" "No error,Error" eventfld.long 0x00 1. " ENC[1] ,ECC noncorrectable error - SRAM_U" "No error,Error" eventfld.long 0x00 0. " [0] ,ECC noncorrectable error - SRAM_L" "No error,Error" rgroup.long 0x490++0x07 line.long 0x00 "LMFAR,LMEM Fault Address Register" line.long 0x04 "LMFATR,LMEM Fault Attribute Register" bitfld.long 0x04 31. " OVR ,Overrun" "No overrun,Overrun" hexmask.long.byte 0x04 8.--15. 1. " PEFMST ,Parity/ECC fault master number" bitfld.long 0x04 7. " PEFW ,Parity/ECC fault write" "No error,Error" bitfld.long 0x04 4.--6. " PEFSIZE ,Parity/ECC fault master size" "8-bit,16-bit,32-bit,64-bit,?..." newline bitfld.long 0x04 3. " PEFPRT[3] ,Parity/ECC fault protection - cacheable" "Non-cacheable,Cacheable" bitfld.long 0x04 2. " [2] ,Parity/ECC fault protection - bufferable" "Non-bufferable,Bufferable" bitfld.long 0x04 1. " [1] ,Parity/ECC fault protection - mode" "User,Supervisor" bitfld.long 0x04 0. " [0] ,Parity/ECC fault protection - type" "I-fetch,Data" rgroup.long 0x4A0++0x07 line.long 0x00 "LMFDHR,LMEM Fault Data High Register" line.long 0x04 "LMFDLR,LMEM Fault Data Low Register" width 0x0B tree.end tree "SIM (System Integration Module)" base ad:0x40048000 width 10. group.long 0x04++0x03 line.long 0x00 "CHIPCTL,Chip Control Register" bitfld.long 0x00 21. " SRAML_RETEN ,SRAML retention" "Retained,Not retained" bitfld.long 0x00 20. " SRAMU_RETEN ,SRAMU retention" "Retained,Not retained" bitfld.long 0x00 19. " ADC_SUPPLYEN ,Enable for internal supply monitoring on ADC0 internal channel 0" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " ADC_SUPPLY ,Internal supplies monitored on ADC0 internal channel 0" "VDD,VDDA,VREFH,VDD_3V,Vdd_flash_3V,VDD_LV,?..." bitfld.long 0x00 13. " PDB_BB_SEL ,PDB back-to-back select" "PDB0 ch0 ADC0 COCO & PDB1 ch0 ADC1 COCO,PDB0/PDB1 ch0 & ADC0/ADC1 COCO" newline sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x00 12. " TRACECLK_SEL ,Debug trace clock select" "Core,?..." textfld " " else bitfld.long 0x00 12. " TRACECLK_SEL ,Debug trace clock select" "Core,Platform" endif bitfld.long 0x00 11. " CLKOUTEN ,CLKOUT enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " CLKOUTDIV ,CLKOUT divide ratio" "1,/2,/3,/4,/5,/6,/7,/8" newline sif cpuis("S32K148") bitfld.long 0x00 4.--7. " CLKOUTSEL ,CLKOUT select" "SCG CLKOUT,,SOSC DIV2 CLK,,SIRC DIV2 CLK,QSPI SFIF_CLK_HYP,FIRC DIV2 CLK,HCLK,SPLL DIV2 CLK,BUS_CLK,LPO128K_CLK,QSPI IPG_CLK,LPO_CLK,QSPI IPG_CLK_SFIF,RTC_CLK,QSPI IPG_CLK_2XSFIF" newline elif cpuis("MWCT1016S") bitfld.long 0x00 4.--7. " CLKOUTSEL ,CLKOUT select" "SCG CLKOUT,,SOSC DIV2 CLK,,SIRC DIV2 CLK,QSPI_SFIF_CLK_HYP_PREMUX,FIRC DIV2 CLK,HCLK,SPLL DIV2 CLK,BUS_CLK,LPO128K_CLK,QSPI module clock,LPO_CLK,QSPI_SFIF_CLK,RTC_CLK,QSPI_2xSFIF_CLK" newline else bitfld.long 0x00 4.--7. " CLKOUTSEL ,CLKOUT select" "SCG CLKOUT,,SOSC DIV2 CLK,,SIRC DIV2 CLK,,FIRC DIV2 CLK,HCLK,SPLL DIV2 CLK,BUS_CLK,LPO128K_CLK,,LPO_CLK,,RTC_CLK,?..." newline endif bitfld.long 0x00 3. " ADC_INTERLEAVE_EN[3] ,ADC interleave channel enable 3 - PTB14 to ADC1_SE9 and ADC0_SE9" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,ADC interleave channel enable 2 - PTB13 to ADC1_SE8 and ADC0_SE8" "Disabled,Enabled" newline sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x00 1. " [1] ,ADC interleave channel enable 1 - PTB1 to ADC0_SE5 and ADC1_SE15" "Disabled,Enabled" else bitfld.long 0x00 1. " [1] ,ADC interleave channel enable 1 - PTB1 to ADC0_SE4 and ADC1_SE15" "Disabled,Enabled" endif bitfld.long 0x00 0. " [0] ,ADC interleave channel enable 0 - PTB0 to ADC0_SE4 and ADC1_SE14" "Disabled,Enabled" group.long 0x0C++0x07 line.long 0x00 "FTMOPT0,FTM Option Register 0" bitfld.long 0x00 30.--31. " FTM3CLKSEL ,FTM3 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" bitfld.long 0x00 28.--29. " FTM2CLKSEL ,FTM2 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" bitfld.long 0x00 26.--27. " FTM1CLKSEL ,FTM1 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" newline bitfld.long 0x00 24.--25. " FTM0CLKSEL ,FTM0 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" newline sif cpuis("S32K148")||cpuis("MWCT1016S") bitfld.long 0x00 22.--23. " FTM7CLKSEL ,FTM7 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" bitfld.long 0x00 20.--21. " FTM6CLKSEL ,FTM6 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" newline endif sif cpuis("S32K146")||cpuis("S32K148")||cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 18.--19. " FTM5CLKSEL ,FTM5 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" bitfld.long 0x00 16.--17. " FTM4CLKSEL ,FTM4 external clock pin select" "TCLK0 pin,TCLK1 pin,TCLK2 pin,No clock input" newline endif bitfld.long 0x00 14. " FTM3FLT2SEL ,FTM3 fault 2 select" "FTM3_FLT2 pin,TRGMUX_FTM3 out" newline bitfld.long 0x00 13. " FTM3FLT1SEL ,FTM3 fault 1 select" "FTM3_FLT1 pin,TRGMUX_FTM3 out" bitfld.long 0x00 12. " FTM3FLT0SEL ,FTM3 fault 0 select" "FTM3_FLT0 pin,TRGMUX_FTM3 out" bitfld.long 0x00 10. " FTM2FLT2SEL ,FTM2 fault 2 select" "FTM2_FLT2 pin,TRGMUX_FTM2 out" newline bitfld.long 0x00 9. " FTM2FLT1SEL ,FTM2 fault 1 select" "FTM2_FLT1 pin,TRGMUX_FTM2 out" bitfld.long 0x00 8. " FTM2FLT0SEL ,FTM2 fault 0 select" "FTM2_FLT0 pin,TRGMUX_FTM2 out" bitfld.long 0x00 6. " FTM1FLT2SEL ,FTM1 fault 2 select" "FTM1_FLT2 pin,TRGMUX_FTM1 out" newline bitfld.long 0x00 5. " FTM1FLT1SEL ,FTM1 fault 1 select" "FTM1_FLT1 pin,TRGMUX_FTM1 out" bitfld.long 0x00 4. " FTM1FLT0SEL ,FTM1 fault 0 select" "FTM1_FLT0 pin,TRGMUX_FTM1 out" bitfld.long 0x00 2. " FTM0FLT2SEL ,FTM0 fault 2 select" "FTM0_FLT2 pin,TRGMUX_FTM0 out" newline bitfld.long 0x00 1. " FTM0FLT1SEL ,FTM0 fault 1 select" "FTM0_FLT1 pin,TRGMUX_FTM0 out" bitfld.long 0x00 0. " FTM0FLT0SEL ,FTM0 fault 0 select" "FTM0_FLT0 pin,TRGMUX_FTM0 out" line.long 0x04 "LPOCLKS,LPO Clock Select Register" bitfld.long 0x04 4.--5. " RTCCLKSEL ,32 kHz clock source select" "SOSCDIV1_CLK,32 kHz LPO_CLK,RTC_CLKIN clock,FIRCDIV1_CLK" bitfld.long 0x04 2.--3. " LPOCLKSEL ,LPO clock source select" "128 kHz LPO_CLK,No clock,32 kHz LPO_CLK/128 kHz LPO_CLK,1 kHz LPO_CLK/128 kHz LPO_CLK" bitfld.long 0x04 1. " LPO32KCLKEN ,32 kHz LPO clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " LPO1KCLKEN ,1 kHz LPO clock enable" "Disabled,Enabled" group.long 0x18++0x0B line.long 0x00 "ADCOPT,ADC Options Register" bitfld.long 0x00 12.--13. " ADC1PRETRGSEL ,ADC1 pretrigger source select" "PDB pretrigger,TRGMUX pretrigger,Software pretrigger,?..." bitfld.long 0x00 9.--11. " ADC1SWPRETRG ,ADC1 software pretrigger sources" "Disabled,,,,SW pretrigger 0,SW pretrigger 1,SW pretrigger 2,SW pretrigger 3" bitfld.long 0x00 8. " ADC1TRGSEL ,ADC1 trigger source select" "PDB output,TRGMUX output" newline bitfld.long 0x00 4.--5. " ADC0PRETRGSEL ,ADC0 pretrigger source select" "PDB pretrigger,TRGMUX pretrigger,Software pretrigger,?..." bitfld.long 0x00 1.--3. " ADC0SWPRETRG ,ADC0 software pretrigger sources" "Disabled,,,,SW pretrigger 0,SW pretrigger 1,SW pretrigger 2,SW pretrigger 3" bitfld.long 0x00 0. " ADC0TRGSEL ,ADC0 trigger source select" "PDB output,TRGMUX output" line.long 0x04 "FTMOPT1,FTM Option Register 1" bitfld.long 0x04 31. " FTM3_OUTSEL[7] ,FTM3 channel 7 FTM2_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 30. " [6] ,FTM3 channel 6 FTM2_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 29. " [5] ,FTM3 channel 5 FTM2_CH1 modulation select" "Disabled,Enabled" newline bitfld.long 0x04 28. " [4] ,FTM3 channel 4 FTM2_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 27. " [3] ,FTM3 channel 3 FTM2_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,FTM3 channel 2 FTM2_CH1 modulation select" "Disabled,Enabled" newline bitfld.long 0x04 25. " [1] ,FTM3 channel 1 FTM2_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,FTM3 channel 0 FTM2_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 23. " FTM0_OUTSEL[7] ,FTM0 channel 7 FTM1_CH1 modulation select" "Disabled,Enabled" newline bitfld.long 0x04 22. " [6] ,FTM0 channel 6 FTM1_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,FTM0 channel 5 FTM1_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,FTM0 channel 4 FTM1_CH1 modulation select" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,FTM0 channel 3 FTM1_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,FTM0 channel 2 FTM1_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 17. " [1] ,FTM0 channel 1 FTM1_CH1 modulation select" "Disabled,Enabled" newline bitfld.long 0x04 16. " [0] ,FTM0 channel 0 FTM1_CH1 modulation select" "Disabled,Enabled" bitfld.long 0x04 15. " FTMGLDOK ,FTM global load enable" "Disabled,Enabled" newline sif cpuis("S32K148")||cpuis("MWCT1016S") bitfld.long 0x04 14. " FTM7SYNCBIT ,FTM7 sync bit" "0,1" bitfld.long 0x04 13. " FTM6SYNCBIT ,FTM6 sync bit" "0,1" newline endif sif cpuis("S32K146")||cpuis("S32K148")||cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 12. " FTM5SYNCBIT ,FTM5 sync bit" "0,1" bitfld.long 0x04 11. " FTM4SYNCBIT ,FTM4 sync bit" "0,1" newline endif bitfld.long 0x04 8. " FTM2CH1SEL ,FTM2 channel 1 select" "FTM2_CH1 input,Xor(FTM2_ch0 FTM2_CH1 FTM1_CH1)" bitfld.long 0x04 6.--7. " FTM2CH0SEL ,FTM2 channel 0 select" "FTM2_CH0 input,CMP0 output,?..." newline bitfld.long 0x04 4.--5. " FTM1CH0SEL ,FTM1 channel 0 select" "FTM1_CH0 input,CMP0 output,?..." bitfld.long 0x04 3. " FTM3SYNCBIT ,FTM3 sync bit" "0,1" bitfld.long 0x04 2. " FTM2SYNCBIT ,FTM2 sync bit" "0,1" newline bitfld.long 0x04 1. " FTM1SYNCBIT ,FTM1 sync bit" "0,1" bitfld.long 0x04 0. " FTM0SYNCBIT ,FTM0 sync bit" "0,1" line.long 0x08 "MISCTRL0,Miscellaneous Control Register 0" bitfld.long 0x08 26. " QSPI_CLK_SEL ,QSPI clock select bit" "Disabled,Enabled" sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") bitfld.long 0x08 25. " RMII_CLK_SEL ,RMII CLK select bit" "FIRCDIV1_CLK,SOSCDIV1_CLK" bitfld.long 0x08 24. " RMII_CLK_OBE ,RMII CLK OBE bit" "Disabled,Enabled" endif newline sif cpuis("S32K148")||cpuis("MWCT1016S") bitfld.long 0x08 23. " FTM7_OBE_CTRL ,FTM7 OBE control bit" "Not retained,Retained" bitfld.long 0x08 22. " FTM6_OBE_CTRL ,FTM6 OBE control bit" "Not retained,Retained" newline endif sif cpuis("S32K146")||cpuis("S32K148")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x08 21. " FTM5_OBE_CTRL ,FTM5 OBE control bit" "Not retained,Retained" bitfld.long 0x08 20. " FTM4_OBE_CTRL ,FTM4 OBE control bit" "Not retained,Retained" newline endif bitfld.long 0x08 19. " FTM3_OBE_CTRL ,FTM3 OBE control bit" "Not retained,Retained" bitfld.long 0x08 18. " FTM2_OBE_CTRL ,FTM2 OBE control bit" "Not retained,Retained" bitfld.long 0x08 17. " FTM1_OBE_CTRL ,FTM1 OBE control bit" "Not retained,Retained" newline bitfld.long 0x08 16. " FTM0_OBE_CTRL ,FTM0 OBE control bit" "Not retained,Retained" bitfld.long 0x08 14. " FTM_GTB_SPLIT_EN ,FTM GTB split enable/disable bit" "Disabled,Enabled" sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") newline eventfld.long 0x08 10. " STOP2_MONITOR ,STOP2 monitor bit" "Aborted,Successful" eventfld.long 0x08 9. " STOP1_MONITOR ,STOP1 monitor bit" "Aborted,Successful" endif rgroup.long 0x24++0x03 line.long 0x00 "SDID,System Device Identification Register" sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") bitfld.long 0x00 28.--31. " GENERATION ,S32K product series generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 28.--31. " GENERATION ,WCT101xS product series generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif bitfld.long 0x00 24.--27. " SUBSERIES ,Subseries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " DERIVATE ,Derivate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("S32K148") bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,,,,128 KB,,160 KB,,192 KB,,,,256 KB" newline elif cpuis("MWCT1016S") bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,,,,,,,,192 KB,,,,256 KB" newline elif cpuis("S32K144")||cpuis("MWCT1014S") bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,,,,,,,,,,48 KB,,64 KB" newline elif (cpuis("S32K142")) bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,,,,,,,,16 KB,,24 KB,,32 KB" newline elif cpuis("MWCT1015S") bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" ",,,,,,,,,,,96 KB,,,,128 KB" newline else bitfld.long 0x00 16.--19. " RAMSIZE ,RAM size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") bitfld.long 0x00 8.--11. " PACKAGE ,Package" ",,48 LQFP,64 LQFP,100 LQFP,,144 LQFP,176 LQFP,100 MAP BGA,?..." else bitfld.long 0x00 8.--11. " PACKAGE ,Package" ",,,64 LQFP,100 LQFP,,,,100 MAPBGA,?..." textfld " " endif bitfld.long 0x00 7. " SECURITY ,Specifies the supported features of the chip" "Present,Not present" newline bitfld.long 0x00 6. " ISO_CAN-FD ,Specifies the ISO CAN-FD feature of the chip" "Not present,Present" bitfld.long 0x00 5. " FLEXIO ,Specifies the flexIO feature of the chip" "Not present,Present" bitfld.long 0x00 4. " QUADSPI ,Specifies the QuadSPI feature of the chip" "Not present,Present" sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") newline bitfld.long 0x00 3. " ENET ,Specifies the supported features of the chip" "Present,Not present" bitfld.long 0x00 1. " SAI ,Specifies the supported features of the chip" "Present,Not present" endif group.long 0x40++0x03 line.long 0x00 "PLATCGC,Platform Clock Gating Control Register" bitfld.long 0x00 4. " CGCEIM ,EIM clock gating control" "Disabled,Enabled" bitfld.long 0x00 3. " CGCERM ,ERM clock gating control" "Disabled,Enabled" bitfld.long 0x00 2. " CGCDMA ,DMA clock gating control" "Disabled,Enabled" newline bitfld.long 0x00 1. " CGCMPU ,MPU clock gating control" "Disabled,Enabled" bitfld.long 0x00 0. " CGCMSCM ,MSCM clock gating control" "Disabled,Enabled" rgroup.long 0x4C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" bitfld.long 0x00 16.--19. " EEERAMSIZE ,EEE SRAM size" ",,4 KB,2 KB,1 KB,512 bytes,256 bytes,128 bytes,64 bytes,32 bytes,,,,,,0 bytes" sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") bitfld.long 0x00 12.--15. " DEPART ,FlexNVM partition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 12.--15. " DEPART ,FlexNVM partition [Data flash/EEPROM backup]" "64/0,,,32/32,0/64,,,,0/64,,16/48,32/32,64/0,?..." endif rgroup.long 0x54++0x0F line.long 0x00 "UIDH,Unique Identification Register High" line.long 0x04 "UIDMH,Unique Identification Register Mid-High" line.long 0x08 "UIDML,Unique Identification Register Mid Low" line.long 0x0C "UIDL,Unique Identification Register Low" group.long 0x68++0x07 line.long 0x00 "CLKDIV4,System Clock Divider Register 4" bitfld.long 0x00 28. " TRACEDIVEN ,Debug trace divider control" "Disabled,Enabled" bitfld.long 0x00 1.--3. " TRACEDIV ,Trace clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " TRACEFRAC ,Trace clock divider fraction" "0,1" line.long 0x04 "MISCTRL1,Miscellaneous Control Register 1" bitfld.long 0x04 0. " SW_TRG ,Software trigger bit to TRGMUX" "0,1" width 0x0B tree.end tree "PORT (Port Control and Interrupts)" tree "PORT A" base ad:0x40049000 width 13. group.long 0x00++0x47 line.long 0x00 "PORTA_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA0,FTM2_CH1,LPI2C0_SCLS,FXIO_D2,FTM2_QD_PHA,LPUART0_CTS,TRGMUX_OUT3" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x04 "PORTA_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTA1,FTM1_CH1,LPI2C0_SDAS,FXIO_D3,FTM1_QD_PHA,LPUART0_RTS,TRGMUX_OUT0" newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x08 "PORTA_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE0,PTA2,FTM3_CH0,LPI2C0_SDA,EWM_OUT_b,FXIO_D4,LPUART0_RX,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x0C "PORTA_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC1_SE1,PTA3,FTM3_CH1,LPI2C0_SCL,EWM_IN,FXIO_D5,LPUART0_TX,?..." newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x10 "PORTA_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4,,,CMP0_OUT,EWM_OUT_b,,JTAG_TMS/SWD_DIO" newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x14 "PORTA_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTA5,,TCLK1,,,,RESET_b" newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x18 "PORTA_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA6,FTM0_FLT1,LPSPI1_PCS1,FTM5_CH5,,LPUART1_CTS,?..." else bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA6,FTM0_FLT1,LPSPI1_PCS1,,,LPUART1_CTS,?..." endif newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x1C "PORTA_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA7,FTM0_FLT2,FTM5_CH3,RTC_CLKIN,,LPUART1_RTS,?..." else bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA7,FTM0_FLT2,,RTC_CLKIN,,LPUART1_RTS,?..." endif newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x1C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x20 "PORTA_PCR8,Pin Control Register 8" eventfld.long 0x20 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x20 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTA8,LPUART2_RX,LPSPI2_SOUT,FXIO_D6,FTM3_FLT3,FTM4_FLT1,?..." else bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTA8,LPUART2_RX,LPSPI2_SOUT,FXIO_D6,FTM3_FLT3,?..." endif newline bitfld.long 0x20 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x20 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x20 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x20 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x24 "PORTA_PCR9,Pin Control Register 9" eventfld.long 0x24 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x24 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTA9,LPUART2_TX,LPSPI2_PCS0,FXIO_D7,FTM3_FLT2,FTM1_FLT3,FTM4_FLT0" else bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTA9,LPUART2_TX,LPSPI2_PCS0,FXIO_D7,FTM3_FLT2,FTM1_FLT3,?..." endif newline bitfld.long 0x24 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x24 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x24 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x24 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x28 "PORTA_PCR10,Pin Control Register 10" eventfld.long 0x28 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x28 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTA10,FTM1_CH4,,FXIO_D0,,,JTAG_TDO/noetm_TRACE_SWO" newline bitfld.long 0x28 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x28 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x28 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x28 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x2C "PORTA_PCR11,Pin Control Register 11" eventfld.long 0x2C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x2C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTA11,FTM1_CH5,,FXIO_D1,CMP0_RRT,SAI0_SYNC,?..." else bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTA11,FTM1_CH5,,FXIO_D1,CMP0_RRT,?..." endif newline bitfld.long 0x2C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x2C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x2C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x2C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x30 "PORTA_PCR12,Pin Control Register 12" eventfld.long 0x30 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x30 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTA12,FTM1_CH6,CAN1_RX,LPI2C1_SDAS,,FTM2_QD_PHB,SAI0_BCLK" else bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTA12,FTM1_CH6,CAN1_RX,,,FTM2_QD_PHB,?..." endif newline bitfld.long 0x30 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x30 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x30 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x30 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x34 "PORTA_PCR13,Pin Control Register 13" eventfld.long 0x34 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x34 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTA13,FTM1_CH7,CAN1_TX,LPI2C1_SCLS,,FTM2_QD_PHA,SAI0_D0" else bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTA13,FTM1_CH7,CAN1_TX,,,FTM2_QD_PHA,?..." endif newline bitfld.long 0x34 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x34 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x34 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x34 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x38 "PORTA_PCR14,Pin Control Register 14" eventfld.long 0x38 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x38 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x38 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x38 8.--10. " MUX ,Pin mux control" ",PTA14,FTM0_FLT0,FTM3_FLT1,EWM_IN,,FTM1_FLT0,SAI0_D3" else bitfld.long 0x38 8.--10. " MUX ,Pin mux control" ",PTA14,FTM0_FLT0,FTM3_FLT1,EWM_IN,,FTM1_FLT0,?..." endif newline bitfld.long 0x38 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x38 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x38 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x38 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x3C "PORTA_PCR15,Pin Control Register 15" eventfld.long 0x3C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x3C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x3C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "ADC1_SE12,PTA15,FTM1_CH2,LPSPI0_PCS3,LPSPI2_PCS3,FTM7_FLT0,?..." else bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "ADC1_SE12,PTA15,FTM1_CH2,LPSPI0_PCS3,LPSPI2_PCS3,?..." endif newline bitfld.long 0x3C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x3C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x3C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x3C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x40 "PORTA_PCR16,Pin Control Register 16" eventfld.long 0x40 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x40 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x40 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x40 8.--10. " MUX ,Pin mux control" "ADC1_SE13,PTA16,FTM1_CH3,LPSPI1_PCS2,?..." newline bitfld.long 0x40 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x40 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x40 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x40 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x44 "PORTA_PCR17,Pin Control Register 17" eventfld.long 0x44 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x44 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x44 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x44 8.--10. " MUX ,Pin mux control" ",PTA17,FTM0_CH6,FTM3_FLT0,EWM_OUT_b,FTM5_FLT0,?..." else bitfld.long 0x44 8.--10. " MUX ,Pin mux control" ",PTA17,FTM0_CH6,FTM3_FLT0,EWM_OUT_b,?..." endif newline bitfld.long 0x44 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x44 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x44 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x44 0. " PS ,Pull select" "Pulldown,Pullup" newline wgroup.long 0x80++0x0F line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable bit 15" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin write enable bit 14" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Global pin write enable bit 13" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin write enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 27. " [11] ,Global pin write enable bit 11" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin write enable bit 10" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin write enable bit 9" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin write enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin write enable bit 7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin write enable bit 6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin write enable bit 5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin write enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin write enable bit 3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin write enable bit 2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin write enable bit 1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin write enable bit 0" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" bitfld.long 0x04 17. " GPWE[17] ,Global pin write enable bit 17" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Global pin write enable bit 16" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" line.long 0x08 "PORTA_GICLR,Global Interrupt Control Low Register" hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x08 15. " GIWE[15] ,Global interrupt write enable bit 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Global interrupt write enable bit 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Global interrupt write enable bit 13" "Disabled,Enabled" newline bitfld.long 0x08 12. " [12] ,Global interrupt write enable bit 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Global interrupt write enable bit 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Global interrupt write enable bit 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Global interrupt write enable bit 9" "Disabled,Enabled" newline bitfld.long 0x08 8. " [8] ,Global interrupt write enable bit 8" "Disabled,Enabled" bitfld.long 0x08 7. " [7] ,Global interrupt write enable bit 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Global interrupt write enable bit 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Global interrupt write enable bit 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Global interrupt write enable bit 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Global interrupt write enable bit 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Global interrupt write enable bit 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Global interrupt write enable bit 1" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Global interrupt write enable bit 0" "Disabled,Enabled" line.long 0x0C "PORTA_GICHR,Global Interrupt Control High Register" hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x0C 1. " GIWE[17] ,Global interrupt write enable bit 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Global interrupt write enable bit 16" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 16. " ISF[17] ,Interrupt status flag bit 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Interrupt status flag bit 16" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Interrupt status flag bit 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Interrupt status flag bit 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt status flag bit 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Interrupt status flag bit 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Interrupt status flag bit 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt status flag bit 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Interrupt status flag bit 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt status flag bit 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Interrupt status flag bit 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Interrupt status flag bit 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt status flag bit 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt status flag bit 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Interrupt status flag bit 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt status flag bit 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt status flag bit 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Interrupt status flag bit 0" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTA_DFER,Digital Filter Enable Register" bitfld.long 0x00 16. " DFE[17] ,Digital filter enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter enable bit 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Digital filter enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Digital filter enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Digital filter enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Digital filter enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Digital filter enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter enable bit 0" "Disabled,Enabled" line.long 0x04 "PORTA_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,LPO" line.long 0x08 "PORTA_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT B" base ad:0x4004A000 width 13. group.long 0x00++0x47 line.long 0x00 "PORTB_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE4/ADC1_SE14,PTB0,LPUART0_RX,LPSPI0_PCS0,LPTMR0_ALT3,CAN0_RX,FTM4_CH6,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE4/ADC1_SE14,PTB0,LPUART0_RX,LPSPI0_PCS0,LPTMR0_ALT3,CAN0_RX,?..." endif newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x04 "PORTB_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/ADC1_SE15,PTB1,LPUART0_TX,LPSPI0_SOUT,TCLK0,CAN0_TX,FTM4_CH5,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/ADC1_SE15,PTB1,LPUART0_TX,LPSPI0_SOUT,TCLK0,CAN0_TX,?..." endif newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x08 "PORTB_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB2,FTM1_CH0,LPSPI0_SCK,FTM1_QD_PHB,,TRGMUX_IN3,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x0C "PORTB_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTB3,FTM1_CH1,LPSPI0_SIN,FTM1_QD_PHA,,TRGMUX_IN2,?..." newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x10 "PORTB_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTB4,FTM0_CH4,LPSPI0_SOUT,,MII_RMII_MDIO,TRGMUX_IN1,QSPI_B_IO0" else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTB4,FTM0_CH4,LPSPI0_SOUT,,,TRGMUX_IN1,?..." endif newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x14 "PORTB_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTB5,FTM0_CH5,LPSPI0_PCS1,LPSPI0_PCS0,CLKOUT,TRGMUX_IN0,MII_RMII_MDC" else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTB5,FTM0_CH5,LPSPI0_PCS1,LPSPI0_PCS0,CLKOUT,TRGMUX_IN0,?..." endif newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x18 "PORTB_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "XTAL,PTB6,LPI2C0_SDA,?..." newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x1C "PORTB_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "EXTAL,PTB7,LPI2C0_SCL,?..." newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x1C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x20 "PORTB_PCR8,Pin Control Register 8" eventfld.long 0x20 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x20 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTB8,FTM3_CH0,,SAI1_BCLK,?..." else bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTB8,FTM3_CH0,?..." endif newline bitfld.long 0x20 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x20 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x20 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x20 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x24 "PORTB_PCR9,Pin Control Register 9" eventfld.long 0x24 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x24 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTB9,FTM3_CH1,LPI2C0_SCLS,SAI1_D0,?..." else bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTB9,FTM3_CH1,LPI2C0_SCLS,?..." endif newline bitfld.long 0x24 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x24 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x24 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x24 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x28 "PORTB_PCR10,Pin Control Register 10" eventfld.long 0x28 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x28 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTB10,FTM3_CH2,LPI2C0_SDAS,SAI1_MCLK,?..." else bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTB10,FTM3_CH2,LPI2C0_SDAS,?..." endif newline bitfld.long 0x28 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x28 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x28 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x28 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x2C "PORTB_PCR11,Pin Control Register 11" eventfld.long 0x2C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x2C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTB11,FTM3_CH3,LPI2C0_HREQ,?..." newline bitfld.long 0x2C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x2C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x2C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x2C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x30 "PORTB_PCR12,Pin Control Register 12" eventfld.long 0x30 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x30 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "ADC1_SE7,PTB12,FTM0_CH0,FTM3_FLT2,CAN2_RX,FTM6_FLT1,?..." else bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "ADC1_SE7,PTB12,FTM0_CH0,FTM3_FLT2,CAN2_RX,?..." endif newline bitfld.long 0x30 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x30 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x30 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x30 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x34 "PORTB_PCR13,Pin Control Register 13" eventfld.long 0x34 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x34 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "ADC1_SE8/ADC0_SE8,PTB13,FTM0_CH1,FTM3_FLT1,CAN2_TX,FTM6_FLT0,?..." else bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "ADC1_SE8/ADC0_SE8,PTB13,FTM0_CH1,FTM3_FLT1,CAN2_TX,?..." endif newline bitfld.long 0x34 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x34 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x34 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x34 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x38 "PORTB_PCR14,Pin Control Register 14" eventfld.long 0x38 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x38 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x38 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "ADC1_SE9/ADC0_SE9,PTB14,FTM0_CH2,LPSPI1_SCK,?..." newline bitfld.long 0x38 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x38 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x38 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x38 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x3C "PORTB_PCR15,Pin Control Register 15" eventfld.long 0x3C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x3C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x3C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "ADC1_SE14,PTB15,FTM0_CH3,LPSPI1_SIN,?..." newline bitfld.long 0x3C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x3C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x3C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x3C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x40 "PORTB_PCR16,Pin Control Register 16" eventfld.long 0x40 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x40 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x40 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x40 8.--10. " MUX ,Pin mux control" "ADC1_SE15,PTB16,FTM0_CH4,LPSPI1_SOUT,?..." newline bitfld.long 0x40 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x40 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x40 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x40 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x44 "PORTB_PCR17,Pin Control Register 17" eventfld.long 0x44 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x44 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x44 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x44 8.--10. " MUX ,Pin mux control" ",PTB17,FTM0_CH5,LPSPI1_PCS3,FTM5_FLT1,?..." else bitfld.long 0x44 8.--10. " MUX ,Pin mux control" ",PTB17,FTM0_CH5,LPSPI1_PCS3,?..." endif newline bitfld.long 0x44 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x44 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x44 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x44 0. " PS ,Pull select" "Pulldown,Pullup" newline wgroup.long 0x80++0x0F line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable bit 15" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin write enable bit 14" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Global pin write enable bit 13" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin write enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 27. " [11] ,Global pin write enable bit 11" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin write enable bit 10" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin write enable bit 9" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin write enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin write enable bit 7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin write enable bit 6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin write enable bit 5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin write enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin write enable bit 3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin write enable bit 2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin write enable bit 1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin write enable bit 0" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register" bitfld.long 0x04 17. " GPWE[17] ,Global pin write enable bit 17" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Global pin write enable bit 16" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" line.long 0x08 "PORTB_GICLR,Global Interrupt Control Low Register" hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x08 15. " GIWE[15] ,Global interrupt write enable bit 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Global interrupt write enable bit 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Global interrupt write enable bit 13" "Disabled,Enabled" newline bitfld.long 0x08 12. " [12] ,Global interrupt write enable bit 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Global interrupt write enable bit 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Global interrupt write enable bit 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Global interrupt write enable bit 9" "Disabled,Enabled" newline bitfld.long 0x08 8. " [8] ,Global interrupt write enable bit 8" "Disabled,Enabled" bitfld.long 0x08 7. " [7] ,Global interrupt write enable bit 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Global interrupt write enable bit 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Global interrupt write enable bit 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Global interrupt write enable bit 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Global interrupt write enable bit 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Global interrupt write enable bit 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Global interrupt write enable bit 1" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Global interrupt write enable bit 0" "Disabled,Enabled" line.long 0x0C "PORTB_GICHR,Global Interrupt Control High Register" hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x0C 1. " GIWE[17] ,Global interrupt write enable bit 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Global interrupt write enable bit 16" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 16. " ISF[17] ,Interrupt status flag bit 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Interrupt status flag bit 16" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Interrupt status flag bit 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Interrupt status flag bit 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt status flag bit 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Interrupt status flag bit 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Interrupt status flag bit 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt status flag bit 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Interrupt status flag bit 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt status flag bit 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Interrupt status flag bit 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Interrupt status flag bit 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt status flag bit 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt status flag bit 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Interrupt status flag bit 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt status flag bit 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt status flag bit 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Interrupt status flag bit 0" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" bitfld.long 0x00 16. " DFE[17] ,Digital filter enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter enable bit 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Digital filter enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Digital filter enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Digital filter enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Digital filter enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Digital filter enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter enable bit 0" "Disabled,Enabled" line.long 0x04 "PORTB_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,LPO" line.long 0x08 "PORTB_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT C" base ad:0x4004B000 width 13. group.long 0x00++0x47 line.long 0x00 "PORTC_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTC0,FTM0_CH0,LPSPI2_SIN,MII_RMII_RXD[1],MII_RMII_RXD[0],FTM1_CH6,QSPI_B_RWDS" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTC0,FTM0_CH0,LPSPI2_SIN,,,FTM1_CH6,?..." endif newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x04 "PORTC_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTC1,FTM0_CH1,LPSPI2_SOUT,MII_RMII_RXD[1],MII_RMII_RXD[0],FTM1_CH7,QSPI_B_SCK" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTC1,FTM0_CH1,LPSPI2_SOUT,,,FTM1_CH7,?..." endif newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x08 "PORTC_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE10/CMP0_IN5,PTC2,FTM0_CH2,CAN0_RX,LPUART0_RX,MII_RMII_TXD[0],ETM_TRACE_CLKOUT,QSPI_A_IO3" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE10/CMP0_IN5,PTC2,FTM0_CH2,CAN0_RX,LPUART0_RX,?..." endif newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x0C "PORTC_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE11/CMP0_IN4,PTC3,FTM0_CH3,CAN0_TX,LPUART0_TX,MII_TX_ER,QSPI_A_CS,QSPI_B_IO3" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE11/CMP0_IN4,PTC3,FTM0_CH3,CAN0_TX,LPUART0_TX,?..." endif newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x10 "PORTC_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC4,FTM1_CH0,RTC_CLKOUT,,EWM_IN,FTM1_QD_PHB,JTAG_TCLK/SWD_CLK" newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x14 "PORTC_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC5,FTM2_CH0,RTC_CLKOUT,LPI2C1_HREQ,,FTM2_QD_PHB,JTAG_TDI" else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC5,FTM2_CH0,RTC_CLKOUT,,,FTM2_QD_PHB,JTAG_TDI" endif newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x18 "PORTC_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC1_SE4,PTC6,LPUART1_RX,CAN1_RX,FTM3_CH2,,FTM1_QD_PHB,?..." newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x1C "PORTC_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC1_SE5,PTC7,LPUART1_TX,CAN1_TX,FTM3_CH3,,FTM1_QD_PHA,?..." newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x1C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x20 "PORTC_PCR8,Pin Control Register 8" eventfld.long 0x20 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x20 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTC8,LPUART1_RX,FTM1_FLT0,FTM5_CH1,,LPUART0_CTS,?..." else bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTC8,LPUART1_RX,FTM1_FLT0,,,LPUART0_CTS,?..." endif newline bitfld.long 0x20 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x20 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x20 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x20 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x24 "PORTC_PCR9,Pin Control Register 9" eventfld.long 0x24 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x24 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTC9,LPUART1_TX,FTM1_FLT1,FTM5_CH0,,LPUART0_RTS,?..." else bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTC9,LPUART1_TX,FTM1_FLT1,,,LPUART0_RTS,?..." endif newline bitfld.long 0x24 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x24 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x24 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x24 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x28 "PORTC_PCR10,Pin Control Register 10" eventfld.long 0x28 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x28 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTC10,FTM3_CH4,,,,TRGMUX_IN11,?..." newline bitfld.long 0x28 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x28 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x28 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x28 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x2C "PORTC_PCR11,Pin Control Register 11" eventfld.long 0x2C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x2C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTC11,FTM3_CH5,FTM4_CH2,,,TRGMUX_IN10,?..." else bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTC11,FTM3_CH5,,,,TRGMUX_IN10,?..." endif newline bitfld.long 0x2C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x2C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x2C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x2C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x30 "PORTC_PCR12,Pin Control Register 12" eventfld.long 0x30 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x30 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTC12,FTM3_CH6,FTM2_CH6,LPUART2_CTS,?..." newline bitfld.long 0x30 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x30 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x30 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x30 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x34 "PORTC_PCR13,Pin Control Register 13" eventfld.long 0x34 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x34 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTC13,FTM3_CH7,FTM2_CH7,LPUART2_RTS,?..." newline bitfld.long 0x34 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x34 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x34 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x34 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x38 "PORTC_PCR14,Pin Control Register 14" eventfld.long 0x38 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x38 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x38 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTC14,FTM1_CH2,LPSPI2_PCS0,MII_COL,,TRGMUX_IN9,?..." else bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTC14,FTM1_CH2,LPSPI2_PCS0,,,TRGMUX_IN9,?..." endif newline bitfld.long 0x38 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x38 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x38 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x38 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x3C "PORTC_PCR15,Pin Control Register 15" eventfld.long 0x3C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x3C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x3C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTC15,FTM1_CH3,LPSPI2_SCK,MII_CRS,,TRGMUX_IN8,QSPI_B_CS" else bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTC15,FTM1_CH3,LPSPI2_SCK,,,TRGMUX_IN8,?..." endif newline bitfld.long 0x3C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x3C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x3C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x3C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x40 "PORTC_PCR16,Pin Control Register 16" eventfld.long 0x40 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x40 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x40 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x40 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC16,FTM1_FLT2,CAN2_RX,LPI2C1_SDAS,MII_RMII_RX_ER,,QSPI_B_IO7" else bitfld.long 0x40 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC16,FTM1_FLT2,CAN2_RX,?..." endif newline bitfld.long 0x40 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x40 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x40 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x40 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x44 "PORTC_PCR17,Pin Control Register 17" eventfld.long 0x44 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x44 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x44 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x44 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC17,FTM1_FLT3,CAN2_TX,LPI2C1_SCLS,MII_RMII_RX_DV,,QSPI_B_IO6" else bitfld.long 0x44 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC17,FTM1_FLT3,CAN2_TX,?..." endif newline bitfld.long 0x44 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x44 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x44 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x44 0. " PS ,Pull select" "Pulldown,Pullup" newline wgroup.long 0x80++0x0F line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable bit 15" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin write enable bit 14" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Global pin write enable bit 13" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin write enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 27. " [11] ,Global pin write enable bit 11" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin write enable bit 10" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin write enable bit 9" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin write enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin write enable bit 7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin write enable bit 6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin write enable bit 5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin write enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin write enable bit 3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin write enable bit 2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin write enable bit 1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin write enable bit 0" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register" bitfld.long 0x04 17. " GPWE[17] ,Global pin write enable bit 17" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Global pin write enable bit 16" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" line.long 0x08 "PORTC_GICLR,Global Interrupt Control Low Register" hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x08 15. " GIWE[15] ,Global interrupt write enable bit 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Global interrupt write enable bit 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Global interrupt write enable bit 13" "Disabled,Enabled" newline bitfld.long 0x08 12. " [12] ,Global interrupt write enable bit 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Global interrupt write enable bit 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Global interrupt write enable bit 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Global interrupt write enable bit 9" "Disabled,Enabled" newline bitfld.long 0x08 8. " [8] ,Global interrupt write enable bit 8" "Disabled,Enabled" bitfld.long 0x08 7. " [7] ,Global interrupt write enable bit 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Global interrupt write enable bit 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Global interrupt write enable bit 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Global interrupt write enable bit 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Global interrupt write enable bit 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Global interrupt write enable bit 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Global interrupt write enable bit 1" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Global interrupt write enable bit 0" "Disabled,Enabled" line.long 0x0C "PORTC_GICHR,Global Interrupt Control High Register" hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x0C 1. " GIWE[17] ,Global interrupt write enable bit 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Global interrupt write enable bit 16" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 16. " ISF[17] ,Interrupt status flag bit 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Interrupt status flag bit 16" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Interrupt status flag bit 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Interrupt status flag bit 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt status flag bit 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Interrupt status flag bit 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Interrupt status flag bit 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt status flag bit 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Interrupt status flag bit 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt status flag bit 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Interrupt status flag bit 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Interrupt status flag bit 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt status flag bit 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt status flag bit 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Interrupt status flag bit 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt status flag bit 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt status flag bit 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Interrupt status flag bit 0" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" bitfld.long 0x00 16. " DFE[17] ,Digital filter enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter enable bit 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Digital filter enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Digital filter enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Digital filter enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Digital filter enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Digital filter enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter enable bit 0" "Disabled,Enabled" line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,LPO" line.long 0x08 "PORTC_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT D" base ad:0x4004C000 width 13. group.long 0x00++0x47 line.long 0x00 "PORTD_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0,FTM0_CH2,LPSPI1_SCK,FTM2_CH0,ETM_TRACE_D0,FXIO_D0,TRGMUX_OUT1" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0,FTM0_CH2,LPSPI1_SCK,FTM2_CH0,,FXIO_D0,TRGMUX_OUT1" endif newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x04 "PORTD_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTD1,FTM0_CH3,LPSPI1_SIN,FTM2_CH1,SAI0_MCLK,FXIO_D1,TRGMUX_OUT2" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTD1,FTM0_CH3,LPSPI1_SIN,FTM2_CH1,,FXIO_D1,TRGMUX_OUT2" endif newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x08 "PORTD_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE2,PTD2,FTM3_CH4,LPSPI1_SOUT,FXIO_D4,FXIO_D6,TRGMUX_IN5,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x0C "PORTD_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC1_SE3,PTD3,FTM3_CH5,LPSPI1_PCS0,FXIO_D5,FXIO_D7,TRGMUX_IN4,NMI_b" newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x10 "PORTD_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC1_SE6,PTD4,FTM0_FLT3,FTM3_FLT3,?..." newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x14 "PORTD_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTD5,FTM2_CH3,LPTMR0_ALT2,FTM2_FLT1,MII_TXD3,TRGMUX_IN7,QSPI_B_IO2" else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTD5,FTM2_CH3,LPTMR0_ALT2,FTM2_FLT1,,TRGMUX_IN7,?..." endif newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x18 "PORTD_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN7,PTD6,LPUART2_RX,,FTM2_FLT2,MII_TXD2,,QSPI_B_IO1" else bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN7,PTD6,LPUART2_RX,,FTM2_FLT2,?..." endif newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x1C "PORTD_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN6,PTD7,LPUART2_TX,,FTM2_FLT3,MII_RMII_TXD[1],ETM_TRACE_D0,QSPI_A_IO1" else bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN6,PTD7,LPUART2_TX,,FTM2_FLT3,?..." endif newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x1C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x20 "PORTD_PCR8,Pin Control Register 8" eventfld.long 0x20 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x20 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTD8,LPI2C1_SDA,MII_RXD3,FTM2_FLT2,FXIO_D1,FTM1_CH4,QSPI_B_IO5" else bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTD8,,,FTM2_FLT2,FXIO_D1,FTM1_CH4,?..." endif newline bitfld.long 0x20 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x20 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x20 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x20 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x24 "PORTD_PCR9,Pin Control Register 9" eventfld.long 0x24 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x24 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTD9,LPI2C1_SCL,FXIO_D0,FTM2_FLT3,MII_RXD2,FTM1_CH5,QSPI_B_IO4" else bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTD9,,FXIO_D0,FTM2_FLT3,,FTM1_CH5,?..." endif newline bitfld.long 0x24 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x24 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x24 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x24 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x28 "PORTD_PCR10,Pin Control Register 10" eventfld.long 0x28 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x28 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTD10,FTM2_CH0,FTM2_QD_PHB,ETM_TRACE_D3,MII_RX_CLK,CLKOUT,QSPI_A_SCK" elif (cpu()=="MWCT1015S") bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTD10,FTM2_CH0,FTM2_QD_PHB,,,CLKOUT,?..." else bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTD10,FTM2_CH0,FTM2_QD_PHB,?..." endif newline bitfld.long 0x28 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x28 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x28 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x28 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x2C "PORTD_PCR11,Pin Control Register 11" eventfld.long 0x2C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x2C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTD11,FTM2_CH1,FTM2_QD_PHA,ETM_TRACE_D2,MII_RMII_TX_CLK,LPUART2_CTS,QSPI_A_IO0" else bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTD11,FTM2_CH1,FTM2_QD_PHA,,,LPUART2_CTS,?..." endif newline bitfld.long 0x2C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x2C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x2C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x2C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x30 "PORTD_PCR12,Pin Control Register 12" eventfld.long 0x30 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x30 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTD12,FTM2_CH2,LPI2C1_HREQ,ETM_TRACE_D1,MII_RMII_TX_EN,LPUART2_RTS,QSPI_A_IO2" else bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTD12,FTM2_CH2,,,,LPUART2_RTS,?..." endif newline bitfld.long 0x30 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x30 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x30 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x30 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x34 "PORTD_PCR13,Pin Control Register 13" eventfld.long 0x34 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x34 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTD13,FTM2_CH4,LPUART1_RX,,ENET_TMR1,,RTC_CLKOUT" else bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTD13,FTM2_CH4,LPUART1_RX,,,,RTC_CLKOUT" endif newline bitfld.long 0x34 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x34 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x34 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x34 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x38 "PORTD_PCR14,Pin Control Register 14" eventfld.long 0x38 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x38 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x38 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x38 8.--10. " MUX ,Pin mux control" ",PTD14,FTM2_CH5,LPUART1_TX,,ENET_TMR0,,CLKOUT" else bitfld.long 0x38 8.--10. " MUX ,Pin mux control" ",PTD14,FTM2_CH5,LPUART1_TX,,,,CLKOUT" endif newline bitfld.long 0x38 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x38 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x38 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x38 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x3C "PORTD_PCR15,Pin Control Register 15" eventfld.long 0x3C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x3C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x3C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" ",PTD15,FTM0_CH0,ETM_TRACE_D3,LPSPI0_SCK,ENET_TMR2,?..." else bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" ",PTD15,FTM0_CH0,,LPSPI0_SCK,?..." endif newline bitfld.long 0x3C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x3C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x3C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x3C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x40 "PORTD_PCR16,Pin Control Register 16" eventfld.long 0x40 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x40 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x40 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x40 8.--10. " MUX ,Pin mux control" ",PTD16,FTM0_CH1,ETM_TRACE_D2,LPSPI0_SIN,CMP0_RRT,ETM_TRACE_CLKOUT,?..." else bitfld.long 0x40 8.--10. " MUX ,Pin mux control" ",PTD16,FTM0_CH1,,LPSPI0_SIN,CMP0_RRT,?..." endif newline bitfld.long 0x40 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x40 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x40 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x40 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x44 "PORTD_PCR17,Pin Control Register 17" eventfld.long 0x44 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x44 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x44 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x44 8.--10. " MUX ,Pin mux control" ",PTD17,FTM0_FLT2,LPUART2_RX,FTM5_FLT1,?..." else bitfld.long 0x44 8.--10. " MUX ,Pin mux control" ",PTD17,FTM0_FLT2,LPUART2_RX,?..." endif newline bitfld.long 0x44 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x44 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x44 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x44 0. " PS ,Pull select" "Pulldown,Pullup" newline wgroup.long 0x80++0x0F line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable bit 15" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin write enable bit 14" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Global pin write enable bit 13" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin write enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 27. " [11] ,Global pin write enable bit 11" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin write enable bit 10" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin write enable bit 9" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin write enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin write enable bit 7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin write enable bit 6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin write enable bit 5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin write enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin write enable bit 3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin write enable bit 2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin write enable bit 1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin write enable bit 0" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTD_GPCHR,Global Pin Control High Register" bitfld.long 0x04 17. " GPWE[17] ,Global pin write enable bit 17" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Global pin write enable bit 16" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" line.long 0x08 "PORTD_GICLR,Global Interrupt Control Low Register" hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x08 15. " GIWE[15] ,Global interrupt write enable bit 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Global interrupt write enable bit 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Global interrupt write enable bit 13" "Disabled,Enabled" newline bitfld.long 0x08 12. " [12] ,Global interrupt write enable bit 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Global interrupt write enable bit 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Global interrupt write enable bit 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Global interrupt write enable bit 9" "Disabled,Enabled" newline bitfld.long 0x08 8. " [8] ,Global interrupt write enable bit 8" "Disabled,Enabled" bitfld.long 0x08 7. " [7] ,Global interrupt write enable bit 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Global interrupt write enable bit 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Global interrupt write enable bit 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Global interrupt write enable bit 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Global interrupt write enable bit 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Global interrupt write enable bit 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Global interrupt write enable bit 1" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Global interrupt write enable bit 0" "Disabled,Enabled" line.long 0x0C "PORTD_GICHR,Global Interrupt Control High Register" hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x0C 1. " GIWE[17] ,Global interrupt write enable bit 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Global interrupt write enable bit 16" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 16. " ISF[17] ,Interrupt status flag bit 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Interrupt status flag bit 16" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Interrupt status flag bit 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Interrupt status flag bit 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt status flag bit 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Interrupt status flag bit 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Interrupt status flag bit 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt status flag bit 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Interrupt status flag bit 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt status flag bit 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Interrupt status flag bit 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Interrupt status flag bit 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt status flag bit 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt status flag bit 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Interrupt status flag bit 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt status flag bit 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt status flag bit 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Interrupt status flag bit 0" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" bitfld.long 0x00 16. " DFE[17] ,Digital filter enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter enable bit 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Digital filter enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Digital filter enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Digital filter enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Digital filter enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Digital filter enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter enable bit 0" "Disabled,Enabled" line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,LPO" line.long 0x08 "PORTD_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT E" base ad:0x4004D000 width 13. group.long 0x00++0x43 line.long 0x00 "PORTE_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE0,LPSPI0_SCK,TCLK1,LPI2C1_SDA,LPSPI1_SOUT,FTM1_FLT2,SAI0_D2" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE0,LPSPI0_SCK,TCLK1,,LPSPI1_SOUT,FTM1_FLT2,?..." endif newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x04 "PORTE_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE1,LPSPI0_SIN,LPI2C0_HREQ,LPI2C1_SCL,LPSPI1_PCS0,FTM1_FLT1,SAI0_D1" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE1,LPSPI0_SIN,LPI2C0_HREQ,,LPSPI1_PCS0,FTM1_FLT1,?..." endif newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x08 "PORTE_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE10,PTE2,LPSPI0_SOUT,LPTMR0_ALT3,FTM3_CH6,,LPUART1_CTS,SAI1_SYNC" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE10,PTE2,LPSPI0_SOUT,LPTMR0_ALT3,FTM3_CH6,,LPUART1_CTS,?..." endif newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x0C "PORTE_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTE3,FTM0_FLT0,LPUART2_RTS,FTM2_FLT0,,TRGMUX_IN6,CMP0_OUT" newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x10 "PORTE_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTE4,ETM_TRACE_D1,FTM2_QD_PHB,FTM2_CH2,CAN0_RX,FXIO_D6,EWM_OUT_b" else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTE4,,FTM2_QD_PHB,FTM2_CH2,CAN0_RX,FXIO_D6,EWM_OUT_b" endif newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x14 "PORTE_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTE5,TCLK2,FTM2_QD_PHA,FTM2_CH3,CAN0_TX,FXIO_D7,EWM_IN" newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x18 "PORTE_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC1_SE11,PTE6,LPSPI0_PCS2,FTM7_FLT1,FTM3_CH7,,LPUART1_RTS,?..." else bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC1_SE11,PTE6,LPSPI0_PCS2,,FTM3_CH7,,LPUART1_RTS,?..." endif newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x1C "PORTE_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" ",PTE7,FTM0_CH7,FTM3_FLT0,?..." newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x1C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x20 "PORTE_PCR8,Pin Control Register 8" eventfld.long 0x20 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x20 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTE8,FTM0_CH6,,,MII_RMII_MDC,?..." else bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTE8,FTM0_CH6,?..." endif newline bitfld.long 0x20 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x20 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x20 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x20 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x24 "PORTE_PCR9,Pin Control Register 9" eventfld.long 0x24 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x24 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTE9,FTM0_CH7,LPUART2_CTS,,ENET_TMR3,?..." else bitfld.long 0x24 8.--10. " MUX ,Pin mux control" ",PTE9,FTM0_CH7,LPUART2_CTS,?..." endif newline bitfld.long 0x24 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x24 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x24 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x24 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x28 "PORTE_PCR10,Pin Control Register 10" eventfld.long 0x28 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x28 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x28 8.--10. " MUX ,Pin mux control" ",PTE10,CLKOUT,LPSPI2_PCS1,FTM2_CH4,,FXIO_D4,TRGMUX_OUT4" newline bitfld.long 0x28 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x28 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x28 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x28 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x2C "PORTE_PCR11,Pin Control Register 11" eventfld.long 0x2C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x2C 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" ",PTE11,LPSPI2_PCS0,LPTMR0_ALT1,FTM2_CH5,,FXIO_D5,TRGMUX_OUT5" newline bitfld.long 0x2C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x2C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x2C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x2C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x30 "PORTE_PCR12,Pin Control Register 12" eventfld.long 0x30 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x30 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S") bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTE12,FTM0_FLT3,LPUART2_TX,FTM5_FLT0,?..." else bitfld.long 0x30 8.--10. " MUX ,Pin mux control" ",PTE12,FTM0_FLT3,LPUART2_TX,?..." endif newline bitfld.long 0x30 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x30 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x30 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x30 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x34 "PORTE_PCR13,Pin Control Register 13" eventfld.long 0x34 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x34 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTE13,FTM4_CH5,LPSPI2_PCS2,FTM2_FLT0,?..." else bitfld.long 0x34 8.--10. " MUX ,Pin mux control" ",PTE13,,LPSPI2_PCS2,FTM2_FLT0,?..." endif newline bitfld.long 0x34 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x34 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x34 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x34 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x38 "PORTE_PCR14,Pin Control Register 14" eventfld.long 0x38 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x38 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x38 15. " LK ,Lock register" "Not locked,Locked" bitfld.long 0x38 8.--10. " MUX ,Pin mux control" ",PTE14,FTM0_FLT1,,FTM2_FLT1,?..." newline bitfld.long 0x38 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x38 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x38 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x38 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x3C "PORTE_PCR15,Pin Control Register 15" eventfld.long 0x3C 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x3C 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x3C 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" ",PTE15,LPUART1_CTS,LPSPI2_SCK,FTM2_CH6,FTM4_FLT1,FXIO_D2,TRGMUX_OUT6" else bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" ",PTE15,LPUART1_CTS,LPSPI2_SCK,FTM2_CH6,,FXIO_D2,TRGMUX_OUT6" endif newline bitfld.long 0x3C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x3C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x3C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x3C 0. " PS ,Pull select" "Pulldown,Pullup" line.long 0x40 "PORTE_PCR16,Pin Control Register 16" eventfld.long 0x40 24. " ISF ,Interrupt status flag" "No interrupt,Interrupt" bitfld.long 0x40 16.--19. " IRQC ,Interrupt configuration" "ISF disabled,ISF and DMA on rising edge,ISF and DMA on falling edge,ISF and DMA on either edge,,,,,ISF and interrupt when 0,ISF and interrupt on rising-edge,ISF and interrupt on falling-edge,ISF and interrupt on either-edge,ISF and interrupt when 1,?..." bitfld.long 0x40 15. " LK ,Lock register" "Not locked,Locked" sif (cpu()=="MWCT1016S")||(cpu()=="MWCT1015S") bitfld.long 0x40 8.--10. " MUX ,Pin mux control" ",PTE16,LPUART1_RTS,LPSPI2_SIN,FTM2_CH7,FTM4_FLT0,FXIO_D3,TRGMUX_OUT7" else bitfld.long 0x40 8.--10. " MUX ,Pin mux control" ",PTE16,LPUART1_RTS,LPSPI2_SIN,FTM2_CH7,,FXIO_D3,TRGMUX_OUT7" endif newline bitfld.long 0x40 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x40 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x40 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x40 0. " PS ,Pull select" "Pulldown,Pullup" newline wgroup.long 0x80++0x0F line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin write enable bit 15" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin write enable bit 14" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Global pin write enable bit 13" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin write enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 27. " [11] ,Global pin write enable bit 11" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin write enable bit 10" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin write enable bit 9" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin write enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin write enable bit 7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin write enable bit 6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin write enable bit 5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin write enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin write enable bit 3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin write enable bit 2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin write enable bit 1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin write enable bit 0" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTE_GPCHR,Global Pin Control High Register" bitfld.long 0x04 16. " GPWE[16] ,Global pin write enable bit 16" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" line.long 0x08 "PORTE_GICLR,Global Interrupt Control Low Register" hexmask.long.word 0x08 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x08 15. " GIWE[15] ,Global interrupt write enable bit 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Global interrupt write enable bit 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Global interrupt write enable bit 13" "Disabled,Enabled" newline bitfld.long 0x08 12. " [12] ,Global interrupt write enable bit 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Global interrupt write enable bit 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Global interrupt write enable bit 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Global interrupt write enable bit 9" "Disabled,Enabled" newline bitfld.long 0x08 8. " [8] ,Global interrupt write enable bit 8" "Disabled,Enabled" bitfld.long 0x08 7. " [7] ,Global interrupt write enable bit 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Global interrupt write enable bit 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Global interrupt write enable bit 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Global interrupt write enable bit 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Global interrupt write enable bit 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Global interrupt write enable bit 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Global interrupt write enable bit 1" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Global interrupt write enable bit 0" "Disabled,Enabled" line.long 0x0C "PORTE_GICHR,Global Interrupt Control High Register" hexmask.long.word 0x0C 16.--31. 1. " GIWD ,Global interrupt write data" bitfld.long 0x0C 0. " GIWE[16] ,Global interrupt write enable bit 16" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 16. " ISF[16] ,Interrupt status flag bit 16" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Interrupt status flag bit 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Interrupt status flag bit 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt status flag bit 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Interrupt status flag bit 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Interrupt status flag bit 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt status flag bit 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Interrupt status flag bit 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt status flag bit 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Interrupt status flag bit 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Interrupt status flag bit 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt status flag bit 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt status flag bit 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Interrupt status flag bit 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt status flag bit 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt status flag bit 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Interrupt status flag bit 0" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" bitfld.long 0x00 16. " DFE[16] ,Digital filter enable bit 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Digital filter enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Digital filter enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Digital filter enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Digital filter enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Digital filter enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter enable bit 0" "Disabled,Enabled" line.long 0x04 "PORTE_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,LPO" line.long 0x08 "PORTE_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.end tree "GPIO (General-Purpose Input/Output)" tree "Port A" base ad:0x400FF000 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PDO[31] ,Port data output 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output 29" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data output 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data output 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output 25" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port data output 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data output 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output 21" "Low,High" newline bitfld.long 0x00 20. " [20] ,Port data output 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port data output 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data output 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data output 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data output 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data output 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data output 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data output 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data output 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data output 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PTSO[31] ,Port set output 31" "Not changed,Changed" bitfld.long 0x00 30. " [30] ,Port set output 30" "Not changed,Changed" bitfld.long 0x00 29. " [29] ,Port set output 29" "Not changed,Changed" bitfld.long 0x00 28. " [28] ,Port set output 28" "Not changed,Changed" newline bitfld.long 0x00 27. " [27] ,Port set output 27" "Not changed,Changed" bitfld.long 0x00 26. " [26] ,Port set output 26" "Not changed,Changed" bitfld.long 0x00 25. " [25] ,Port set output 25" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port set output 24" "Not changed,Changed" bitfld.long 0x00 23. " [23] ,Port set output 23" "Not changed,Changed" bitfld.long 0x00 22. " [22] ,Port set output 22" "Not changed,Changed" bitfld.long 0x00 21. " [21] ,Port set output 21" "Not changed,Changed" newline bitfld.long 0x00 20. " [20] ,Port set output 20" "Not changed,Changed" bitfld.long 0x00 19. " [19] ,Port set output 19" "Not changed,Changed" bitfld.long 0x00 18. " [18] ,Port set output 18" "Not changed,Changed" newline endif bitfld.long 0x00 17. " [17] ,Port set output 17" "Not changed,Changed" bitfld.long 0x00 16. " [16] ,Port set output 16" "Not changed,Changed" bitfld.long 0x00 15. " [15] ,Port set output 15" "Not changed,Changed" bitfld.long 0x00 14. " [14] ,Port set output 14" "Not changed,Changed" newline bitfld.long 0x00 13. " [13] ,Port set output 13" "Not changed,Changed" bitfld.long 0x00 12. " [12] ,Port set output 12" "Not changed,Changed" bitfld.long 0x00 11. " [11] ,Port set output 11" "Not changed,Changed" bitfld.long 0x00 10. " [10] ,Port set output 10" "Not changed,Changed" newline bitfld.long 0x00 9. " [9] ,Port set output 9" "Not changed,Changed" bitfld.long 0x00 8. " [8] ,Port set output 8" "Not changed,Changed" bitfld.long 0x00 7. " [7] ,Port set output 7" "Not changed,Changed" bitfld.long 0x00 6. " [6] ,Port set output 6" "Not changed,Changed" newline bitfld.long 0x00 5. " [5] ,Port set output 5" "Not changed,Changed" bitfld.long 0x00 4. " [4] ,Port set output 4" "Not changed,Changed" bitfld.long 0x00 3. " [3] ,Port set output 3" "Not changed,Changed" bitfld.long 0x00 2. " [2] ,Port set output 2" "Not changed,Changed" newline bitfld.long 0x00 1. " [1] ,Port set output 1" "Not changed,Changed" bitfld.long 0x00 0. " [0] ,Port set output 0" "Not changed,Changed" line.long 0x04 "PCOR,Port Clear Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 31. " PTCO[31] ,Port clear output 31" "Not cleared,Cleared" bitfld.long 0x04 30. " [30] ,Port clear output 30" "Not cleared,Cleared" bitfld.long 0x04 29. " [29] ,Port clear output 29" "Not cleared,Cleared" bitfld.long 0x04 28. " [28] ,Port clear output 28" "Not cleared,Cleared" newline bitfld.long 0x04 27. " [27] ,Port clear output 27" "Not cleared,Cleared" bitfld.long 0x04 26. " [26] ,Port clear output 26" "Not cleared,Cleared" bitfld.long 0x04 25. " [25] ,Port clear output 25" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 24. " [24] ,Port clear output 24" "Not cleared,Cleared" bitfld.long 0x04 23. " [23] ,Port clear output 23" "Not cleared,Cleared" bitfld.long 0x04 22. " [22] ,Port clear output 22" "Not cleared,Cleared" bitfld.long 0x04 21. " [21] ,Port clear output 21" "Not cleared,Cleared" newline bitfld.long 0x04 20. " [20] ,Port clear output 20" "Not cleared,Cleared" bitfld.long 0x04 19. " [19] ,Port clear output 19" "Not cleared,Cleared" bitfld.long 0x04 18. " [18] ,Port clear output 18" "Not cleared,Cleared" newline endif bitfld.long 0x04 17. " [17] ,Port clear output 17" "Not cleared,Cleared" bitfld.long 0x04 16. " [16] ,Port clear output 16" "Not cleared,Cleared" bitfld.long 0x04 15. " [15] ,Port clear output 15" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Port clear output 14" "Not cleared,Cleared" newline bitfld.long 0x04 13. " [13] ,Port clear output 13" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Port clear output 12" "Not cleared,Cleared" bitfld.long 0x04 11. " [11] ,Port clear output 11" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Port clear output 10" "Not cleared,Cleared" newline bitfld.long 0x04 9. " [9] ,Port clear output 9" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Port clear output 8" "Not cleared,Cleared" bitfld.long 0x04 7. " [7] ,Port clear output 7" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Port clear output 6" "Not cleared,Cleared" newline bitfld.long 0x04 5. " [5] ,Port clear output 5" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Port clear output 4" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Port clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Port clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Port clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Port clear output 0" "Not cleared,Cleared" line.long 0x08 "PTOR,Port Toggle Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 31. " PTTO[31] ,Port toggle output 31" "Not inverted,Inverted" bitfld.long 0x08 30. " [30] ,Port toggle output 30" "Not inverted,Inverted" bitfld.long 0x08 29. " [29] ,Port toggle output 29" "Not inverted,Inverted" bitfld.long 0x08 28. " [28] ,Port toggle output 28" "Not inverted,Inverted" newline bitfld.long 0x08 27. " [27] ,Port toggle output 27" "Not inverted,Inverted" bitfld.long 0x08 26. " [26] ,Port toggle output 26" "Not inverted,Inverted" bitfld.long 0x08 25. " [25] ,Port toggle output 25" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 24. " [24] ,Port toggle output 24" "Not inverted,Inverted" bitfld.long 0x08 23. " [23] ,Port toggle output 23" "Not inverted,Inverted" bitfld.long 0x08 22. " [22] ,Port toggle output 22" "Not inverted,Inverted" bitfld.long 0x08 21. " [21] ,Port toggle output 21" "Not inverted,Inverted" newline bitfld.long 0x08 20. " [20] ,Port toggle output 20" "Not inverted,Inverted" bitfld.long 0x08 19. " [19] ,Port toggle output 19" "Not inverted,Inverted" bitfld.long 0x08 18. " [18] ,Port toggle output 18" "Not inverted,Inverted" newline endif bitfld.long 0x08 17. " [17] ,Port toggle output 17" "Not inverted,Inverted" bitfld.long 0x08 16. " [16] ,Port toggle output 16" "Not inverted,Inverted" bitfld.long 0x08 15. " [15] ,Port toggle output 15" "Not inverted,Inverted" bitfld.long 0x08 14. " [14] ,Port toggle output 14" "Not inverted,Inverted" newline bitfld.long 0x08 13. " [13] ,Port toggle output 13" "Not inverted,Inverted" bitfld.long 0x08 12. " [12] ,Port toggle output 12" "Not inverted,Inverted" bitfld.long 0x08 11. " [11] ,Port toggle output 11" "Not inverted,Inverted" bitfld.long 0x08 10. " [10] ,Port toggle output 10" "Not inverted,Inverted" newline bitfld.long 0x08 9. " [9] ,Port toggle output 9" "Not inverted,Inverted" bitfld.long 0x08 8. " [8] ,Port toggle output 8" "Not inverted,Inverted" bitfld.long 0x08 7. " [7] ,Port toggle output 7" "Not inverted,Inverted" bitfld.long 0x08 6. " [6] ,Port toggle output 6" "Not inverted,Inverted" newline bitfld.long 0x08 5. " [5] ,Port toggle output 5" "Not inverted,Inverted" bitfld.long 0x08 4. " [4] ,Port toggle output 4" "Not inverted,Inverted" bitfld.long 0x08 3. " [3] ,Port toggle output 3" "Not inverted,Inverted" bitfld.long 0x08 2. " [2] ,Port toggle output 2" "Not inverted,Inverted" newline bitfld.long 0x08 1. " [1] ,Port toggle output 1" "Not inverted,Inverted" bitfld.long 0x08 0. " [0] ,Port toggle output 0" "Not inverted,Inverted" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PDI[31] ,Port data input 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data input 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data input 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data input 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data input 25" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port data input 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data input 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data input 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data input 21" "Low,High" newline bitfld.long 0x00 20. " [20] ,Port data input 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port data input 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data input 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data input 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data input 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data input 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data input 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data input 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data input 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data input 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input 0" "Low,High" group.long 0x14++0x07 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PDD[31] ,Port data direction 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction 28" "Input,Output" newline bitfld.long 0x00 27. " [27] ,Port data direction 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction 25" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port data direction 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Port data direction 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction 21" "Input,Output" newline bitfld.long 0x00 20. " [20] ,Port data direction 20" "Input,Output" bitfld.long 0x00 19. " [19] ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction 18" "Input,Output" newline endif bitfld.long 0x00 17. " [17] ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Port data direction 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction 10" "Input,Output" newline bitfld.long 0x00 9. " [9] ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction 8" "Input,Output" bitfld.long 0x00 7. " [7] ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction 6" "Input,Output" newline bitfld.long 0x00 5. " [5] ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction 0" "Input,Output" line.long 0x04 "PIDR,Port Input Disable Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 31. " PID[31] ,Port input disable 31" "No,Yes" bitfld.long 0x04 30. " [30] ,Port input disable 30" "No,Yes" bitfld.long 0x04 29. " [29] ,Port input disable 29" "No,Yes" bitfld.long 0x04 28. " [28] ,Port input disable 28" "No,Yes" newline bitfld.long 0x04 27. " [27] ,Port input disable 27" "No,Yes" bitfld.long 0x04 26. " [26] ,Port input disable 26" "No,Yes" bitfld.long 0x04 25. " [25] ,Port input disable 25" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 24. " [24] ,Port input disable 24" "No,Yes" bitfld.long 0x04 23. " [23] ,Port input disable 23" "No,Yes" bitfld.long 0x04 22. " [22] ,Port input disable 22" "No,Yes" bitfld.long 0x04 21. " [21] ,Port input disable 21" "No,Yes" newline bitfld.long 0x04 20. " [20] ,Port input disable 20" "No,Yes" bitfld.long 0x04 19. " [19] ,Port input disable 19" "No,Yes" bitfld.long 0x04 18. " [18] ,Port input disable 18" "No,Yes" newline endif bitfld.long 0x04 17. " [17] ,Port input disable 17" "No,Yes" bitfld.long 0x04 16. " [16] ,Port input disable 16" "No,Yes" bitfld.long 0x04 15. " [15] ,Port input disable 15" "No,Yes" bitfld.long 0x04 14. " [14] ,Port input disable 14" "No,Yes" newline bitfld.long 0x04 13. " [13] ,Port input disable 13" "No,Yes" bitfld.long 0x04 12. " [12] ,Port input disable 12" "No,Yes" bitfld.long 0x04 11. " [11] ,Port input disable 11" "No,Yes" bitfld.long 0x04 10. " [10] ,Port input disable 10" "No,Yes" newline bitfld.long 0x04 9. " [9] ,Port input disable 9" "No,Yes" bitfld.long 0x04 8. " [8] ,Port input disable 8" "No,Yes" bitfld.long 0x04 7. " [7] ,Port input disable 7" "No,Yes" bitfld.long 0x04 6. " [6] ,Port input disable 6" "No,Yes" newline bitfld.long 0x04 5. " [5] ,Port input disable 5" "No,Yes" bitfld.long 0x04 4. " [4] ,Port input disable 4" "No,Yes" bitfld.long 0x04 3. " [3] ,Port input disable 3" "No,Yes" bitfld.long 0x04 2. " [2] ,Port input disable 2" "No,Yes" newline bitfld.long 0x04 1. " [1] ,Port input disable 1" "No,Yes" bitfld.long 0x04 0. " [0] ,Port input disable 0" "No,Yes" width 0x0B tree.end tree "Port B" base ad:0x400FF040 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PDO[31] ,Port data output 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output 30" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 29. " [29] ,Port data output 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data output 27" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data output 26" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port data output 25" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port data output 24" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port data output 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output 20" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 19. " [19] ,Port data output 19" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 18. " [18] ,Port data output 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data output 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data output 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data output 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data output 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data output 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data output 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data output 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PTSO[31] ,Port set output 31" "Not changed,Changed" bitfld.long 0x00 30. " [30] ,Port set output 30" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 29. " [29] ,Port set output 29" "Not changed,Changed" bitfld.long 0x00 28. " [28] ,Port set output 28" "Not changed,Changed" bitfld.long 0x00 27. " [27] ,Port set output 27" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port set output 26" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port set output 25" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port set output 24" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port set output 23" "Not changed,Changed" bitfld.long 0x00 22. " [22] ,Port set output 22" "Not changed,Changed" bitfld.long 0x00 21. " [21] ,Port set output 21" "Not changed,Changed" bitfld.long 0x00 20. " [20] ,Port set output 20" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 19. " [19] ,Port set output 19" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 18. " [18] ,Port set output 18" "Not changed,Changed" newline endif bitfld.long 0x00 17. " [17] ,Port set output 17" "Not changed,Changed" bitfld.long 0x00 16. " [16] ,Port set output 16" "Not changed,Changed" bitfld.long 0x00 15. " [15] ,Port set output 15" "Not changed,Changed" bitfld.long 0x00 14. " [14] ,Port set output 14" "Not changed,Changed" newline bitfld.long 0x00 13. " [13] ,Port set output 13" "Not changed,Changed" bitfld.long 0x00 12. " [12] ,Port set output 12" "Not changed,Changed" bitfld.long 0x00 11. " [11] ,Port set output 11" "Not changed,Changed" bitfld.long 0x00 10. " [10] ,Port set output 10" "Not changed,Changed" newline bitfld.long 0x00 9. " [9] ,Port set output 9" "Not changed,Changed" bitfld.long 0x00 8. " [8] ,Port set output 8" "Not changed,Changed" bitfld.long 0x00 7. " [7] ,Port set output 7" "Not changed,Changed" bitfld.long 0x00 6. " [6] ,Port set output 6" "Not changed,Changed" newline bitfld.long 0x00 5. " [5] ,Port set output 5" "Not changed,Changed" bitfld.long 0x00 4. " [4] ,Port set output 4" "Not changed,Changed" bitfld.long 0x00 3. " [3] ,Port set output 3" "Not changed,Changed" bitfld.long 0x00 2. " [2] ,Port set output 2" "Not changed,Changed" newline bitfld.long 0x00 1. " [1] ,Port set outpu 1" "Not changed,Changed" bitfld.long 0x00 0. " [0] ,Port set output 0" "Not changed,Changed" line.long 0x04 "PCOR,Port Clear Output Register" sif cpuis("MWCT1016S") bitfld.long 0x04 31. " PTCO[31] ,Port clear output 31" "Not cleared,Cleared" bitfld.long 0x04 30. " [30] ,Port clear output 30" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 29. " [29] ,Port clear output 29" "Not cleared,Cleared" bitfld.long 0x04 28. " [28] ,Port clear output 28" "Not cleared,Cleared" bitfld.long 0x04 27. " [27] ,Port clear output 27" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 26. " [26] ,Port clear output 26" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 25. " [25] ,Port clear output 25" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 24. " [24] ,Port clear output 24" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 23. " [23] ,Port clear output 23" "Not cleared,Cleared" bitfld.long 0x04 22. " [22] ,Port clear output 22" "Not cleared,Cleared" bitfld.long 0x04 21. " [21] ,Port clear output 21" "Not cleared,Cleared" bitfld.long 0x04 20. " [20] ,Port clear output 20" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 19. " [19] ,Port clear output 19" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 18. " [18] ,Port clear output 18" "Not cleared,Cleared" newline endif bitfld.long 0x04 17. " [17] ,Port clear output 17" "Not cleared,Cleared" bitfld.long 0x04 16. " [16] ,Port clear output 16" "Not cleared,Cleared" bitfld.long 0x04 15. " [15] ,Port clear output 15" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Port clear output 14" "Not cleared,Cleared" newline bitfld.long 0x04 13. " [13] ,Port clear output 13" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Port clear output 12" "Not cleared,Cleared" bitfld.long 0x04 11. " [11] ,Port clear output 11" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Port clear output 10" "Not cleared,Cleared" newline bitfld.long 0x04 9. " [9] ,Port clear output 9" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Port clear output 8" "Not cleared,Cleared" bitfld.long 0x04 7. " [7] ,Port clear output 7" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Port clear output 6" "Not cleared,Cleared" newline bitfld.long 0x04 5. " [5] ,Port clear output 5" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Port clear output 4" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Port clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Port clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Port clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Port clear output 0" "Not cleared,Cleared" line.long 0x08 "PTOR,Port Toggle Output Register" sif cpuis("MWCT1016S") bitfld.long 0x08 31. " PTTO[31] ,Port toggle output 31" "Not inverted,Inverted" bitfld.long 0x08 30. " [30] ,Port toggle output 30" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 29. " [29] ,Port toggle output 29" "Not inverted,Inverted" bitfld.long 0x08 28. " [28] ,Port toggle output 28" "Not inverted,Inverted" bitfld.long 0x08 27. " [27] ,Port toggle output 27" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 26. " [26] ,Port toggle output 26" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 25. " [25] ,Port toggle output 25" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 24. " [24] ,Port toggle output 24" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 23. " [23] ,Port toggle output 23" "Not inverted,Inverted" bitfld.long 0x08 22. " [22] ,Port toggle output 22" "Not inverted,Inverted" bitfld.long 0x08 21. " [21] ,Port toggle output 21" "Not inverted,Inverted" bitfld.long 0x08 20. " [20] ,Port toggle output 20" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 19. " [19] ,Port toggle output 19" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 18. " [18] ,Port toggle output 18" "Not inverted,Inverted" newline endif bitfld.long 0x08 17. " [17] ,Port toggle output 17" "Not inverted,Inverted" bitfld.long 0x08 16. " [16] ,Port toggle output 16" "Not inverted,Inverted" bitfld.long 0x08 15. " [15] ,Port toggle output 15" "Not inverted,Inverted" bitfld.long 0x08 14. " [14] ,Port toggle output 14" "Not inverted,Inverted" newline bitfld.long 0x08 13. " [13] ,Port toggle output 13" "Not inverted,Inverted" bitfld.long 0x08 12. " [12] ,Port toggle output 12" "Not inverted,Inverted" bitfld.long 0x08 11. " [11] ,Port toggle output 11" "Not inverted,Inverted" bitfld.long 0x08 10. " [10] ,Port toggle output 10" "Not inverted,Inverted" newline bitfld.long 0x08 9. " [9] ,Port toggle output 9" "Not inverted,Inverted" bitfld.long 0x08 8. " [8] ,Port toggle output 8" "Not inverted,Inverted" bitfld.long 0x08 7. " [7] ,Port toggle output 7" "Not inverted,Inverted" bitfld.long 0x08 6. " [6] ,Port toggle output 6" "Not inverted,Inverted" newline bitfld.long 0x08 5. " [5] ,Port toggle output 5" "Not inverted,Inverted" bitfld.long 0x08 4. " [4] ,Port toggle output 4" "Not inverted,Inverted" bitfld.long 0x08 3. " [3] ,Port toggle output 3" "Not inverted,Inverted" bitfld.long 0x08 2. " [2] ,Port toggle output 2" "Not inverted,Inverted" newline bitfld.long 0x08 1. " [1] ,Port toggle output 1" "Not inverted,Inverted" bitfld.long 0x08 0. " [0] ,Port toggle output 0" "Not inverted,Inverted" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PDI[31] ,Port data input 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data input 30" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 29. " [29] ,Port data input 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data input 27" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data input 26" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port data input 25" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port data input 24" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port data input 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data input 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data input 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data input 20" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 19. " [19] ,Port data input 19" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 18. " [18] ,Port data input 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data input 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data input 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data input 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data input 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data input 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data input 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data input 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input 0" "Low,High" group.long 0x14++0x07 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PDD[31] ,Port data direction 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction 30" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 29. " [29] ,Port data direction 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Port data direction 27" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data direction 26" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port data direction 25" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 24. " [24] ,Port data direction 24" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port data direction 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction 20" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 19. " [19] ,Port data direction 19" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 18. " [18] ,Port data direction 18" "Input,Output" newline endif bitfld.long 0x00 17. " [17] ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Port data direction 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction 10" "Input,Output" newline bitfld.long 0x00 9. " [9] ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction 8" "Input,Output" bitfld.long 0x00 7. " [7] ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction 6" "Input,Output" newline bitfld.long 0x00 5. " [5] ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction 0" "Input,Output" line.long 0x04 "PIDR,Port Input Disable Register" sif cpuis("MWCT1016S") bitfld.long 0x04 31. " PID[31] ,Port input disable 31" "No,Yes" bitfld.long 0x04 30. " [30] ,Port input disable 30" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 29. " [29] ,Port input disable 29" "No,Yes" bitfld.long 0x04 28. " [28] ,Port input disable 28" "No,Yes" bitfld.long 0x04 27. " [27] ,Port input disable 27" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 26. " [26] ,Port input disable 26" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 25. " [25] ,Port input disable 25" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 24. " [24] ,Port input disable 24" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 23. " [23] ,Port input disable 23" "No,Yes" bitfld.long 0x04 22. " [22] ,Port input disable 22" "No,Yes" bitfld.long 0x04 21. " [21] ,Port input disable 21" "No,Yes" bitfld.long 0x04 20. " [20] ,Port input disable 20" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 19. " [19] ,Port input disable 19" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 18. " [18] ,Port input disable 18" "No,Yes" newline endif bitfld.long 0x04 17. " [17] ,Port input disable 17" "No,Yes" bitfld.long 0x04 16. " [16] ,Port input disable 16" "No,Yes" bitfld.long 0x04 15. " [15] ,Port input disable 15" "No,Yes" bitfld.long 0x04 14. " [14] ,Port input disable 14" "No,Yes" newline bitfld.long 0x04 13. " [13] ,Port input disable 13" "No,Yes" bitfld.long 0x04 12. " [12] ,Port input disable 12" "No,Yes" bitfld.long 0x04 11. " [11] ,Port input disable 11" "No,Yes" bitfld.long 0x04 10. " [10] ,Port input disable 10" "No,Yes" newline bitfld.long 0x04 9. " [9] ,Port input disable 9" "No,Yes" bitfld.long 0x04 8. " [8] ,Port input disable 8" "No,Yes" bitfld.long 0x04 7. " [7] ,Port input disable 7" "No,Yes" bitfld.long 0x04 6. " [6] ,Port input disable 6" "No,Yes" newline bitfld.long 0x04 5. " [5] ,Port input disable 5" "No,Yes" bitfld.long 0x04 4. " [4] ,Port input disable 4" "No,Yes" bitfld.long 0x04 3. " [3] ,Port input disable 3" "No,Yes" bitfld.long 0x04 2. " [2] ,Port input disable 2" "No,Yes" newline bitfld.long 0x04 1. " [1] ,Port input disable 1" "No,Yes" bitfld.long 0x04 0. " [0] ,Port input disable 0" "No,Yes" width 0x0B tree.end tree "Port C" base ad:0x400FF080 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PDO[31] ,Port data output 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data output 27" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data output 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data output 24" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port data output 23" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 22. " [22] ,Port data output 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output 20" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port data output 19" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port data output 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data output 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data output 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data output 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data output 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data output 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data output 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data output 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PTSO[31] ,Port set output 31" "Not changed,Changed" bitfld.long 0x00 30. " [30] ,Port set output 30" "Not changed,Changed" bitfld.long 0x00 29. " [29] ,Port set output 29" "Not changed,Changed" bitfld.long 0x00 28. " [28] ,Port set output 28" "Not changed,Changed" newline bitfld.long 0x00 27. " [27] ,Port set output 27" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port set output 26" "Not changed,Changed" bitfld.long 0x00 25. " [25] ,Port set output 25" "Not changed,Changed" bitfld.long 0x00 24. " [24] ,Port set output 24" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port set output 23" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 22. " [22] ,Port set output 22" "Not changed,Changed" bitfld.long 0x00 21. " [21] ,Port set output 21" "Not changed,Changed" bitfld.long 0x00 20. " [20] ,Port set output 20" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port set output 19" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port set output 18" "Not changed,Changed" newline endif bitfld.long 0x00 17. " [17] ,Port set output 17" "Not changed,Changed" bitfld.long 0x00 16. " [16] ,Port set output 16" "Not changed,Changed" bitfld.long 0x00 15. " [15] ,Port set output 15" "Not changed,Changed" bitfld.long 0x00 14. " [14] ,Port set output 14" "Not changed,Changed" newline bitfld.long 0x00 13. " [13] ,Port set output 13" "Not changed,Changed" bitfld.long 0x00 12. " [12] ,Port set output 12" "Not changed,Changed" bitfld.long 0x00 11. " [11] ,Port set output 11" "Not changed,Changed" bitfld.long 0x00 10. " [10] ,Port set output 10" "Not changed,Changed" newline bitfld.long 0x00 9. " [9] ,Port set output 9" "Not changed,Changed" bitfld.long 0x00 8. " [8] ,Port set output 8" "Not changed,Changed" bitfld.long 0x00 7. " [7] ,Port set output 7" "Not changed,Changed" bitfld.long 0x00 6. " [6] ,Port set output 6" "Not changed,Changed" newline bitfld.long 0x00 5. " [5] ,Port set output 5" "Not changed,Changed" bitfld.long 0x00 4. " [4] ,Port set output 4" "Not changed,Changed" bitfld.long 0x00 3. " [3] ,Port set output 3" "Not changed,Changed" bitfld.long 0x00 2. " [2] ,Port set output 2" "Not changed,Changed" newline bitfld.long 0x00 1. " [1] ,Port set output 1" "Not changed,Changed" bitfld.long 0x00 0. " [0] ,Port set output 0" "Not changed,Changed" line.long 0x04 "PCOR,Port Clear Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 31. " PTCO[31] ,Port clear output 31" "Not cleared,Cleared" bitfld.long 0x04 30. " [30] ,Port clear output 30" "Not cleared,Cleared" bitfld.long 0x04 29. " [29] ,Port clear output 29" "Not cleared,Cleared" bitfld.long 0x04 28. " [28] ,Port clear output 28" "Not cleared,Cleared" newline bitfld.long 0x04 27. " [27] ,Port clear output 27" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 26. " [26] ,Port clear output 26" "Not cleared,Cleared" bitfld.long 0x04 25. " [25] ,Port clear output 25" "Not cleared,Cleared" bitfld.long 0x04 24. " [24] ,Port clear output 24" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 23. " [23] ,Port clear output 23" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 22. " [22] ,Port clear output 22" "Not cleared,Cleared" bitfld.long 0x04 21. " [21] ,Port clear output 21" "Not cleared,Cleared" bitfld.long 0x04 20. " [20] ,Port clear output 20" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 19. " [19] ,Port clear output 19" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 18. " [18] ,Port clear output 18" "Not cleared,Cleared" newline endif bitfld.long 0x04 17. " [17] ,Port clear output 17" "Not cleared,Cleared" bitfld.long 0x04 16. " [16] ,Port clear output 16" "Not cleared,Cleared" bitfld.long 0x04 15. " [15] ,Port clear output 15" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Port clear output 14" "Not cleared,Cleared" newline bitfld.long 0x04 13. " [13] ,Port clear output 13" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Port clear output 12" "Not cleared,Cleared" bitfld.long 0x04 11. " [11] ,Port clear output 11" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Port clear output 10" "Not cleared,Cleared" newline bitfld.long 0x04 9. " [9] ,Port clear output 9" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Port clear output 8" "Not cleared,Cleared" bitfld.long 0x04 7. " [7] ,Port clear output 7" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Port clear output 6" "Not cleared,Cleared" newline bitfld.long 0x04 5. " [5] ,Port clear output 5" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Port clear output 4" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Port clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Port clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Port clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Port clear output 0" "Not cleared,Cleared" line.long 0x08 "PTOR,Port Toggle Output Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 31. " PTTO[31] ,Port toggle output 31" "Not inverted,Inverted" bitfld.long 0x08 30. " [30] ,Port toggle output 30" "Not inverted,Inverted" bitfld.long 0x08 29. " [29] ,Port toggle output 29" "Not inverted,Inverted" bitfld.long 0x08 28. " [28] ,Port toggle output 28" "Not inverted,Inverted" newline bitfld.long 0x08 27. " [27] ,Port toggle output 27" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 26. " [26] ,Port toggle output 26" "Not inverted,Inverted" bitfld.long 0x08 25. " [25] ,Port toggle output 25" "Not inverted,Inverted" bitfld.long 0x08 24. " [24] ,Port toggle output 24" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 23. " [23] ,Port toggle output 23" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 22. " [22] ,Port toggle output 22" "Not inverted,Inverted" bitfld.long 0x08 21. " [21] ,Port toggle output 21" "Not inverted,Inverted" bitfld.long 0x08 20. " [20] ,Port toggle output 20" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 19. " [19] ,Port toggle output 19" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 18. " [18] ,Port toggle output 18" "Not inverted,Inverted" newline endif bitfld.long 0x08 17. " [17] ,Port toggle output 17" "Not inverted,Inverted" bitfld.long 0x08 16. " [16] ,Port toggle output 16" "Not inverted,Inverted" bitfld.long 0x08 15. " [15] ,Port toggle output 15" "Not inverted,Inverted" bitfld.long 0x08 14. " [14] ,Port toggle output 14" "Not inverted,Inverted" newline bitfld.long 0x08 13. " [13] ,Port toggle output 13" "Not inverted,Inverted" bitfld.long 0x08 12. " [12] ,Port toggle output 12" "Not inverted,Inverted" bitfld.long 0x08 11. " [11] ,Port toggle output 11" "Not inverted,Inverted" bitfld.long 0x08 10. " [10] ,Port toggle output 10" "Not inverted,Inverted" newline bitfld.long 0x08 9. " [9] ,Port toggle output 9" "Not inverted,Inverted" bitfld.long 0x08 8. " [8] ,Port toggle output 8" "Not inverted,Inverted" bitfld.long 0x08 7. " [7] ,Port toggle output 7" "Not inverted,Inverted" bitfld.long 0x08 6. " [6] ,Port toggle output 6" "Not inverted,Inverted" newline bitfld.long 0x08 5. " [5] ,Port toggle output 5" "Not inverted,Inverted" bitfld.long 0x08 4. " [4] ,Port toggle output 4" "Not inverted,Inverted" bitfld.long 0x08 3. " [3] ,Port toggle output 3" "Not inverted,Inverted" bitfld.long 0x08 2. " [2] ,Port toggle output 2" "Not inverted,Inverted" newline bitfld.long 0x08 1. " [1] ,Port toggle output 1" "Not inverted,Inverted" bitfld.long 0x08 0. " [0] ,Port toggle output 0" "Not inverted,Inverted" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PDI[31] ,Port data input 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data input 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data input 27" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data input 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data input 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data input 24" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port data input 23" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 22. " [22] ,Port data input 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data input 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data input 20" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port data input 19" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port data input 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data input 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data input 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data input 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data input 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data input 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data input 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data input 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input 0" "Low,High" group.long 0x14++0x07 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 31. " PDD[31] ,Port data direction 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction 28" "Input,Output" newline bitfld.long 0x00 27. " [27] ,Port data direction 27" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data direction 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction 24" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 23. " [23] ,Port data direction 23" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 22. " [22] ,Port data direction 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction 20" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port data direction 19" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port data direction 18" "Input,Output" newline endif bitfld.long 0x00 17. " [17] ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Port data direction 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction 10" "Input,Output" newline bitfld.long 0x00 9. " [9] ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction 8" "Input,Output" bitfld.long 0x00 7. " [7] ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction 6" "Input,Output" newline bitfld.long 0x00 5. " [5] ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction 0" "Input,Output" line.long 0x04 "PIDR,Port Input Disable Register" sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 31. " PID[31] ,Port input disable 31" "No,Yes" bitfld.long 0x04 30. " [30] ,Port input disable 30" "No,Yes" bitfld.long 0x04 29. " [29] ,Port input disable 29" "No,Yes" bitfld.long 0x04 28. " [28] ,Port input disable 28" "No,Yes" newline bitfld.long 0x04 27. " [27] ,Port input disable 27" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 26. " [26] ,Port input disable 26" "No,Yes" bitfld.long 0x04 25. " [25] ,Port input disable 25" "No,Yes" bitfld.long 0x04 24. " [24] ,Port input disable 24" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 23. " [23] ,Port input disable 23" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 22. " [22] ,Port input disable 22" "No,Yes" bitfld.long 0x04 21. " [21] ,Port input disable 21" "No,Yes" bitfld.long 0x04 20. " [20] ,Port input disable 20" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 19. " [19] ,Port input disable 19" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 18. " [18] ,Port input disable 18" "No,Yes" newline endif bitfld.long 0x04 17. " [17] ,Port input disable 17" "No,Yes" bitfld.long 0x04 16. " [16] ,Port input disable 16" "No,Yes" bitfld.long 0x04 15. " [15] ,Port input disable 15" "No,Yes" bitfld.long 0x04 14. " [14] ,Port input disable 14" "No,Yes" newline bitfld.long 0x04 13. " [13] ,Port input disable 13" "No,Yes" bitfld.long 0x04 12. " [12] ,Port input disable 12" "No,Yes" bitfld.long 0x04 11. " [11] ,Port input disable 11" "No,Yes" bitfld.long 0x04 10. " [10] ,Port input disable 10" "No,Yes" newline bitfld.long 0x04 9. " [9] ,Port input disable 9" "No,Yes" bitfld.long 0x04 8. " [8] ,Port input disable 8" "No,Yes" bitfld.long 0x04 7. " [7] ,Port input disable 7" "No,Yes" bitfld.long 0x04 6. " [6] ,Port input disable 6" "No,Yes" newline bitfld.long 0x04 5. " [5] ,Port input disable 5" "No,Yes" bitfld.long 0x04 4. " [4] ,Port input disable 4" "No,Yes" bitfld.long 0x04 3. " [3] ,Port input disable 3" "No,Yes" bitfld.long 0x04 2. " [2] ,Port input disable 2" "No,Yes" newline bitfld.long 0x04 1. " [1] ,Port input disable 1" "No,Yes" bitfld.long 0x04 0. " [0] ,Port input disable 0" "No,Yes" width 0x0B tree.end tree "Port D" base ad:0x400FF0C0 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PDO[31] ,Port data output 31" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 30. " [30] ,Port data output 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data output 27" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data output 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output 25" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 24. " [24] ,Port data output 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data output 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output 22" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 21. " [21] ,Port data output 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output 20" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port data output 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data output 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data output 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data output 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data output 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data output 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data output 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data output 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data output 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PTSO[31] ,Port set output 31" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 30. " [30] ,Port set output 30" "Not changed,Changed" bitfld.long 0x00 29. " [29] ,Port set output 29" "Not changed,Changed" bitfld.long 0x00 28. " [28] ,Port set output 28" "Not changed,Changed" bitfld.long 0x00 27. " [27] ,Port set output 27" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port set output 26" "Not changed,Changed" bitfld.long 0x00 25. " [25] ,Port set output 25" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 24. " [24] ,Port set output 24" "Not changed,Changed" bitfld.long 0x00 23. " [23] ,Port set output 23" "Not changed,Changed" bitfld.long 0x00 22. " [22] ,Port set output 22" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 21. " [21] ,Port set output 21" "Not changed,Changed" bitfld.long 0x00 20. " [20] ,Port set output 20" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port set output 19" "Not changed,Changed" bitfld.long 0x00 18. " [18] ,Port set output 18" "Not changed,Changed" newline endif bitfld.long 0x00 17. " [17] ,Port set output 17" "Not changed,Changed" bitfld.long 0x00 16. " [16] ,Port set output 16" "Not changed,Changed" bitfld.long 0x00 15. " [15] ,Port set output 15" "Not changed,Changed" bitfld.long 0x00 14. " [14] ,Port set output 14" "Not changed,Changed" newline bitfld.long 0x00 13. " [13] ,Port set output 13" "Not changed,Changed" bitfld.long 0x00 12. " [12] ,Port set output 12" "Not changed,Changed" bitfld.long 0x00 11. " [11] ,Port set output 11" "Not changed,Changed" bitfld.long 0x00 10. " [10] ,Port set output 10" "Not changed,Changed" newline bitfld.long 0x00 9. " [9] ,Port set output 9" "Not changed,Changed" bitfld.long 0x00 8. " [8] ,Port set output 8" "Not changed,Changed" bitfld.long 0x00 7. " [7] ,Port set output 7" "Not changed,Changed" bitfld.long 0x00 6. " [6] ,Port set output 6" "Not changed,Changed" newline bitfld.long 0x00 5. " [5] ,Port set output 5" "Not changed,Changed" bitfld.long 0x00 4. " [4] ,Port set output 4" "Not changed,Changed" bitfld.long 0x00 3. " [3] ,Port set output 3" "Not changed,Changed" bitfld.long 0x00 2. " [2] ,Port set output 2" "Not changed,Changed" newline bitfld.long 0x00 1. " [1] ,Port set output 1" "Not changed,Changed" bitfld.long 0x00 0. " [0] ,Port set output 0" "Not changed,Changed" line.long 0x04 "PCOR,Port Clear Output Register" sif cpuis("MWCT1016S") bitfld.long 0x04 31. " PTCO[31] ,Port clear output 31" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 30. " [30] ,Port clear output 30" "Not cleared,Cleared" bitfld.long 0x04 29. " [29] ,Port clear output 29" "Not cleared,Cleared" bitfld.long 0x04 28. " [28] ,Port clear output 28" "Not cleared,Cleared" bitfld.long 0x04 27. " [27] ,Port clear output 27" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 26. " [26] ,Port clear output 26" "Not cleared,Cleared" bitfld.long 0x04 25. " [25] ,Port clear output 25" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 24. " [24] ,Port clear output 24" "Not cleared,Cleared" bitfld.long 0x04 23. " [23] ,Port clear output 23" "Not cleared,Cleared" bitfld.long 0x04 22. " [22] ,Port clear output 22" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 21. " [21] ,Port clear output 21" "Not cleared,Cleared" bitfld.long 0x04 20. " [20] ,Port clear output 20" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 19. " [19] ,Port clear output 19" "Not cleared,Cleared" bitfld.long 0x04 18. " [18] ,Port clear output 18" "Not cleared,Cleared" newline endif bitfld.long 0x04 17. " [17] ,Port clear output 17" "Not cleared,Cleared" bitfld.long 0x04 16. " [16] ,Port clear output 16" "Not cleared,Cleared" bitfld.long 0x04 15. " [15] ,Port clear output 15" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Port clear output 14" "Not cleared,Cleared" newline bitfld.long 0x04 13. " [13] ,Port clear output 13" "Not cleared,Cleared" bitfld.long 0x04 12. " [12] ,Port clear output 12" "Not cleared,Cleared" bitfld.long 0x04 11. " [11] ,Port clear output 11" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Port clear output 10" "Not cleared,Cleared" newline bitfld.long 0x04 9. " [9] ,Port clear output 9" "Not cleared,Cleared" bitfld.long 0x04 8. " [8] ,Port clear output 8" "Not cleared,Cleared" bitfld.long 0x04 7. " [7] ,Port clear output 7" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Port clear output 6" "Not cleared,Cleared" newline bitfld.long 0x04 5. " [5] ,Port clear output 5" "Not cleared,Cleared" bitfld.long 0x04 4. " [4] ,Port clear output 4" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Port clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Port clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Port clear output 1" "Not cleared,Cleared" bitfld.long 0x04 0. " [0] ,Port clear output 0" "Not cleared,Cleared" line.long 0x08 "PTOR,Port Toggle Output Register" sif cpuis("MWCT1016S") bitfld.long 0x08 31. " PTTO[31] ,Port toggle output 31" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 30. " [30] ,Port toggle output 30" "Not inverted,Inverted" bitfld.long 0x08 29. " [29] ,Port toggle output 29" "Not inverted,Inverted" bitfld.long 0x08 28. " [28] ,Port toggle output 28" "Not inverted,Inverted" bitfld.long 0x08 27. " [27] ,Port toggle output 27" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 26. " [26] ,Port toggle output 26" "Not inverted,Inverted" bitfld.long 0x08 25. " [25] ,Port toggle output 25" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 24. " [24] ,Port toggle output 24" "Not inverted,Inverted" bitfld.long 0x08 23. " [23] ,Port toggle output 23" "Not inverted,Inverted" bitfld.long 0x08 22. " [22] ,Port toggle output 22" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 21. " [21] ,Port toggle output 21" "Not inverted,Inverted" bitfld.long 0x08 20. " [20] ,Port toggle output 20" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 19. " [19] ,Port toggle output 19" "Not inverted,Inverted" bitfld.long 0x08 18. " [18] ,Port toggle output 18" "Not inverted,Inverted" newline endif bitfld.long 0x08 17. " [17] ,Port toggle output 17" "Not inverted,Inverted" bitfld.long 0x08 16. " [16] ,Port toggle output 16" "Not inverted,Inverted" bitfld.long 0x08 15. " [15] ,Port toggle output 15" "Not inverted,Inverted" bitfld.long 0x08 14. " [14] ,Port toggle output 14" "Not inverted,Inverted" newline bitfld.long 0x08 13. " [13] ,Port toggle output 13" "Not inverted,Inverted" bitfld.long 0x08 12. " [12] ,Port toggle output 12" "Not inverted,Inverted" bitfld.long 0x08 11. " [11] ,Port toggle output 10" "Not inverted,Inverted" bitfld.long 0x08 10. " [10] ,Port toggle output 10" "Not inverted,Inverted" newline bitfld.long 0x08 9. " [9] ,Port toggle output 9" "Not inverted,Inverted" bitfld.long 0x08 8. " [8] ,Port toggle output 8" "Not inverted,Inverted" bitfld.long 0x08 7. " [7] ,Port toggle output 7" "Not inverted,Inverted" bitfld.long 0x08 6. " [6] ,Port toggle output 6" "Not inverted,Inverted" newline bitfld.long 0x08 5. " [5] ,Port toggle output 5" "Not inverted,Inverted" bitfld.long 0x08 4. " [4] ,Port toggle output 4" "Not inverted,Inverted" bitfld.long 0x08 3. " [3] ,Port toggle output 3" "Not inverted,Inverted" bitfld.long 0x08 2. " [2] ,Port toggle output 2" "Not inverted,Inverted" newline bitfld.long 0x08 1. " [1] ,Port toggle output 1" "Not inverted,Inverted" bitfld.long 0x08 0. " [0] ,Port toggle output 0" "Not inverted,Inverted" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PDI[31] ,Port data input 31" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 30. " [30] ,Port data input 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data input 27" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data input 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data input 25" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 24. " [24] ,Port data input 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data input 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data input 22" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 21. " [21] ,Port data input 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data input 20" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port data input 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data input 18" "Low,High" newline endif bitfld.long 0x00 17. " [17] ,Port data input 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data input 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port data input 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input 10" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port data input 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data input 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,Port data input 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port data input 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input 0" "Low,High" group.long 0x14++0x07 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MWCT1016S") bitfld.long 0x00 31. " PDD[31] ,Port data direction 31" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 30. " [30] ,Port data direction 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Port data direction 27" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 26. " [26] ,Port data direction 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction 25" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 24. " [24] ,Port data direction 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Port data direction 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction 22" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 21. " [21] ,Port data direction 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction 20" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 19. " [19] ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction 18" "Input,Output" newline endif bitfld.long 0x00 17. " [17] ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Port data direction 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction 10" "Input,Output" newline bitfld.long 0x00 9. " [9] ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction 8" "Input,Output" bitfld.long 0x00 7. " [7] ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction 6" "Input,Output" newline bitfld.long 0x00 5. " [5] ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction 0" "Input,Output" line.long 0x04 "PIDR,Port Input Disable Register" sif cpuis("MWCT1016S") bitfld.long 0x04 31. " PID[31] ,Port input disable 31" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 30. " [30] ,Port input disable 30" "No,Yes" bitfld.long 0x04 29. " [29] ,Port input disable 29" "No,Yes" bitfld.long 0x04 28. " [28] ,Port input disable 28" "No,Yes" bitfld.long 0x04 27. " [27] ,Port input disable 27" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 26. " [26] ,Port input disable 26" "No,Yes" bitfld.long 0x04 25. " [25] ,Port input disable 25" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 24. " [24] ,Port input disable 24" "No,Yes" bitfld.long 0x04 23. " [23] ,Port input disable 23" "No,Yes" bitfld.long 0x04 22. " [22] ,Port input disable 22" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 21. " [21] ,Port input disable 21" "No,Yes" bitfld.long 0x04 20. " [20] ,Port input disable 20" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 19. " [19] ,Port input disable 19" "No,Yes" bitfld.long 0x04 18. " [18] ,Port input disable 18" "No,Yes" newline endif bitfld.long 0x04 17. " [17] ,Port input disable 17" "No,Yes" bitfld.long 0x04 16. " [16] ,Port input disable 16" "No,Yes" bitfld.long 0x04 15. " [15] ,Port input disable 15" "No,Yes" bitfld.long 0x04 14. " [14] ,Port input disable 14" "No,Yes" newline bitfld.long 0x04 13. " [13] ,Port input disable 13" "No,Yes" bitfld.long 0x04 12. " [12] ,Port input disable 12" "No,Yes" bitfld.long 0x04 11. " [11] ,Port input disable 11" "No,Yes" bitfld.long 0x04 10. " [10] ,Port input disable 10" "No,Yes" newline bitfld.long 0x04 9. " [9] ,Port input disable 9" "No,Yes" bitfld.long 0x04 8. " [8] ,Port input disable 8" "No,Yes" bitfld.long 0x04 7. " [7] ,Port input disable 7" "No,Yes" bitfld.long 0x04 6. " [6] ,Port input disable 6" "No,Yes" newline bitfld.long 0x04 5. " [5] ,Port input disable 5" "No,Yes" bitfld.long 0x04 4. " [4] ,Port input disable 4" "No,Yes" bitfld.long 0x04 3. " [3] ,Port input disable 3" "No,Yes" bitfld.long 0x04 2. " [2] ,Port input disable 2" "No,Yes" newline bitfld.long 0x04 1. " [1] ,Port input disable 1" "No,Yes" bitfld.long 0x04 0. " [0] ,Port input disable 0" "No,Yes" width 0x0B tree.end tree "Port E" base ad:0x400FF100 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("MWCT1016S") bitfld.long 0x00 27. " [27] ,Port data output 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data output 26" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port data output 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data output 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data output 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output 22" "Low,High" newline bitfld.long 0x00 21. " [21] ,Port data output 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port data output 19" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port data output 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data output 17" "Low,High" newline endif bitfld.long 0x00 16. " [16] ,Port data output 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data output 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data output 13" "Low,High" newline bitfld.long 0x00 12. " [12] ,Port data output 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data output 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data output 9" "Low,High" newline bitfld.long 0x00 8. " [8] ,Port data output 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data output 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data output 5" "Low,High" newline bitfld.long 0x00 4. " [4] ,Port data output 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data output 1" "Low,High" newline bitfld.long 0x00 0. " [0] ,Port data output 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" sif cpuis("MWCT1016S") bitfld.long 0x00 27. " [27] ,Port set output 27" "Not changed,Changed" bitfld.long 0x00 26. " [26] ,Port set output 26" "Not changed,Changed" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port set output 25" "Not changed,Changed" bitfld.long 0x00 24. " [24] ,Port set output 24" "Not changed,Changed" bitfld.long 0x00 23. " [23] ,Port set output 23" "Not changed,Changed" bitfld.long 0x00 22. " [22] ,Port set output 22" "Not changed,Changed" newline bitfld.long 0x00 21. " [21] ,Port set output 21" "Not changed,Changed" bitfld.long 0x00 20. " [20] ,Port set output 20" "Not changed,Changed" bitfld.long 0x00 19. " [19] ,Port set output 19" "Not changed,Changed" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port set output 18" "Not changed,Changed" bitfld.long 0x00 17. " [17] ,Port set output 17" "Not changed,Changed" newline endif bitfld.long 0x00 16. " [16] ,Port set output 16" "Not changed,Changed" bitfld.long 0x00 15. " [15] ,Port set output 15" "Not changed,Changed" bitfld.long 0x00 14. " [14] ,Port set output 14" "Not changed,Changed" bitfld.long 0x00 13. " [13] ,Port set output 13" "Not changed,Changed" newline bitfld.long 0x00 12. " [12] ,Port set output 12" "Not changed,Changed" bitfld.long 0x00 11. " [11] ,Port set output 11" "Not changed,Changed" bitfld.long 0x00 10. " [10] ,Port set output 10" "Not changed,Changed" bitfld.long 0x00 9. " [9] ,Port set output 9" "Not changed,Changed" newline bitfld.long 0x00 8. " [8] ,Port set output 8" "Not changed,Changed" bitfld.long 0x00 7. " [7] ,Port set output 7" "Not changed,Changed" bitfld.long 0x00 6. " [6] ,Port set output 6" "Not changed,Changed" bitfld.long 0x00 5. " [5] ,Port set output 5" "Not changed,Changed" newline bitfld.long 0x00 4. " [4] ,Port set output 4" "Not changed,Changed" bitfld.long 0x00 3. " [3] ,Port set output 3" "Not changed,Changed" bitfld.long 0x00 2. " [2] ,Port set output 2" "Not changed,Changed" bitfld.long 0x00 1. " [1] ,Port set output 1" "Not changed,Changed" newline bitfld.long 0x00 0. " [0] ,Port set output 0" "Not changed,Changed" line.long 0x04 "PCOR,Port Clear Output Register" sif cpuis("MWCT1016S") bitfld.long 0x04 27. " [27] ,Port clear output 27" "Not cleared,Cleared" bitfld.long 0x04 26. " [26] ,Port clear output 26" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 25. " [25] ,Port clear output 25" "Not cleared,Cleared" bitfld.long 0x04 24. " [24] ,Port clear output 24" "Not cleared,Cleared" bitfld.long 0x04 23. " [23] ,Port clear output 23" "Not cleared,Cleared" bitfld.long 0x04 22. " [22] ,Port clear output 22" "Not cleared,Cleared" newline bitfld.long 0x04 21. " [21] ,Port clear output 21" "Not cleared,Cleared" bitfld.long 0x04 20. " [20] ,Port clear output 20" "Not cleared,Cleared" bitfld.long 0x04 19. " [19] ,Port clear output 19" "Not cleared,Cleared" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 18. " [18] ,Port clear output 18" "Not cleared,Cleared" bitfld.long 0x04 17. " [17] ,Port clear output 17" "Not cleared,Cleared" newline endif bitfld.long 0x04 16. " [16] ,Port clear output 16" "Not cleared,Cleared" bitfld.long 0x04 15. " [15] ,Port clear output 15" "Not cleared,Cleared" bitfld.long 0x04 14. " [14] ,Port clear output 14" "Not cleared,Cleared" bitfld.long 0x04 13. " [13] ,Port clear output 13" "Not cleared,Cleared" newline bitfld.long 0x04 12. " [12] ,Port clear output 12" "Not cleared,Cleared" bitfld.long 0x04 11. " [11] ,Port clear output 11" "Not cleared,Cleared" bitfld.long 0x04 10. " [10] ,Port clear output 10" "Not cleared,Cleared" bitfld.long 0x04 9. " [9] ,Port clear output 9" "Not cleared,Cleared" newline bitfld.long 0x04 8. " [8] ,Port clear output 8" "Not cleared,Cleared" bitfld.long 0x04 7. " [7] ,Port clear output 7" "Not cleared,Cleared" bitfld.long 0x04 6. " [6] ,Port clear output 6" "Not cleared,Cleared" bitfld.long 0x04 5. " [5] ,Port clear output 5" "Not cleared,Cleared" newline bitfld.long 0x04 4. " [4] ,Port clear output 4" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Port clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Port clear output 2" "Not cleared,Cleared" bitfld.long 0x04 1. " [1] ,Port clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 0. " [0] ,Port clear output 0" "Not cleared,Cleared" line.long 0x08 "PTOR,Port Toggle Output Register" sif cpuis("MWCT1016S") bitfld.long 0x08 27. " [27] ,Port toggle output 27" "Not inverted,Inverted" bitfld.long 0x08 26. " [26] ,Port toggle output 26" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x08 25. " [25] ,Port toggle output 25" "Not inverted,Inverted" bitfld.long 0x08 24. " [24] ,Port toggle output 24" "Not inverted,Inverted" bitfld.long 0x08 23. " [23] ,Port toggle output 23" "Not inverted,Inverted" bitfld.long 0x08 22. " [22] ,Port toggle output 22" "Not inverted,Inverted" newline bitfld.long 0x08 21. " [21] ,Port toggle output 21" "Not inverted,Inverted" bitfld.long 0x08 20. " [20] ,Port toggle output 20" "Not inverted,Inverted" bitfld.long 0x08 19. " [19] ,Port toggle output 19" "Not inverted,Inverted" newline endif sif cpuis("MWCT1016S") bitfld.long 0x08 18. " [18] ,Port toggle output 18" "Not inverted,Inverted" bitfld.long 0x08 17. " [17] ,Port toggle output 17" "Not inverted,Inverted" newline endif bitfld.long 0x08 16. " [16] ,Port toggle output 16" "Not inverted,Inverted" bitfld.long 0x08 15. " [15] ,Port toggle output 15" "Not inverted,Inverted" bitfld.long 0x08 14. " [14] ,Port toggle output 14" "Not inverted,Inverted" bitfld.long 0x08 13. " [13] ,Port toggle output 13" "Not inverted,Inverted" newline bitfld.long 0x08 12. " [12] ,Port toggle output 12" "Not inverted,Inverted" bitfld.long 0x08 11. " [11] ,Port toggle output 11" "Not inverted,Inverted" bitfld.long 0x08 10. " [10] ,Port toggle output 10" "Not inverted,Inverted" bitfld.long 0x08 9. " [9] ,Port toggle output 9" "Not inverted,Inverted" newline bitfld.long 0x08 8. " [8] ,Port toggle output 8" "Not inverted,Inverted" bitfld.long 0x08 7. " [7] ,Port toggle output 7" "Not inverted,Inverted" bitfld.long 0x08 6. " [6] ,Port toggle output 6" "Not inverted,Inverted" bitfld.long 0x08 5. " [5] ,Port toggle output 5" "Not inverted,Inverted" newline bitfld.long 0x08 4. " [4] ,Port toggle output 4" "Not inverted,Inverted" bitfld.long 0x08 3. " [3] ,Port toggle output 3" "Not inverted,Inverted" bitfld.long 0x08 2. " [2] ,Port toggle output 2" "Not inverted,Inverted" bitfld.long 0x08 1. " [1] ,Port toggle output 1" "Not inverted,Inverted" newline bitfld.long 0x08 0. " [0] ,Port toggle output 0" "Not inverted,Inverted" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MWCT1016S") bitfld.long 0x00 27. " [27] ,Port data input 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data input 26" "Low,High" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port data input" "Low,High" bitfld.long 0x00 24. " [24] ,Port data input 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data input 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data input 22" "Low,High" newline bitfld.long 0x00 21. " [21] ,Port data input 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data input 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port data input 19" "Low,High" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port data input 19" "Low,High" bitfld.long 0x00 17. " [17] ,Port data input 17" "Low,High" newline endif bitfld.long 0x00 16. " [16] ,Port data input 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data input 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data input 13" "Low,High" newline bitfld.long 0x00 12. " [12] ,Port data input 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data input 9" "Low,High" newline bitfld.long 0x00 8. " [8] ,Port data input 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data input 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data input 5" "Low,High" newline bitfld.long 0x00 4. " [4] ,Port data input 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data input 1" "Low,High" newline bitfld.long 0x00 0. " [0] ,Port data input 0" "Low,High" group.long 0x14++0x07 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MWCT1016S") bitfld.long 0x00 27. " [27] ,Port data direction 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction 26" "Input,Output" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x00 25. " [25] ,Port data direction 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Port data direction 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction 22" "Input,Output" newline bitfld.long 0x00 21. " [21] ,Port data direction 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction 20" "Input,Output" bitfld.long 0x00 19. " [19] ,Port data direction 19" "Input,Output" newline endif sif cpuis("MWCT1016S") bitfld.long 0x00 18. " [18] ,Port data direction 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction 17" "Input,Output" newline endif bitfld.long 0x00 16. " [16] ,Port data direction 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Port data direction 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction 13" "Input,Output" newline bitfld.long 0x00 12. " [12] ,Port data direction 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction 9" "Input,Output" newline bitfld.long 0x00 8. " [8] ,Port data direction 8" "Input,Output" bitfld.long 0x00 7. " [7] ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction 5" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction 1" "Input,Output" newline bitfld.long 0x00 0. " [0] ,Port data direction 0" "Input,Output" line.long 0x04 "PIDR,Port Input Disable Register" sif cpuis("MWCT1016S") bitfld.long 0x04 27. " [27] ,Port input disable 27" "No,Yes" bitfld.long 0x04 26. " [26] ,Port input disable 26" "No,Yes" newline endif sif cpuis("MWCT1016S")||cpuis("MWCT1015S") bitfld.long 0x04 25. " [25] ,Port input disable 25" "No,Yes" bitfld.long 0x04 24. " [24] ,Port input disable 24" "No,Yes" bitfld.long 0x04 23. " [23] ,Port input disable 23" "No,Yes" bitfld.long 0x04 22. " [22] ,Port input disable 22" "No,Yes" newline bitfld.long 0x04 21. " [21] ,Port input disable 21" "No,Yes" bitfld.long 0x04 20. " [20] ,Port input disable 20" "No,Yes" bitfld.long 0x04 19. " [19] ,Port input disable 19" "No,Yes" newline endif sif cpuis("MWCT1016S") bitfld.long 0x04 18. " [18] ,Port input disable 18" "No,Yes" bitfld.long 0x04 17. " [17] ,Port input disable 17" "No,Yes" newline endif bitfld.long 0x04 16. " [16] ,Port input disable 16" "No,Yes" bitfld.long 0x04 15. " [15] ,Port input disable 15" "No,Yes" bitfld.long 0x04 14. " [14] ,Port input disable 14" "No,Yes" bitfld.long 0x04 13. " [13] ,Port input disable 13" "No,Yes" newline bitfld.long 0x04 12. " [12] ,Port input disable 12" "No,Yes" bitfld.long 0x04 11. " [11] ,Port input disable 11" "No,Yes" bitfld.long 0x04 10. " [10] ,Port input disable 10" "No,Yes" bitfld.long 0x04 9. " [9] ,Port input disable 9" "No,Yes" newline bitfld.long 0x04 8. " [8] ,Port input disable 8" "No,Yes" bitfld.long 0x04 7. " [7] ,Port input disable 7" "No,Yes" bitfld.long 0x04 6. " [6] ,Port input disable 6" "No,Yes" bitfld.long 0x04 5. " [5] ,Port input disable 5" "No,Yes" newline bitfld.long 0x04 4. " [4] ,Port input disable 4" "No,Yes" bitfld.long 0x04 3. " [3] ,Port input disable 3" "No,Yes" bitfld.long 0x04 2. " [2] ,Port input disable 2" "No,Yes" bitfld.long 0x04 1. " [1] ,Port input disable 1" "No,Yes" newline bitfld.long 0x04 0. " [0] ,Port input disable 0" "No,Yes" width 0x0B tree.end tree.end tree "MPU (Memory Protection Unit)" base ad:0x4000D000 width 13. group.long 0x00++0x03 line.long 0x00 "CESR,Control/Error Status Register" eventfld.long 0x00 31. " SPERR[31] ,Slave port 0 error" "No error,Error" eventfld.long 0x00 30. " [30] ,Slave port 1 error" "No error,Error" eventfld.long 0x00 29. " [29] ,Slave port 2 error" "No error,Error" eventfld.long 0x00 28. " [28] ,Slave port 3 error" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Slave port 4 error" "No error,Error" newline rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8,12,16,?..." bitfld.long 0x00 0. " VLD ,Global enable/disable for the MPU" "Disabled,Enabled" rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register (Slave Port 0)" line.long 0x04 "EDR0,Error Detail Register (Slave Port 0)" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register (Slave Port 1)" line.long 0x04 "EDR1,Error Detail Register (Slave Port 1)" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register (Slave Port 2)" line.long 0x04 "EDR2,Error Detail Register (Slave Port 2)" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register (Slave Port 3)" line.long 0x04 "EDR3,Error Detail Register (Slave Port 3)" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register (Slave Port 4)" line.long 0x04 "EDR4,Error Detail Register (Slave Port 4)" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" newline group.long 0x400++0x0F line.long 0x00 "RGD0_WORD0,Region Descriptor 0 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD0_WORD1,Region Descriptor 0 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD0_WORD2,Region Descriptor 0 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD0_WORD3,Region Descriptor 0 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x410++0x0F line.long 0x00 "RGD1_WORD0,Region Descriptor 1 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD1_WORD1,Region Descriptor 1 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD1_WORD2,Region Descriptor 1 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD1_WORD3,Region Descriptor 1 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x420++0x0F line.long 0x00 "RGD2_WORD0,Region Descriptor 2 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD2_WORD1,Region Descriptor 2 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD2_WORD2,Region Descriptor 2 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD2_WORD3,Region Descriptor 2 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x430++0x0F line.long 0x00 "RGD3_WORD0,Region Descriptor 3 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD3_WORD1,Region Descriptor 3 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD3_WORD2,Region Descriptor 3 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD3_WORD3,Region Descriptor 3 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x440++0x0F line.long 0x00 "RGD4_WORD0,Region Descriptor 4 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD4_WORD1,Region Descriptor 4 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD4_WORD2,Region Descriptor 4 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD4_WORD3,Region Descriptor 4 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x450++0x0F line.long 0x00 "RGD5_WORD0,Region Descriptor 5 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD5_WORD1,Region Descriptor 5 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD5_WORD2,Region Descriptor 5 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD5_WORD3,Region Descriptor 5 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x460++0x0F line.long 0x00 "RGD6_WORD0,Region Descriptor 6 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD6_WORD1,Region Descriptor 6 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD6_WORD2,Region Descriptor 6 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD6_WORD3,Region Descriptor 6 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x470++0x0F line.long 0x00 "RGD7_WORD0,Region Descriptor 7 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD7_WORD1,Region Descriptor 7 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD7_WORD2,Region Descriptor 7 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD7_WORD3,Region Descriptor 7 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x480++0x0F line.long 0x00 "RGD8_WORD0,Region Descriptor 8 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD8_WORD1,Region Descriptor 8 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD8_WORD2,Region Descriptor 8 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD8_WORD3,Region Descriptor 8 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x490++0x0F line.long 0x00 "RGD9_WORD0,Region Descriptor 9 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD9_WORD1,Region Descriptor 9 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD9_WORD2,Region Descriptor 9 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD9_WORD3,Region Descriptor 9 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x4A0++0x0F line.long 0x00 "RGD10_WORD0,Region Descriptor 10 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD10_WORD1,Region Descriptor 10 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD10_WORD2,Region Descriptor 10 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD10_WORD3,Region Descriptor 10 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x4B0++0x0F line.long 0x00 "RGD11_WORD0,Region Descriptor 11 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD11_WORD1,Region Descriptor 11 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD11_WORD2,Region Descriptor 11 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD11_WORD3,Region Descriptor 11 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x4C0++0x0F line.long 0x00 "RGD12_WORD0,Region Descriptor 12 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD12_WORD1,Region Descriptor 12 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD12_WORD2,Region Descriptor 12 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD12_WORD3,Region Descriptor 12 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x4D0++0x0F line.long 0x00 "RGD13_WORD0,Region Descriptor 13 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD13_WORD1,Region Descriptor 13 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD13_WORD2,Region Descriptor 13 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD13_WORD3,Region Descriptor 13 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x4E0++0x0F line.long 0x00 "RGD14_WORD0,Region Descriptor 14 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD14_WORD1,Region Descriptor 14 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD14_WORD2,Region Descriptor 14 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD14_WORD3,Region Descriptor 14 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x4F0++0x0F line.long 0x00 "RGD15_WORD0,Region Descriptor 15 Word 0 Register" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD15_WORD1,Region Descriptor 15 Word 1 Register" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD15_WORD2,Region Descriptor 15 Word 2 Register" bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x08 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x08 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x08 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x08 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x08 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" line.long 0x0C "RGD15_WORD3,Region Descriptor 15 Word 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x0C 0. " VLD ,Valid" "Invalid,Valid" group.long 0x800++0x03 line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x804++0x03 line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x808++0x03 line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x80C++0x03 line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x810++0x03 line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x814++0x03 line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x818++0x03 line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x81C++0x03 line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x820++0x03 line.long 0x00 "RGDAAC8,Region Descriptor Alternate Access Control 8 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x824++0x03 line.long 0x00 "RGDAAC9,Region Descriptor Alternate Access Control 9 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x828++0x03 line.long 0x00 "RGDAAC10,Region Descriptor Alternate Access Control 10 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x82C++0x03 line.long 0x00 "RGDAAC11,Region Descriptor Alternate Access Control 11 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x830++0x03 line.long 0x00 "RGDAAC12,Region Descriptor Alternate Access Control 12 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x834++0x03 line.long 0x00 "RGDAAC13,Region Descriptor Alternate Access Control 13 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x838++0x03 line.long 0x00 "RGDAAC14,Region Descriptor Alternate Access Control 14 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" group.long 0x83C++0x03 line.long 0x00 "RGDAAC15,Region Descriptor Alternate Access Control 15 Register" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Not allowed,Allowed" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Not allowed,Allowed" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Not allowed,Allowed" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Not allowed,Allowed" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Not allowed,Allowed" bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Not allowed,Allowed" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Not allowed,Allowed" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 20. " M3UM_R ,Bus master 3 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 19. " M3UM_W ,Bus master 3 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 18. " M3UM_X ,Bus master 3 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 14. " M2UM_R ,Bus master 2 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 13. " M2UM_W ,Bus master 2 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 12. " M2UM_X ,Bus master 2 user mode access control for execute" "Not allowed,Allowed" newline bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Not included,Included" bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 8. " M1UM_R ,Bus master 1 user mode access control for read" "Not allowed,Allowed" bitfld.long 0x00 7. " M1UM_W ,Bus master 1 user mode access control for write" "Not allowed,Allowed" newline bitfld.long 0x00 6. " M1UM_X ,Bus master 1 user mode access control for execute" "Not allowed,Allowed" bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Not included,Included" bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,Same as user mode" bitfld.long 0x00 2. " M0UM_R ,Bus master 0 user mode access control for read" "Not allowed,Allowed" newline bitfld.long 0x00 1. " M0UM_W ,Bus master 0 user mode access control for write" "Not allowed,Allowed" bitfld.long 0x00 0. " M0UM_X ,Bus master 0 user mode access control for execute" "Not allowed,Allowed" width 0x0B tree.end tree "AIPS-LITE (Peripheral Bridge)" base ad:0x40000000 width 8. group.long 0x00++0x03 line.long 0x00 "MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master 0 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master 0 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master 0 privilege level" "Forced,Not forced" newline bitfld.long 0x00 26. " MTR1 ,Master 1 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW1 ,Master 1 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master 1 privilege level" "Forced,Not forced" newline bitfld.long 0x00 22. " MTR2 ,Master 2 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master 2 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL2 ,Master 2 privilege level" "Forced,Not forced" newline bitfld.long 0x00 18. " MTR3 ,Master 3 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW3 ,Master 3 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL3 ,Master 3 privilege level" "Forced,Not forced" sif cpuis("S32D248*") newline bitfld.long 0x00 14. " MTR4 ,Master 4 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 13. " MTW4 ,Master 4 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 12. " MPL4 ,Master 4 privilege level" "Forced,Not forced" newline bitfld.long 0x00 10. " MTR5 ,Master 5 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW5 ,Master 5 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL5 ,Master 5 privilege level" "Forced,Not forced" newline bitfld.long 0x00 6. " MTR6 ,Master 6 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 5. " MTW6 ,Master 6 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 4. " MPL6 ,Master 6 privilege level" "Forced,Not forced" newline bitfld.long 0x00 2. " MTR7 ,Master 7 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 1. " MTW7 ,Master 7 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 0. " MPL7 ,Master 7 privilege level" "Forced,Not forced" endif sif cpuis("S32D248*") group.long 0x04++0x03 line.long 0x00 "MPRB,Master Privilege Register B" bitfld.long 0x00 30. " MTR8 ,Master 8 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW8 ,Master 8 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL8 ,Master 8 privilege level" "Forced,Not forced" newline bitfld.long 0x00 26. " MTR9 ,Master 9 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW9 ,Master 9 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL9 ,Master 9 privilege level" "Forced,Not forced" newline bitfld.long 0x00 22. " MTR10 ,Master 10 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW10 ,Master 10 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL10 ,Master 10 privilege level" "Forced,Not forced" newline bitfld.long 0x00 18. " MTR11 ,Master 11 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW11 ,Master 11 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL11 ,Master 11 privilege level" "Forced,Not forced" newline bitfld.long 0x00 14. " MTR12 ,Master 12 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 13. " MTW12 ,Master 12 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 12. " MPL12 ,Master 12 privilege level" "Forced,Not forced" newline bitfld.long 0x00 10. " MTR13 ,Master 13 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW13 ,Master 13 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL13 ,Master 13 privilege level" "Forced,Not forced" newline bitfld.long 0x00 6. " MTR14 ,Master 14 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 5. " MTW14 ,Master 14 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 4. " MPL14 ,Master 14 privilege level" "Forced,Not forced" newline bitfld.long 0x00 2. " MTR15 ,Master 15 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 1. " MTW15 ,Master 15 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 0. " MPL15 ,Master 15 privilege level" "Forced,Not forced" endif group.long 0x20++0x03 line.long 0x00 "PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" sif cpuis("S32D248*") newline bitfld.long 0x00 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" endif sif !cpuis("S32D248*")&&!cpuis("S32S*") group.long 0x24++0x03 line.long 0x00 "PACRB,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" group.long 0x2C++0x03 line.long 0x00 "PACRD,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" endif group.long 0x40++0x17 line.long 0x00 "OPACRA,Off-Platform Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline sif cpuis("S32D248*")||cpuis("S32S*") bitfld.long 0x00 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline endif bitfld.long 0x00 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect 7" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect 7" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect 7" "Unprotected,Protected" line.long 0x04 "OPACRB,Off-Platform Peripheral Access Control Register" sif cpuis("S32D248*")||cpuis("S32S*") bitfld.long 0x04 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x04 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x04 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x04 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x04 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x04 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x04 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x04 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x04 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline endif bitfld.long 0x04 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x04 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x04 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline bitfld.long 0x04 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x04 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x04 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x04 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x04 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x04 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" newline bitfld.long 0x04 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x04 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x04 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" line.long 0x08 "OPACRC,Off-Platform Peripheral Access Control Register" sif cpuis("S32D248*") bitfld.long 0x08 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x08 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x08 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline endif bitfld.long 0x08 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x08 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x08 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" sif !cpuis("S32D248*")&&!cpuis("S32S*") newline bitfld.long 0x08 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x08 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x08 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x08 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x08 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x08 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" newline bitfld.long 0x08 2. " SP7 ,Supervisor protect 7" "Unprotected,Protected" bitfld.long 0x08 1. " WP7 ,Write protect 7" "Unprotected,Protected" bitfld.long 0x08 0. " TP7 ,Trusted protect 7" "Unprotected,Protected" endif line.long 0x0C "OPACRD,Off-Platform Peripheral Access Control Register" sif !cpuis("S32D248*")&&!cpuis("S32S*") bitfld.long 0x0C 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x0C 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x0C 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x0C 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x0C 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x0C 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x0C 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x0C 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x0C 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x0C 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x0C 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x0C 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" else newline bitfld.long 0x0C 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x0C 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x0C 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" endif newline bitfld.long 0x0C 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x0C 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x0C 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" line.long 0x10 "OPACRE,Off-Platform Peripheral Access Control Register" bitfld.long 0x10 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x10 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x10 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" sif cpuis("S32D248*")||cpuis("S32S*") newline bitfld.long 0x10 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x10 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x10 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x10 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x10 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x10 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x10 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x10 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x10 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline bitfld.long 0x10 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x10 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x10 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x10 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x10 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x10 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" else newline bitfld.long 0x10 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x10 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x10 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" endif line.long 0x14 "OPACRF,Off-Platform Peripheral Access Control Register" bitfld.long 0x14 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x14 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x14 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x14 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x14 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x14 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x14 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x14 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x14 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x14 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x14 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x14 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline bitfld.long 0x14 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x14 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x14 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x14 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x14 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x14 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" sif !cpuis("S32D248*")&&!cpuis("S32S*") group.long 0x58++0x17 line.long 0x00 "OPACRG,Off-Platform Peripheral Access Control Register" bitfld.long 0x00 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" line.long 0x04 "OPACRH,Off-Platform Peripheral Access Control Register" bitfld.long 0x04 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x04 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x04 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" line.long 0x08 "OPACRI,Off-Platform Peripheral Access Control Register" bitfld.long 0x08 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x08 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x08 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x08 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x08 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x08 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline bitfld.long 0x08 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x08 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x08 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x08 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x08 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x08 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" newline bitfld.long 0x08 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x08 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x08 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" newline bitfld.long 0x08 2. " SP7 ,Supervisor protect 7" "Unprotected,Protected" bitfld.long 0x08 1. " WP7 ,Write protect 7" "Unprotected,Protected" bitfld.long 0x08 0. " TP7 ,Trusted protect 7" "Unprotected,Protected" line.long 0x0C "OPACRJ,Off-Platform Peripheral Access Control Register" bitfld.long 0x0C 22. " SP2 ,Supervisor protect 2" "Unprotected,Protected" bitfld.long 0x0C 21. " WP2 ,Write protect 2" "Unprotected,Protected" bitfld.long 0x0C 20. " TP2 ,Trusted protect 2" "Unprotected,Protected" newline bitfld.long 0x0C 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x0C 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x0C 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline bitfld.long 0x0C 14. " SP4 ,Supervisor protect 4" "Unprotected,Protected" bitfld.long 0x0C 13. " WP4 ,Write protect 4" "Unprotected,Protected" bitfld.long 0x0C 12. " TP4 ,Trusted protect 4" "Unprotected,Protected" newline bitfld.long 0x0C 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x0C 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x0C 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" newline bitfld.long 0x0C 2. " SP7 ,Supervisor protect 7" "Unprotected,Protected" bitfld.long 0x0C 1. " WP7 ,Write protect 7" "Unprotected,Protected" bitfld.long 0x0C 0. " TP7 ,Trusted protect 7" "Unprotected,Protected" line.long 0x10 "OPACRK,Off-Platform Peripheral Access Control Register" bitfld.long 0x10 30. " SP0 ,Supervisor protect 0" "Unprotected,Protected" bitfld.long 0x10 29. " WP0 ,Write protect 0" "Unprotected,Protected" bitfld.long 0x10 28. " TP0 ,Trusted protect 0" "Unprotected,Protected" newline bitfld.long 0x10 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x10 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x10 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x10 18. " SP3 ,Supervisor protect 3" "Unprotected,Protected" bitfld.long 0x10 17. " WP3 ,Write protect 3" "Unprotected,Protected" bitfld.long 0x10 16. " TP3 ,Trusted protect 3" "Unprotected,Protected" newline bitfld.long 0x10 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x10 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x10 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" line.long 0x14 "OPACRL,Off-Platform Peripheral Access Control Register" bitfld.long 0x14 26. " SP1 ,Supervisor protect 1" "Unprotected,Protected" bitfld.long 0x14 25. " WP1 ,Write protect 1" "Unprotected,Protected" bitfld.long 0x14 24. " TP1 ,Trusted protect 1" "Unprotected,Protected" newline bitfld.long 0x14 10. " SP5 ,Supervisor protect 5" "Unprotected,Protected" bitfld.long 0x14 9. " WP5 ,Write protect 5" "Unprotected,Protected" bitfld.long 0x14 8. " TP5 ,Trusted protect 5" "Unprotected,Protected" newline bitfld.long 0x14 6. " SP6 ,Supervisor protect 6" "Unprotected,Protected" bitfld.long 0x14 5. " WP6 ,Write protect 6" "Unprotected,Protected" bitfld.long 0x14 4. " TP6 ,Trusted protect 6" "Unprotected,Protected" newline bitfld.long 0x14 2. " SP7 ,Supervisor protect 7" "Unprotected,Protected" bitfld.long 0x14 1. " WP7 ,Write protect 7" "Unprotected,Protected" bitfld.long 0x14 0. " TP7 ,Trusted protect 7" "Unprotected,Protected" endif width 0x0B tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x40021000 width 9. if (((per.b(ad:0x40021000+0x0))&0x80)==0x80) group.byte 0x0++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x0++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x1))&0x80)==0x80) group.byte 0x1++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x1++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x2))&0x80)==0x80) group.byte 0x2++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x2++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x3))&0x80)==0x80) group.byte 0x3++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x3++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x4))&0x80)==0x80) group.byte 0x4++0x00 line.byte 0x00 "CHCFG7,Channel 7 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x4++0x00 line.byte 0x00 "CHCFG7,Channel 7 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x5))&0x80)==0x80) group.byte 0x5++0x00 line.byte 0x00 "CHCFG6,Channel 6 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x5++0x00 line.byte 0x00 "CHCFG6,Channel 6 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x6))&0x80)==0x80) group.byte 0x6++0x00 line.byte 0x00 "CHCFG5,Channel 5 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x6++0x00 line.byte 0x00 "CHCFG5,Channel 5 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x7))&0x80)==0x80) group.byte 0x7++0x00 line.byte 0x00 "CHCFG4,Channel 4 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x7++0x00 line.byte 0x00 "CHCFG4,Channel 4 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x8))&0x80)==0x80) group.byte 0x8++0x00 line.byte 0x00 "CHCFG11,Channel 11 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x8++0x00 line.byte 0x00 "CHCFG11,Channel 11 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0x9))&0x80)==0x80) group.byte 0x9++0x00 line.byte 0x00 "CHCFG10,Channel 10 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0x9++0x00 line.byte 0x00 "CHCFG10,Channel 10 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0xA))&0x80)==0x80) group.byte 0xA++0x00 line.byte 0x00 "CHCFG9,Channel 9 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0xA++0x00 line.byte 0x00 "CHCFG9,Channel 9 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0xB))&0x80)==0x80) group.byte 0xB++0x00 line.byte 0x00 "CHCFG8,Channel 8 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0xB++0x00 line.byte 0x00 "CHCFG8,Channel 8 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0xC))&0x80)==0x80) group.byte 0xC++0x00 line.byte 0x00 "CHCFG15,Channel 15 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0xC++0x00 line.byte 0x00 "CHCFG15,Channel 15 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0xD))&0x80)==0x80) group.byte 0xD++0x00 line.byte 0x00 "CHCFG14,Channel 14 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0xD++0x00 line.byte 0x00 "CHCFG14,Channel 14 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0xE))&0x80)==0x80) group.byte 0xE++0x00 line.byte 0x00 "CHCFG13,Channel 13 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0xE++0x00 line.byte 0x00 "CHCFG13,Channel 13 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif if (((per.b(ad:0x40021000+0xF))&0x80)==0x80) group.byte 0xF++0x00 line.byte 0x00 "CHCFG12,Channel 12 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else rbitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif else group.byte 0xF++0x00 line.byte 0x00 "CHCFG12,Channel 12 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MWCT1014S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,,,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" elif cpuis("MWCT1015S") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),,,FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,,,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,,,LPTMR0,,,Always on,Always on" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",ENET,LPUART0 (RX),LPUART0 (TX),LPUART1 (RX),LPUART1 (TX),LPUART2 (RX),LPUART2 (TX),LPI2C1 (RX),LPI2C1 (TX),FlexIO Shifter0,FlexIO Shifter1,FlexIO Shifter2/SAI1,FlexIO Shifter3/SAI1,LPSPI0 (RX),LPSPI0 (TX),LPSPI1 (RX),LPSPI1 (TX),LPSPI2 (RX),LPSPI2 (TX),FTM1ch0,FTM1ch1,FTM1ch2,FTM1ch3,FTM1ch4,FTM1ch5,FTM1ch6,FTM1ch7,FTM2ch0,FTM2ch1,FTM2ch2,FTM2ch3,FTM2ch4,FTM2ch5,FTM2ch6,FTM2ch7,FTM0,FTM3,FTM4,FTM5,FTM6,FTM7,ADC0,ADC1,LPI2C0 (RX),LPI2C0 (TX),PDB0,PDB1,CMP0,PORTA,PORTB,PORTC,PORTD,PORTE,Flexcan0,Flexcan1,Flexcan2,SAI0 (RX),SAI0 (TX),LPTMR0,QuadSPI (RX),QuadSPI (TX),Always on,Always on" endif endif width 0x0B tree.end tree "EDMA (Enhanced Direct Memory Access)" base ad:0x40008000 width 10. group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Active" bitfld.long 0x00 17. " CX ,Cancel transfer" "Normal,Canceled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Normal,Canceled" bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Low,High" newline bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Low,High" textfld " " else bitfld.long 0x00 17. " CX ,Cancel transfer" "Normal,Canceled" newline bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Normal,Canceled" endif bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Disabled,Enabled" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Normal,Held" newline bitfld.long 0x00 4. " HOE ,Halt on error" "Normal,Halted" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Disabled,Enabled" bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" else bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" endif rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "No error,Error" bitfld.long 0x00 16. " ECX ,Transfer canceled" "Not canceled,Canceled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" newline bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" newline bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline endif bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "No interrupt,Interrupt" newline endif bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "No interrupt,Interrupt" newline wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "Clear one,Clear all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "Set one,Set all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "Clear one,Clear all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "Set one,Set all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x03 0.--4. " SERQ ,Set enable request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x03 0.--3. " SERQ ,Set enable request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clears All DONE bits" "Clear one,Clear all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START Bits (activates all channels)" "Set one,Set all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x05 0.--4. " SSRT ,Set START Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x05 0.--3. " SSRT ,Set START Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear All Error indicators" "Clear one,Clear all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No Op enable" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt requests" "Clear one,Clear all" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " [20] ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline endif eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline endif eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not requested,Requested" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not requested,Requested" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not requested,Requested" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not requested,Requested" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not requested,Requested" newline endif bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not requested,Requested" group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop mode for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop mode for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop mode for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop mode for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop mode for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop mode for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop mode for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop mode for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop mode for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop mode for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop mode for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop mode for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop mode for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop mode for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop mode for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop mode for channel 16" "Disabled,Enabled" newline endif bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop mode for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop mode for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop mode for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop mode for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop mode for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop mode for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop mode for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop mode for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop mode for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop mode for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop mode for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop mode for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop mode for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop mode for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop mode for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop mode for channel 0" "Disabled,Enabled" group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "0,1,2,3" endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") group.byte 0x110++0x0F line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x01 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x01 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x01 4.--5. " GRPPRI ,Channel 18 current group priority" "0,1,2,3" bitfld.byte 0x01 0.--3. " CHPRI ,Channel 18 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x02 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x02 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x02 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x02 4.--5. " GRPPRI ,Channel 17 current group priority" "0,1,2,3" bitfld.byte 0x02 0.--3. " CHPRI ,Channel 17 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x03 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x03 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x03 4.--5. " GRPPRI ,Channel 16 current group priority" "0,1,2,3" bitfld.byte 0x03 0.--3. " CHPRI ,Channel 16 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x04 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x04 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x04 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x04 4.--5. " GRPPRI ,Channel 23 current group priority" "0,1,2,3" bitfld.byte 0x04 0.--3. " CHPRI ,Channel 23 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x05 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x05 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x05 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x05 4.--5. " GRPPRI ,Channel 22 current group priority" "0,1,2,3" bitfld.byte 0x05 0.--3. " CHPRI ,Channel 22 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x06 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x06 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x06 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x06 4.--5. " GRPPRI ,Channel 21 current group priority" "0,1,2,3" bitfld.byte 0x06 0.--3. " CHPRI ,Channel 21 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x07 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x07 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x07 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x07 4.--5. " GRPPRI ,Channel 20 current group priority" "0,1,2,3" bitfld.byte 0x07 0.--3. " CHPRI ,Channel 20 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x08 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x08 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x08 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x08 4.--5. " GRPPRI ,Channel 27 current group priority" "0,1,2,3" bitfld.byte 0x08 0.--3. " CHPRI ,Channel 27 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x09 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x09 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x09 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x09 4.--5. " GRPPRI ,Channel 26 current group priority" "0,1,2,3" bitfld.byte 0x09 0.--3. " CHPRI ,Channel 26 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0A "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x0A 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x0A 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x0A 4.--5. " GRPPRI ,Channel 25 current group priority" "0,1,2,3" bitfld.byte 0x0A 0.--3. " CHPRI ,Channel 25 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0B "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x0B 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x0B 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x0B 4.--5. " GRPPRI ,Channel 24 current group priority" "0,1,2,3" bitfld.byte 0x0B 0.--3. " CHPRI ,Channel 24 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0C "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x0C 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x0C 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x0C 4.--5. " GRPPRI ,Channel 31 current group priority" "0,1,2,3" bitfld.byte 0x0C 0.--3. " CHPRI ,Channel 31 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0D "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x0D 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x0D 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x0D 4.--5. " GRPPRI ,Channel 30 current group priority" "0,1,2,3" bitfld.byte 0x0D 0.--3. " CHPRI ,Channel 30 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0E "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x0E 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x0E 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x0E 4.--5. " GRPPRI ,Channel 29 current group priority" "0,1,2,3" bitfld.byte 0x0E 0.--3. " CHPRI ,Channel 29 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0F "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x0F 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x0F 6. " DPA ,Disable preempt ability" "Disabled,Enabled" rbitfld.byte 0x0F 4.--5. " GRPPRI ,Channel 28 current group priority" "0,1,2,3" bitfld.byte 0x0F 0.--3. " CHPRI ,Channel 28 arbitration priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline width 21. group.long 0x1000++0x03 "eDMA Channel 0" line.long 0x00 "TCD0_SADDR,TCD Source Address Register" group.word (0x1000+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1000+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1000+0x08)&0xC0000000)==0x00)) group.long (0x1000+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1000+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1000+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1000+0x08)&0xC0000000)==0x40000000))) group.long (0x1000+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1000+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD0_DADDR,TCD Destination Address Register" group.word (0x1000+0x14)++0x1 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1000+0x16)&0x8000)==0x00)) group.word (0x1000+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1000+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1000+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1000+0x1C)&0x20)==0x20)) group.word (0x1000+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1000+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1000+0x1E)&0x8000)==0x00)) group.word (0x1000+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1000+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1020++0x03 "eDMA Channel 1" line.long 0x00 "TCD1_SADDR,TCD Source Address Register" group.word (0x1020+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1020+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1020+0x08)&0xC0000000)==0x00)) group.long (0x1020+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1020+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1020+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1020+0x08)&0xC0000000)==0x40000000))) group.long (0x1020+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1020+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD1_DADDR,TCD Destination Address Register" group.word (0x1020+0x14)++0x1 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1020+0x16)&0x8000)==0x00)) group.word (0x1020+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1020+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1020+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1020+0x1C)&0x20)==0x20)) group.word (0x1020+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1020+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1020+0x1E)&0x8000)==0x00)) group.word (0x1020+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1020+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1040++0x03 "eDMA Channel 2" line.long 0x00 "TCD2_SADDR,TCD Source Address Register" group.word (0x1040+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1040+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1040+0x08)&0xC0000000)==0x00)) group.long (0x1040+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1040+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1040+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1040+0x08)&0xC0000000)==0x40000000))) group.long (0x1040+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1040+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD2_DADDR,TCD Destination Address Register" group.word (0x1040+0x14)++0x1 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1040+0x16)&0x8000)==0x00)) group.word (0x1040+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1040+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1040+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1040+0x1C)&0x20)==0x20)) group.word (0x1040+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1040+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1040+0x1E)&0x8000)==0x00)) group.word (0x1040+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1040+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1060++0x03 "eDMA Channel 3" line.long 0x00 "TCD3_SADDR,TCD Source Address Register" group.word (0x1060+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1060+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1060+0x08)&0xC0000000)==0x00)) group.long (0x1060+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1060+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1060+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1060+0x08)&0xC0000000)==0x40000000))) group.long (0x1060+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1060+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD3_DADDR,TCD Destination Address Register" group.word (0x1060+0x14)++0x1 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1060+0x16)&0x8000)==0x00)) group.word (0x1060+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1060+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1060+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1060+0x1C)&0x20)==0x20)) group.word (0x1060+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1060+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1060+0x1E)&0x8000)==0x00)) group.word (0x1060+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1060+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1080++0x03 "eDMA Channel 4" line.long 0x00 "TCD4_SADDR,TCD Source Address Register" group.word (0x1080+0x04)++0x03 line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1080+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1080+0x08)&0xC0000000)==0x00)) group.long (0x1080+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1080+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1080+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1080+0x08)&0xC0000000)==0x40000000))) group.long (0x1080+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1080+0x0C)++0x07 line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD4_DADDR,TCD Destination Address Register" group.word (0x1080+0x14)++0x1 line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1080+0x16)&0x8000)==0x00)) group.word (0x1080+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1080+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1080+0x18)++0x03 line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1080+0x1C)&0x20)==0x20)) group.word (0x1080+0x1C)++0x01 line.word 0x00 "TCD4_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1080+0x1C)++0x01 line.word 0x00 "TCD4_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1080+0x1E)&0x8000)==0x00)) group.word (0x1080+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1080+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x10A0++0x03 "eDMA Channel 5" line.long 0x00 "TCD5_SADDR,TCD Source Address Register" group.word (0x10A0+0x04)++0x03 line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x10A0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x10A0+0x08)&0xC0000000)==0x00)) group.long (0x10A0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x10A0+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x10A0+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x10A0+0x08)&0xC0000000)==0x40000000))) group.long (0x10A0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x10A0+0x0C)++0x07 line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD5_DADDR,TCD Destination Address Register" group.word (0x10A0+0x14)++0x1 line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x10A0+0x16)&0x8000)==0x00)) group.word (0x10A0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x10A0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x10A0+0x18)++0x03 line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x10A0+0x1C)&0x20)==0x20)) group.word (0x10A0+0x1C)++0x01 line.word 0x00 "TCD5_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x10A0+0x1C)++0x01 line.word 0x00 "TCD5_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x10A0+0x1E)&0x8000)==0x00)) group.word (0x10A0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x10A0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x10C0++0x03 "eDMA Channel 6" line.long 0x00 "TCD6_SADDR,TCD Source Address Register" group.word (0x10C0+0x04)++0x03 line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x10C0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x10C0+0x08)&0xC0000000)==0x00)) group.long (0x10C0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x10C0+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x10C0+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x10C0+0x08)&0xC0000000)==0x40000000))) group.long (0x10C0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x10C0+0x0C)++0x07 line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD6_DADDR,TCD Destination Address Register" group.word (0x10C0+0x14)++0x1 line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x10C0+0x16)&0x8000)==0x00)) group.word (0x10C0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x10C0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x10C0+0x18)++0x03 line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x10C0+0x1C)&0x20)==0x20)) group.word (0x10C0+0x1C)++0x01 line.word 0x00 "TCD6_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x10C0+0x1C)++0x01 line.word 0x00 "TCD6_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x10C0+0x1E)&0x8000)==0x00)) group.word (0x10C0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x10C0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x10E0++0x03 "eDMA Channel 7" line.long 0x00 "TCD7_SADDR,TCD Source Address Register" group.word (0x10E0+0x04)++0x03 line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x10E0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x10E0+0x08)&0xC0000000)==0x00)) group.long (0x10E0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x10E0+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x10E0+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x10E0+0x08)&0xC0000000)==0x40000000))) group.long (0x10E0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x10E0+0x0C)++0x07 line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD7_DADDR,TCD Destination Address Register" group.word (0x10E0+0x14)++0x1 line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x10E0+0x16)&0x8000)==0x00)) group.word (0x10E0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x10E0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x10E0+0x18)++0x03 line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x10E0+0x1C)&0x20)==0x20)) group.word (0x10E0+0x1C)++0x01 line.word 0x00 "TCD7_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x10E0+0x1C)++0x01 line.word 0x00 "TCD7_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x10E0+0x1E)&0x8000)==0x00)) group.word (0x10E0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x10E0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1100++0x03 "eDMA Channel 8" line.long 0x00 "TCD8_SADDR,TCD Source Address Register" group.word (0x1100+0x04)++0x03 line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1100+0x08)&0xC0000000)==0x00)) group.long (0x1100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1100+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1100+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1100+0x08)&0xC0000000)==0x40000000))) group.long (0x1100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1100+0x0C)++0x07 line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD8_DADDR,TCD Destination Address Register" group.word (0x1100+0x14)++0x1 line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1100+0x16)&0x8000)==0x00)) group.word (0x1100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1100+0x18)++0x03 line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1100+0x1C)&0x20)==0x20)) group.word (0x1100+0x1C)++0x01 line.word 0x00 "TCD8_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1100+0x1C)++0x01 line.word 0x00 "TCD8_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1100+0x1E)&0x8000)==0x00)) group.word (0x1100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1120++0x03 "eDMA Channel 9" line.long 0x00 "TCD9_SADDR,TCD Source Address Register" group.word (0x1120+0x04)++0x03 line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1120+0x08)&0xC0000000)==0x00)) group.long (0x1120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1120+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1120+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1120+0x08)&0xC0000000)==0x40000000))) group.long (0x1120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1120+0x0C)++0x07 line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD9_DADDR,TCD Destination Address Register" group.word (0x1120+0x14)++0x1 line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1120+0x16)&0x8000)==0x00)) group.word (0x1120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1120+0x18)++0x03 line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1120+0x1C)&0x20)==0x20)) group.word (0x1120+0x1C)++0x01 line.word 0x00 "TCD9_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1120+0x1C)++0x01 line.word 0x00 "TCD9_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1120+0x1E)&0x8000)==0x00)) group.word (0x1120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1140++0x03 "eDMA Channel 10" line.long 0x00 "TCD10_SADDR,TCD Source Address Register" group.word (0x1140+0x04)++0x03 line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1140+0x08)&0xC0000000)==0x00)) group.long (0x1140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1140+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1140+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1140+0x08)&0xC0000000)==0x40000000))) group.long (0x1140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1140+0x0C)++0x07 line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD10_DADDR,TCD Destination Address Register" group.word (0x1140+0x14)++0x1 line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1140+0x16)&0x8000)==0x00)) group.word (0x1140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1140+0x18)++0x03 line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1140+0x1C)&0x20)==0x20)) group.word (0x1140+0x1C)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1140+0x1C)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1140+0x1E)&0x8000)==0x00)) group.word (0x1140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1160++0x03 "eDMA Channel 11" line.long 0x00 "TCD11_SADDR,TCD Source Address Register" group.word (0x1160+0x04)++0x03 line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1160+0x08)&0xC0000000)==0x00)) group.long (0x1160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1160+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1160+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1160+0x08)&0xC0000000)==0x40000000))) group.long (0x1160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1160+0x0C)++0x07 line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD11_DADDR,TCD Destination Address Register" group.word (0x1160+0x14)++0x1 line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1160+0x16)&0x8000)==0x00)) group.word (0x1160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1160+0x18)++0x03 line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1160+0x1C)&0x20)==0x20)) group.word (0x1160+0x1C)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1160+0x1C)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1160+0x1E)&0x8000)==0x00)) group.word (0x1160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x1180++0x03 "eDMA Channel 12" line.long 0x00 "TCD12_SADDR,TCD Source Address Register" group.word (0x1180+0x04)++0x03 line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x1180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1180+0x08)&0xC0000000)==0x00)) group.long (0x1180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x1180+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x1180+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x1180+0x08)&0xC0000000)==0x40000000))) group.long (0x1180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1180+0x0C)++0x07 line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD12_DADDR,TCD Destination Address Register" group.word (0x1180+0x14)++0x1 line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x1180+0x16)&0x8000)==0x00)) group.word (0x1180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1180+0x18)++0x03 line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x1180+0x1C)&0x20)==0x20)) group.word (0x1180+0x1C)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1180+0x1C)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x1180+0x1E)&0x8000)==0x00)) group.word (0x1180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x11A0++0x03 "eDMA Channel 13" line.long 0x00 "TCD13_SADDR,TCD Source Address Register" group.word (0x11A0+0x04)++0x03 line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x11A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x11A0+0x08)&0xC0000000)==0x00)) group.long (0x11A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x11A0+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x11A0+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x11A0+0x08)&0xC0000000)==0x40000000))) group.long (0x11A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x11A0+0x0C)++0x07 line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD13_DADDR,TCD Destination Address Register" group.word (0x11A0+0x14)++0x1 line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x11A0+0x16)&0x8000)==0x00)) group.word (0x11A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x11A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x11A0+0x18)++0x03 line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x11A0+0x1C)&0x20)==0x20)) group.word (0x11A0+0x1C)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x11A0+0x1C)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x11A0+0x1E)&0x8000)==0x00)) group.word (0x11A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x11A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x11C0++0x03 "eDMA Channel 14" line.long 0x00 "TCD14_SADDR,TCD Source Address Register" group.word (0x11C0+0x04)++0x03 line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x11C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x11C0+0x08)&0xC0000000)==0x00)) group.long (0x11C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x11C0+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x11C0+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x11C0+0x08)&0xC0000000)==0x40000000))) group.long (0x11C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x11C0+0x0C)++0x07 line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD14_DADDR,TCD Destination Address Register" group.word (0x11C0+0x14)++0x1 line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x11C0+0x16)&0x8000)==0x00)) group.word (0x11C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x11C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x11C0+0x18)++0x03 line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x11C0+0x1C)&0x20)==0x20)) group.word (0x11C0+0x1C)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x11C0+0x1C)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x11C0+0x1E)&0x8000)==0x00)) group.word (0x11C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x11C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif group.long 0x11E0++0x03 "eDMA Channel 15" line.long 0x00 "TCD15_SADDR,TCD Source Address Register" group.word (0x11E0+0x04)++0x03 line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "Disabled,1,2,3,4,5,6,7" else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." endif if (((per.l(ad:0x40008000)&0x80)==0x00)) group.long (0x11E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count Register" hexmask.long 0x00 0.--31. 1. " NBYTES ,Minor byte transfer count" elif (((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x11E0+0x08)&0xC0000000)==0x00)) group.long (0x11E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset Register(Minor Loop Mapping Enabled and Offset Disabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" elif ((((per.l(ad:0x40008000)&0x80)==0x80))&&(((per.l(ad:0x40008000+0x11E0+0x08)&0xC0000000)==0xC0000000)||((per.l(ad:0x40008000+0x11E0+0x08)&0xC0000000)==0x80000000)||((per.l(ad:0x40008000+0x11E0+0x08)&0xC0000000)==0x40000000))) group.long (0x11E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset Register(Minor Loop Mapping and Offset Enabled)" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" newline hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x11E0+0x0C)++0x07 line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment Register" line.long 0x04 "TCD15_DADDR,TCD Destination Address Register" group.word (0x11E0+0x14)++0x1 line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset Register" if (((per.l(ad:0x40008000+0x11E0+0x16)&0x8000)==0x00)) group.word (0x11E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x11E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x11E0+0x18)++0x03 line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address Register" newline if (((per.l(ad:0x40008000+0x11E0+0x1C)&0x20)==0x20)) group.word (0x11E0+0x1C)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x11E0+0x1C)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status Register" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA engine stalls,,Stalls for 4 cycles after each R/W,Stalls for 8 cycles after each R/W" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "Disabled,?..." newline bitfld.word 0x00 7. " DONE ,eDMA has completed the major loop" "Not completed,Completed" rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,eDMA hardware auto clear the corresponding ERQ bit when the current major iteration count reaches zero" "Not cleared,Cleared" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif if (((per.l(ad:0x40008000+0x11E0+0x1E)&0x8000)==0x00)) group.word (0x11E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x11E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link/Major Loop Count Register" bitfld.word 0x00 15. " ELINK ,Enables channel-to-channel linking on minor loop complete" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "TRGMUX (Trigger MUX Control)" base ad:0x40063000 width 12. if ((per.l(ad:0x40063000+0x00)&0x80000000)==0x80000000) rgroup.long 0x00++0x03 line.long 0x00 "DMAMUX0,DMAMUX0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x00++0x03 line.long 0x00 "DMAMUX0,DMAMUX0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x04)&0x80000000)==0x80000000) rgroup.long 0x04++0x03 line.long 0x00 "EXTOUT0,EXTOUT0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x04++0x03 line.long 0x00 "EXTOUT0,EXTOUT0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x08)&0x80000000)==0x80000000) rgroup.long 0x08++0x03 line.long 0x00 "EXTOUT1,EXTOUT1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x08++0x03 line.long 0x00 "EXTOUT1,EXTOUT1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x0C)&0x80000000)==0x80000000) rgroup.long 0x0C++0x03 line.long 0x00 "ADC0,ADC0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x0C++0x03 line.long 0x00 "ADC0,ADC0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x10)&0x80000000)==0x80000000) rgroup.long 0x10++0x03 line.long 0x00 "ADC1,ADC1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x10++0x03 line.long 0x00 "ADC1,ADC1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x1C)&0x80000000)==0x80000000) rgroup.long 0x1C++0x03 line.long 0x00 "CMP0,CMP0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x1C++0x03 line.long 0x00 "CMP0,CMP0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x28)&0x80000000)==0x80000000) rgroup.long 0x28++0x03 line.long 0x00 "FTM0,FTM0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x28++0x03 line.long 0x00 "FTM0,FTM0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x2C)&0x80000000)==0x80000000) rgroup.long 0x2C++0x03 line.long 0x00 "FTM1,FTM1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x2C++0x03 line.long 0x00 "FTM1,FTM1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x30)&0x80000000)==0x80000000) rgroup.long 0x30++0x03 line.long 0x00 "FTM2,FTM2 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x30++0x03 line.long 0x00 "FTM2,FTM2 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x34)&0x80000000)==0x80000000) rgroup.long 0x34++0x03 line.long 0x00 "FTM3,FTM3 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x34++0x03 line.long 0x00 "FTM3,FTM3 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x38)&0x80000000)==0x80000000) rgroup.long 0x38++0x03 line.long 0x00 "PDB0,PDB0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x38++0x03 line.long 0x00 "PDB0,PDB0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x3C)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "PDB1,PDB1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x3C++0x03 line.long 0x00 "PDB1,PDB1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x44)&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "FLEXIO,FLEXIO Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x44++0x03 line.long 0x00 "FLEXIO,FLEXIO Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x48)&0x80000000)==0x80000000) rgroup.long 0x48++0x03 line.long 0x00 "LPIT0,LPIT0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x48++0x03 line.long 0x00 "LPIT0,LPIT0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 24.--30. " SEL3 ,Trigger MUX input 3 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 16.--22. " SEL2 ,Trigger MUX input 2 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 8.--14. " SEL1 ,Trigger MUX input 1 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x4C)&0x80000000)==0x80000000) rgroup.long 0x4C++0x03 line.long 0x00 "LPUART0,LPUART0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x4C++0x03 line.long 0x00 "LPUART0,LPUART0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x50)&0x80000000)==0x80000000) rgroup.long 0x50++0x03 line.long 0x00 "LPUART1,LPUART1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x50++0x03 line.long 0x00 "LPUART1,LPUART1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x54)&0x80000000)==0x80000000) rgroup.long 0x54++0x03 line.long 0x00 "LPI2C0,LPI2C0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x54++0x03 line.long 0x00 "LPI2C0,LPI2C0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x5C)&0x80000000)==0x80000000) rgroup.long 0x5C++0x03 line.long 0x00 "LPSPI0,LPSPI0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x5C++0x03 line.long 0x00 "LPSPI0,LPSPI0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x60)&0x80000000)==0x80000000) rgroup.long 0x60++0x03 line.long 0x00 "LPSPI1,LPSPI1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x60++0x03 line.long 0x00 "LPSPI1,LPSPI1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if (per.l(ad:0x40063000+0x64)&0x80000000)==0x80000000 rgroup.long 0x64++0x03 line.long 0x00 "LPTMR0,LPTMR0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x64++0x03 line.long 0x00 "LPTMR0,LPTMR0 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." elif cpuis("MWCT1014S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif sif !cpuis("MWCT1015S")&&!cpuis("MWCT1014S") if ((per.l(ad:0x40063000+0x6C)&0x80000000)==0x80000000) rgroup.long 0x6C++0x03 line.long 0x00 "LPI2C1,LPI2C1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." else group.long 0x6C++0x03 line.long 0x00 "LPI2C1,LPI2C1 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif sif !cpuis("MWCT1014S") if ((per.l(ad:0x40063000+0x70)&0x80000000)==0x80000000) rgroup.long 0x70++0x03 line.long 0x00 "FTM4,FTM4 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x70++0x03 line.long 0x00 "FTM4,FTM4 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif if ((per.l(ad:0x40063000+0x74)&0x80000000)==0x80000000) rgroup.long 0x74++0x03 line.long 0x00 "FTM5,FTM5 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif else group.long 0x74++0x03 line.long 0x00 "FTM5,FTM5 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" sif cpuis("MWCT1015S") bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,,,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,?..." else bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif endif sif !cpuis("MWCT1015S")&&!cpuis("MWCT1014S") if ((per.l(ad:0x40063000+0x78)&0x80000000)==0x80000000) rgroup.long 0x78++0x03 line.long 0x00 "FTM6,FTM6 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." else group.long 0x78++0x03 line.long 0x00 "FTM6,FTM6 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif if ((per.l(ad:0x40063000+0x7C)&0x80000000)==0x80000000) rgroup.long 0x7C++0x03 line.long 0x00 "FTM7,FTM7 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." else group.long 0x7C++0x03 line.long 0x00 "FTM7,FTM7 Register" bitfld.long 0x00 31. " LK ,Register lock" "Unlocked,Locked" bitfld.long 0x00 0.--6. " SEL0 ,Trigger MUX input 0 source select" ",VDD,TRGMUX_IN0,TRGMUX_IN1,TRGMUX_IN2,TRGMUX_IN3,TRGMUX_IN4,TRGMUX_IN5,TRGMUX_IN6,TRGMUX_IN7,TRGMUX_IN8,TRGMUX_IN9,TRGMUX_IN10,TRGMUX_IN11,CMP0_OUT,,,LPIT_CH0,LPIT_CH1,LPIT_CH2,LPIT_CH3,LPTMR0,FTM0_INIT_TRIG,FTM0_EXT_TRIG,FTM1_INIT_TRIG,FTM1_EXT_TRIG,FTM2_INIT_TRIG,FTM2_EXT_TRIG,FTM3_INIT_TRIG,FTM3_EXT_TRIG,ADC0_SC1A[COCO],ADC0_SC1B[COCO],ADC1_SC1A[COCO],ADC1_SC1B[COCO],PDB0_CH0_TRIG,,PDB0_PULSE_OUT,PDB1_CH0_TRIG,,PDB1_PULSE_OUT,,,,RTC_alarm,RTC_second,FlexIO_TRIG0,FlexIO_TRIG1,FlexIO_TRIG2,FlexIO_TRIG3,LPUART0_RX_data,LPUART0_TX_data,LPUART0_RX_idle,LPUART1_RX_data,LPUART1_TX_data,LPUART1_RX_idle,LPI2C0_Master_trigger,LPI2C0_Slave_trigger,,,LPSPI0_Frame,LPSPI0_RX_data,LPSPI1_Frame,LPSPI1_RX_data,SIM_SW_TRIG,,,,LPI2C1_Master_trigger,LPI2C1_Slave_trigger,FTM4_INIT_TRIG,FTM4_EXT_TRIG,FTM5_INIT_TRIG,FTM5_EXT_TRIG,FTM6_INIT_TRIG,FTM6_EXT_TRIG,FTM7_INIT_TRIG,FTM7_EXT_TRIG,?..." endif endif width 0x0B tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " INEN ,Input enable" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,EWM_in's assertion state select" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High Register" group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" width 0x0B tree.end tree "EIM (Error Injection Module)" base ad:0x40019000 width 15. group.long 0x00++0x03 line.long 0x00 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x00 0. " GEIEN ,Global error injection enable" "Disabled,Enabled" if (((per.l(ad:0x40019000+0x00))&0x01)==0x01) group.long 0x04++0x03 line.long 0x00 "EICHEN,Error Injection Channel Enable Register" bitfld.long 0x00 31. " EICHEN[0] ,Error injection channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Error injection channel 1 enable" "Disabled,Enabled" else hgroup.long 0x04++0x03 hide.long 0x00 "EICHEN,Error Injection Channel Enable Register" endif group.long 0x100++0x07 "Channel 0" line.long 0x00 "EICHD0_WORD0,Error Injection Channel 0 Descriptor- Word0 Register" bitfld.long 0x00 31. " CHKBIT_MASK[31] ,Check bit mask 31" "Unmodified,Inverted" bitfld.long 0x00 30. " [30] ,Check bit mask 30" "Unmodified,Inverted" bitfld.long 0x00 29. " [29] ,Check bit mask 29" "Unmodified,Inverted" bitfld.long 0x00 28. " [28] ,Check bit mask 28" "Unmodified,Inverted" newline bitfld.long 0x00 27. " [27] ,Check bit mask 27" "Unmodified,Inverted" bitfld.long 0x00 26. " [26] ,Check bit mask 26" "Unmodified,Inverted" bitfld.long 0x00 25. " [25] ,Check bit mask 25" "Unmodified,Inverted" line.long 0x04 "EICHD0_WORD1,Error Injection Channel 0 Descriptor- Word1 Register" bitfld.long 0x04 31. " B0_3DATA_MASK[31] ,Data mask bytes 0-3 bit 31" "Unmodified,Inverted" bitfld.long 0x04 30. " [30] ,Data mask bytes 0-3 bit 30" "Unmodified,Inverted" bitfld.long 0x04 29. " [29] ,Data mask bytes 0-3 bit 29" "Unmodified,Inverted" bitfld.long 0x04 28. " [28] ,Data mask bytes 0-3 bit 28" "Unmodified,Inverted" newline bitfld.long 0x04 27. " [27] ,Data mask bytes 0-3 bit 27" "Unmodified,Inverted" bitfld.long 0x04 26. " [26] ,Data mask bytes 0-3 bit 26" "Unmodified,Inverted" bitfld.long 0x04 25. " [25] ,Data mask bytes 0-3 bit 25" "Unmodified,Inverted" bitfld.long 0x04 24. " [24] ,Data mask bytes 0-3 bit 24" "Unmodified,Inverted" newline bitfld.long 0x04 23. " [23] ,Data mask bytes 0-3 bit 23" "Unmodified,Inverted" bitfld.long 0x04 22. " [22] ,Data mask bytes 0-3 bit 22" "Unmodified,Inverted" bitfld.long 0x04 21. " [21] ,Data mask bytes 0-3 bit 21" "Unmodified,Inverted" bitfld.long 0x04 20. " [20] ,Data mask bytes 0-3 bit 20" "Unmodified,Inverted" newline bitfld.long 0x04 19. " [19] ,Data mask bytes 0-3 bit 19" "Unmodified,Inverted" bitfld.long 0x04 18. " [18] ,Data mask bytes 0-3 bit 18" "Unmodified,Inverted" bitfld.long 0x04 17. " [17] ,Data mask bytes 0-3 bit 17" "Unmodified,Inverted" bitfld.long 0x04 16. " [16] ,Data mask bytes 0-3 bit 16" "Unmodified,Inverted" newline bitfld.long 0x04 15. " [15] ,Data mask bytes 0-3 bit 15" "Unmodified,Inverted" bitfld.long 0x04 14. " [14] ,Data mask bytes 0-3 bit 14" "Unmodified,Inverted" bitfld.long 0x04 13. " [13] ,Data mask bytes 0-3 bit 13" "Unmodified,Inverted" bitfld.long 0x04 12. " [12] ,Data mask bytes 0-3 bit 12" "Unmodified,Inverted" newline bitfld.long 0x04 11. " [11] ,Data mask bytes 0-3 bit 11" "Unmodified,Inverted" bitfld.long 0x04 10. " [10] ,Data mask bytes 0-3 bit 10" "Unmodified,Inverted" bitfld.long 0x04 9. " [9] ,Data mask bytes 0-3 bit 9" "Unmodified,Inverted" bitfld.long 0x04 8. " [8] ,Data mask bytes 0-3 bit 8" "Unmodified,Inverted" newline bitfld.long 0x04 7. " [7] ,Data mask bytes 0-3 bit 7" "Unmodified,Inverted" bitfld.long 0x04 6. " [6] ,Data mask bytes 0-3 bit 6" "Unmodified,Inverted" bitfld.long 0x04 5. " [5] ,Data mask bytes 0-3 bit 5" "Unmodified,Inverted" bitfld.long 0x04 4. " [4] ,Data mask bytes 0-3 bit 4" "Unmodified,Inverted" newline bitfld.long 0x04 3. " [3] ,Data mask bytes 0-3 bit 3" "Unmodified,Inverted" bitfld.long 0x04 2. " [2] ,Data mask bytes 0-3 bit 2" "Unmodified,Inverted" bitfld.long 0x04 1. " [1] ,Data mask bytes 0-3 bit 1" "Unmodified,Inverted" bitfld.long 0x04 0. " [0] ,Data mask bytes 0-3 bit 0" "Unmodified,Inverted" group.long 0x200++0x07 "Channel 1" line.long 0x00 "EICHD1_WORD0,Error Injection Channel 1 Descriptor- Word0 Register" bitfld.long 0x00 31. " CHKBIT_MASK[31] ,Check bit mask 31" "Unmodified,Inverted" bitfld.long 0x00 30. " [30] ,Check bit mask 30" "Unmodified,Inverted" bitfld.long 0x00 29. " [29] ,Check bit mask 29" "Unmodified,Inverted" bitfld.long 0x00 28. " [28] ,Check bit mask 28" "Unmodified,Inverted" newline bitfld.long 0x00 27. " [27] ,Check bit mask 27" "Unmodified,Inverted" bitfld.long 0x00 26. " [26] ,Check bit mask 26" "Unmodified,Inverted" bitfld.long 0x00 25. " [25] ,Check bit mask 25" "Unmodified,Inverted" line.long 0x04 "EICHD1_WORD1,Error Injection Channel 1 Descriptor- Word1 Register" bitfld.long 0x04 31. " B0_3DATA_MASK[31] ,Data mask bytes 0-3 bit 31" "Unmodified,Inverted" bitfld.long 0x04 30. " [30] ,Data mask bytes 0-3 bit 30" "Unmodified,Inverted" bitfld.long 0x04 29. " [29] ,Data mask bytes 0-3 bit 29" "Unmodified,Inverted" bitfld.long 0x04 28. " [28] ,Data mask bytes 0-3 bit 28" "Unmodified,Inverted" newline bitfld.long 0x04 27. " [27] ,Data mask bytes 0-3 bit 27" "Unmodified,Inverted" bitfld.long 0x04 26. " [26] ,Data mask bytes 0-3 bit 26" "Unmodified,Inverted" bitfld.long 0x04 25. " [25] ,Data mask bytes 0-3 bit 25" "Unmodified,Inverted" bitfld.long 0x04 24. " [24] ,Data mask bytes 0-3 bit 24" "Unmodified,Inverted" newline bitfld.long 0x04 23. " [23] ,Data mask bytes 0-3 bit 23" "Unmodified,Inverted" bitfld.long 0x04 22. " [22] ,Data mask bytes 0-3 bit 22" "Unmodified,Inverted" bitfld.long 0x04 21. " [21] ,Data mask bytes 0-3 bit 21" "Unmodified,Inverted" bitfld.long 0x04 20. " [20] ,Data mask bytes 0-3 bit 20" "Unmodified,Inverted" newline bitfld.long 0x04 19. " [19] ,Data mask bytes 0-3 bit 19" "Unmodified,Inverted" bitfld.long 0x04 18. " [18] ,Data mask bytes 0-3 bit 18" "Unmodified,Inverted" bitfld.long 0x04 17. " [17] ,Data mask bytes 0-3 bit 17" "Unmodified,Inverted" bitfld.long 0x04 16. " [16] ,Data mask bytes 0-3 bit 16" "Unmodified,Inverted" newline bitfld.long 0x04 15. " [15] ,Data mask bytes 0-3 bit 15" "Unmodified,Inverted" bitfld.long 0x04 14. " [14] ,Data mask bytes 0-3 bit 14" "Unmodified,Inverted" bitfld.long 0x04 13. " [13] ,Data mask bytes 0-3 bit 13" "Unmodified,Inverted" bitfld.long 0x04 12. " [12] ,Data mask bytes 0-3 bit 12" "Unmodified,Inverted" newline bitfld.long 0x04 11. " [11] ,Data mask bytes 0-3 bit 11" "Unmodified,Inverted" bitfld.long 0x04 10. " [10] ,Data mask bytes 0-3 bit 10" "Unmodified,Inverted" bitfld.long 0x04 9. " [9] ,Data mask bytes 0-3 bit 9" "Unmodified,Inverted" bitfld.long 0x04 8. " [8] ,Data mask bytes 0-3 bit 8" "Unmodified,Inverted" newline bitfld.long 0x04 7. " [7] ,Data mask bytes 0-3 bit 7" "Unmodified,Inverted" bitfld.long 0x04 6. " [6] ,Data mask bytes 0-3 bit 6" "Unmodified,Inverted" bitfld.long 0x04 5. " [5] ,Data mask bytes 0-3 bit 5" "Unmodified,Inverted" bitfld.long 0x04 4. " [4] ,Data mask bytes 0-3 bit 4" "Unmodified,Inverted" newline bitfld.long 0x04 3. " [3] ,Data mask bytes 0-3 bit 3" "Unmodified,Inverted" bitfld.long 0x04 2. " [2] ,Data mask bytes 0-3 bit 2" "Unmodified,Inverted" bitfld.long 0x04 1. " [1] ,Data mask bytes 0-3 bit 1" "Unmodified,Inverted" bitfld.long 0x04 0. " [0] ,Data mask bytes 0-3 bit 0" "Unmodified,Inverted" width 0x0B tree.end tree "ERM (Error Reporting Module)" base ad:0x40018000 width 7. group.long 0x00++0x03 line.long 0x00 "CR0,ERM Configuration 0 Register" bitfld.long 0x00 31. " ESCIE0 ,Enable memory 0 single correction interrupt notification" "Disabled,Enabled" bitfld.long 0x00 30. " ENCIE0 ,Enable memory 0 non-correctable interrupt notification" "Disabled,Enabled" bitfld.long 0x00 27. " ESCIE1 ,Enable memory 1 single correction interrupt notification" "Disabled,Enabled" bitfld.long 0x00 26. " ENCIE1 ,Enable memory 1 non-correctable interrupt notification" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "SR0,ERM Status 0 Register" eventfld.long 0x00 31. " SBC0 ,Memory 0 single-bit correction event" "Not occurred,Occurred" eventfld.long 0x00 30. " NCE0 ,Memory 0 non-correctable error event" "No error,Error" eventfld.long 0x00 27. " SBC1 ,Memory 1 single-bit correction event" "Not occurred,Occurred" eventfld.long 0x00 26. " NCE1 ,Memory 1 non-correctable error event" "No error,Error" rgroup.long 0x100++0x03 line.long 0x00 "EAR0,ERM Memory 0 Error Address Register" rgroup.long 0x110++0x03 line.long 0x00 "EAR1,ERM Memory 1 Error Address Register" width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 7. group.long 0x00++0x0F line.long 0x00 "CS,Watchdog Control And Status Register" bitfld.long 0x00 15. " WIN ,Watchdog window" "Disabled,Enabled" eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " CMD32EN ,Enables or disables WDOG support for 32-bit" "Disabled,Enabled" bitfld.long 0x00 12. " PRES ,Watchdog prescaler" "Disabled,Enabled" newline rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked" rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "No success,Success" bitfld.long 0x00 8.--9. " CLK ,Watchdog clock" "Bus,LPO,INTCLK,ERCLK" bitfld.long 0x00 7. " EN ,Watchdog enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed" bitfld.long 0x00 3.--4. " TST ,Watchdog test" "Disabled,User mode,Enabled for LB,Enabled for HB" bitfld.long 0x00 2. " DBG ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " WAIT ,Wait enable" "Disabled,Enabled" bitfld.long 0x00 0. " STOP ,Stop enable" "Disabled,Enabled" line.long 0x04 "CNT,Watchdog Counter Register" hexmask.long.byte 0x04 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter" hexmask.long.byte 0x04 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter" line.long 0x08 "TOVAL,Watchdog Timeout Value Register" hexmask.long.byte 0x08 8.--15. 1. " TOVALHIGH ,High byte of the timeout value" hexmask.long.byte 0x08 0.--7. 1. " TOVALLOW ,Low byte of the timeout value" line.long 0x0C "WIN,Watchdog Window Register" hexmask.long.byte 0x0C 8.--15. 1. " WINHIGH ,High byte of watchdog window" hexmask.long.byte 0x0C 0.--7. 1. " WINLOW ,Low byte of watchdog window" width 0x0B tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40032000 width 7. if (per.l(ad:0x40032000+0x08)&0x1000000)==0x1000000 group.long 0x00++0x07 line.long 0x00 "DATA,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal half-word" hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" else group.long 0x00++0x07 line.long 0x00 "DATA,CRC Data Register" textfld " " hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" textfld " " hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" endif group.long 0x08++0x03 line.long 0x00 "CTRL,CRC Control Register" bitfld.long 0x00 30.--31. " TOT ,Type of transpose for writes" "No transposition,Only bits,Bits and bytes,Only bytes" bitfld.long 0x00 28.--29. " TOTR ,Type of transpose for read" "No transposition,Only bits,Bits and bytes,Only bytes" newline bitfld.long 0x00 26. " FXOR ,Complement read of CRC data register" "Not XORed,XORed" bitfld.long 0x00 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" bitfld.long 0x00 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" width 0x0B tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 7. rgroup.long 0x00++0x0B line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 16. " ECORE1 ,Existence of SRS[CORE1] status indication feature" "Not available,Available" bitfld.long 0x04 15. " ETAMPER ,Existence of SRS[TAMPER] status indication feature" "Not available,Available" bitfld.long 0x04 13. " ESACKERR ,Existence of SRS[SACKERR] status indication feature" "Not available,Available" bitfld.long 0x04 11. " EMDM_AP ,Existence of SRS[MDM_AP] status indication feature" "Not available,Available" newline bitfld.long 0x04 10. " ESW ,Existence of SRS[SW] status indication feature" "Not available,Available" bitfld.long 0x04 9. " ELOCKUP ,Existence of SRS[LOCKUP] status indication feature" "Not available,Available" bitfld.long 0x04 8. " EJTAG ,Existence of SRS[JTAG] status indication feature" "Not available,Available" bitfld.long 0x04 7. " EPOR ,Existence of SRS[POR] status indication feature" "Not available,Available" newline bitfld.long 0x04 6. " EPIN ,Existence of SRS[PIN] status indication feature" "Not available,Available" bitfld.long 0x04 5. " EWDOG ,Existence of SRS[WDOG] status indication feature" "Not available,Available" newline sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x04 4. " ECMU_LOC ,Existence of SRS[CMU_LOC] status indication feature" "Not available,Available" bitfld.long 0x04 3. " ELOL ,Existence of SRS[LOL] status indication feature" "Not available,Available" bitfld.long 0x04 2. " ELOC ,Existence of SRS[LOC] status indication feature" "Not available,Available" else bitfld.long 0x04 3. " ELOL ,Existence of SRS[LOL] status indication feature" "Not available,Available" bitfld.long 0x04 2. " ELOC ,Existence of SRS[LOC] status indication feature" "Not available,Available" endif newline bitfld.long 0x04 1. " ELVD ,Existence of SRS[LVD] status indication feature" "Not available,Available" bitfld.long 0x04 0. " EWAKEUP ,Existence of SRS[WAKEUP] status indication feature" "Not available,Available" line.long 0x08 "SRS,System Reset Status Register" bitfld.long 0x08 13. " SACKERR ,Stop acknowledge error reset" "No reset,Reset" bitfld.long 0x08 11. " MDM_AP ,MDM-AP system reset" "No reset,Reset" bitfld.long 0x08 10. " SW ,Software reset" "No reset,Reset" bitfld.long 0x08 9. " LOCKUP ,Core lockup reset" "No reset,Reset" newline bitfld.long 0x08 8. " JTAG ,JTAG generated reset" "No reset,Reset" bitfld.long 0x08 7. " POR ,Power-On reset" "No reset,Reset" bitfld.long 0x08 6. " PIN ,External reset pin" "No reset,Reset" bitfld.long 0x08 5. " WDOG ,Watchdog reset" "No reset,Reset" newline bitfld.long 0x08 3. " LOL ,Loss-of-Lock reset" "No reset,Reset" bitfld.long 0x08 2. " LOC ,Loss-of-Clock reset" "No reset,Reset" bitfld.long 0x08 1. " LVD ,Low-Voltage/High-Voltage detect reset" "No reset,Reset" group.long 0x0C++0x03 line.long 0x00 "RPC,Reset Pin Control Register" bitfld.long 0x00 8.--12. " RSTFLTSEL ,Reset pin filter bus clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "All filtering disabled,LPO clock filter enabled" bitfld.long 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All filtering disabled,Bus clock filter enabled,LPO clock filter enabled,?..." group.long 0x18++0x07 line.long 0x00 "SSRS,Sticky System Reset Status Register" eventfld.long 0x00 13. " SSACKERR ,Sticky stop acknowledge error reset" "No reset,Reset" eventfld.long 0x00 11. " SMDM_AP ,Sticky MDM-AP system reset" "No reset,Reset" eventfld.long 0x00 10. " SSW ,Sticky software reset" "No reset,Reset" eventfld.long 0x00 9. " SLOCKUP ,Sticky core lockup reset" "No reset,Reset" newline eventfld.long 0x00 8. " SJTAG ,Sticky JTAG generated reset" "No reset,Reset" eventfld.long 0x00 7. " SPOR ,Sticky Power-On reset" "No reset,Reset" eventfld.long 0x00 6. " SPIN ,Sticky external reset pin" "No reset,Reset" eventfld.long 0x00 5. " SWDOG ,Sticky watchdog reset" "No reset,Reset" newline eventfld.long 0x00 3. " SLOL ,Sticky Loss-of-Lock reset" "No reset,Reset" eventfld.long 0x00 2. " SLOC ,Sticky Loss-of-Clock reset" "No reset,Reset" eventfld.long 0x00 1. " SLVD ,Sticky Low-Voltage detect reset" "No reset,Reset" line.long 0x04 "SRIE,System Reset Interrupt Enable Register" bitfld.long 0x04 13. " SACKERR ,Stop acknowledge error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " MDM_AP ,Sticky MDM-AP system interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " SW ,Software interrupt enable" "Disabled,Enabled" bitfld.long 0x04 9. " LOCKUP ,Core lockup interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " JTAG ,JTAG generated reset interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " GIE ,Global interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " PIN ,External reset pin interrupt" "No reset,Reset" bitfld.long 0x04 5. " WDOG ,Watchdog interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " LOL ,Loss-of-Lock interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " LOC ,Loss-of-Clock interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " DELAY ,Reset delay time" "10 LPO cycles,34 LPO cycles,130 LPO cycles,514 LPO cycles" width 0x0B tree.end tree "SCG (System Clock Generator)" base ad:0x40064000 width 12. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 31. " DIVPRES[31] ,DIVCORE divider present" "Absent,Present" newline sif (cpuis("K32W*")) bitfld.long 0x04 30. " [30] ,DIVCORE divider present" "Absent,Present" bitfld.long 0x04 29. " [29] ,DIVEXT divider present" "Absent,Present" endif sif !cpuis("MKL28Z*") bitfld.long 0x04 28. " [28] ,DIVBUS divider present" "Absent,Present" newline endif bitfld.long 0x04 27. " [27] ,DIVSLOW divider present" "Absent,Present" newline sif !cpuis("K32W*") bitfld.long 0x04 6. " CLKPRES[6] ,System PLL clock present" "Absent,Present" endif newline sif (cpuis("K32W*")) bitfld.long 0x04 5. " [5] ,System PLL clock present" "Absent,Present" bitfld.long 0x04 4. " [4] ,System PLL clock present" "Absent,Present" endif bitfld.long 0x04 3. " [3] ,Fast IRC clock present" "Absent,Present" bitfld.long 0x04 2. " [2] ,Slow IRC clock present" "Absent,Present" newline bitfld.long 0x04 1. " [1] ,System OSC clock present" "Absent,Present" rgroup.long 0x10++0x03 line.long 0x00 "CSR,Clock Status Register" bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..." bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif (cpuis("K32W*")) bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif newline sif cpuis("MKL28Z*") bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." endif group.long 0x14++0x07 line.long 0x00 "RCCR,Run Clock Control Register" sif (cpuis("K32W*")) bitfld.long 0x00 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..." else bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..." endif bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif (cpuis("K32W*")) bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif newline sif !cpuis("MKL28Z*") bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." newline else bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif line.long 0x04 "VCCR,VLPR Clock Control Register" sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..." bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" elif cpuis("MKL28Z*") bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..." bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." elif cpuis("S32MTV") bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..." bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." elif (cpuis("K32W*")) bitfld.long 0x04 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,,ROSC_CLK,?..." bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..." bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." else bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..." bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 8.--11. " DIVEXT ,External Clock Divide Ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." endif sif (!cpuis("S32MTV")) group.long 0x1C++0x03 line.long 0x00 "HCCR,HSRUN Clock Control Register" sif (cpuis("K32W*")) bitfld.long 0x00 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..." else bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..." endif bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif (cpuis("K32W*")) bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif newline sif cpuis("MKL28Z*") bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" elif (cpuis("K32W*")) bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..." endif endif group.long 0x20++0x03 line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register" sif (cpuis("K32W*")) bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG clkout select" "SCG_EXTERNAL_CLOCK,SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..." else bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG clkout select" "SCG SLOW clock,System OSC,Slow IRC,Fast IRC,,,System PLL,?..." endif if (((per.l(ad:0x40064000+0x100))&0x800000)==0x800000) group.long 0x100++0x03 line.long 0x00 "SOSCCSR,System OSC Control Status Register" rbitfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error" rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected" rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" newline rbitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled" sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*")) newline rbitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled" elif cpuis("MKL28Z*") newline bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled" bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled" bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled" else rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled" endif else group.long 0x100++0x03 line.long 0x00 "SOSCCSR,System OSC Control Status Register" eventfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error" rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected" rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" newline bitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled" bitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled" sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*")) newline bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled" bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled" elif cpuis("MKL28Z*") newline bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled" bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled" bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled" else bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40064000+0x100))&0x01)==0x01) rgroup.long 0x104++0x03 line.long 0x00 "SOSCDIV,System OSC Divide Register" sif (cpuis("K32W*"))||cpuis("MKL28Z*") bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" sif (!cpuis("K32W*")) rgroup.long 0x108++0x03 line.long 0x00 "SOSCCFG,System Oscillator Configuration Register" sif cpuis("MKL28Z*") bitfld.long 0x00 11. " SC2P ,Oscillator 2 pF capacitor load" "0,1" bitfld.long 0x00 10. " SC4P ,Oscillator 4 pF capacitor load" "0,1" bitfld.long 0x00 9. " SC8P ,Oscillator 8 pF capacitor load" "0,1" bitfld.long 0x00 8. " SC16P ,Oscillator 16 pF capacitor load" "0,1" newline endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",,4 Mhz-8 Mhz,8 Mhz-40 Mhz" else bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz" endif bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-gain,High-gain" bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal" endif else group.long 0x104++0x03 line.long 0x00 "SOSCDIV,System OSC Divide Register" sif (cpuis("K32W*"))||cpuis("MKL28Z*") bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" sif (!cpuis("K32W*")) group.long 0x108++0x03 line.long 0x00 "SOSCCFG,System Oscillator Configuration Register" sif cpuis("MKL28Z*") bitfld.long 0x00 11. " SC2P ,Oscillator 2 pF capacitor load" "0,1" bitfld.long 0x00 10. " SC4P ,Oscillator 4 pF capacitor load" "0,1" bitfld.long 0x00 9. " SC8P ,Oscillator 8 pF capacitor load" "0,1" bitfld.long 0x00 8. " SC16P ,Oscillator 16 pF capacitor load" "0,1" newline endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",,4 Mhz-8 Mhz,8 Mhz-40 Mhz" else bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz" endif bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-gain,High-gain" bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal" endif endif if (((per.l(ad:0x40064000+0x200))&0x800000)==0x800000) group.long 0x200++0x03 line.long 0x00 "SIRCCSR,Slow IRC Control Status Register" rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected" rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" rbitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "SIRCCSR,Slow IRC Control Status Register" rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected" rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" bitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled" bitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled" endif if (((per.l(ad:0x40064000+0x200))&0x01)==0x01) rgroup.long 0x204++0x07 line.long 0x00 "SIRCDIV,Slow IRC Divide Register" sif (cpuis("K32W*"))||cpuis("MKL28Z*") bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" line.long 0x04 "SIRCCFG,Slow IRC Configuration Register" sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x04 0. " RANGE ,Frequency range" ",8 MHz" else bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz" endif else group.long 0x204++0x07 line.long 0x00 "SIRCDIV,Slow IRC Divide Register" sif (cpuis("K32W*"))||cpuis("MKL28Z*") bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" line.long 0x04 "SIRCCFG,Slow IRC Configuration Register" sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x04 0. " RANGE ,Frequency range" ",8 MHz" else bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz" endif endif if (((per.l(ad:0x40064000+0x300))&0x800000)==0x800000) group.long 0x300++0x03 line.long 0x00 "FIRCCSR,Fast IRC Control Status Register" rbitfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error" rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected" rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" newline sif (!cpuis("S32MTV")) rbitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled" rbitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled" endif rbitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled" newline sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))||cpuis("MKL28Z*") rbitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled" else rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled" endif else group.long 0x300++0x03 line.long 0x00 "FIRCCSR,Fast IRC Control Status Register" eventfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error" rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected" rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" newline sif (!cpuis("S32MTV")) bitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled" bitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled" newline sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*") bitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Disabled,Enabled" bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled" else bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40064000+0x300))&0x01)==0x01) rgroup.long 0x304++0x07 line.long 0x00 "FIRCDIV,Fast IRC Divide Register" sif cpuis("MKL28Z*")||cpuis("K32W*") bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" line.long 0x04 "FIRCCFG,Fast IRC Configuration Register" sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,?..." else bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz" endif else group.long 0x304++0x07 line.long 0x00 "FIRCDIV,Fast IRC Divide Register" sif cpuis("MKL28Z*")||cpuis("K32W*") bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" line.long 0x04 "FIRCCFG,Fast IRC Configuration Register" sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,?..." else bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz" endif endif sif (!cpuis("S32MTV")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S")) if (((per.l(ad:0x40064000+0x300))&0x01)==0x01) rgroup.long 0x30C++0x03 line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register" bitfld.long 0x00 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..." bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC_OSC" else rgroup.long 0x30C++0x03 line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register" bitfld.long 0x00 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..." bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC_OSC" endif endif sif (cpuis("K32W*"))||cpuis("MKL28Z*") if (((per.l(ad:0x40064000+0x318))&0x200)==0x000)&&(((per.l(ad:0x40064000+0x318))&0x100)==0x000) group.long 0x318++0x03 line.long 0x00 "FIRCSTAT,Fast IRC Status Register" hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse" hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status" else rgroup.long 0x318++0x03 line.long 0x00 "FIRCSTAT,Fast IRC Status Register" hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse" hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status" endif sif ((!cpuis("MKL28Z*"))&&!cpuis("S32MTV")) group.long 0x400++0x0B line.long 0x00 "ROSCCSR,RTC OSC Control Status Register" bitfld.long 0x00 26. " ROSCERR ,RTC OSC clock error" "Disabled,Enabled" bitfld.long 0x00 25. " ROSCSEL ,RTC OSC selected" "Not the system,The system" bitfld.long 0x00 24. " ROSCVLD ,RTC OSC valid" "Disabled,Enabled" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" bitfld.long 0x00 17. " ROSCCMRE ,RTC OSC clock monitor reset enable" "Interrupt,Reset" bitfld.long 0x00 16. " ROSCCM ,RTC OSC clock monitor" "Disabled,Enabled" line.long 0x04 "LPFLLCSR,Low Power FLL Control Status Register" bitfld.long 0x04 26. " LPFLLERR ,LPFLL clock error" "Not detected,Detected" bitfld.long 0x04 25. " LPFLLSEL ,LPFLL selected" "Not the system,The system" bitfld.long 0x04 24. " LPFLLVLD ,LPFLL valid" "Disabled,Enabled" bitfld.long 0x04 23. " LK ,Lock register" "Unlocked,Locked" bitfld.long 0x04 17. " LPFLLCMRE ,LPFLL clock monitor reset enable" "Interrupt,Reset" bitfld.long 0x04 16. " LPFLLCM ,LPFLL clock monitor" "Disabled,Enabled" bitfld.long 0x04 10. " LPFLLTRMLOCK ,LPFLL trim LOCK" "Not locked,Locked" bitfld.long 0x04 9. " LPFLLVLD ,LPFLL trim update" "AUTOTRIM,Referenced" bitfld.long 0x04 8. " LPFLLTREN ,LPFLL trim enable" "Disabled,Enabled" bitfld.long 0x04 1. " LPFLLSTEN ,LPFLL stop enable" "Disabled,Enabled" bitfld.long 0x04 0. " LPFLLEN ,LPFLL enable" "Disabled,Enabled" line.long 0x08 "LPFLLDIV,Low Power FLL Divide Register" bitfld.long 0x08 16.--18. " LPFLLDIV3 ,LPFLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x08 8.--10. " LPFLLDIV2 ,LPFLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x08 0.--2. " LPFLLDIV1 ,LPFLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" group.long 0x508++0x03 line.long 0x00 "LPFLLCFG,Low Power FLL Configuration Register" bitfld.long 0x00 0.--1. " FSEL ,Frequency select" "48 MHZ,72 MHZ,?..." group.long 0x50C++0x03 line.long 0x00 "LPFLLTCFG,Low Power FLL Trim Configuration Register" bitfld.long 0x00 16. " LOCKW2LSB ,Lock LPFLL with 2 LSBS" "1LSB,2LSB" bitfld.long 0x00 8.--12. " TRIMDIV ,LPFLL trim predivide" "Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8,Divide by 9,Divide by 10,Divide by 11,Divide by 12,Divide by 13,Divide by 14,Divide by 15,Divide by 16,Divide by 17,Divide by 18,Divide by 19,Divide by 20,Divide by 21,Divide by 22,Divide by 23,Divide by 24,Divide by 25,Divide by 26,Divide by 27,Divide by 28,Divide by 29,Divide by 30,Divide by 31,Divide by 32" bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" "SIRC,FIRC,System OSC,RTC OSC" group.long 0x514++0x03 line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register" hexmask.long.byte 0x00 0.--7. 1. " AUTOTRIM ,Auto tune trim status" endif endif sif (!cpuis("K32W*")) if (((per.l(ad:0x40064000+0x600))&0x800000)==0x800000) group.long 0x600++0x03 line.long 0x00 "SPLLCSR,System PLL Control Status Register" rbitfld.long 0x00 26. " SPLLERR ,System PLL clock error" "No error,Error" rbitfld.long 0x00 25. " SPLLSEL ,System PLL selected" "Not selected,Selected" rbitfld.long 0x00 24. " SPLLVLD ,System PLL valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" newline rbitfld.long 0x00 17. " SPLLCMRE ,System PLL clock monitor reset enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SPLLCM ,System PLL clock monitor" "Disabled,Enabled" newline sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*") rbitfld.long 0x00 1. " SPLLSTEN ,System PLL stop enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled" else rbitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled" endif else group.long 0x600++0x03 line.long 0x00 "SPLLCSR,System PLL Control Status Register" eventfld.long 0x00 26. " SPLLERR ,System PLL clock error" "No error,Error" rbitfld.long 0x00 25. " SPLLSEL ,System PLL selected" "Not selected,Selected" rbitfld.long 0x00 24. " SPLLVLD ,System PLL valid" "Invalid,Valid" bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked" newline bitfld.long 0x00 17. " SPLLCMRE ,System PLL clock monitor reset enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPLLCM ,System PLL clock monitor" "Disabled,Enabled" newline sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*") bitfld.long 0x00 1. " SPLLSTEN ,System PLL stop enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled" else bitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40064000+0x600))&0x01)==0x01) rgroup.long 0x604++0x07 line.long 0x00 "SPLLDIV,System PLL Divide Register" sif cpuis("MKL28Z*") bitfld.long 0x00 16.--18. " SPLLDIV3 ,System PLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " SPLLDIV2 ,System PLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " SPLLDIV1 ,System PLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" line.long 0x04 "SPLLCFG,System PLL Configuration Register" bitfld.long 0x04 16.--20. " MULT ,System PLL multiplier" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47" bitfld.long 0x04 8.--10. " PREDIV ,PLL reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8" newline sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKL28Z*")||cpuis("S32MTV")) bitfld.long 0x04 0. " SOURCE ,Clock source" "SOSC,FIRC" endif else group.long 0x604++0x07 line.long 0x00 "SPLLDIV,System PLL Divide Register" sif cpuis("MKL28Z*") bitfld.long 0x00 16.--18. " SPLLDIV3 ,System PLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64" newline endif bitfld.long 0x00 8.--10. " SPLLDIV2 ,System PLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64" bitfld.long 0x00 0.--2. " SPLLDIV1 ,System PLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64" line.long 0x04 "SPLLCFG,System PLL Configuration Register" bitfld.long 0x04 16.--20. " MULT ,System PLL multiplier" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47" bitfld.long 0x04 8.--10. " PREDIV ,PLL reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8" newline sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKL28Z*")||cpuis("S32MTV")) bitfld.long 0x04 0. " SOURCE ,Clock source" "SOSC,FIRC" endif endif endif width 0x0B tree.end tree "PCC (Peripheral Clock Controller)" base ad:0x40065000 width 10. group.long 0x80++0x07 line.long 0x00 "FTFC,FTFC Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x04 "DMAMUX,DMAMUX Register" rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x04 30. " CGC ,Clock gate control" "Disabled,Enabled" group.long 0x90++0x07 line.long 0x00 "FLEXCAN0,FlexCAN0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x04 "FLEXCAN1,FlexCAN1 Register" rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x04 30. " CGC ,Clock gate control" "Disabled,Enabled" if (((per.l(ad:0x40065000+0x98))&0x40000000)==0x40000000) group.long 0x98++0x03 line.long 0x00 "FTM3,FTM3 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x98++0x03 line.long 0x00 "FTM3,FTM3 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0x9C))&0x40000000)==0x40000000) group.long 0x9C++0x03 line.long 0x00 "ADC1,ADC1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x9C++0x03 line.long 0x00 "ADC1,ADC1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif group.long 0xAC++0x03 line.long 0x00 "FLEXCAN2,FlexCAN2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" if (((per.l(ad:0x40065000+0xB0))&0x40000000)==0x40000000) group.long 0xB0++0x03 line.long 0x00 "LPSPI0,LPSPI0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xB0++0x03 line.long 0x00 "LPSPI0,LPSPI0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0xB4))&0x40000000)==0x40000000) group.long 0xB4++0x03 line.long 0x00 "LPSPI1,LPSPI1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xB4++0x03 line.long 0x00 "LPSPI1,LPSPI1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0xB8))&0x40000000)==0x40000000) group.long 0xB8++0x03 line.long 0x00 "LPSPI2,LPSPI2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xB8++0x03 line.long 0x00 "LPSPI2,LPSPI2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif group.long 0xC4++0x07 line.long 0x00 "PDB1,PDB1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x04 "CRC,CRC Register" rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x04 30. " CGC ,Clock gate control" "Disabled,Enabled" group.long 0xD8++0x03 line.long 0x00 "PDB0,PDB0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" if (((per.l(ad:0x40065000+0xDC))&0x40000000)==0x40000000) group.long 0xDC++0x03 line.long 0x00 "LPIT,LPIT Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xDC++0x03 line.long 0x00 "LPIT,LPIT Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0xE0))&0x40000000)==0x40000000) group.long 0xE0++0x03 line.long 0x00 "FTM0,FTM0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xE0++0x03 line.long 0x00 "FTM0,FTM0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0xE4))&0x40000000)==0x40000000) group.long 0xE4++0x03 line.long 0x00 "FTM1,FTM1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xE4++0x03 line.long 0x00 "FTM1,FTM1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0xE8))&0x40000000)==0x40000000) group.long 0xE8++0x03 line.long 0x00 "FTM2,FTM2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xE8++0x03 line.long 0x00 "FTM2,FTM2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0xEC))&0x40000000)==0x40000000) group.long 0xEC++0x03 line.long 0x00 "ADC0,ADC0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0xEC++0x03 line.long 0x00 "ADC0,ADC0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif group.long 0xF4++0x03 line.long 0x00 "RTC,RTC Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" if (((per.l(ad:0x40065000+0x100))&0x40000000)==0x40000000) group.long 0x100++0x03 line.long 0x00 "LPTMR0,LPTMR0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" rbitfld.long 0x00 3. " FRAC ,Fractional clock divider multiplier value" "0,1" rbitfld.long 0x00 0.--2. " PCD ,Fractional clock divider division value" "/1,/2,/3,/4,/5,/6,/7,/8" else group.long 0x100++0x03 line.long 0x00 "LPTMR0,LPTMR0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" bitfld.long 0x00 3. " FRAC ,Fractional clock divider multiplier value" "0,1" bitfld.long 0x00 0.--2. " PCD ,Fractional clock divider division value" "/1,/2,/3,/4,/5,/6,/7,/8" endif group.long 0x124++0x13 line.long 0x00 "PORTA,PORTA Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x04 "PORTB,PORTB Register" rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x04 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x08 "PORTC,PORTC Register" rbitfld.long 0x08 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x08 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x0C "PORTD,PORTD Register" rbitfld.long 0x0C 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x0C 30. " CGC ,Clock gate control" "Disabled,Enabled" line.long 0x10 "PORTE,PORTE Register" rbitfld.long 0x10 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x10 30. " CGC ,Clock gate control" "Disabled,Enabled" sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") group.long 0x150++0x07 line.long 0x00 "SAI0,SAI0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled" line.long 0x04 "SAI1,SAI1 Register" rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled" endif if (((per.l(ad:0x40065000+0x168))&0x40000000)==0x40000000) group.long 0x168++0x03 line.long 0x00 "FLEXIO,FlexIO Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x168++0x03 line.long 0x00 "FLEXIO,FlexIO Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif group.long 0x184++0x03 line.long 0x00 "EWM,EWM Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" if (((per.l(ad:0x40065000+0x198))&0x40000000)==0x40000000) group.long 0x198++0x03 line.long 0x00 "LPI2C0,LPI2C0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x198++0x03 line.long 0x00 "LPI2C0,LPI2C0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif sif cpuis("MWCT1016S") if (((per.l(ad:0x40065000+0x19C))&0x40000000)==0x40000000) group.long 0x19C++0x03 line.long 0x00 "LPI2C1,LPI2C1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x19C++0x03 line.long 0x00 "LPI2C1,LPI2C1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif endif if (((per.l(ad:0x40065000+0x1A8))&0x40000000)==0x40000000) group.long 0x1A8++0x03 line.long 0x00 "LPUART0,LPUART0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1A8++0x03 line.long 0x00 "LPUART0,LPUART0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0x1AC))&0x40000000)==0x40000000) group.long 0x1AC++0x03 line.long 0x00 "LPUART1,LPUART1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1AC++0x03 line.long 0x00 "LPUART1,LPUART1 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0x1B0))&0x40000000)==0x40000000) group.long 0x1B0++0x03 line.long 0x00 "LPUART2,LPUART2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1B0++0x03 line.long 0x00 "LPUART2,LPUART2 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif sif !cpuis("MWCT1014S") if (((per.l(ad:0x40065000+0x1B8))&0x40000000)==0x40000000) group.long 0x1B8++0x03 line.long 0x00 "FTM4,FTM4 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1B8++0x03 line.long 0x00 "FTM4,FTM4 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0x1BC))&0x40000000)==0x40000000) group.long 0x1BC++0x03 line.long 0x00 "FTM5,FTM5 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1BC++0x03 line.long 0x00 "FTM5,FTM5 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif endif sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S") if (((per.l(ad:0x40065000+0x1C0))&0x40000000)==0x40000000) group.long 0x1C0++0x03 line.long 0x00 "FTM6,FTM6 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1C0++0x03 line.long 0x00 "FTM6,FTM6 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif if (((per.l(ad:0x40065000+0x1C4))&0x40000000)==0x40000000) group.long 0x1C4++0x03 line.long 0x00 "FTM7,FTM7 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" else group.long 0x1C4++0x03 line.long 0x00 "FTM7,FTM7 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" endif endif group.long 0x1CC++0x03 line.long 0x00 "CMP0,CMP0 Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S") group.long 0x1D8++0x03 line.long 0x00 "QSPI,QSPI Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock gate control" "Disabled,Enabled" endif sif !cpuis("MWCT1016S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1014S") if (per.l(ad:0x40065000+0x1E4)&0x40000000)==0x40000000 group.long 0x1E4++0x03 line.long 0x00 "ENET,ENET Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" rbitfld.long 0x00 3. " FRAC ,Fractional clock divider multiplier value" "0,1" rbitfld.long 0x00 0.--2. " PCD ,Fractional clock divider division value" "/1,/2,/3,/4,/5,/6,/7,/8" else group.long 0x1E4++0x03 line.long 0x00 "ENET,ENET Register" rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present" bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Option 1,Option 2,Option 3,Option 4,Option 5,Option 6,Option 7" bitfld.long 0x00 3. " FRAC ,Fractional clock divider multiplier value" "0,1" bitfld.long 0x00 0.--2. " PCD ,Fractional clock divider division value" "/1,/2,/3,/4,/5,/6,/7,/8" endif endif width 0x0B tree.end tree "LMEM (Local Memory Controller)" base ad:0xE0082000 width 8. group.long 0x00++0x03 line.long 0x00 "PCCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Not active,Active" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "No operation,Pushed" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "No operation,Invalidated" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "No operation,Pushed" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "No operation,Invalidated" bitfld.long 0x00 3. " PCCR3 ,Forces no allocation on cache misses (Must also have PCCR2 asserted)" "Not forced,Forced" newline bitfld.long 0x00 2. " PCCR2 ,Forces all cacheable spaces to write through" "Not forced,Forced" bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" if (((per.l(ad:0xE0082000+0x04))&0x100000)==0x100000) if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x10000) group.long 0x04++0x03 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read/write,Invalidate,Push,Clear" newline bitfld.long 0x00 22. " LCWAY ,Line command way" "Way 0,Way 1" bitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" bitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.byte 0x00 4.--10. 0x10 " CACHEADDR ,Cache address for access the tag arrays" newline bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not active,Active" else group.long 0x04++0x03 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read/write,Invalidate,Push,Clear" newline bitfld.long 0x00 22. " LCWAY ,Line command way" "Way 0,Way 1" bitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" bitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.word 0x00 2.--10. 0x04 " CACHEADDR ,Cache address for access the data arrays" newline bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not active,Active" endif else if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x10000) group.long 0x04++0x03 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read/write,Invalidate,Push,Clear" newline textfld " " bitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" bitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.byte 0x00 4.--10. 0x10 " CACHEADDR ,Cache address for access the tag arrays" newline bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not active,Active" else group.long 0x04++0x03 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache,Physical" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and read/write,Invalidate,Push,Clear" newline textfld " " bitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" bitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.word 0x00 2.--10. 0x04 " CACHEADDR ,Cache address for access the data arrays" newline bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not active,Active" endif endif if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x10000) group.long 0x08++0x03 line.long 0x00 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " PHYADDR ,Physical address for tag compare" hexmask.long.byte 0x00 4.--10. 0x10 " PHYADDR ,Physical address for access the tag arrays" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not active,Active" if (((per.l(ad:0xE0082000+0x04))&0x8000000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 11.--31. 1. " CCVR[31:11] ,Tag array R/W value" hexmask.long.byte 0x00 4.--10. 0x10 " CCVR[10:4] ,Tag set address on reads" bitfld.long 0x00 1. " CCVR[1] ,Tag modify bit" "No effect,Modified" bitfld.long 0x00 0. " CCVR[0] ,Tag valid bit" "Not validated,Validated" else group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 11.--31. 1. " CCVR[31:11] ,Tag array R/W value" bitfld.long 0x00 1. " CCVR[1] ,Tag modify bit" "No effect,Modified" bitfld.long 0x00 0. " CCVR[0] ,Tag valid bit" "Not validated,Validated" endif else group.long 0x08++0x07 line.long 0x00 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " PHYADDR ,Physical address for tag compare" hexmask.long.word 0x00 2.--10. 0x04 " PHYADDR ,Physical address for access the data arrays" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not active,Active" line.long 0x04 "PCCCVR,Cache Read/Write Value Register" endif group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" bitfld.long 0x00 30.--31. " R0 ,Region 0 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 28.--29. " R1 ,Region 1 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 26.--27. " R2 ,Region 2 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 24.--25. " R3 ,Region 3 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 22.--23. " R4 ,Region 4 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 20.--21. " R5 ,Region 5 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 18.--19. " R6 ,Region 6 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,Region 7 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 14.--15. " R8 ,Region 8 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,Region 9 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 10.--11. " R10 ,Region 10 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 8.--9. " R11 ,Region 11 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 6.--7. " R12 ,Region 12 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 4.--5. " R13 ,Region 13 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 2.--3. " R14 ,Region 14 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 0.--1. " R15 ,Region 15 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" width 0x0B tree.end tree "MSCM (Miscellaneous System Control Module)" base ad:0x40001000 width 11. rgroup.long 0x00++0x3F line.long 0x00 "CPXTYPE,Processor X Type Register" hexmask.long.tbyte 0x00 8.--31. 1. " PERSONALITY ,Processor x personality" hexmask.long.byte 0x00 0.--7. 1. " RYPZ ,Processor x revision" line.long 0x04 "CPXNUM,Processor X Number Register" bitfld.long 0x04 0. " CPN ,Processor x number" "0,1" line.long 0x08 "CPXMASTER,Processor X Master Register" bitfld.long 0x08 0.--5. " PPN ,Processor x physical port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "CPXCOUNT,Processor X Count Register" bitfld.long 0x0C 0.--1. " PCNT ,Processor x count" "Single core,1,2,3" line.long 0x10 "CPXCFG0,Processor X Configuration Register 0" hexmask.long.byte 0x10 24.--31. 1. " ICSZ ,Level 1 instruction cache size" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") hexmask.long.byte 0x10 16.--23. 1. " ICWY ,Level 1 instruction cache ways" hexmask.long.byte 0x10 8.--15. 1. " DCSZ ,Level 1 data cache size" hexmask.long.byte 0x10 0.--7. 1. " DCWY ,Level 1 data cache ways" endif line.long 0x14 "CPXCFG1,Processor X Configuration Register 1" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") hexmask.long.byte 0x14 24.--31. 1. " L2SZ ,Level 2 instruction cache size" hexmask.long.byte 0x14 16.--23. 1. " L2WY ,Level 2 instruction cache ways" else hexmask.long.byte 0x14 24.--31. 1. " ICSZ ,Level 1 instruction cache size" endif line.long 0x18 "CPXCFG2,Processor X Configuration Register 2" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") hexmask.long.byte 0x18 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size" hexmask.long.byte 0x18 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size" else hexmask.long.byte 0x18 24.--31. 1. " ICSZ ,Level 1 instruction cache size" endif line.long 0x1C "CPXCFG3,Processor X Configuration Register 3" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") bitfld.long 0x1C 8.--9. " SBP ,System bus ports" "0,1,2,3" bitfld.long 0x1C 6. " BB ,Bit banding" "Not supported,Supported" bitfld.long 0x1C 5. " CMP ,Core memory protection unit" "Not included,Included" bitfld.long 0x1C 4. " TZ ,Trust zone" "Not included,Included" newline bitfld.long 0x1C 3. " MMU ,Memory management unit" "Not included,Included" bitfld.long 0x1C 2. " JAZ ,Jazelle support" "Not included,Included" bitfld.long 0x1C 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included" bitfld.long 0x1C 0. " FPU ,Floating point unit" "Not included,Included" else hexmask.long.byte 0x1C 24.--31. 1. " ICSZ ,Level 1 instruction cache size" endif line.long 0x20 "CP0TYPE,Processor 0 Type Register" hexmask.long.tbyte 0x20 8.--31. 1. " PERSONALITY ,Processor 0 personality" hexmask.long.byte 0x20 0.--7. 1. " RYPZ ,Processor 0 revision" line.long 0x24 "CP0NUM,Processor 0 Number Register" bitfld.long 0x24 0. " CPN ,Processor 0 number" "0,1" line.long 0x28 "CP0MASTER,Processor 0 Master Register" bitfld.long 0x28 0.--5. " PPMN ,Processor 0 physical master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "CP0COUNT,Processor 0 Count Register" bitfld.long 0x2C 0.--1. " PCNT ,Processor count" "Single core,1,2,3" line.long 0x30 "CP0CFG0,Processor 0 Configuration Register 0" hexmask.long.byte 0x30 24.--31. 1. " ICSZ ,Level 1 instruction cache size" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") hexmask.long.byte 0x30 16.--23. 1. " ICWY ,Level 1 instruction cache ways" hexmask.long.byte 0x30 8.--15. 1. " DCSZ ,Level 1 data cache size" hexmask.long.byte 0x30 0.--7. 1. " DCWY ,Level 1 data cache ways" endif line.long 0x34 "CP0CFG1,Processor 0 Configuration Register 1" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") hexmask.long.byte 0x34 24.--31. 1. " L2SZ ,Level 2 instruction cache size" hexmask.long.byte 0x34 16.--23. 1. " L2WY ,Level 2 instruction cache ways" else hexmask.long.byte 0x34 24.--31. 1. " ICSZ ,Level 1 instruction cache size" endif line.long 0x38 "CP0CFG2,Processor 0 Configuration Register 2" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") hexmask.long.byte 0x38 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size" hexmask.long.byte 0x38 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size" else hexmask.long.byte 0x38 24.--31. 1. " ICSZ ,Level 1 instruction cache size" endif line.long 0x3C "CP0CFG3,Processor 0 Configuration Register 3" sif !cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*") bitfld.long 0x3C 8.--9. " SBP ,System bus ports" "0,1,2,3" bitfld.long 0x3C 6. " BB ,Bit banding" "Not supported,Supported" bitfld.long 0x3C 5. " CMP ,Core memory protection unit" "Not included,Included" bitfld.long 0x3C 4. " TZ ,Trust zone" "Not included,Included" newline bitfld.long 0x3C 3. " MMU ,Memory management unit" "Not included,Included" bitfld.long 0x3C 2. " JAZ ,Jazelle support" "Not included,Included" bitfld.long 0x3C 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included" bitfld.long 0x3C 0. " FPU ,Floating point unit" "Not included,Included" else hexmask.long.byte 0x3C 24.--31. 1. " ICSZ ,Level 1 instruction cache size" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40001000+0x400))&0x10000)==0x10000) group.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." newline rbitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..." rbitfld.long 0x00 5. " OCMCDR0[5] ,Flash speculate enable" "Disabled,Enabled" rbitfld.long 0x00 4. " OCMCDR0[4] ,Data prefetch enable" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." newline bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..." bitfld.long 0x00 5. " OCMCDR0[5] ,Flash speculate enable" "Disabled,Enabled" bitfld.long 0x00 4. " OCMCDR0[4] ,Data prefetch enable" "Disabled,Enabled" endif if (((per.l(ad:0x40001000+0x404))&0x10000)==0x10000) group.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." newline rbitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..." rbitfld.long 0x00 5. " OCMCDR1[5] ,Flash speculate enable" "Disabled,Enabled" rbitfld.long 0x00 4. " OCMCDR1[4] ,Data prefetch enable" "Disabled,Enabled" else group.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." newline bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..." bitfld.long 0x00 5. " OCMCDR1[5] ,Flash speculate enable" "Disabled,Enabled" bitfld.long 0x00 4. " OCMCDR1[4] ,Data prefetch enable" "Disabled,Enabled" endif if (((per.l(ad:0x40001000+0x408))&0x10000)==0x10000) group.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." newline rbitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..." else group.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." newline bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,,Program flash,Data flash,EEE,?..." endif else if (((per.l(ad:0x40001000+0x400))&0x10000)==0x10000) group.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..." newline rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline else rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline endif rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline endif bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40001000+0x404))&0x10000)==0x10000) group.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..." newline rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline else rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline endif rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline endif bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40001000+0x408))&0x10000)==0x10000) group.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..." newline rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline else rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline endif rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline endif bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40001000+0x40C))&0x10000)==0x10000) group.long 0x40C++0x03 line.long 0x00 "OCMDR3,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" ",,,ROM,Program flash,Data flash,EEE,?..." newline rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline else rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline endif rbitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x40C++0x03 line.long 0x00 "OCMDR3,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size 'hole' (Power-of-2 capacity)" "Enabled,Disabled" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "None,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1024KB,2048KB,4096KB,8192KB,16384KB" newline rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,Read-only" "Disabled,Enabled" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." newline sif cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" newline endif bitfld.long 0x00 8.--11. " OCMC2 ,OCMEM control field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " OCMC1 ,OCMEM control field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " OCMC0 ,OCMEM control field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif width 0x0B tree.end tree "FTFC (Flash Memory Module)" base ad:0x40020000 width 10. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "In progress,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFE read collision error flag" "No error,Error" eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not violated,Violated" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not requested,Requested" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready" rgroup.byte 0x02++0x01 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" bitfld.byte 0x00 2.--3. " FSLACC ,Factory failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" line.byte 0x01 "FOPT,Flash Option Register" if (((per.l(ad:0x40020000))&0x080)==0x080)&&(((per.l(ad:0x40020000+0x01))&0x10)==0x00) sif cpuis("S32MTV") endian.be group.byte 0x04++0x0B line.byte 0x00 "FCCOB3,Flash address [7:0] Register" line.byte 0x01 "FCCOB2,Flash address [15:8] Register" line.byte 0x02 "FCCOB1,Flash address [23:16] Register" line.byte 0x03 "FCCOB0,FCMD (a code that defines the FTFC command) Register" line.byte 0x04 "FCCOB7,Data Byte 3 Register" line.byte 0x05 "FCCOB6,Data Byte 2 Register" line.byte 0x06 "FCCOB5,Data Byte 1 Register" line.byte 0x07 "FCCOB4,Data Byte 0 Register" line.byte 0x08 "FCCOBB,Data Byte 7 Register" line.byte 0x09 "FCCOBA,Data Byte 6 Register" line.byte 0x0A "FCCOB9,Data Byte 5 Register" line.byte 0x0B "FCCOB8,Data Byte 4 Register" endian.le else group.byte 0x04++0x0B line.byte 0x00 "FCCOB3,Flash Common Command Object Register" line.byte 0x01 "FCCOB2,Flash Common Command Object Register" line.byte 0x02 "FCCOB1,Flash Common Command Object Register" line.byte 0x03 "FCCOB0,Flash Common Command Object Register" line.byte 0x04 "FCCOB7,Flash Common Command Object Register" line.byte 0x05 "FCCOB6,Flash Common Command Object Register" line.byte 0x06 "FCCOB5,Flash Common Command Object Register" line.byte 0x07 "FCCOB4,Flash Common Command Object Register" line.byte 0x08 "FCCOBB,Flash Common Command Object Register" line.byte 0x09 "FCCOBA,Flash Common Command Object Register" line.byte 0x0A "FCCOB9,Flash Common Command Object Register" line.byte 0x0B "FCCOB8,Flash Common Command Object Register" endif group.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection 3 Register" bitfld.byte 0x00 7. " PROT[7] ,Program flash region 7 protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region 6 protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region 5 protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region 4 protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region 3 protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region 2 protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region 1 protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region 0 protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection 2 Register" bitfld.byte 0x01 7. " PROT[15] ,Program flash region 15 protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region 14 protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region 13 protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region 12 protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region 11 protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region 10 protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region 9 protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region 8 protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection 1 Register" bitfld.byte 0x02 7. " PROT[23] ,Program flash region 23 protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region 22 protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region 21 protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region 20 protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region 19 protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region 18 protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region 17 protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region 16 protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection 0 Register" bitfld.byte 0x03 7. " PROT[31] ,Program flash region 31 protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region 30 protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region 29 protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region 28 protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region 27 protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region 26 protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region 25 protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region 24 protect" "Protected,Not protected" group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected" bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected" bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected" rgroup.byte 0x2C++0x00 line.byte 0x00 "FCSESTAT,Flash CSEc Status Register" bitfld.byte 0x00 7. " IDB ,Internal debug" "Disabled,Enabled" bitfld.byte 0x00 6. " EDB ,External debug" "Not attached,Attached" bitfld.byte 0x00 5. " RIN ,Random number generator initialized" "Not initialized,Initialized" bitfld.byte 0x00 4. " BOK ,Secure boot OK" "Not completed/failed,Successful" newline bitfld.byte 0x00 3. " BFN ,Secure boot finished" "Not finished,Finished" bitfld.byte 0x00 2. " BIN ,Secure boot initialization" "Not completed,Completed" bitfld.byte 0x00 1. " SB ,Secure boot" "Not activated,Activated" bitfld.byte 0x00 0. " BSY ,Busy" "Completed,In progress" group.byte 0x2E++0x01 line.byte 0x00 "FERSTAT,Flash Error Status Register" eventfld.byte 0x00 1. " DFDIF ,Double bit fault detect interrupt flag" "Not detected,Detected" line.byte 0x01 "FERCNFG,Flash Error Configuration Register" bitfld.byte 0x01 5. " FDFD ,Force double bit fault detect" "Not forced,Forced" bitfld.byte 0x01 1. " DFDIE ,Double bit fault detect interrupt enable" "Disabled,Enabled" else sif (cpuis("S32MTV")) endian.be rgroup.byte 0x04++0x0B line.byte 0x00 "FCCOB3,Flash address [7:0] Register" line.byte 0x01 "FCCOB2,Flash address [15:8] Register" line.byte 0x02 "FCCOB1,Flash address [23:16] Register" line.byte 0x03 "FCCOB0,FCMD (a code that defines the FTFC command) Register" line.byte 0x04 "FCCOB7,Data Byte 3 Register" line.byte 0x05 "FCCOB6,Data Byte 2 Register" line.byte 0x06 "FCCOB5,Data Byte 1 Register" line.byte 0x07 "FCCOB4,Data Byte 0 Register" line.byte 0x08 "FCCOBB,Data Byte 7 Register" line.byte 0x09 "FCCOBA,Data Byte 6 Register" line.byte 0x0A "FCCOB9,Data Byte 5 Register" line.byte 0x0B "FCCOB8,Data Byte 4 Register" endian.le else rgroup.byte 0x04++0x0B line.byte 0x00 "FCCOB3,Flash Common Command Object Register" line.byte 0x01 "FCCOB2,Flash Common Command Object Register" line.byte 0x02 "FCCOB1,Flash Common Command Object Register" line.byte 0x03 "FCCOB0,Flash Common Command Object Register" line.byte 0x04 "FCCOB7,Flash Common Command Object Register" line.byte 0x05 "FCCOB6,Flash Common Command Object Register" line.byte 0x06 "FCCOB5,Flash Common Command Object Register" line.byte 0x07 "FCCOB4,Flash Common Command Object Register" line.byte 0x08 "FCCOBB,Flash Common Command Object Register" line.byte 0x09 "FCCOBA,Flash Common Command Object Register" line.byte 0x0A "FCCOB9,Flash Common Command Object Register" line.byte 0x0B "FCCOB8,Flash Common Command Object Register" endif rgroup.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection 4 Register" bitfld.byte 0x00 7. " PROT[7] ,Program flash region 7 protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region 6 protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region 5 protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region 4 protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region 3 protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region 2 protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region 1 protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region 0 protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection 2 Register" bitfld.byte 0x01 7. " PROT[15] ,Program flash region 15 protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region 14 protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region 13 protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region 12 protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region 11 protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region 10 protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region 9 protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region 8 protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection 2 Register" bitfld.byte 0x02 7. " PROT[23] ,Program flash region 23 protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region 22 protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region 21 protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region 20 protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region 19 protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region 18 protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region 17 protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region 16 protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection 2 Register" bitfld.byte 0x03 7. " PROT[31] ,Program flash region 31 protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region 30 protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region 29 protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region 28 protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region 27 protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region 26 protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region 25 protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region 24 protect" "Protected,Not protected" rgroup.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected" bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected" bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected" rgroup.byte 0x2C++0x00 line.byte 0x00 "FCSESTAT,Flash CSEc Status Register" bitfld.byte 0x00 7. " IDB ,Internal debug" "Disabled,Enabled" bitfld.byte 0x00 6. " EDB ,External debug" "Not attached,Attached" bitfld.byte 0x00 5. " RIN ,Random number generator initialized" "Not initialized,Initialized" bitfld.byte 0x00 4. " BOK ,Secure boot OK" "Not completed/failed,Successful" newline bitfld.byte 0x00 3. " BFN ,Secure boot finished" "Not finished,Finished" bitfld.byte 0x00 2. " BIN ,Secure boot initialization" "Not completed,Completed" bitfld.byte 0x00 1. " SB ,Secure boot" "Not activated,Activated" bitfld.byte 0x00 0. " BSY ,Busy" "Completed,In progress" rgroup.byte 0x2E++0x01 line.byte 0x00 "FERSTAT,Flash Error Status Register" bitfld.byte 0x00 1. " DFDIF ,Double bit fault detect interrupt flag" "Not detected,Detected" line.byte 0x01 "FERCNFG,Flash Error Configuration Register" bitfld.byte 0x01 5. " FDFD ,Force double bit fault detect" "Not forced,Forced" bitfld.byte 0x01 1. " DFDIE ,Double bit fault detect interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S") tree "QUADSPI (Quad Serial Peripheral Interface)" base ad:0x40076000 width 14. sif cpuis("MWCT1016S") if ((per.l(ad:0x40076000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 19. " ISD3FB ,Idle signal drive IOFB[3] flash B" "Low,High" bitfld.long 0x00 18. " ISD2FB ,Idle signal drive IOFB[2] flash B" "Low,High" bitfld.long 0x00 17. " ISD3FA ,Idle signal drive IOFA[3] flash A" "Low,High" newline bitfld.long 0x00 16. " ISD2FA ,Idle signal drive IOFA[2] flash A" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No action,Cleared" newline bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No action,Cleared" bitfld.long 0x00 8. " VAR_LAT_EN ,Variable latency enable" "Disabled,Enabled" bitfld.long 0x00 7. " DDR_EN ,DDR mode enable" "SDR,SDR & DDR" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" bitfld.long 0x00 4. " DQS_OUT_EN ,DQS used as an output enable bit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI module" "64-bit BE,32-bit LE,32-bit BE,64-bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No action,Reset" newline bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No action,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" rbitfld.long 0x00 19. " ISD3FB ,Idle signal drive IOFB[3] flash B" "Low,High" rbitfld.long 0x00 18. " ISD2FB ,Idle signal drive IOFB[2] flash B" "Low,High" rbitfld.long 0x00 17. " ISD3FA ,Idle signal drive IOFA[3] flash A" "Low,High" newline rbitfld.long 0x00 16. " ISD2FA ,Idle signal drive IOFA[2] flash A" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/buffer" "No action,Cleared" newline bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No action,Cleared" bitfld.long 0x00 8. " VAR_LAT_EN ,Variable latency enable" "Disabled,Enabled" bitfld.long 0x00 7. " DDR_EN ,DDR mode enable" "SDR,SDR & DDR" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" bitfld.long 0x00 4. " DQS_OUT_EN ,DQS used as an output enable bit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI module" "64-bit BE,32-bit LE,32-bit BE,64-bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No action,Reset" newline bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No action,Reset" endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 19. " ISD3FB ,Idle signal drive IOFB[3] Flash B" "Low,High" bitfld.long 0x00 18. " ISD2FB ,Idle signal drive IOFB[2] Flash B" "Low,High" bitfld.long 0x00 17. " ISD3FA ,Idle signal drive IOFA[3] Flash A" "Low,High" newline bitfld.long 0x00 16. " ISD2FA ,Idle signal drive IOFA[2] Flash A" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No action,Cleared" newline bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No action,Cleared" bitfld.long 0x00 8. " VAR_LAT_EN ,Variable latency enable" "Disabled,Enabled" bitfld.long 0x00 7. " DDR_EN ,DDR mode enable" "SDR,SDR & DDR" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " DQS_LAT_EN ,DQS latency enable" "Disabled,Enabled" bitfld.long 0x00 4. " DQS_OUT_EN ,DQS used as an output enable bit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI module" "64-bit BE,32-bit LE,32-bit BE,64-bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for HOST domain" "No action,Reset" newline bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No action,Reset" endif if ((per.l(ad:0x40076000+0x15C)&0x02)==0x00) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Points to a sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,IP data transfer size" else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Points to a sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,IP data transfer size" endif if ((per.l(ad:0x40076000+0x15C)&0x02)==0x00)&&((per.l(ad:0x40076000+0x15C)&0x04)==0x00) if (((per.l(ad:0x40076000))&0x80)==0x80) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time (Data sent to flash alignment select)" "QuadSPI int. ref. clk,2x int. ref. half clk,?..." newline bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x40076000))&0x80)==0x80) rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time (Data sent to flash alignment select)" "QuadSPI int. ref. clk,2x int. ref. half clk,?..." newline bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if ((per.l(ad:0x40076000+0x15C)&0x04)==0x00) group.long 0x10++0x17 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x10 12.--15. " SEQID ,Points to a sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SOCCR,SOC Configuration Register" group.long (0x0+0x30)++0x03 line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 0x08 " TPINDX0 ,Top index of buffer 0" group.long (0x4+0x30)++0x03 line.long 0x00 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x00 3.--31. 0x08 " TPINDX1 ,Top index of buffer 1" group.long (0x8+0x30)++0x03 line.long 0x00 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x00 3.--31. 0x08 " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x17 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,Master ID - the ID of the AHB master associated with BUFFER3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x10 12.--15. " SEQID ,Points to a sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SOCCR,SOC Configuration Register" rgroup.long (0x0+0x30)++0x03 line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 0x08 " TPINDX0 ,Top index of buffer 0" rgroup.long (0x4+0x30)++0x03 line.long 0x00 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x00 3.--31. 0x08 " TPINDX1 ,Top index of buffer 1" rgroup.long (0x8+0x30)++0x03 line.long 0x00 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x00 3.--31. 0x08 " TPINDX2 ,Top index of buffer 2" endif if ((per.l(ad:0x40076000+0x15C)&0x02)==0x00) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif if ((per.l(ad:0x40076000+0x15C)&0x02)==0x00)&&((per.l(ad:0x40076000+0x15C)&0x04)==0x00) group.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte,Word" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Word addressable" "Byte,Word" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.l(ad:0x40076000)&0x4000)==0x4000) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection" "1 cycle,2 cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection" "Not inverted,Inverted" else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection" "1 cycle,2 cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection" "Not inverted,Inverted" endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Read counter" bitfld.long 0x00 8.--13. " RDBFL ,RX buffer fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(ad:0x40076000+0x15C)&0x02)==0x00) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,RX buffer readout" "AHB bus registers,IP bus registers" bitfld.long 0x00 0.--4. " WMRK ,RX buffer watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,RX buffer readout" "AHB bus registers,IP bus registers" bitfld.long 0x00 0.--4. " WMRK ,RX buffer watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Transmit counter" bitfld.long 0x00 8.--13. " TRBFL ,TX buffer fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(ad:0x40076000+0x15C)&0x8000000)==0x00) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif group.long 0x158++0x03 line.long 0x00 "TBCT,TX Buffer Control Register" bitfld.long 0x00 0.--4. " WMRK ,Determines the watermark for the TX buffer" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128" rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" bitfld.long 0x00 26. " TXDMA ,TXFIFO fill via DMA is active" "Not requested,Requested" bitfld.long 0x00 25. " TXWA ,TX buffer watermark available" "Not available,Available" newline bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" bitfld.long 0x00 23. " RXDMA ,RX buffer DMA" "Not requested,Requested" bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" newline bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" newline bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "Empty,Not empty" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "Empty,Not empty" bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "Empty,Not empty" bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "Empty,Not empty" newline bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "Not requested,Requested" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not initiated,Initiated" bitfld.long 0x00 1. " IP_ACC ,IP access" "Not initiated,Initiated" newline bitfld.long 0x00 0. " BUSY ,Module busy" "Idle,Busy" if ((per.l(ad:0x40076000)&0x4000)==0x0000) rgroup.long 0x160++0x03 line.long 0x00 "FR,Flag Register" bitfld.long 0x00 27. " TBFF ,TX buffer fill flag" "Low,High" bitfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "Low,High" bitfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "Low,High" newline bitfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Low,High" bitfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "Low,High" bitfld.long 0x00 14. " AITEF ,AHB illegal transaction error flag" "Low,High" newline bitfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error flag" "Low,High" bitfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "Low,High" newline bitfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "Low,High" bitfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "Low,High" bitfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Low,High" else group.long 0x160++0x03 line.long 0x00 "FR,Flag Register" eventfld.long 0x00 27. " TBFF ,TX buffer fill flag" "Low,High" eventfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "Low,High" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "Low,High" newline eventfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Low,High" eventfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "Low,High" eventfld.long 0x00 14. " AITEF ,AHB illegal transaction error flag" "Low,High" newline eventfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error flag" "Low,High" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "Low,High" newline eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "Low,High" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "Low,High" eventfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Low,High" endif group.long 0x164++0x03 line.long 0x00 "RSER,Interrupt And DMA Request Select And Enable Register" bitfld.long 0x00 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " TBFDE ,TX buffer fill DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " RBDIE ,RBDF interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " AITIE ,AHB illegal transaction interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " AIBSIE ,AHB illegal burst size interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" sif cpuis("MWCT1016S") if ((per.l(ad:0x40076000+0x168)&0x01)==0x01) group.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" newline bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer" "0,1,2,3" bitfld.long 0x00 0. " SUSPND ,Suspend state" "Not suspended,Suspended" else group.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" newline bitfld.long 0x00 0. " SUSPND ,Suspend state" "Not suspended,Suspended" endif else if ((per.l(ad:0x40076000+0x168)&0x01)==0x01) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" newline bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer" "0,1,2,3" bitfld.long 0x00 0. " SUSPND ,Suspend state" "Not suspended,Suspended" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" newline bitfld.long 0x00 0. " SUSPND ,Suspend state" "Not suspended,Suspended" endif endif sif cpuis("MWCT1016S") group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" eventfld.long 0x00 8. " IPPTRC ,Clears the sequence pointer for IP" "No effect,Clear" eventfld.long 0x00 0. " BFPTRC ,Clears the sequence pointer for AHB buffers" "No effect,Clear" else wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,Clears the sequence pointer for IP" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Clears the sequence pointer for AHB buffers" "No effect,Clear" endif if ((per.l(ad:0x40076000+0x15C)&0x02)==0x00)&&((per.l(ad:0x40076000+0x15C)&0x04)==0x00) group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial Flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial Flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial Flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial Flash B2" sif !cpuis("MWCT1016S") group.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" endif else rgroup.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial Flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial Flash A2" line.long 0x08 "SFB1AD,Serial Flash B1Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial Flash B1" line.long 0x0C "SFB2AD,Serial Flash B2Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial Flash B2" sif !cpuis("MWCT1016S") rgroup.long 0x190++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" endif endif rgroup.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data 0 Register" rgroup.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data 1 Register" rgroup.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data 2 Register" rgroup.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data 3 Register" rgroup.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data 4 Register" rgroup.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data 5 Register" rgroup.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data 6 Register" rgroup.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data 7 Register" rgroup.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data 8 Register" rgroup.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data 9 Register" rgroup.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data 10 Register" rgroup.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data 11 Register" rgroup.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data 12 Register" rgroup.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data 13 Register" rgroup.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data 14 Register" rgroup.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data 15 Register" rgroup.long 0x240++0x03 line.long 0x00 "RBDR16,RX Buffer Data 16 Register" rgroup.long 0x244++0x03 line.long 0x00 "RBDR17,RX Buffer Data 17 Register" rgroup.long 0x248++0x03 line.long 0x00 "RBDR18,RX Buffer Data 18 Register" rgroup.long 0x24C++0x03 line.long 0x00 "RBDR19,RX Buffer Data 19 Register" rgroup.long 0x250++0x03 line.long 0x00 "RBDR20,RX Buffer Data 20 Register" rgroup.long 0x254++0x03 line.long 0x00 "RBDR21,RX Buffer Data 21 Register" rgroup.long 0x258++0x03 line.long 0x00 "RBDR22,RX Buffer Data 22 Register" rgroup.long 0x25C++0x03 line.long 0x00 "RBDR23,RX Buffer Data 23 Register" rgroup.long 0x260++0x03 line.long 0x00 "RBDR24,RX Buffer Data 24 Register" rgroup.long 0x264++0x03 line.long 0x00 "RBDR25,RX Buffer Data 25 Register" rgroup.long 0x268++0x03 line.long 0x00 "RBDR26,RX Buffer Data 26 Register" rgroup.long 0x26C++0x03 line.long 0x00 "RBDR27,RX Buffer Data 27 Register" rgroup.long 0x270++0x03 line.long 0x00 "RBDR28,RX Buffer Data 28 Register" rgroup.long 0x274++0x03 line.long 0x00 "RBDR29,RX Buffer Data 29 Register" rgroup.long 0x278++0x03 line.long 0x00 "RBDR30,RX Buffer Data 30 Register" rgroup.long 0x27C++0x03 line.long 0x00 "RBDR31,RX Buffer Data 31 Register" group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 0.--1. " LOCK ,Lock the LUT" ",Locked,Unlocked,?..." group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table 0 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table 1 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table 2 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table 3 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table 4 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table 5 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table 6 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table 7 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table 8 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table 9 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table 10 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table 11 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table 12 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table 13 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table 14 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table 15 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table 16 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table 17 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table 18 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table 19 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table 20 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table 21 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table 22 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table 23 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table 24 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table 25 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table 26 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table 27 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table 28 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table 29 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table 30 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table 31 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table 32 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table 33 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table 34 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table 35 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table 36 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table 37 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table 38 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table 39 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table 40 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table 41 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table 42 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table 43 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table 44 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table 45 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table 46 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table 47 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table 48 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table 49 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table 50 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table 51 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table 52 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table 53 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table 54 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table 55 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table 56 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table 57 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table 58 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table 59 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table 60 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table 61 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table 62 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table 63 Register" sif cpuis("MWCT1016S") bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline sif cpuis("MWCT1016S") bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,,CMD_DDR,CADDR,CADDR_DDR,?..." else bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" width 0x0B tree.end endif tree "SMC (System Mode Controller)" base ad:0x4007E000 width 10. rgroup.long 0x00++0x07 line.long 0x00 "VERID,SMC Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,SMC Parameter Register" bitfld.long 0x04 6. " EVLLS0 ,Existence of VLLS0 feature" "Not available,Available" bitfld.long 0x04 5. " ELLS2 ,Existence of LLS2 feature" "Not available,Available" bitfld.long 0x04 3. " ELLS ,Existence of LLS feature" "Not available,Available" bitfld.long 0x04 0. " EHSRUN ,Existence of HSRUN feature" "Not available,Available" group.long 0x08++0x0B line.long 0x00 "PMPROT,Power Mode Protection Register" sif (!cpuis("S32MTV")) bitfld.long 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.long 0x00 5. " AVLP ,Allow Very-Low-Power modes" "Not allowed,Allowed" else bitfld.long 0x00 5. " AVLP ,Allow Very-Low-Power modes" "Not allowed,Allowed" endif line.long 0x04 "PMCTRL,Power Mode Control Register" sif (cpuis("S32MTV")) bitfld.long 0x04 5.--6. " RUNM ,Run mode control" "RUN,,VLPR,?..." textfld " " else bitfld.long 0x04 5.--6. " RUNM ,Run mode control" "RUN,,VLPR,HSRUN" endif rbitfld.long 0x04 3. " VLPSA ,Very low power stop aborted" "Not aborted,Aborted" bitfld.long 0x04 0.--2. " STOPM ,Stop mode control" "STOP,,VLPS,?..." line.long 0x08 "STOPCTRL,Stop Control Register" bitfld.long 0x08 6.--7. " STOPO ,Stop option" ",STOP1,STOP2,?..." rgroup.long 0x14++0x03 line.long 0x00 "PMSTAT,Power Mode Status Register" hexmask.long.byte 0x00 0.--7. 1. " PMSTAT ,Power mode status" width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 9. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 Register" rbitfld.byte 0x00 7. " LVDF ,Low voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low voltage detect acknowledge" "No effect,Clear" bitfld.byte 0x00 5. " LVDIE ,Low voltage detect interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LVDRE ,Low voltage detect reset enable" "No reset,Reset" line.byte 0x01 "LVDSC2,Low Voltage Detect Status And Control 2 Register" rbitfld.byte 0x01 7. " LVWF ,Low-Voltage warning flag" "Not detected,Detected" sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.byte 0x01 6. " LVWACK ,Low-Voltage warning acknowledge" "No effect,Clear" else bitfld.byte 0x01 6. " LVDWCK ,Low-Voltage detect acknowledge" "No effect,Clear" endif bitfld.byte 0x01 5. " LVWIE ,Low-Voltage warning interrupt enable" "Disabled,Enabled" line.byte 0x02 "REGSC,Regulator Status And Control Register" bitfld.byte 0x02 7. " LPODIS ,LPO disable bit" "No,Yes" rbitfld.byte 0x02 6. " LPOSTAT ,LPO status bit" "Low phase,High phase" rbitfld.byte 0x02 2. " REGFPM ,Regulator in full performance mode status bit" "Disabled,Enabled" bitfld.byte 0x02 1. " CLKBIASDIS ,Clock bias disable bit" "No,Yes" bitfld.byte 0x02 0. " BIASEN ,Bias enable bit" "Disabled,Enabled" group.byte 0x04++0x00 line.byte 0x00 "LPOTRIM,Low Power Oscillator Trim Register" bitfld.byte 0x00 0.--4. " LPOTRIM ,LPO trimming bits" "-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "ADC (Analog-to-Digital Converter)" tree "ADC0" base ad:0x4003B000 width 10. group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x8++0x03 line.long 0x00 "SC1C,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0xC++0x03 line.long 0x00 "SC1D,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x10++0x03 line.long 0x00 "SC1E,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x14++0x03 line.long 0x00 "SC1F,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x18++0x03 line.long 0x00 "SC1G,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x1C++0x03 line.long 0x00 "SC1H,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x20++0x03 line.long 0x00 "SC1I,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x24++0x03 line.long 0x00 "SC1J,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x28++0x03 line.long 0x00 "SC1K,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x2C++0x03 line.long 0x00 "SC1L,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x30++0x03 line.long 0x00 "SC1M,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x34++0x03 line.long 0x00 "SC1N,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x38++0x03 line.long 0x00 "SC1O,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x3C++0x03 line.long 0x00 "SC1P,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif sif (cpu()=="MWCT1015S")||(cpu()=="MWCT1016S") group.long 0x108++0x03 line.long 0x00 "ASC1A,ADC Status And Control Register 1 (Alias For SC1A)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x10C++0x03 line.long 0x00 "ASC1B,ADC Status And Control Register 1 (Alias For SC1B)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x110++0x03 line.long 0x00 "ASC1C,ADC Status And Control Register 1 (Alias For SC1C)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x114++0x03 line.long 0x00 "ASC1D,ADC Status And Control Register 1 (Alias For SC1D)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x118++0x03 line.long 0x00 "ASC1E,ADC Status And Control Register 1 (Alias For SC1E)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x11C++0x03 line.long 0x00 "ASC1F,ADC Status And Control Register 1 (Alias For SC1F)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x120++0x03 line.long 0x00 "ASC1G,ADC Status And Control Register 1 (Alias For SC1G)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x124++0x03 line.long 0x00 "ASC1H,ADC Status And Control Register 1 (Alias For SC1H)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x128++0x03 line.long 0x00 "ASC1I,ADC Status And Control Register 1 (Alias For SC1I)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x12C++0x03 line.long 0x00 "ASC1J,ADC Status And Control Register 1 (Alias For SC1J)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x130++0x03 line.long 0x00 "ASC1K,ADC Status And Control Register 1 (Alias For SC1K)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x134++0x03 line.long 0x00 "ASC1L,ADC Status And Control Register 1 (Alias For SC1L)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x138++0x03 line.long 0x00 "ASC1M,ADC Status And Control Register 1 (Alias For SC1M)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x13C++0x03 line.long 0x00 "ASC1N,ADC Status And Control Register 1 (Alias For SC1N)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x140++0x03 line.long 0x00 "ASC1O,ADC Status And Control Register 1 (Alias For SC1O)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x144++0x03 line.long 0x00 "ASC1P,ADC Status And Control Register 1 (Alias For SC1P)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x40++0x07 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..." bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "ALTCLK1,ALTCLK2,ALTCLK3,ALTCLK4" line.long 0x04 "CFG2,ADC Configuration Register 2" hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample time select" newline hgroup.long 0x48++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x4C++0x03 hide.long 0x00 "RB,ADC Data Result Register" in hgroup.long 0x50++0x03 hide.long 0x00 "RC,ADC Data Result Register" in hgroup.long 0x54++0x03 hide.long 0x00 "RD,ADC Data Result Register" in hgroup.long 0x58++0x03 hide.long 0x00 "RE,ADC Data Result Register" in hgroup.long 0x5C++0x03 hide.long 0x00 "RF,ADC Data Result Register" in hgroup.long 0x60++0x03 hide.long 0x00 "RG,ADC Data Result Register" in hgroup.long 0x64++0x03 hide.long 0x00 "RH,ADC Data Result Register" in hgroup.long 0x68++0x03 hide.long 0x00 "RI,ADC Data Result Register" in hgroup.long 0x6C++0x03 hide.long 0x00 "RJ,ADC Data Result Register" in hgroup.long 0x70++0x03 hide.long 0x00 "RK,ADC Data Result Register" in hgroup.long 0x74++0x03 hide.long 0x00 "RL,ADC Data Result Register" in hgroup.long 0x78++0x03 hide.long 0x00 "RM,ADC Data Result Register" in hgroup.long 0x7C++0x03 hide.long 0x00 "RN,ADC Data Result Register" in hgroup.long 0x80++0x03 hide.long 0x00 "RO,ADC Data Result Register" in hgroup.long 0x84++0x03 hide.long 0x00 "RP,ADC Data Result Register" in sif (cpu()=="MWCT1015S")||(cpu()=="MWCT1016S") hgroup.long 0x188++0x03 hide.long 0x00 "ARA,ADC Data Result Register (Alias For RA)" in hgroup.long 0x18C++0x03 hide.long 0x00 "ARB,ADC Data Result Register (Alias For RB)" in hgroup.long 0x190++0x03 hide.long 0x00 "ARC,ADC Data Result Register (Alias For RC)" in hgroup.long 0x194++0x03 hide.long 0x00 "ARD,ADC Data Result Register (Alias For RD)" in hgroup.long 0x198++0x03 hide.long 0x00 "ARE,ADC Data Result Register (Alias For RE)" in hgroup.long 0x19C++0x03 hide.long 0x00 "ARF,ADC Data Result Register (Alias For RF)" in hgroup.long 0x1A0++0x03 hide.long 0x00 "ARG,ADC Data Result Register (Alias For RG)" in hgroup.long 0x1A4++0x03 hide.long 0x00 "ARH,ADC Data Result Register (Alias For RH)" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ARI,ADC Data Result Register (Alias For RI)" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ARJ,ADC Data Result Register (Alias For RJ)" in hgroup.long 0x1B0++0x03 hide.long 0x00 "ARK,ADC Data Result Register (Alias For RK)" in hgroup.long 0x1B4++0x03 hide.long 0x00 "ARL,ADC Data Result Register (Alias For RL)" in hgroup.long 0x1B8++0x03 hide.long 0x00 "ARM,ADC Data Result Register (Alias For RM)" in hgroup.long 0x1BC++0x03 hide.long 0x00 "ARN,ADC Data Result Register (Alias For RN)" in hgroup.long 0x1C0++0x03 hide.long 0x00 "ARO,ADC Data Result Register (Alias For RO)" in hgroup.long 0x1C4++0x03 hide.long 0x00 "ARP,ADC Data Result Register (Alias For RP)" in endif newline if (((per.l(ad:0x4003B000+0x90))&0x20)==0x20) group.long 0x88++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x90))&0x8)==0x8) group.long 0x8C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." group.long 0x94++0x57 line.long 0x00 "SC3,Status And Control Register 3" bitfld.long 0x00 7. " CAL ,Calibration" "No effect,Start" bitfld.long 0x00 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x00 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x04 "BASE_OFS,ADC Offset Correction Register" hexmask.long.byte 0x04 0.--7. 1. " BA_OFS ,Base offset error correction value" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "USR_OFS,ADC USER Offset Correction Register" hexmask.long.byte 0x0C 0.--7. 1. " USR_OFS ,USER offset error correction value" line.long 0x10 "XOFS,ADC X Offset Correction Register" bitfld.long 0x10 0.--5. " OFS ,Offset error correction value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "YOFS,ADC Y Offset Correction Register" hexmask.long.byte 0x14 0.--7. 1. " YOFS ,Y offset error correction value" line.long 0x18 "G,ADC Gain Register" hexmask.long.word 0x18 0.--10. 1. " G ,Gain error adjustment factor for the overall conversion" line.long 0x1C "UG,ADC User Gain Register" hexmask.long.word 0x1C 0.--9. 1. " UG ,User gain error correction value" line.long 0x20 "CLPS,ADC General Calibration Value Register S" hexmask.long.byte 0x20 0.--6. 1. " CLPS ,Calibration value" line.long 0x24 "CLP3,ADC Plus-Side General Calibration Value Register 3" hexmask.long.word 0x24 0.--9. 1. " CLP3 ,Calibration value" line.long 0x28 "CLP2,ADC Plus-Side General Calibration Value Register 2" hexmask.long.word 0x28 0.--9. 1. " CLP2 ,Calibration value" line.long 0x2C "CLP1,ADC Plus-Side General Calibration Value Register 1" hexmask.long.word 0x2C 0.--8. 1. " CLP1 ,Calibration value" line.long 0x30 "CLP0,ADC Plus-Side General Calibration Value Register 0" hexmask.long.byte 0x30 0.--7. 1. " CLP0 ,Calibration value" line.long 0x34 "CLPX,ADC Plus-Side General Calibration Value Register X" hexmask.long.byte 0x34 0.--6. 1. " CLPX ,Calibration value" line.long 0x38 "CLP9,ADC Plus-Side General Calibration Value Register 9" hexmask.long.byte 0x38 0.--6. 1. " CLP9 ,Calibration value" line.long 0x3C "CLPS_OFS,ADC General Calibration Offset Value Register S" bitfld.long 0x3C 0.--3. " CLPS_OFS ,CLPS offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "CLP3_OFS,ADC Plus-Side General Calibration Offset Value Register 3" bitfld.long 0x40 0.--3. " CLP3_OFS ,CLP3 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "CLP2_OFS,ADC Plus-Side General Calibration Offset Value Register 2" bitfld.long 0x44 0.--3. " CLP2_OFS ,CLP2 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "CLP1_OFS,ADC Plus-Side General Calibration Offset Value Register 1" bitfld.long 0x48 0.--3. " CLP1_OFS ,CLP1 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4C "CLP0_OFS,ADC Plus-Side General Calibration Offset Value Register 0" bitfld.long 0x4C 0.--3. " CLP0_OFS ,CLP0 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x50 "CLPX_OFS,ADC Plus-Side General Calibration Offset Value Register X" hexmask.long.word 0x50 0.--11. 1. " CLPX_OFS ,CLPX offset" line.long 0x54 "CLP9_OFS,ADC Plus-Side General Calibration Offset Value Register 9" hexmask.long.word 0x54 0.--11. 1. " CLP9_OFS ,CLP9 offset" sif (cpu()=="MWCT1015S") group.long 0x148++0x03 line.long 0x00 "SC1Q,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x14C++0x03 line.long 0x00 "SC1R,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x150++0x03 line.long 0x00 "SC1S,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x154++0x03 line.long 0x00 "SC1T,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x158++0x03 line.long 0x00 "SC1U,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x15C++0x03 line.long 0x00 "SC1V,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x160++0x03 line.long 0x00 "SC1W,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x164++0x03 line.long 0x00 "SC1X,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" newline hgroup.long 0x1C8++0x03 hide.long 0x00 "RQ,ADC Data Result Register" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RR,ADC Data Result Register" in hgroup.long 0x1D0++0x03 hide.long 0x00 "RS,ADC Data Result Register" in hgroup.long 0x1D4++0x03 hide.long 0x00 "RT,ADC Data Result Register" in hgroup.long 0x1D8++0x03 hide.long 0x00 "RU,ADC Data Result Register" in hgroup.long 0x1DC++0x03 hide.long 0x00 "RV,ADC Data Result Register" in hgroup.long 0x1E0++0x03 hide.long 0x00 "RW,ADC Data Result Register" in hgroup.long 0x1E4++0x03 hide.long 0x00 "RX,ADC Data Result Register" in elif (cpu()=="MWCT1016S") group.long 0x148++0x03 line.long 0x00 "SC1Q,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x14C++0x03 line.long 0x00 "SC1R,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x150++0x03 line.long 0x00 "SC1S,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x154++0x03 line.long 0x00 "SC1T,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x158++0x03 line.long 0x00 "SC1U,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x15C++0x03 line.long 0x00 "SC1V,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x160++0x03 line.long 0x00 "SC1W,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x164++0x03 line.long 0x00 "SC1X,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x168++0x03 line.long 0x00 "SC1Y,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x16C++0x03 line.long 0x00 "SC1Z,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x170++0x03 line.long 0x00 "SC1AA,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x174++0x03 line.long 0x00 "SC1AB,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x178++0x03 line.long 0x00 "SC1AC,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x17C++0x03 line.long 0x00 "SC1AD,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x180++0x03 line.long 0x00 "SC1AE,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x184++0x03 line.long 0x00 "SC1AF,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,Internal 0,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" newline hgroup.long 0x1C8++0x03 hide.long 0x00 "RQ,ADC Data Result Register" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RR,ADC Data Result Register" in hgroup.long 0x1D0++0x03 hide.long 0x00 "RS,ADC Data Result Register" in hgroup.long 0x1D4++0x03 hide.long 0x00 "RT,ADC Data Result Register" in hgroup.long 0x1D8++0x03 hide.long 0x00 "RU,ADC Data Result Register" in hgroup.long 0x1DC++0x03 hide.long 0x00 "RV,ADC Data Result Register" in hgroup.long 0x1E0++0x03 hide.long 0x00 "RW,ADC Data Result Register" in hgroup.long 0x1E4++0x03 hide.long 0x00 "RX,ADC Data Result Register" in hgroup.long 0x1E8++0x03 hide.long 0x00 "RY,ADC Data Result Register" in hgroup.long 0x1EC++0x03 hide.long 0x00 "RZ,ADC Data Result Register" in hgroup.long 0x1F0++0x03 hide.long 0x00 "RAA,ADC Data Result Register" in hgroup.long 0x1F4++0x03 hide.long 0x00 "RAB,ADC Data Result Register" in hgroup.long 0x1F8++0x03 hide.long 0x00 "RAC,ADC Data Result Register" in hgroup.long 0x1FC++0x03 hide.long 0x00 "RAD,ADC Data Result Register" in hgroup.long 0x200++0x03 hide.long 0x00 "RAE,ADC Data Result Register" in hgroup.long 0x204++0x03 hide.long 0x00 "RAF,ADC Data Result Register" in endif width 0x0B tree.end tree "ADC1" base ad:0x40027000 width 10. group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x8++0x03 line.long 0x00 "SC1C,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0xC++0x03 line.long 0x00 "SC1D,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x10++0x03 line.long 0x00 "SC1E,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x14++0x03 line.long 0x00 "SC1F,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x18++0x03 line.long 0x00 "SC1G,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x1C++0x03 line.long 0x00 "SC1H,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x20++0x03 line.long 0x00 "SC1I,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x24++0x03 line.long 0x00 "SC1J,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x28++0x03 line.long 0x00 "SC1K,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x2C++0x03 line.long 0x00 "SC1L,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x30++0x03 line.long 0x00 "SC1M,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x34++0x03 line.long 0x00 "SC1N,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x38++0x03 line.long 0x00 "SC1O,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x3C++0x03 line.long 0x00 "SC1P,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" sif (cpu()=="MWCT1014S") bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,Disabled,?..." else bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif sif (cpu()=="MWCT1015S")||(cpu()=="MWCT1016S") group.long 0x108++0x03 line.long 0x00 "ASC1A,ADC Status And Control Register 1 (Alias For SC1A)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x10C++0x03 line.long 0x00 "ASC1B,ADC Status And Control Register 1 (Alias For SC1B)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x110++0x03 line.long 0x00 "ASC1C,ADC Status And Control Register 1 (Alias For SC1C)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x114++0x03 line.long 0x00 "ASC1D,ADC Status And Control Register 1 (Alias For SC1D)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x118++0x03 line.long 0x00 "ASC1E,ADC Status And Control Register 1 (Alias For SC1E)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x11C++0x03 line.long 0x00 "ASC1F,ADC Status And Control Register 1 (Alias For SC1F)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x120++0x03 line.long 0x00 "ASC1G,ADC Status And Control Register 1 (Alias For SC1G)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x124++0x03 line.long 0x00 "ASC1H,ADC Status And Control Register 1 (Alias For SC1H)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x128++0x03 line.long 0x00 "ASC1I,ADC Status And Control Register 1 (Alias For SC1I)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x12C++0x03 line.long 0x00 "ASC1J,ADC Status And Control Register 1 (Alias For SC1J)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x130++0x03 line.long 0x00 "ASC1K,ADC Status And Control Register 1 (Alias For SC1K)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x134++0x03 line.long 0x00 "ASC1L,ADC Status And Control Register 1 (Alias For SC1L)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x138++0x03 line.long 0x00 "ASC1M,ADC Status And Control Register 1 (Alias For SC1M)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x13C++0x03 line.long 0x00 "ASC1N,ADC Status And Control Register 1 (Alias For SC1N)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x140++0x03 line.long 0x00 "ASC1O,ADC Status And Control Register 1 (Alias For SC1O)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x144++0x03 line.long 0x00 "ASC1P,ADC Status And Control Register 1 (Alias For SC1P)" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" endif group.long 0x40++0x07 line.long 0x00 "CFG1,ADC Configuration Register 1" eventfld.long 0x00 8. " CLRLTRG ,Clear latch trigger in trigger handler block" "Not cleared,Cleared" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,12-bit,10-bit,?..." bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "ALTCLK1,ALTCLK2,ALTCLK3,ALTCLK4" line.long 0x04 "CFG2,ADC Configuration Register 2" hexmask.long.byte 0x04 0.--7. 1. " SMPLTS ,Sample time select" newline hgroup.long 0x48++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x4C++0x03 hide.long 0x00 "RB,ADC Data Result Register" in hgroup.long 0x50++0x03 hide.long 0x00 "RC,ADC Data Result Register" in hgroup.long 0x54++0x03 hide.long 0x00 "RD,ADC Data Result Register" in hgroup.long 0x58++0x03 hide.long 0x00 "RE,ADC Data Result Register" in hgroup.long 0x5C++0x03 hide.long 0x00 "RF,ADC Data Result Register" in hgroup.long 0x60++0x03 hide.long 0x00 "RG,ADC Data Result Register" in hgroup.long 0x64++0x03 hide.long 0x00 "RH,ADC Data Result Register" in hgroup.long 0x68++0x03 hide.long 0x00 "RI,ADC Data Result Register" in hgroup.long 0x6C++0x03 hide.long 0x00 "RJ,ADC Data Result Register" in hgroup.long 0x70++0x03 hide.long 0x00 "RK,ADC Data Result Register" in hgroup.long 0x74++0x03 hide.long 0x00 "RL,ADC Data Result Register" in hgroup.long 0x78++0x03 hide.long 0x00 "RM,ADC Data Result Register" in hgroup.long 0x7C++0x03 hide.long 0x00 "RN,ADC Data Result Register" in hgroup.long 0x80++0x03 hide.long 0x00 "RO,ADC Data Result Register" in hgroup.long 0x84++0x03 hide.long 0x00 "RP,ADC Data Result Register" in sif (cpu()=="MWCT1015S")||(cpu()=="MWCT1016S") hgroup.long 0x188++0x03 hide.long 0x00 "ARA,ADC Data Result Register (Alias For RA)" in hgroup.long 0x18C++0x03 hide.long 0x00 "ARB,ADC Data Result Register (Alias For RB)" in hgroup.long 0x190++0x03 hide.long 0x00 "ARC,ADC Data Result Register (Alias For RC)" in hgroup.long 0x194++0x03 hide.long 0x00 "ARD,ADC Data Result Register (Alias For RD)" in hgroup.long 0x198++0x03 hide.long 0x00 "ARE,ADC Data Result Register (Alias For RE)" in hgroup.long 0x19C++0x03 hide.long 0x00 "ARF,ADC Data Result Register (Alias For RF)" in hgroup.long 0x1A0++0x03 hide.long 0x00 "ARG,ADC Data Result Register (Alias For RG)" in hgroup.long 0x1A4++0x03 hide.long 0x00 "ARH,ADC Data Result Register (Alias For RH)" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ARI,ADC Data Result Register (Alias For RI)" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ARJ,ADC Data Result Register (Alias For RJ)" in hgroup.long 0x1B0++0x03 hide.long 0x00 "ARK,ADC Data Result Register (Alias For RK)" in hgroup.long 0x1B4++0x03 hide.long 0x00 "ARL,ADC Data Result Register (Alias For RL)" in hgroup.long 0x1B8++0x03 hide.long 0x00 "ARM,ADC Data Result Register (Alias For RM)" in hgroup.long 0x1BC++0x03 hide.long 0x00 "ARN,ADC Data Result Register (Alias For RN)" in hgroup.long 0x1C0++0x03 hide.long 0x00 "ARO,ADC Data Result Register (Alias For RO)" in hgroup.long 0x1C4++0x03 hide.long 0x00 "ARP,ADC Data Result Register (Alias For RP)" in endif newline if (((per.l(ad:0x40027000+0x90))&0x20)==0x20) group.long 0x88++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x40027000+0x90))&0x8)==0x8) group.long 0x8C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif if (((per.l(ad:0x40027000+0x90))&0xF0000)==0xF0000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,1,2,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0xE0000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,1,2,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0xD0000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,1,,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0xC0000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,1,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0xB0000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,,2,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0xA0000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,,2,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x90000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,,,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x80000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "0,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x70000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",1,2,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x60000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",1,2,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x50000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",1,,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x40000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",1,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x30000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",,2,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x20000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",,2,?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." elif (((per.l(ad:0x40027000+0x90))&0xF0000)==0x10000) group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" ",,,3" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." else group.long 0x90++0x03 line.long 0x00 "SC2,Status And Control Register 2" bitfld.long 0x00 27. " TRGSTERR3 ,Error in multiplexed trigger request 3" "No error,Error" bitfld.long 0x00 26. " TRGSTERR2 ,Error in multiplexed trigger request 2" "No error,Error" bitfld.long 0x00 25. " TRGSTERR1 ,Error in multiplexed trigger request 1" "No error,Error" bitfld.long 0x00 24. " TRGSTERR0 ,Error in multiplexed trigger request 0" "No error,Error" newline bitfld.long 0x00 19. " TRGSTLAT3 ,Trigger status 3" "Not requested,Requested" bitfld.long 0x00 18. " TRGSTLAT2 ,Trigger status 2" "Not requested,Requested" bitfld.long 0x00 17. " TRGSTLAT1 ,Trigger status 1" "Not requested,Requested" bitfld.long 0x00 16. " TRGSTLAT0 ,Trigger status 0" "Not requested,Requested" newline bitfld.long 0x00 13.--14. " TRGPRNUM ,Trigger process number" "?..." rbitfld.long 0x00 7. " ADACT ,Conversion active" "Inactive,Active" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "VREFH/VREFL,VALTH/VALTL,?..." endif group.long 0x94++0x57 line.long 0x00 "SC3,Status And Control Register 3" bitfld.long 0x00 7. " CAL ,Calibration" "No effect,Start" bitfld.long 0x00 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x00 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x04 "BASE_OFS,ADC Offset Correction Register" hexmask.long.byte 0x04 0.--7. 1. " BA_OFS ,Base offset error correction value" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "USR_OFS,ADC USER Offset Correction Register" hexmask.long.byte 0x0C 0.--7. 1. " USR_OFS ,USER offset error correction value" line.long 0x10 "XOFS,ADC X Offset Correction Register" bitfld.long 0x10 0.--5. " OFS ,Offset error correction value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "YOFS,ADC Y Offset Correction Register" hexmask.long.byte 0x14 0.--7. 1. " YOFS ,Y offset error correction value" line.long 0x18 "G,ADC Gain Register" hexmask.long.word 0x18 0.--10. 1. " G ,Gain error adjustment factor for the overall conversion" line.long 0x1C "UG,ADC User Gain Register" hexmask.long.word 0x1C 0.--9. 1. " UG ,User gain error correction value" line.long 0x20 "CLPS,ADC General Calibration Value Register S" hexmask.long.byte 0x20 0.--6. 1. " CLPS ,Calibration value" line.long 0x24 "CLP3,ADC Plus-Side General Calibration Value Register 3" hexmask.long.word 0x24 0.--9. 1. " CLP3 ,Calibration value" line.long 0x28 "CLP2,ADC Plus-Side General Calibration Value Register 2" hexmask.long.word 0x28 0.--9. 1. " CLP2 ,Calibration value" line.long 0x2C "CLP1,ADC Plus-Side General Calibration Value Register 1" hexmask.long.word 0x2C 0.--8. 1. " CLP1 ,Calibration value" line.long 0x30 "CLP0,ADC Plus-Side General Calibration Value Register 0" hexmask.long.byte 0x30 0.--7. 1. " CLP0 ,Calibration value" line.long 0x34 "CLPX,ADC Plus-Side General Calibration Value Register X" hexmask.long.byte 0x34 0.--6. 1. " CLPX ,Calibration value" line.long 0x38 "CLP9,ADC Plus-Side General Calibration Value Register 9" hexmask.long.byte 0x38 0.--6. 1. " CLP9 ,Calibration value" line.long 0x3C "CLPS_OFS,ADC General Calibration Offset Value Register S" bitfld.long 0x3C 0.--3. " CLPS_OFS ,CLPS offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "CLP3_OFS,ADC Plus-Side General Calibration Offset Value Register 3" bitfld.long 0x40 0.--3. " CLP3_OFS ,CLP3 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "CLP2_OFS,ADC Plus-Side General Calibration Offset Value Register 2" bitfld.long 0x44 0.--3. " CLP2_OFS ,CLP2 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "CLP1_OFS,ADC Plus-Side General Calibration Offset Value Register 1" bitfld.long 0x48 0.--3. " CLP1_OFS ,CLP1 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4C "CLP0_OFS,ADC Plus-Side General Calibration Offset Value Register 0" bitfld.long 0x4C 0.--3. " CLP0_OFS ,CLP0 offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x50 "CLPX_OFS,ADC Plus-Side General Calibration Offset Value Register X" hexmask.long.word 0x50 0.--11. 1. " CLPX_OFS ,CLPX offset" line.long 0x54 "CLP9_OFS,ADC Plus-Side General Calibration Offset Value Register 9" hexmask.long.word 0x54 0.--11. 1. " CLP9_OFS ,CLP9 offset" sif (cpu()=="MWCT1015S") group.long 0x148++0x03 line.long 0x00 "SC1Q,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x14C++0x03 line.long 0x00 "SC1R,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x150++0x03 line.long 0x00 "SC1S,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x154++0x03 line.long 0x00 "SC1T,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x158++0x03 line.long 0x00 "SC1U,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x15C++0x03 line.long 0x00 "SC1V,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x160++0x03 line.long 0x00 "SC1W,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x164++0x03 line.long 0x00 "SC1X,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" newline hgroup.long 0x1C8++0x03 hide.long 0x00 "RQ,ADC Data Result Register" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RR,ADC Data Result Register" in hgroup.long 0x1D0++0x03 hide.long 0x00 "RS,ADC Data Result Register" in hgroup.long 0x1D4++0x03 hide.long 0x00 "RT,ADC Data Result Register" in hgroup.long 0x1D8++0x03 hide.long 0x00 "RU,ADC Data Result Register" in hgroup.long 0x1DC++0x03 hide.long 0x00 "RV,ADC Data Result Register" in hgroup.long 0x1E0++0x03 hide.long 0x00 "RW,ADC Data Result Register" in hgroup.long 0x1E4++0x03 hide.long 0x00 "RX,ADC Data Result Register" in elif (cpu()=="MWCT1016S") group.long 0x148++0x03 line.long 0x00 "SC1Q,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x14C++0x03 line.long 0x00 "SC1R,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x150++0x03 line.long 0x00 "SC1S,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x154++0x03 line.long 0x00 "SC1T,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x158++0x03 line.long 0x00 "SC1U,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x15C++0x03 line.long 0x00 "SC1V,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x160++0x03 line.long 0x00 "SC1W,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x164++0x03 line.long 0x00 "SC1X,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x168++0x03 line.long 0x00 "SC1Y,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x16C++0x03 line.long 0x00 "SC1Z,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x170++0x03 line.long 0x00 "SC1AA,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x174++0x03 line.long 0x00 "SC1AB,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x178++0x03 line.long 0x00 "SC1AC,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x17C++0x03 line.long 0x00 "SC1AD,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x180++0x03 line.long 0x00 "SC1AE,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" group.long 0x184++0x03 line.long 0x00 "SC1AF,ADC Status And Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " ADCH ,Input channel select" "External 0,External 1,External 2,External 3,External 4,External 5,External 6,External 7,External 8,External 9,External 10,External 11,External 12,External 13,External 14,External 15,,,,,,,,,,,,Band Gap,,VREFSH,VREFSL,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Disabled" newline hgroup.long 0x1C8++0x03 hide.long 0x00 "RQ,ADC Data Result Register" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RR,ADC Data Result Register" in hgroup.long 0x1D0++0x03 hide.long 0x00 "RS,ADC Data Result Register" in hgroup.long 0x1D4++0x03 hide.long 0x00 "RT,ADC Data Result Register" in hgroup.long 0x1D8++0x03 hide.long 0x00 "RU,ADC Data Result Register" in hgroup.long 0x1DC++0x03 hide.long 0x00 "RV,ADC Data Result Register" in hgroup.long 0x1E0++0x03 hide.long 0x00 "RW,ADC Data Result Register" in hgroup.long 0x1E4++0x03 hide.long 0x00 "RX,ADC Data Result Register" in hgroup.long 0x1E8++0x03 hide.long 0x00 "RY,ADC Data Result Register" in hgroup.long 0x1EC++0x03 hide.long 0x00 "RZ,ADC Data Result Register" in hgroup.long 0x1F0++0x03 hide.long 0x00 "RAA,ADC Data Result Register" in hgroup.long 0x1F4++0x03 hide.long 0x00 "RAB,ADC Data Result Register" in hgroup.long 0x1F8++0x03 hide.long 0x00 "RAC,ADC Data Result Register" in hgroup.long 0x1FC++0x03 hide.long 0x00 "RAD,ADC Data Result Register" in hgroup.long 0x200++0x03 hide.long 0x00 "RAE,ADC Data Result Register" in hgroup.long 0x204++0x03 hide.long 0x00 "RAF,ADC Data Result Register" in endif width 0x0B tree.end tree.end tree "CMP (Comparator)" base ad:0x40073000 width 5. group.long 0x00++0x0B line.long 0x00 "C0,CMP Control Register 0" bitfld.long 0x00 30. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 28. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.long 0x00 27. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.long 0x00 26. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.long 0x00 25. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.long 0x00 24. " COUT ,Analog comparator output" "0,1" hexmask.long.byte 0x00 16.--23. 1. " FPR ,Filter sample period" bitfld.long 0x00 14.--15. " WE_SE ,Windowing/Sample enable" "None,Windowing mode,Sampling mode,?..." newline bitfld.long 0x00 12. " PMODE ,Power mode select" "Low speed,High speed" bitfld.long 0x00 11. " INVT ,Comparator invert" "Not inverted,Inverted" bitfld.long 0x00 10. " COS ,Comparator output select" "COUT,COUTA" bitfld.long 0x00 9. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " EN ,Comparator module enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Filter disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.long 0x00 2. " OFFSET ,Comparator hard block offset control" "Level 0,Level 1" bitfld.long 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.long 0x04 "C1,CMP Control Register 1" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) bitfld.long 0x04 29. " DACOE ,DAC output enable" "Disabled,Enabled" bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..." bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..." else bitfld.long 0x04 27.--28. " INPSEL ,Selection of the input to the positive port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..." bitfld.long 0x04 24.--25. " INNSEL ,Selection of the input to the negative port of the comparator" "8b DAC output IN0,Analog 8-1 mux IN1,?..." endif newline sif (cpuis("S32MTV*")) bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled" bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled" bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled" bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled" else bitfld.long 0x04 23. " CHN7 ,Channel 7 input enable" "Disabled,Enabled" bitfld.long 0x04 22. " CHN6 ,Channel 6 input enable" "Disabled,Enabled" bitfld.long 0x04 21. " CHN5 ,Channel 5 input enable" "Disabled,Enabled" bitfld.long 0x04 20. " CHN4 ,Channel 4 input enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " CHN3 ,Channel 3 input enable" "Disabled,Enabled" bitfld.long 0x04 18. " CHN2 ,Channel 2 input enable" "Disabled,Enabled" bitfld.long 0x04 17. " CHN1 ,Channel 1 input enable" "Disabled,Enabled" bitfld.long 0x04 16. " CHN0 ,Channel 0 input enable" "Disabled,Enabled" endif newline bitfld.long 0x04 15. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.long 0x04 14. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" sif (cpuis("S32MTV*")) bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,?..." bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,?..." elif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." else bitfld.long 0x04 11.--13. " PSEL ,Plus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.long 0x04 8.--10. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif newline hexmask.long.byte 0x04 0.--7. 1. " VOSEL ,DAC output voltage select" line.long 0x08 "C2,CMP Control Register 2" bitfld.long 0x08 31. " RRE ,Round-Robin enable" "Disabled,Enabled" bitfld.long 0x08 30. " RRIE ,Round-Robin interrupt enable" "Disabled,Enabled" bitfld.long 0x08 29. " FXMP ,Fixed MUX port" "Plus fixed,Minus fixed" sif (cpuis("S32MTV*")) bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,?..." newline eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed" eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed" eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed" eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed" else bitfld.long 0x08 25.--27. " FXMXCH ,Fixed channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" newline eventfld.long 0x08 23. " CH7F ,Channel 7 input changed flag" "Not changed,Changed" eventfld.long 0x08 22. " CH6F ,Channel 6 input changed flag" "Not changed,Changed" eventfld.long 0x08 21. " CH5F ,Channel 5 input changed flag" "Not changed,Changed" eventfld.long 0x08 20. " CH4F ,Channel 4 input changed flag" "Not changed,Changed" newline eventfld.long 0x08 19. " CH3F ,Channel 3 input changed flag" "Not changed,Changed" eventfld.long 0x08 18. " CH2F ,Channel 2 input changed flag" "Not changed,Changed" eventfld.long 0x08 17. " CH1F ,Channel 1 input changed flag" "Not changed,Changed" eventfld.long 0x08 16. " CH0F ,Channel 0 input changed flag" "Not changed,Changed" endif newline bitfld.long 0x08 14.--15. " NSAM ,Number of sample clocks" "Same cycle,1 cycle,2 cycles,3 cycles" bitfld.long 0x08 8.--13. " INITMOD ,Comparator and DAC initialization delay modulus" "64,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif (cpuis("S32MTV*")) bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1" bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1" bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1" bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1" else bitfld.long 0x08 7. " ACO7 ,The result of the input comparison for channel 7" "0,1" bitfld.long 0x08 6. " ACO6 ,The result of the input comparison for channel 6" "0,1" bitfld.long 0x08 5. " ACO5 ,The result of the input comparison for channel 5" "0,1" bitfld.long 0x08 4. " ACO4 ,The result of the input comparison for channel 4" "0,1" newline bitfld.long 0x08 3. " ACO3 ,The result of the input comparison for channel 3" "0,1" bitfld.long 0x08 2. " ACO2 ,The result of the input comparison for channel 2" "0,1" bitfld.long 0x08 1. " ACO1 ,The result of the input comparison for channel 1" "0,1" bitfld.long 0x08 0. " ACO0 ,The result of the input comparison for channel 0" "0,1" endif width 0x0B tree.end tree "PDB (Programmable Delay Block)" tree "PDB0" base ad:0x40036000 width 18. group.long 0x00++0x07 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,When PDB counter reaches MOD value,When input event is detected,When PDB counter reaches MOD value/Input event" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "No effect,Clear" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "Not set,Set" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "*1,*10,*20,*40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" newline line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x0B line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" line.long 0x04 "CH0C1,Channel 0 Control Register 1" bitfld.long 0x04 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x04 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x04 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x08 "CH0S,Channel 0 Status Register" sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")) bitfld.long 0x08 23. " CF[7] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 22. " [6] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 21. " [5] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 20. " [4] ,PDB channel flag" "Not matched,Matched" newline bitfld.long 0x08 19. " [3] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 18. " [2] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 17. " [1] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 16. " [0] ,PDB channel flag" "Not matched,Matched" else hexmask.long.byte 0x08 16.--23. 1. " CF ,PDB channel flags" endif newline bitfld.long 0x08 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x08 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 0. " [0] ,PDB channel sequence error flags" "No error,Error" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) group.long 0x18++0x03 line.long 0x00 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x1C++0x03 line.long 0x00 "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x18++0x03 line.long 0x00 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x1C++0x03 line.long 0x00 "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x20++0x03 line.long 0x00 "CH0DLY2,Channel 0 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x24++0x03 line.long 0x00 "CH0DLY3,Channel 0 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x28++0x03 line.long 0x00 "CH0DLY4,Channel 0 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x2C++0x03 line.long 0x00 "CH0DLY5,Channel 0 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x30++0x03 line.long 0x00 "CH0DLY6,Channel 0 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x34++0x03 line.long 0x00 "CH0DLY7,Channel 0 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC External Trigger Input Enable" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC External Trigger Input Enable" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")) group.long 0x38++0x07 line.long 0x00 "CH1C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x04 "CH1S,Channel 0 Status Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")) bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "No error,Error" bitfld.long 0x04 22. " [6] ,PDB channel flag" "No error,Error" bitfld.long 0x04 21. " [5] ,PDB channel flag" "No error,Error" bitfld.long 0x04 20. " [4] ,PDB channel flag" "No error,Error" newline bitfld.long 0x04 19. " [3] ,PDB channel flag" "No error,Error" bitfld.long 0x04 18. " [2] ,PDB channel flag" "No error,Error" bitfld.long 0x04 17. " [1] ,PDB channel flag" "No error,Error" bitfld.long 0x04 16. " [0] ,PDB channel flag" "No error,Error" else hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" endif newline bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) group.long 0x40++0x03 line.long 0x00 "CH1DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x44++0x03 line.long 0x00 "CH1DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x40++0x03 line.long 0x00 "CH1DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x44++0x03 line.long 0x00 "CH1DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x48++0x03 line.long 0x00 "CH1DLY2,Channel 0 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x4C++0x03 line.long 0x00 "CH1DLY3,Channel 0 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x50++0x03 line.long 0x00 "CH1DLY4,Channel 0 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x54++0x03 line.long 0x00 "CH1DLY5,Channel 0 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x58++0x03 line.long 0x00 "CH1DLY6,Channel 0 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x5C++0x03 line.long 0x00 "CH1DLY7,Channel 0 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif endif sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")) group.long 0x60++0x07 line.long 0x00 "CH2C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x04 "CH2S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error" group.long 0x68++0x03 line.long 0x00 "CH2DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x6C++0x03 line.long 0x00 "CH2DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x70++0x03 line.long 0x00 "CH2DLY2,Channel 0 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x74++0x03 line.long 0x00 "CH2DLY3,Channel 0 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x78++0x03 line.long 0x00 "CH2DLY4,Channel 0 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x7C++0x03 line.long 0x00 "CH2DLY5,Channel 0 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x80++0x03 line.long 0x00 "CH2DLY6,Channel 0 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x84++0x03 line.long 0x00 "CH2DLY7,Channel 0 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S")) group.long 0x88++0x07 line.long 0x00 "CH3C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x04 "CH3S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error" group.long 0x90++0x03 line.long 0x00 "CH3DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x94++0x03 line.long 0x00 "CH3DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x98++0x03 line.long 0x00 "CH3DLY2,Channel 0 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x9C++0x03 line.long 0x00 "CH3DLY3,Channel 0 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xA0++0x03 line.long 0x00 "CH3DLY4,Channel 0 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xA4++0x03 line.long 0x00 "CH3DLY5,Channel 0 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xA8++0x03 line.long 0x00 "CH3DLY6,Channel 0 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xAC++0x03 line.long 0x00 "CH3DLY7,Channel 0 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif group.long 0x190++0x07 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 7. " POEN_[7] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB Pulse-Out enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB Pulse-Out enable" "Disabled,Enabled" line.long 0x04 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x04 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1" hexmask.long.word 0x04 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2" endif width 0x0B tree.end tree "PDB1" base ad:0x40031000 width 18. group.long 0x00++0x07 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,When PDB counter reaches MOD value,When input event is detected,When PDB counter reaches MOD value/Input event" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "No effect,Clear" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "Not set,Set" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "*1,*10,*20,*40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" newline line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x0B line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" line.long 0x04 "CH0C1,Channel 1 Control Register 1" bitfld.long 0x04 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x04 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x04 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x04 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x08 "CH0S,Channel 1 Status Register" sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")) bitfld.long 0x08 23. " CF[7] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 22. " [6] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 21. " [5] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 20. " [4] ,PDB channel flag" "Not matched,Matched" newline bitfld.long 0x08 19. " [3] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 18. " [2] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 17. " [1] ,PDB channel flag" "Not matched,Matched" bitfld.long 0x08 16. " [0] ,PDB channel flag" "Not matched,Matched" else hexmask.long.byte 0x08 16.--23. 1. " CF ,PDB channel flags" endif newline bitfld.long 0x08 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x08 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x08 0. " [0] ,PDB channel sequence error flags" "No error,Error" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) group.long 0x18++0x03 line.long 0x00 "CH0DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x1C++0x03 line.long 0x00 "CH0DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x18++0x03 line.long 0x00 "CH0DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x1C++0x03 line.long 0x00 "CH0DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x20++0x03 line.long 0x00 "CH0DLY2,Channel 1 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x24++0x03 line.long 0x00 "CH0DLY3,Channel 1 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x28++0x03 line.long 0x00 "CH0DLY4,Channel 1 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x2C++0x03 line.long 0x00 "CH0DLY5,Channel 1 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x30++0x03 line.long 0x00 "CH0DLY6,Channel 1 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x34++0x03 line.long 0x00 "CH0DLY7,Channel 1 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC External Trigger Input Enable" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC External Trigger Input Enable" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")) group.long 0x38++0x07 line.long 0x00 "CH1C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x04 "CH1S,Channel 1 Status Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")) bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "No error,Error" bitfld.long 0x04 22. " [6] ,PDB channel flag" "No error,Error" bitfld.long 0x04 21. " [5] ,PDB channel flag" "No error,Error" bitfld.long 0x04 20. " [4] ,PDB channel flag" "No error,Error" newline bitfld.long 0x04 19. " [3] ,PDB channel flag" "No error,Error" bitfld.long 0x04 18. " [2] ,PDB channel flag" "No error,Error" bitfld.long 0x04 17. " [1] ,PDB channel flag" "No error,Error" bitfld.long 0x04 16. " [0] ,PDB channel flag" "No error,Error" else hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" endif newline bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) group.long 0x40++0x03 line.long 0x00 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x44++0x03 line.long 0x00 "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x40++0x03 line.long 0x00 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x44++0x03 line.long 0x00 "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x48++0x03 line.long 0x00 "CH1DLY2,Channel 1 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x4C++0x03 line.long 0x00 "CH1DLY3,Channel 1 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x50++0x03 line.long 0x00 "CH1DLY4,Channel 1 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x54++0x03 line.long 0x00 "CH1DLY5,Channel 1 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x58++0x03 line.long 0x00 "CH1DLY6,Channel 1 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x5C++0x03 line.long 0x00 "CH1DLY7,Channel 1 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif endif sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")) group.long 0x60++0x07 line.long 0x00 "CH2C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x04 "CH2S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error" group.long 0x68++0x03 line.long 0x00 "CH2DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x6C++0x03 line.long 0x00 "CH2DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x70++0x03 line.long 0x00 "CH2DLY2,Channel 1 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x74++0x03 line.long 0x00 "CH2DLY3,Channel 1 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x78++0x03 line.long 0x00 "CH2DLY4,Channel 1 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x7C++0x03 line.long 0x00 "CH2DLY5,Channel 1 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x80++0x03 line.long 0x00 "CH2DLY6,Channel 1 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x84++0x03 line.long 0x00 "CH2DLY7,Channel 1 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif sif (!cpuis("MKE14F*")&&!cpuis("MKE16F*")&&!cpuis("MKE18F*")&&!cpuis("MKE14Z*")&&!cpuis("MKE15Z*")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S")) group.long 0x88++0x07 line.long 0x00 "CH3C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB_[7] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel Pre-Trigger Back-to-Back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS_[7] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 14. " [6] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 13. " [5] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 12. " [4] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 11. " [3] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 10. " [2] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 9. " [1] ,PDB channel Pre-Trigger output select" "0,1" bitfld.long 0x00 8. " [0] ,PDB channel Pre-Trigger output select" "0,1" newline bitfld.long 0x00 7. " EN_[7] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel Pre-Trigger enable" "Disabled,Enabled" line.long 0x04 "CH3S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR_[7] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " [1] ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flags" "No error,Error" group.long 0x90++0x03 line.long 0x00 "CH3DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x94++0x03 line.long 0x00 "CH3DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x98++0x03 line.long 0x00 "CH3DLY2,Channel 1 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0x9C++0x03 line.long 0x00 "CH3DLY3,Channel 1 Delay 3 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xA0++0x03 line.long 0x00 "CH3DLY4,Channel 1 Delay 4 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xA4++0x03 line.long 0x00 "CH3DLY5,Channel 1 Delay 5 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xA8++0x03 line.long 0x00 "CH3DLY6,Channel 1 Delay 6 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" group.long 0xAC++0x03 line.long 0x00 "CH3DLY7,Channel 1 Delay 7 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" endif group.long 0x190++0x07 line.long 0x00 "POEN,Pulse-Out 1 Enable Register" bitfld.long 0x00 7. " POEN_[7] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB Pulse-Out enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB Pulse-Out enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB Pulse-Out enable" "Disabled,Enabled" line.long 0x04 "PO0DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x04 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1" hexmask.long.word 0x04 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")) group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB Pulse-Out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB Pulse-Out delay 2" endif width 0x0B tree.end tree.end tree "FTM (FlexTimer Module)" tree "FTM0" base ad:0x40038000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM0 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM0 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM0 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM0 Capture And Compare Status Register" in newline if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM0 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM0 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM0 External Trigger Register" in newline if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM0 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM0 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM0 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM0 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM0 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM0 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM0 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM0 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM0 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x40038000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40038000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40038000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40038000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif width 0x0B tree.end tree "FTM1" base ad:0x40039000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM1 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM1 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM1 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM1 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM1 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM1 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM1 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM1 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM1 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM1 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM1 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM1 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM1 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM1 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM1 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM1 Capture And Compare Status Register" in newline if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM1 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM1 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM1 External Trigger Register" in newline if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM1 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM1 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM1 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM1 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM1 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM1 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM1 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM1 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM1 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x40039000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40039000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40039000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40039000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x200++0x03 line.long 0x00 "MOD_MIRROR,Mirror Of Modulo Value" hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the modulo integer value" bitfld.long 0x00 11.--15. " FRACMOD ,Modulo fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x204++0x03 line.long 0x00 "C0V_MIRROR,Mirror Of Channel 0 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 0 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x208++0x03 line.long 0x00 "C1V_MIRROR,Mirror Of Channel 1 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 1 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20C++0x03 line.long 0x00 "C2V_MIRROR,Mirror Of Channel 2 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 2 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "C3V_MIRROR,Mirror Of Channel 3 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 3 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x214++0x03 line.long 0x00 "C4V_MIRROR,Mirror Of Channel 4 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 4 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x218++0x03 line.long 0x00 "C5V_MIRROR,Mirror Of Channel 5 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 5 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21C++0x03 line.long 0x00 "C6V_MIRROR,Mirror Of Channel 6 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 6 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x03 line.long 0x00 "C7V_MIRROR,Mirror Of Channel 7 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 7 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "FTM2" base ad:0x4003A000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM2 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM2 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM2 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM2 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM2 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM2 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM2 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM2 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM2 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM2 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM2 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM2 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM2 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM2 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM2 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM2 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM2 Capture And Compare Status Register" in newline if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM2 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM2 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM2 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM2 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM2 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM2 External Trigger Register" in newline if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM2 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM2 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM2 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM2 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM2 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM2 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM2 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM2 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM2 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM2 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM2 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x4003A000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4003A000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4003A000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4003A000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x200++0x03 line.long 0x00 "MOD_MIRROR,Mirror Of Modulo Value" hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the modulo integer value" bitfld.long 0x00 11.--15. " FRACMOD ,Modulo fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x204++0x03 line.long 0x00 "C0V_MIRROR,Mirror Of Channel 0 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 0 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x208++0x03 line.long 0x00 "C1V_MIRROR,Mirror Of Channel 1 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 1 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20C++0x03 line.long 0x00 "C2V_MIRROR,Mirror Of Channel 2 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 2 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "C3V_MIRROR,Mirror Of Channel 3 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 3 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x214++0x03 line.long 0x00 "C4V_MIRROR,Mirror Of Channel 4 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 4 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x218++0x03 line.long 0x00 "C5V_MIRROR,Mirror Of Channel 5 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 5 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21C++0x03 line.long 0x00 "C6V_MIRROR,Mirror Of Channel 6 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 6 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x03 line.long 0x00 "C7V_MIRROR,Mirror Of Channel 7 Match Value" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 7 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "FTM3" base ad:0x40026000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM3 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM3 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM3 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM3 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM3 Capture And Compare Status Register" in newline if ((per.l(ad:0x40026000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM3 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM3 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM3 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x40026000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM3 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM3 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40026000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM3 External Trigger Register" in newline if ((per.l(ad:0x40026000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM3 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM3 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM3 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x40026000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM3 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40026000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM3 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM3 Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM3 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM3 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM3 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM3 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM3 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x40026000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40026000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40026000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40026000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif width 0x0B tree.end sif !cpuis("MWCT1014S") tree "FTM4" base ad:0x4006E000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM4 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM4 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM4 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM4 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM4 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM4 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM4 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM4 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM4 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM4 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM4 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM4 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM4 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM4 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM4 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM4 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM4 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM4 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM4 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM4 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM4 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM4 Capture And Compare Status Register" in newline if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM4 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM4 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM4 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM4 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM4 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM4 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM4 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM4 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM4 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM4 External Trigger Register" in newline if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM4 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM4 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM4 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM4 Quadrature Decoder Control And Status Register" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM4 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM4 Quadrature Decoder Control And Status Register" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM4 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM4 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x4006E000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM4 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM4 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM4 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM4 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM4 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM4 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM4 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x4006E000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4006E000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4006E000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4006E000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif width 0x0B tree.end tree "FTM5" base ad:0x4006F000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM5 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM5 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM5 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM5 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM5 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM5 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM5 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM5 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM5 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM5 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM5 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM5 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM5 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM5 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM5 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM5 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM5 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM5 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM5 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM5 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM5 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM5 Capture And Compare Status Register" in newline if ((per.l(ad:0x4006F000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM5 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM5 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM5 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM5 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM5 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x4006F000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM5 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM5 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x4006F000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM5 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM5 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM5 External Trigger Register" in newline if ((per.l(ad:0x4006F000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM5 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM5 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM5 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x4006F000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM5 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x4006F000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM5 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM5 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM5 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM5 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM5 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM5 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM5 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x4006F000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4006F000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4006F000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x4006F000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif width 0x0B tree.end endif sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S") tree "FTM6" base ad:0x40070000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM6 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM6 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM6 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM6 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM6 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM6 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM6 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM6 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM6 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM6 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM6 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM6 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM6 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM6 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM6 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM6 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM6 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM6 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM6 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM6 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM6 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM6 Capture And Compare Status Register" in newline if ((per.l(ad:0x40070000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM6 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM6 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM6 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM6 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM6 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x40070000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM6 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM6 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40070000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM6 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM6 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM6 External Trigger Register" in newline if ((per.l(ad:0x40070000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM6 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM6 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM6 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x40070000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM6 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40070000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM6 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM6 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM6 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM6 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM6 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM6 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM6 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x40070000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40070000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40070000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40070000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif width 0x0B tree.end tree "FTM7" base ad:0x40071000 width 16. hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM7 Status And Control Register" in newline group.long 0x04++0x07 line.long 0x00 "CNT,FTM7 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM7 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM7 Channel 0 Status And Control Register" in newline group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM7 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" newline hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM7 Channel 1 Status And Control Register" in newline group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM7 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" newline hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM7 Channel 2 Status And Control Register" in newline group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM7 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" newline hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM7 Channel 3 Status And Control Register" in newline group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM7 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" newline hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM7 Channel 4 Status And Control Register" in newline group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM7 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" newline hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM7 Channel 5 Status And Control Register" in newline group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM7 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" newline hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM7 Channel 6 Status And Control Register" in newline group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM7 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" newline hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM7 Channel 7 Status And Control Register" in newline group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM7 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM7 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM7 counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM7 Capture And Compare Status Register" in newline if ((per.l(ad:0x40071000+0x54)&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM7 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM7 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channel enabled,Manual enabled,Autoamic enabled" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No restrictions,MOD cnv / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM7 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,FTM7 Initial State For Channels Output Register" bitfld.long 0x04 7. " CHOI[7] ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,FTM7 Output Mask Register" bitfld.long 0x08 7. " CHOM[7] ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if ((per.l(ad:0x40071000+0x54)&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM7 Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channel 6" "Input,Modified" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM7 Function For Linked Channels Register" rbitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6" "Input,Modified" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6v/c7v)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channel 4" "Input,Modified" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4v/c5v)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2" "Input,Modified" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2v/c3v)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0" "Input,Modified" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0v/c1v)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40071000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM7 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM7 Deadtime Insertion Control Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif newline hgroup.long 0x6C++0x03 hide.long 0x00 "EXTTRIG,FTM7 External Trigger Register" in newline if ((per.l(ad:0x40071000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM7 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM7 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif newline hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,FTM7 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.l(ad:0x40071000+0x54)&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe state,Tristate" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM7 Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "Counter wrap events,Reload point is reached" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/safe val forced,Stopped/frozen,Functional/functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40071000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM7 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM7 Fault Input Polarity" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x13 line.long 0x00 "SYNCONF,FTM7 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" newline bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sys clk posedge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "TRIG[1/2/3] clear,No TRIG[1/2/3] clear" line.long 0x04 "INVCTRL,FTM7 Inverting Control Register" bitfld.long 0x04 3. " INVEN[3] ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM7 Software Output Control Register" bitfld.long 0x08 15. " CHOCV[7] ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CHOC[7] ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM7 PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,LDOK" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CHSE[7] ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" line.long 0x10 "HCR,FTM7 Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. " HCVAL ,Half cycle value" if ((per.l(ad:0x40071000+0xA0)&0x04)==0x04) group.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA0++0x03 line.long 0x00 "PAIR0DEADTIME,FTM Pair 0 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40071000+0xA8)&0x04)==0x04) group.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xA8++0x03 line.long 0x00 "PAIR1DEADTIME,FTM Pair 1 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40071000+0xB0)&0x04)==0x04) group.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB0++0x03 line.long 0x00 "PAIR2DEADTIME,FTM Pair 2 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.l(ad:0x40071000+0xB8)&0x04)==0x04) group.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0xB8++0x03 line.long 0x00 "PAIR3DEADTIME,FTM Pair 3 Deadtime Configuration" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif width 0x0B tree.end endif tree.end tree "LPIT (Low Power Interrupt Timer)" base ad:0x40037000 width 22. endian.be rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " EXT_TRIG ,Number of external trigger inputs" hexmask.long.byte 0x04 0.--7. 1. " CHANNEL ,Number of timer channels" group.long 0x08++0x0B line.long 0x00 "MCR,Module Control Register" bitfld.long 0x00 3. " DBG_EN ,Debug enable bit" "Disabled,Enabled" bitfld.long 0x00 2. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " SW_RST ,Software reset bit" "No reset,Reset" bitfld.long 0x00 0. " M_CEN ,Module clock enable" "Disabled,Enabled" line.long 0x04 "MSR,Module Status Register" eventfld.long 0x04 3. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 2. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 1. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 0. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" line.long 0x08 "MIER,Module Interrupt Enable Register" bitfld.long 0x08 3. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" rgroup.long (0x20+0x04)++0x03 line.long 0x00 "CVAL0,Current Timer Value" if (((per.l.be(ad:0x40037000+0x20+0x08))&0x01)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" endif group.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" rgroup.long (0x30+0x04)++0x03 line.long 0x00 "CVAL1,Current Timer Value" if (((per.l.be(ad:0x40037000+0x30+0x08))&0x01)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" endif group.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CVAL2,Current Timer Value" if (((per.l.be(ad:0x40037000+0x40+0x08))&0x01)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" endif group.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" rgroup.long (0x50+0x04)++0x03 line.long 0x00 "CVAL3,Current Timer Value" if (((per.l.be(ad:0x40037000+0x50+0x08))&0x01)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" else group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..." bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" newline bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled" endif endian.le width 0x0B tree.end tree "LPTMR (Low Power Timer)" base ad:0x40040000 width 5. if (((per.l(ad:0x40040000))&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Disabled,Enabled" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equal,Equal" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "0,1,2,3" newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active-high/Rising-edge,Active-low/Falling-edge" bitfld.long 0x00 2. " TFC ,Timer Free-Running counter" "Reset whenever TCF is set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Disabled,Enabled" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equal,Equal" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "0,1,2,3" newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active-high/rising-edge,Active-low/falling-edge" rbitfld.long 0x00 2. " TFC ,Timer Free-Running counter" "Reset whenever TCF is set,Reset on overflow" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if (((per.l(ad:0x40040000))&0x03)==0x00) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Enabled,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "0,1,2,3" elif (((per.l(ad:0x40040000))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")) rbitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" rbitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Enabled,Bypassed" else bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Enabled,Bypassed" endif rbitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "0,1,2,3" elif (((per.l(ad:0x40040000))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Glitch filter value" "Disabled,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Enabled,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Glitch filter clock select" "0,1,2,3" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")) rbitfld.long 0x00 3.--6. " PRESCALE ,Glitch filter value" "Disabled,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" rbitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Enabled,Bypassed" else bitfld.long 0x00 3.--6. " PRESCALE ,Glitch filter value" "Disabled,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Enabled,Bypassed" endif rbitfld.long 0x00 0.--1. " PCS ,Glitch filter clock select" "0,1,2,3" endif group.long 0x08++0x07 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" line.long 0x04 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x04 0.--15. 1. " COUNTER ,Counter value" width 0x0B tree.end tree "RTC (Real Time Clock)" base ad:0x4003D000 width 5. group.long 0x00++0x0B line.long 0x00 "TSR,RTC Time Seconds Register" line.long 0x04 "TPR,RTC Time Prescaler Register" hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler register" line.long 0x08 "TAR,RTC Time Alarm Register" if (per.l(ad:0x4003D000+0x18)&0x08)==0x08 group.long 0x0C++0x03 line.long 0x00 "TCR,RTC Time Compensation Register" hexmask.long.byte 0x00 24.--31. 1. " CIC ,Compensation interval counter" hexmask.long.byte 0x00 16.--23. 1. " TCV ,Time compensation value" hexmask.long.byte 0x00 8.--15. 1. " CIR ,Compensation interval register" hexmask.long.byte 0x00 0.--7. 1. " TCR ,Time compensation register" else rgroup.long 0x0C++0x03 line.long 0x00 "TCR,RTC Time Compensation Register" hexmask.long.byte 0x00 24.--31. 1. " CIC ,Compensation interval counter" hexmask.long.byte 0x00 16.--23. 1. " TCV ,Time compensation value" hexmask.long.byte 0x00 8.--15. 1. " CIR ,Compensation interval register" hexmask.long.byte 0x00 0.--7. 1. " TCR ,Time compensation register" endif if (per.l(ad:0x4003D000+0x18)&0x10)==0x10 group.long 0x10++0x03 line.long 0x00 "CR,RTC Control Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")) bitfld.long 0x00 24.--25. " CPE ,Clock pin enable" "Disabled,Enabled,?..." newline sif cpuis("K32W0?2S1M*") bitfld.long 0x00 16.--17. " PORS ,POR Select" "128ms,64ms,32ms,Enabled" bitfld.long 0x00 15. " OSCM ,Oscillator Mode Select" "Wide range,Limited range" bitfld.long 0x00 13. " SC2P ,Oscillator 2pF Load Configure" "Disabled,Enabled" newline bitfld.long 0x00 12. " SC4P ,Oscillator 4pF Load Configure" "Disabled,Enabled" bitfld.long 0x00 11. " SC8P ,Oscillator 8pF Load Configure" "Disabled,Enabled" bitfld.long 0x00 10. " SC16P ,Oscillator 16pF Load Configure" "Disabled,Enabled" newline endif bitfld.long 0x00 9. " CLKO ,Clock output" "Allowed,Not allowed" bitfld.long 0x00 8. " OSCE ,Oscillator enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " LPOS ,LPO select" "32kHz crystal,LPO/prescaler bypassed" bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32kHz crystal" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("K32W0?2S1M*")) bitfld.long 0x00 4. " WPS ,Wakeup pin select" "Asserted,RTC 32kHz CLK" endif newline bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled" bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported" bitfld.long 0x00 1. " WPE ,Wakeup pin enable" "Disabled,Enabled" bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset" elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x00 24. " CPE ,Clock pin enable" "Disabled,Enabled" bitfld.long 0x00 9. " CLKO ,Clock output" "Allowed,Not allowed" bitfld.long 0x00 7. " LPOS ,LPO select" "32.768kHz clock,1khz LPO/prescaler bypassed" bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32.768kHz clock" newline bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled" bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported" bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset" else bitfld.long 0x00 24. " CPE ,Clock pin enable" "Disabled,Enabled" bitfld.long 0x00 7. " LPOS ,LPO select" "32kHz crystal,1khz lpo/prescaler bypassed" bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32kHz crystal" bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported" bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset" endif else rgroup.long 0x10++0x03 line.long 0x00 "CR,RTC Control Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")) bitfld.long 0x00 24.--25. " CPE ,Clock pin enable" "Disabled,Enabled,?..." newline sif cpuis("K32W0?2S1M*") bitfld.long 0x00 16.--17. " PORS ,POR Select" "128ms,64ms,32ms,Enabled" bitfld.long 0x00 15. " OSCM ,Oscillator Mode Select" "Wide range,Limited range" bitfld.long 0x00 13. " SC2P ,Oscillator 2pF Load Configure" "Disabled,Enabled" newline bitfld.long 0x00 12. " SC4P ,Oscillator 4pF Load Configure" "Disabled,Enabled" bitfld.long 0x00 11. " SC8P ,Oscillator 8pF Load Configure" "Disabled,Enabled" bitfld.long 0x00 10. " SC16P ,Oscillator 16pF Load Configure" "Disabled,Enabled" newline endif bitfld.long 0x00 9. " CLKO ,Clock output" "Allowed,Not allowed" bitfld.long 0x00 8. " OSCE ,Oscillator enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " LPOS ,LPO select" "32kHz crystal,LPO/prescaler bypassed" bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32kHz crystal" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("K32W0?2S1M*")) bitfld.long 0x00 4. " WPS ,Wakeup pin select" "Asserted,RTC 32kHz CLK" endif newline bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled" bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported" bitfld.long 0x00 1. " WPE ,Wakeup pin enable" "Disabled,Enabled" bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset" elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x00 24. " CPE ,Clock pin enable" "Disabled,Enabled" bitfld.long 0x00 9. " CLKO ,Clock output" "Allowed,Not allowed" bitfld.long 0x00 7. " LPOS ,LPO select" "32.768kHz clock,1khz LPO/prescaler bypassed" bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32.768kHz clock" newline bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled" bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported" bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset" else bitfld.long 0x00 24. " CPE ,Clock pin enable" "Disabled,Enabled" bitfld.long 0x00 7. " LPOS ,LPO select" "32kHz crystal,1khz lpo/prescaler bypassed" bitfld.long 0x00 5. " CPS ,Clock pin select" "Prescaler out,32kHz crystal" bitfld.long 0x00 3. " UM ,Update mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " SUP ,Supervisor access" "Supervisor only,Non-supervisor supported" bitfld.long 0x00 0. " SWR ,Software reset" "No effect,Reset" endif endif if (per.l(ad:0x4003D000+0x18)&0x20)==0x20 group.long 0x14++0x03 line.long 0x00 "SR,RTC Status Register" sif cpuis("K32W0?2S1M*") rbitfld.long 0x00 7. " TIDF ,The Tamper Interrupt Detect Flag" "Not asserted,Asserted" newline endif bitfld.long 0x00 4. " TCE ,Time counter enable" "Disabled,Enabled" newline sif cpuis("K32W0?2S1M*") rbitfld.long 0x00 3. " MOF ,Monotonic Overflow Flag" "Not occurred,Occurred" newline endif rbitfld.long 0x00 2. " TAF ,Time alarm flag" "Not occurred,Occurred" rbitfld.long 0x00 1. " TOF ,Time overflow flag" "No overflow,Overflow" rbitfld.long 0x00 0. " TIF ,Time invalid flag" "Valid,Invalid" else rgroup.long 0x14++0x03 line.long 0x00 "SR,RTC Status Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 7. " TIDF ,The Tamper Interrupt Detect Flag" "Not asserted,Asserted" newline endif bitfld.long 0x00 4. " TCE ,Time counter enable" "Disabled,Enabled" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x00 3. " MOF ,Monotonic Overflow Flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 2. " TAF ,Time alarm flag" "Not occurred,Occurred" bitfld.long 0x00 1. " TOF ,Time overflow flag" "No overflow,Overflow" bitfld.long 0x00 0. " TIF ,Time invalid flag" "Valid,Invalid" endif if (per.l(ad:0x4003D000+0x18)&0x40)==0x40 group.long 0x18++0x03 line.long 0x00 "LR,RTC Lock Register" bitfld.long 0x00 6. " LRL ,Lock register lock" "Locked,Unlocked" bitfld.long 0x00 5. " SRL ,Status register lock" "Locked,Unlocked" bitfld.long 0x00 4. " CRL ,Control register lock" "Locked,Unlocked" bitfld.long 0x00 3. " TCL ,Time compensation lock" "Locked,Unlocked" else rgroup.long 0x18++0x03 line.long 0x00 "LR,RTC Lock Register" bitfld.long 0x00 6. " LRL ,Lock register lock" "Locked,Unlocked" bitfld.long 0x00 5. " SRL ,Status register lock" "Locked,Unlocked" bitfld.long 0x00 4. " CRL ,Control register lock" "Locked,Unlocked" bitfld.long 0x00 3. " TCL ,Time compensation lock" "Locked,Unlocked" endif group.long 0x1C++0x03 line.long 0x00 "IER,RTC Interrupt Enable Register" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")) bitfld.long 0x00 16.--18. " TSIC ,Timer seconds interrupt configuration" "1 hz,2 hz,4 hz,8 hz,16 hz,32 hz,64 hz,128 hz" bitfld.long 0x00 7. " WPON ,Wakeup pin on" "No effect,On" bitfld.long 0x00 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 16.--18. " TSIC ,Timer seconds interrupt configuration" "1 hz,2 hz,4 hz,8 hz,16 hz,32 hz,64 hz,128 hz" bitfld.long 0x00 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end tree "LPSPI (Low Power Serial Peripheral Interface)" tree "LPSPI0" base ad:0x4002C000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" newline sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) bitfld.long 0x10 2. " HRSEL ,Host request select" ",Input trigger" newline elif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" newline else bitfld.long 0x10 2. " HRSEL ,Host request select" "LPSPI_HREQ pin,Input trigger" newline endif bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x4002C000+0x10))&0x01)==0x01) if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*") if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01) if (((per.l(ad:0x4002C000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif endif elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01) if (((per.l(ad:0x4002C000+0x10))&0x01)==0x01) rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" in newline endif else group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif sif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" else group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count" endif sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x4002C000+0x24))&0x01)==0x01) group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" else rgroup.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" endif else group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" endif wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in endif width 0x0B tree.end tree "LPSPI1" base ad:0x4002D000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" newline sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) bitfld.long 0x10 2. " HRSEL ,Host request select" ",Input trigger" newline elif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" newline else bitfld.long 0x10 2. " HRSEL ,Host request select" "LPSPI_HREQ pin,Input trigger" newline endif bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x4002D000+0x10))&0x01)==0x01) if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*") if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01) if (((per.l(ad:0x4002D000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif endif elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01) if (((per.l(ad:0x4002D000+0x10))&0x01)==0x01) rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" in newline endif else group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif sif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" else group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count" endif sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x4002D000+0x24))&0x01)==0x01) group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" else rgroup.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" endif else group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" endif wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in endif width 0x0B tree.end tree "LPSPI2" base ad:0x4002E000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" newline sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) bitfld.long 0x10 2. " HRSEL ,Host request select" ",Input trigger" newline elif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" newline else bitfld.long 0x10 2. " HRSEL ,Host request select" "LPSPI_HREQ pin,Input trigger" newline endif bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x4002E000+0x10))&0x01)==0x01) if (((per.l(ad:0x4002E000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x4002E000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*") if (((per.l(ad:0x4002E000+0x24))&0x01)==0x01) if (((per.l(ad:0x4002E000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif endif elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x4002E000+0x24))&0x01)==0x01) if (((per.l(ad:0x4002E000+0x10))&0x01)==0x01) rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" in newline endif else group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif sif cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" else group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count" endif sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W0?2S1M*")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x4002E000+0x24))&0x01)==0x01) group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" else rgroup.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" endif else group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" endif wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" sif !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S") hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in endif width 0x0B tree.end tree.end tree "LPI2C (Low Power Inter-Integrated Circuit)" tree "LPI2C0" base ad:0x40066000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "No match,Match" newline eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "No timeout,Timeout" eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" newline eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " EPF ,End packet flag" "Not end packet,End packet" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Matched only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "LPI2C_HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40066000+0x10))&0x01)==0x00) group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" newline bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" newline bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40066000+0x10))&0x01)==0x00)||(((per.l(ad:0x40066000+0x14))&0x1000000)==0x00) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif else group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x40066000+0x10))&0x01)==0x00) group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" newline bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" else group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count" endif wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit DATA[7:0],Receive (Data[7:0] + 1) bytes,Generate STOP condition,Receive and discard (Data[7:0] + 1) bytes,Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode,Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40066000+0x110))&0x01)==0x00) group.long 0x110++0x03 line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" else group.long 0x110++0x03 line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" rbitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" endif group.long 0x114++0x0B line.long 0x00 "SSR,Slave Status Register" rbitfld.long 0x00 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x00 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x00 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x00 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x00 13. " AM1F ,Address match 1 flag" "No match,Match" rbitfld.long 0x00 12. " AM0F ,Address match 0 flag" "No match,Match" eventfld.long 0x00 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x00 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x00 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x00 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x00 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x00 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x00 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x00 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x04 "SIER,Slave Interrupt Enable Register" bitfld.long 0x04 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x04 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x04 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x08 "SDER,Slave DMA Enable Register" bitfld.long 0x08 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" else group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" sif cpuis("IMX8DV*")||cpuis("K32W0?2S1M*")||cpuis("MKL28*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12") bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" newline endif bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" newline rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "No match,Match" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "No match,Match" newline eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" endif newline sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40066000+0x110))&0x01)==0x00) group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)" newline bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored" newline bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty" newline bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)" newline bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored" newline bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty" newline bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)" newline bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored" newline bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty" newline bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40066000+0x110))&0x01)==0x00) group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif newline sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("S32K1*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") hgroup.long 0x150++0x03 hide.long 0x00 "SASR,Slave Address Status Register" in newline else rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address not valid" "Valid,Invalid" hexmask.long.word 0x00 0.--10. 1. " RADDR ,Received address" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40066000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" endif else group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" endif group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x170++0x03 hide.long 0x00 "SRDR,Slave Receive Data Register" in width 0x0B tree.end sif (cpu()=="MWCT1016S") tree "LPI2C1" base ad:0x40067000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "No match,Match" newline eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "No timeout,Timeout" eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" newline eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " EPF ,End packet flag" "Not end packet,End packet" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Matched only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "LPI2C_HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40067000+0x10))&0x01)==0x00) group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" newline bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" newline bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40067000+0x10))&0x01)==0x00)||(((per.l(ad:0x40067000+0x14))&0x1000000)==0x00) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif else group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x40067000+0x10))&0x01)==0x00) group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" newline bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" else group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count" endif wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit DATA[7:0],Receive (Data[7:0] + 1) bytes,Generate STOP condition,Receive and discard (Data[7:0] + 1) bytes,Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode,Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40067000+0x110))&0x01)==0x00) group.long 0x110++0x03 line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" else group.long 0x110++0x03 line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" rbitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" endif group.long 0x114++0x0B line.long 0x00 "SSR,Slave Status Register" rbitfld.long 0x00 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x00 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x00 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x00 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x00 13. " AM1F ,Address match 1 flag" "No match,Match" rbitfld.long 0x00 12. " AM0F ,Address match 0 flag" "No match,Match" eventfld.long 0x00 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x00 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x00 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x00 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x00 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x00 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x00 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x00 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x04 "SIER,Slave Interrupt Enable Register" bitfld.long 0x04 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x04 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x04 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x08 "SDER,Slave DMA Enable Register" bitfld.long 0x08 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" else group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" sif cpuis("IMX8DV*")||cpuis("K32W0?2S1M*")||cpuis("MKL28*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12") bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" newline endif bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" newline rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "No match,Match" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "No match,Match" newline eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" endif newline sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40067000+0x110))&0x01)==0x00) group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)" newline bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored" newline bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty" newline bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)" newline bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored" newline bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty" newline bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)" newline bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored" newline bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty" newline bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40067000+0x110))&0x01)==0x00) group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif newline sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("S32K1*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") hgroup.long 0x150++0x03 hide.long 0x00 "SASR,Slave Address Status Register" in newline else rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address not valid" "Valid,Invalid" hexmask.long.word 0x00 0.--10. 1. " RADDR ,Received address" endif sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S") if (((per.l(ad:0x40067000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" endif else group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" endif group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes" wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x170++0x03 hide.long 0x00 "SRDR,Slave Receive Data Register" in width 0x0B tree.end endif tree.end tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" tree "LPUART0" base ad:0x4006A000 width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation" endif if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1,2" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x40000) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1,2" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" rbitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x80000) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" rbitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00) if (((per.b(ad:0x4006A000+0x18))&0x8)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif newline hgroup.long 0x1C++0x03 hide.long 0x00 "DATA,Data Register" in newline group.long 0x20++0x03 line.long 0x00 "MATCH,Match Address Register" hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" rbitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x4006A000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" rbitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x4006A000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x4006A000+0x28))&0x800000)==0x800000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x4006A000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--26. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " RXWATER ,Receive watermark" "0,1,2,3" bitfld.long 0x00 8.--10. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TXWATER ,Transmit watermark" "0,1,2,3" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--26. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " RXWATER ,Receive watermark" "0,1,2,3" bitfld.long 0x00 8.--10. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TXWATER ,Transmit watermark" "0,1,2,3" endif width 0x0B tree.end tree "LPUART1" base ad:0x4006B000 width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation" endif if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1,2" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x40000) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1,2" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" rbitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x80000) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" rbitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00) if (((per.b(ad:0x4006B000+0x18))&0x8)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif newline hgroup.long 0x1C++0x03 hide.long 0x00 "DATA,Data Register" in newline group.long 0x20++0x03 line.long 0x00 "MATCH,Match Address Register" hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" rbitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x4006B000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" rbitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x4006B000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x4006B000+0x28))&0x800000)==0x800000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x4006B000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--26. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " RXWATER ,Receive watermark" "0,1,2,3" bitfld.long 0x00 8.--10. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TXWATER ,Transmit watermark" "0,1,2,3" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--26. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " RXWATER ,Receive watermark" "0,1,2,3" bitfld.long 0x00 8.--10. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TXWATER ,Transmit watermark" "0,1,2,3" endif width 0x0B tree.end tree "LPUART2" base ad:0x4006C000 width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RXD in,Instead CTS in,TXD out modulation" endif if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1,2" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x40000) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1,2" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" rbitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x80000) group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" newline rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" rbitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" newline rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" newline eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00) if (((per.b(ad:0x4006C000+0x18))&0x8)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" newline rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" newline rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif newline hgroup.long 0x1C++0x03 hide.long 0x00 "DATA,Data Register" in newline group.long 0x20++0x03 line.long 0x00 "MATCH,Match Address Register" hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" rbitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x4006C000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" rbitfld.long 0x00 8.--9. " RTSWATER ,Receive RTS configuration" "0,1,2,3" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x4006C000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x4006C000+0x28))&0x800000)==0x800000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x4006C000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--26. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " RXWATER ,Receive watermark" "0,1,2,3" bitfld.long 0x00 8.--10. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TXWATER ,Transmit watermark" "0,1,2,3" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--26. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " RXWATER ,Receive watermark" "0,1,2,3" bitfld.long 0x00 8.--10. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TXWATER ,Transmit watermark" "0,1,2,3" endif width 0x0B tree.end tree.end tree "FLEXIO (Flexible I/O)" base ad:0x4005A000 width 16. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " TRIGGER ,Trigger number" hexmask.long.byte 0x04 16.--23. 1. " PIN ,Pin number" hexmask.long.byte 0x04 8.--15. 1. " TIMER ,Timer number" hexmask.long.byte 0x04 0.--7. 1. " SHIFTER ,Shifter number" group.long 0x08++0x03 line.long 0x00 "CTRL,FlexIO Control Register" bitfld.long 0x00 31. " DOZEN ,Disable FlexIO operation in doze modes" "No,Yes" bitfld.long 0x00 30. " DBGE ,Enable FlexIO operation in debug mode" "Disabled,Enabled" bitfld.long 0x00 2. " FASTACC ,Fast access" "Normal,Fast" bitfld.long 0x00 1. " SWRST ,Software reset" "Disabled,Enabled" newline bitfld.long 0x00 0. " FLEXEN ,FlexIO enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "PIN,Pin State Register" sif cpuis("IMXRT106*") hexmask.long.word 0x00 0.--15. 1. " PDI ,Pin Data Input" elif cpuis("MWCT101?S") hexmask.long.byte 0x00 0.--7. 1. " PDI ,Pin data input" endif group.long 0x10++0x0B line.long 0x00 "SHIFTSTAT,Shifter Status Register" eventfld.long 0x00 3. " SSF[3] ,Shifter status flag 3" "Cleared,Set" eventfld.long 0x00 2. " [2] ,Shifter status flag 2" "Cleared,Set" eventfld.long 0x00 1. " [1] ,Shifter status flag 1" "Cleared,Set" eventfld.long 0x00 0. " [0] ,Shifter status flag 0" "Cleared,Set" line.long 0x04 "SHIFTERR,Shifter Error Register" eventfld.long 0x04 3. " SEF[3] ,Shifter error flag 3" "Cleared,Set" eventfld.long 0x04 2. " [2] ,Shifter error flag 2" "Cleared,Set" eventfld.long 0x04 1. " [1] ,Shifter error flag 1" "Cleared,Set" eventfld.long 0x04 0. " [0] ,Shifter error flag 0" "Cleared,Set" line.long 0x08 "TIMSTAT,Timer Status Register" eventfld.long 0x08 3. " TSF[3] ,Timer status flag 3" "Cleared,Set" eventfld.long 0x08 2. " [2] ,Timer status flag 2" "Cleared,Set" eventfld.long 0x08 1. " [1] ,Timer status flag 1" "Cleared,Set" eventfld.long 0x08 0. " [0] ,Timer status flag 0" "Cleared,Set" group.long 0x20++0x0B line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable Register" bitfld.long 0x00 3. " SSIE[3] ,Shifter status 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Shifter status 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Shifter status 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Shifter status 0 interrupt enable" "Disabled,Enabled" line.long 0x04 "SHIFTEIEN,Shifter Error Interrupt Enable Register" bitfld.long 0x04 3. " SEIE[3] ,Shifter error 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Shifter error 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Shifter error 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Shifter error 0 interrupt enable" "Disabled,Enabled" line.long 0x08 "TIMIEN,Timer Interrupt Enable Register" bitfld.long 0x08 3. " TEIE[3] ,Timer status 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Timer status 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Timer status 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Timer status 0 interrupt enable" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable Register" bitfld.long 0x00 3. " SSDE[3] ,Shifter status 3 DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Shifter status 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Shifter status 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Shifter status 0 DMA enable" "Disabled,Enabled" sif !cpuis("MWCT101?S") group.long 0x40++0x03 line.long 0x00 "SHIFTSTATE,Shifter State Register" bitfld.long 0x00 0.--2. " STATE ,Current state pointer" "0,1,2,3,4,5,6,7" endif newline group.long 0x80++0x03 line.long 0x00 "SHIFTCTL0,Shifter Control 0 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" newline bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" sif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7" else bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("MWCT101?S") bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..." else bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" endif group.long 0x84++0x03 line.long 0x00 "SHIFTCTL1,Shifter Control 1 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" newline bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" sif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7" else bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("MWCT101?S") bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..." else bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" endif group.long 0x88++0x03 line.long 0x00 "SHIFTCTL2,Shifter Control 2 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" newline bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" sif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7" else bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("MWCT101?S") bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..." else bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" endif group.long 0x8C++0x03 line.long 0x00 "SHIFTCTL3,Shifter Control 3 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Timer select" "0,1,2,3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" newline bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" sif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7" else bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("MWCT101?S") bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,?..." else bitfld.long 0x00 0.--2. " SMOD ,Shifter mode" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" endif newline group.long 0x100++0x03 line.long 0x00 "SHIFTCFG0,Shifter Configuration 0 Register" sif !cpuis("MWCT101?S") bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline endif bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter n+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Stop bit 0,Stop bit 1" newline sif !cpuis("MWCT101?S") bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled for transmitter/receiver/match store,Disabled for transmitter/receiver/match store,Start bit 0,Start bit 1" else bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled/data loaded on enable,Disabled/data loaded on shift,Start bit 0,Start bit 1" endif group.long 0x104++0x03 line.long 0x00 "SHIFTCFG1,Shifter Configuration 1 Register" sif !cpuis("MWCT101?S") bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline endif bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter n+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Stop bit 0,Stop bit 1" newline sif !cpuis("MWCT101?S") bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled for transmitter/receiver/match store,Disabled for transmitter/receiver/match store,Start bit 0,Start bit 1" else bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled/data loaded on enable,Disabled/data loaded on shift,Start bit 0,Start bit 1" endif group.long 0x108++0x03 line.long 0x00 "SHIFTCFG2,Shifter Configuration 2 Register" sif !cpuis("MWCT101?S") bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline endif bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter n+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Stop bit 0,Stop bit 1" newline sif !cpuis("MWCT101?S") bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled for transmitter/receiver/match store,Disabled for transmitter/receiver/match store,Start bit 0,Start bit 1" else bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled/data loaded on enable,Disabled/data loaded on shift,Start bit 0,Start bit 1" endif group.long 0x10C++0x03 line.long 0x00 "SHIFTCFG3,Shifter Configuration 3 Register" sif !cpuis("MWCT101?S") bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline endif bitfld.long 0x00 8. " INSRC ,Input source" "Pin,Shifter n+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Stop bit 0,Stop bit 1" newline sif !cpuis("MWCT101?S") bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled for transmitter/receiver/match store,Disabled for transmitter/receiver/match store,Start bit 0,Start bit 1" else bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled/data loaded on enable,Disabled/data loaded on shift,Start bit 0,Start bit 1" endif sif cpuis("MWCT101?S") newline hgroup.long 0x200++0x03 hide.long 0x00 "SHIFTBUF0,Shifter Buffer 0 Register" in hgroup.long 0x204++0x03 hide.long 0x00 "SHIFTBUF1,Shifter Buffer 1 Register" in hgroup.long 0x208++0x03 hide.long 0x00 "SHIFTBUF2,Shifter Buffer 2 Register" in hgroup.long 0x20C++0x03 hide.long 0x00 "SHIFTBUF3,Shifter Buffer 3 Register" in newline else group.long 0x200++0x03 line.long 0x00 "SHIFTBUF0,Shifter Buffer 0 Register" group.long 0x204++0x03 line.long 0x00 "SHIFTBUF1,Shifter Buffer 1 Register" group.long 0x208++0x03 line.long 0x00 "SHIFTBUF2,Shifter Buffer 2 Register" group.long 0x20C++0x03 line.long 0x00 "SHIFTBUF3,Shifter Buffer 3 Register" endif group.long 0x280++0x03 line.long 0x00 "SHIFTBUFBIS0,Shifter Buffer 0 Bit Swapped Register" group.long 0x284++0x03 line.long 0x00 "SHIFTBUFBIS1,Shifter Buffer 1 Bit Swapped Register" group.long 0x288++0x03 line.long 0x00 "SHIFTBUFBIS2,Shifter Buffer 2 Bit Swapped Register" group.long 0x28C++0x03 line.long 0x00 "SHIFTBUFBIS3,Shifter Buffer 3 Bit Swapped Register" group.long 0x300++0x03 line.long 0x00 "SHIFTBUFBYS0,Shifter Buffer 0 Byte Swapped Register" group.long 0x304++0x03 line.long 0x00 "SHIFTBUFBYS1,Shifter Buffer 1 Byte Swapped Register" group.long 0x308++0x03 line.long 0x00 "SHIFTBUFBYS2,Shifter Buffer 2 Byte Swapped Register" group.long 0x30C++0x03 line.long 0x00 "SHIFTBUFBYS3,Shifter Buffer 3 Byte Swapped Register" group.long 0x380++0x03 line.long 0x00 "SHIFTBUFBBS0,Shifter Buffer 0 Bit Byte Swapped Register" group.long 0x384++0x03 line.long 0x00 "SHIFTBUFBBS1,Shifter Buffer 1 Bit Byte Swapped Register" group.long 0x388++0x03 line.long 0x00 "SHIFTBUFBBS2,Shifter Buffer 2 Bit Byte Swapped Register" group.long 0x38C++0x03 line.long 0x00 "SHIFTBUFBBS3,Shifter Buffer 3 Bit Byte Swapped Register" newline group.long 0x400++0x03 line.long 0x00 "TIMCTL0,Timer Control 0 Register" sif cpuis("IMXRT106*") bitfld.long 0x00 24.--28. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textfld " " elif cpuis("MWCT101?S") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3" else bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." textfld " " endif bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" newline sif cpuis("IMXRT106*") bitfld.long 0x00 8.--11. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7" textfld " " else bitfld.long 0x00 8.--12. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low" newline bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit cnt baud,Dual 8-bit cnt PWM,Single 16-bit cnt" group.long 0x404++0x03 line.long 0x00 "TIMCTL1,Timer Control 1 Register" sif cpuis("IMXRT106*") bitfld.long 0x00 24.--28. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textfld " " elif cpuis("MWCT101?S") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3" else bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." textfld " " endif bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" newline sif cpuis("IMXRT106*") bitfld.long 0x00 8.--11. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7" textfld " " else bitfld.long 0x00 8.--12. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low" newline bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit cnt baud,Dual 8-bit cnt PWM,Single 16-bit cnt" group.long 0x408++0x03 line.long 0x00 "TIMCTL2,Timer Control 2 Register" sif cpuis("IMXRT106*") bitfld.long 0x00 24.--28. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textfld " " elif cpuis("MWCT101?S") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3" else bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." textfld " " endif bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" newline sif cpuis("IMXRT106*") bitfld.long 0x00 8.--11. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7" textfld " " else bitfld.long 0x00 8.--12. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low" newline bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit cnt baud,Dual 8-bit cnt PWM,Single 16-bit cnt" group.long 0x40C++0x03 line.long 0x00 "TIMCTL3,Timer Control 3 Register" sif cpuis("IMXRT106*") bitfld.long 0x00 24.--28. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textfld " " elif cpuis("MWCT101?S") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "Pin 0,Shifter 0,Pin 1,Timer 0,Pin 2,Shifter 1,Pin 3,Timer 1,Pin 4,Shifter 2,Pin 5,Timer 2,Pin 6,Shifter 3,Pin 7,Timer 3" else bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." textfld " " endif bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain/bidirectional,Bidirectional,Output" newline sif cpuis("IMXRT106*") bitfld.long 0x00 8.--11. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MWCT101?S") bitfld.long 0x00 8.--10. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7" textfld " " else bitfld.long 0x00 8.--12. " PINSEL ,Timer pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "High,Low" newline bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit cnt baud,Dual 8-bit cnt PWM,Single 16-bit cnt" newline group.long 0x480++0x03 line.long 0x00 "TIMCFG0,Timer Configuration 0 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "Logic one when enabled not affected by timer reset,Logic zero when enabled not affected by timer reset,Logic one when enabled timer reset,Logic zero when enabled timer reset" newline bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement" "Decremented on FlexIO clk,Decremented on trigger input(timer output),Decremented on pin input,Decremented on trigger input(trigger output)" newline bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "Never reset,,Timer pin equal to timer output,Timer trigger equal to timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising or falling edge" newline bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Disabled,Disabled on timer N-1 disabled,Disabled on timer compare,Disabled on timer compare and trigger low,Disabled on pin rising or falling edge,Disabled on pin rising or falling edge provided trigger is high,Disabled on trigger falling edge,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Enabled on timer N-1 enable,Enabled on trigger high,Enabled on trigger high and pin high,Enabled on pin rising edge,Enabled on pin rising edge and trigger high,Enabled on trigger rising edge,Enabled on trigger rising of falling edge" newline bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Enabled on timer compare,Enabled on timer disabled,Enabled on timer compare and timer disabled" newline bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled" group.long 0x484++0x03 line.long 0x00 "TIMCFG1,Timer Configuration 1 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "Logic one when enabled not affected by timer reset,Logic zero when enabled not affected by timer reset,Logic one when enabled timer reset,Logic zero when enabled timer reset" newline bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement" "Decremented on FlexIO clk,Decremented on trigger input(timer output),Decremented on pin input,Decremented on trigger input(trigger output)" newline bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "Never reset,,Timer pin equal to timer output,Timer trigger equal to timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising or falling edge" newline bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Disabled,Disabled on timer N-1 disabled,Disabled on timer compare,Disabled on timer compare and trigger low,Disabled on pin rising or falling edge,Disabled on pin rising or falling edge provided trigger is high,Disabled on trigger falling edge,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Enabled on timer N-1 enable,Enabled on trigger high,Enabled on trigger high and pin high,Enabled on pin rising edge,Enabled on pin rising edge and trigger high,Enabled on trigger rising edge,Enabled on trigger rising of falling edge" newline bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Enabled on timer compare,Enabled on timer disabled,Enabled on timer compare and timer disabled" newline bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled" group.long 0x488++0x03 line.long 0x00 "TIMCFG2,Timer Configuration 2 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "Logic one when enabled not affected by timer reset,Logic zero when enabled not affected by timer reset,Logic one when enabled timer reset,Logic zero when enabled timer reset" newline bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement" "Decremented on FlexIO clk,Decremented on trigger input(timer output),Decremented on pin input,Decremented on trigger input(trigger output)" newline bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "Never reset,,Timer pin equal to timer output,Timer trigger equal to timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising or falling edge" newline bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Disabled,Disabled on timer N-1 disabled,Disabled on timer compare,Disabled on timer compare and trigger low,Disabled on pin rising or falling edge,Disabled on pin rising or falling edge provided trigger is high,Disabled on trigger falling edge,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Enabled on timer N-1 enable,Enabled on trigger high,Enabled on trigger high and pin high,Enabled on pin rising edge,Enabled on pin rising edge and trigger high,Enabled on trigger rising edge,Enabled on trigger rising of falling edge" newline bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Enabled on timer compare,Enabled on timer disabled,Enabled on timer compare and timer disabled" newline bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled" group.long 0x48C++0x03 line.long 0x00 "TIMCFG3,Timer Configuration 3 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Timer output" "Logic one when enabled not affected by timer reset,Logic zero when enabled not affected by timer reset,Logic one when enabled timer reset,Logic zero when enabled timer reset" newline bitfld.long 0x00 20.--21. " TIMDEC ,Timer decrement" "Decremented on FlexIO clk,Decremented on trigger input(timer output),Decremented on pin input,Decremented on trigger input(trigger output)" newline bitfld.long 0x00 16.--18. " TIMRST ,Timer reset" "Never reset,,Timer pin equal to timer output,Timer trigger equal to timer output,Timer pin rising edge,,Trigger rising edge,Trigger rising or falling edge" newline bitfld.long 0x00 12.--14. " TIMDIS ,Timer disable" "Disabled,Disabled on timer N-1 disabled,Disabled on timer compare,Disabled on timer compare and trigger low,Disabled on pin rising or falling edge,Disabled on pin rising or falling edge provided trigger is high,Disabled on trigger falling edge,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Timer enable" "Always enabled,Enabled on timer N-1 enable,Enabled on trigger high,Enabled on trigger high and pin high,Enabled on pin rising edge,Enabled on pin rising edge and trigger high,Enabled on trigger rising edge,Enabled on trigger rising of falling edge" newline bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,Enabled on timer compare,Enabled on timer disabled,Enabled on timer compare and timer disabled" newline bitfld.long 0x00 1. " TSTART ,Timer start bit" "Disabled,Enabled" newline group.long 0x500++0x03 line.long 0x00 "TIMCMP0,Timer Compare 0 Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value" group.long 0x504++0x03 line.long 0x00 "TIMCMP1,Timer Compare 1 Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value" group.long 0x508++0x03 line.long 0x00 "TIMCMP2,Timer Compare 2 Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value" group.long 0x50C++0x03 line.long 0x00 "TIMCMP3,Timer Compare 3 Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Timer compare value" sif !cpuis("MWCT101?S") group.long 0x680++0x03 line.long 0x00 "SHIFTBUFNBS0,Shifter Buffer 0 Nibble Byte Swapped Register" group.long 0x684++0x03 line.long 0x00 "SHIFTBUFNBS1,Shifter Buffer 1 Nibble Byte Swapped Register" group.long 0x688++0x03 line.long 0x00 "SHIFTBUFNBS2,Shifter Buffer 2 Nibble Byte Swapped Register" group.long 0x68C++0x03 line.long 0x00 "SHIFTBUFNBS3,Shifter Buffer 3 Nibble Byte Swapped Register" group.long 0x700++0x03 line.long 0x00 "SHIFTBUFHWS0,Shifter Buffer 0 Half Word Swapped Register" group.long 0x704++0x03 line.long 0x00 "SHIFTBUFHWS1,Shifter Buffer 1 Half Word Swapped Register" group.long 0x708++0x03 line.long 0x00 "SHIFTBUFHWS2,Shifter Buffer 2 Half Word Swapped Register" group.long 0x70C++0x03 line.long 0x00 "SHIFTBUFHWS3,Shifter Buffer 3 Half Word Swapped Register" group.long 0x780++0x03 line.long 0x00 "SHIFTBUFNIS0,Shifter Buffer 0 Nibble Swapped Register" group.long 0x784++0x03 line.long 0x00 "SHIFTBUFNIS1,Shifter Buffer 1 Nibble Swapped Register" group.long 0x788++0x03 line.long 0x00 "SHIFTBUFNIS2,Shifter Buffer 2 Nibble Swapped Register" group.long 0x78C++0x03 line.long 0x00 "SHIFTBUFNIS3,Shifter Buffer 3 Nibble Swapped Register" endif width 0x0B tree.end tree "FCAN (FlexCAN)" tree "FCAN0" base ad:0x40024000 width 16. if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40024000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x40024000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 14. " PNET_EN ,Pretended networking enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 14. " PNET_EN ,Pretended networking enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if (((per.l(ad:0x40024000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 14. " PNET_EN ,Pretended networking enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 14. " PNET_EN ,Pretended networking enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x40024000+0x00))&0x20000000)==0x20000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 14. " PNET_EN ,Pretended networking enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 14. " PNET_EN ,Pretended networking enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40024000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x40024000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" newline if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) if ((((per.l(ad:0x40024000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40024000+0x34))&0x10000)==0x10000)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x40024000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40024000+0x34))&0x10000)==0x00)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif else if ((((per.l(ad:0x40024000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40024000+0x34))&0x10000)==0x10000)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x40024000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40024000+0x34))&0x10000)==0x00)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif endif if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" else rgroup.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" endif newline group.long 0x1C++0x03 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit error counter" newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Message buffer 30 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Message buffer 29 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Message buffer 28 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Message buffer 27 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Message buffer 26 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Message buffer 25 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Message buffer 24 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Message buffer 23 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Message buffer 22 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Message buffer 21 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Message buffer 20 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Message buffer 19 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Message buffer 18 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Message buffer 17 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Message buffer 16 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Message buffer 15 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Message buffer 14 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Message buffer 13 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Message buffer 12 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Message buffer 11 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Message buffer 10 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Message buffer 9 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Message buffer 8 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Message buffer 7 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Message buffer 6 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Message buffer 5 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Message buffer 4 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Message buffer 3 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Message buffer 2 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Message buffer 1 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Message buffer 0 interrupt mask" "Disabled,Enabled" if (((per.l(ad:0x40024000))&0x20000000)==0x20000000) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Message buffer 30 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Message buffer 29 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Message buffer 28 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Message buffer 27 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Message buffer 26 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Message buffer 25 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Message buffer 24 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Message buffer 23 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Message buffer 22 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Message buffer 21 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Message buffer 20 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Message buffer 19 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Message buffer 18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Message buffer 17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Message buffer 16 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,RX FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,RX FIFO warning flag" "No warning,Warning" eventfld.long 0x00 5. " [5] ,Frames available in RX FIFO flag" "No frames,Frames available" newline eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Message buffer 30 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Message buffer 29 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Message buffer 28 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Message buffer 27 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Message buffer 26 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Message buffer 25 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Message buffer 24 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Message buffer 23 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Message buffer 22 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Message buffer 21 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Message buffer 20 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Message buffer 19 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Message buffer 18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Message buffer 17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Message buffer 16 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Message buffer 7 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Message buffer 6 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Message buffer 5 in RX FIFO interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Message buffer 4 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Message buffer 3 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Message buffer 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Message buffer 1 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Message buffer 0 interrupt flag" "No interrupt,Interrupt" endif newline if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." bitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." rbitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority TX mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "Not inactive,Inactive" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value" newline if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40024000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40024000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40024000))&0x300)==0x200) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif else if (((per.l(ad:0x40024000))&0x300)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40024000))&0x300)==0x100) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40024000))&0x300)==0x200) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "RXFIR,RX FIFO Information Register" in newline if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline group.long 0x880++0x03 line.long 0x00 "RXIMR0,RX Individual Mask Register 0" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR1,RX Individual Mask Register 1" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR2,RX Individual Mask Register 2" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR3,RX Individual Mask Register 3" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR4,RX Individual Mask Register 4" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR5,RX Individual Mask Register 5" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR6,RX Individual Mask Register 6" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR7,RX Individual Mask Register 7" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR8,RX Individual Mask Register 8" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR9,RX Individual Mask Register 9" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR10,RX Individual Mask Register 10" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR11,RX Individual Mask Register 11" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR12,RX Individual Mask Register 12" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR13,RX Individual Mask Register 13" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR14,RX Individual Mask Register 14" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR15,RX Individual Mask Register 15" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR16,RX Individual Mask Register 16" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR17,RX Individual Mask Register 17" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR18,RX Individual Mask Register 18" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR19,RX Individual Mask Register 19" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR20,RX Individual Mask Register 20" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR21,RX Individual Mask Register 21" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR22,RX Individual Mask Register 22" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR23,RX Individual Mask Register 23" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR24,RX Individual Mask Register 24" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR25,RX Individual Mask Register 25" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR26,RX Individual Mask Register 26" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR27,RX Individual Mask Register 27" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR28,RX Individual Mask Register 28" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR29,RX Individual Mask Register 29" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR30,RX Individual Mask Register 30" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR31,RX Individual Mask Register 31" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" newline if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0xB00++0x07 line.long 0x00 "CTRL1_PN,Pretended Networking Control 1 Register" bitfld.long 0x00 17. " WTOF_MSK ,Wake up by timeout flag mask bit" "Disabled,Enabled" bitfld.long 0x00 16. " WUMF_MSK ,Wake up by match flag mask bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,Number of messages matching the same filtering criteria" bitfld.long 0x00 4.--5. " PLFS ,Payload filtering selection" "== target value,>= target value,<= target value,Inside range" newline bitfld.long 0x00 2.--3. " IDFS ,ID filtering selection" "== target value,>= target value,<= target value,Inside range" bitfld.long 0x00 0.--1. " FCS ,Filtering combination selection" "Message ID filtering only,Message ID and payload filtering,Message ID filtering repeated,Message ID and payload filtering repeated" line.long 0x04 "CTRL2_PN,Pretended Networking Control 2 Register" hexmask.long.word 0x04 0.--15. 1. " MATCHTO ,Timeout for no message matching the filtering criteria" else group.long 0xB00++0x03 line.long 0x00 "CTRL1_PN,Pretended Networking Control 1 Register" bitfld.long 0x00 17. " WTOF_MSK ,Wake up by timeout flag mask bit" "Disabled,Enabled" bitfld.long 0x00 16. " WUMF_MSK ,Wake up by match flag mask bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " NMATCH ,Number of messages matching the same filtering criteria" rbitfld.long 0x00 4.--5. " PLFS ,Payload filtering selection" "== target value,>= target value,<= target value,Inside range" newline rbitfld.long 0x00 2.--3. " IDFS ,ID filtering selection" "== target value,>= target value,<= target value,Inside range" rbitfld.long 0x00 0.--1. " FCS ,Filtering combination selection" "Message ID filtering only,Message ID and payload filtering,Message ID filtering repeated,Message ID and payload filtering repeated" rgroup.long 0xB04++0x03 line.long 0x00 "CTRL2_PN,Pretended Networking Control 2 Register" hexmask.long.word 0x00 0.--15. 1. " MATCHTO ,Timeout for no message matching the filtering criteria" endif newline group.long 0xB08++0x03 line.long 0x00 "WU_MTC,Pretended Networking Wake Up Match Register" eventfld.long 0x00 17. " WTOF ,Wake up by timeout flag bit" "No timeout,Timeout" eventfld.long 0x00 16. " WUMF ,Wake up by match flag bit" "No wake up,Wake up" hexmask.long.byte 0x00 8.--15. 1. " MCOUNTER ,Number of matches while in pretended networking" if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0xB0C++0x03 line.long 0x00 "FLT_ID1,Pretended Networking ID Filter 1 Register" bitfld.long 0x00 30. " FLT_IDE ,ID extended filter" "Standard,Extended" bitfld.long 0x00 29. " FLT_RTR ,Remote transmission request filter" "Rejected,Accepted" hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,ID filter 1 for pretended networking filtering" else rgroup.long 0xB0C++0x03 line.long 0x00 "FLT_ID1,Pretended Networking ID Filter 1 Register" bitfld.long 0x00 30. " FLT_IDE ,ID extended filter" "Standard,Extended" bitfld.long 0x00 29. " FLT_RTR ,Remote transmission request filter" "Rejected,Accepted" hexmask.long 0x00 0.--28. 1. " FLT_ID1 ,ID filter 1 for pretended networking filtering" endif group.long 0xB10++0x03 line.long 0x00 "FLT_DLC,Pretended Networking DLC Filter Register" bitfld.long 0x00 16.--19. " FLT_DLC_LO ,Lower limit for length of data bytes filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " FLT_DLC_HI ,Upper limit for length of data bytes filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0xB14++0x13 line.long 0x00 "PL1_LO,Pretended Networking Payload Low Filter 1 Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_BYTE_0 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 0" hexmask.long.byte 0x00 16.--23. 1. " DATA_BYTE_1 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 1" hexmask.long.byte 0x00 8.--15. 1. " DATA_BYTE_2 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 2" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE_3 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 3" line.long 0x04 "PL1_HI,Pretended Networking Payload High Filter 1 Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_BYTE_4 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 4" hexmask.long.byte 0x04 16.--23. 1. " DATA_BYTE_5 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 5" hexmask.long.byte 0x04 8.--15. 1. " DATA_BYTE_6 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 6" hexmask.long.byte 0x04 0.--7. 1. " DATA_BYTE_7 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 7" line.long 0x08 "FLT_ID2_IDMASK,Pretended Networking ID Filter 2 Register / ID Mask Register" bitfld.long 0x08 30. " IDE_MSK ,ID extended mask bit" "Standard,Extended" bitfld.long 0x08 29. " RTR_MSK ,Remote transmission request mask bit" "Rejected,Accepted" hexmask.long 0x08 0.--28. 1. " FLT_ID2_IDMASK ,ID filter 2 for pretended networking filtering / ID mask bits for pretended networking ID filtering" line.long 0x0C "PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_0 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 0" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_1 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 1" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_2 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 2" hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_3 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 3" line.long 0x10 "PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 Low Order Bits / Payload High Mask Register" hexmask.long.byte 0x10 24.--31. 1. " DATA_BYTE_4 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 4" hexmask.long.byte 0x10 16.--23. 1. " DATA_BYTE_5 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 5" hexmask.long.byte 0x10 8.--15. 1. " DATA_BYTE_6 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 6" hexmask.long.byte 0x10 0.--7. 1. " DATA_BYTE_7 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 7" else rgroup.long 0xB14++0x13 line.long 0x00 "PL1_LO,Pretended Networking Payload Low Filter 1 Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_BYTE_0 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 0" hexmask.long.byte 0x00 16.--23. 1. " DATA_BYTE_1 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 1" hexmask.long.byte 0x00 8.--15. 1. " DATA_BYTE_2 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 2" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE_3 ,Payload filter 1 low order bits for pretended networking payload filtering corresponding to the data byte 3" line.long 0x04 "PL1_HI,Pretended Networking Payload High Filter 1 Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_BYTE_4 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 4" hexmask.long.byte 0x04 16.--23. 1. " DATA_BYTE_5 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 5" hexmask.long.byte 0x04 8.--15. 1. " DATA_BYTE_6 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 6" hexmask.long.byte 0x04 0.--7. 1. " DATA_BYTE_7 ,Payload filter 1 high order bits for pretended networking payload filtering corresponding to the data byte 7" line.long 0x08 "FLT_ID2_IDMASK,Pretended Networking ID Filter 2 Register / ID Mask Register" bitfld.long 0x08 30. " IDE_MSK ,ID extended mask bit" "Standard,Extended" bitfld.long 0x08 29. " RTR_MSK ,Remote transmission request mask bit" "Rejected,Accepted" hexmask.long 0x08 0.--28. 1. " FLT_ID2_IDMASK ,ID filter 2 for pretended networking filtering / ID mask bits for pretended networking ID filtering" line.long 0x0C "PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_0 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 0" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_1 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 1" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_2 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 2" hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_3 ,Payload filter 2 low order bits / payload mask low order bits for pretended networking payload filtering corresponding to the data byte 3" line.long 0x10 "PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 Low Order Bits / Payload High Mask Register" hexmask.long.byte 0x10 24.--31. 1. " DATA_BYTE_4 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 4" hexmask.long.byte 0x10 16.--23. 1. " DATA_BYTE_5 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 5" hexmask.long.byte 0x10 8.--15. 1. " DATA_BYTE_6 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 6" hexmask.long.byte 0x10 0.--7. 1. " DATA_BYTE_7 ,Payload filter 2 high order bits / payload mask high order bits for pretended networking payload filtering corresponding to the data byte 7" endif rgroup.long 0xB40++0x0F line.long 0x00 "WMB0_CS,Wake Up Message Buffer 0 Register For C/S" bitfld.long 0x00 22. " SRR ,Substitute remote request" "0,1" bitfld.long 0x00 21. " IDE ,ID extended bit" "Standard,Extended" bitfld.long 0x00 20. " RTR ,Remote transmission request bit" "Data,Remote" bitfld.long 0x00 16.--19. " DLC ,Length of data in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WMB0_ID,Wake Up Message Buffer 0 Register For ID" hexmask.long 0x04 0.--28. 1. " ID ,Received ID under pretended networking mode" line.long 0x08 "WMB0_D03,Wake Up Message Buffer 0 Register For Data 0" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Received payload corresponding to the data byte 0 under pretended networking mode" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Received payload corresponding to the data byte 1 under pretended networking mode" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Received payload corresponding to the data byte 2 under pretended networking mode" hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Received payload corresponding to the data byte 3 under pretended networking mode" line.long 0x0C "WMB0_D47,Wake Up Message Buffer 0 Register Data 4" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Received payload corresponding to the data byte 4 under pretended networking mode" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Received payload corresponding to the data byte 5 under pretended networking mode" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Received payload corresponding to the data byte 6 under pretended networking mode" hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Received payload corresponding to the data byte 7 under pretended networking mode" rgroup.long 0xB50++0x0F line.long 0x00 "WMB1_CS,Wake Up Message Buffer 1 Register For C/S" bitfld.long 0x00 22. " SRR ,Substitute remote request" "0,1" bitfld.long 0x00 21. " IDE ,ID extended bit" "Standard,Extended" bitfld.long 0x00 20. " RTR ,Remote transmission request bit" "Data,Remote" bitfld.long 0x00 16.--19. " DLC ,Length of data in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WMB1_ID,Wake Up Message Buffer 1 Register For ID" hexmask.long 0x04 0.--28. 1. " ID ,Received ID under pretended networking mode" line.long 0x08 "WMB1_D03,Wake Up Message Buffer 1 Register For Data 1" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Received payload corresponding to the data byte 0 under pretended networking mode" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Received payload corresponding to the data byte 1 under pretended networking mode" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Received payload corresponding to the data byte 2 under pretended networking mode" hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Received payload corresponding to the data byte 3 under pretended networking mode" line.long 0x0C "WMB1_D47,Wake Up Message Buffer 1 Register Data 5" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Received payload corresponding to the data byte 4 under pretended networking mode" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Received payload corresponding to the data byte 5 under pretended networking mode" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Received payload corresponding to the data byte 6 under pretended networking mode" hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Received payload corresponding to the data byte 7 under pretended networking mode" rgroup.long 0xB60++0x0F line.long 0x00 "WMB2_CS,Wake Up Message Buffer 2 Register For C/S" bitfld.long 0x00 22. " SRR ,Substitute remote request" "0,1" bitfld.long 0x00 21. " IDE ,ID extended bit" "Standard,Extended" bitfld.long 0x00 20. " RTR ,Remote transmission request bit" "Data,Remote" bitfld.long 0x00 16.--19. " DLC ,Length of data in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WMB2_ID,Wake Up Message Buffer 2 Register For ID" hexmask.long 0x04 0.--28. 1. " ID ,Received ID under pretended networking mode" line.long 0x08 "WMB2_D03,Wake Up Message Buffer 2 Register For Data 2" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Received payload corresponding to the data byte 0 under pretended networking mode" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Received payload corresponding to the data byte 1 under pretended networking mode" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Received payload corresponding to the data byte 2 under pretended networking mode" hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Received payload corresponding to the data byte 3 under pretended networking mode" line.long 0x0C "WMB2_D47,Wake Up Message Buffer 2 Register Data 6" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Received payload corresponding to the data byte 4 under pretended networking mode" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Received payload corresponding to the data byte 5 under pretended networking mode" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Received payload corresponding to the data byte 6 under pretended networking mode" hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Received payload corresponding to the data byte 7 under pretended networking mode" rgroup.long 0xB70++0x0F line.long 0x00 "WMB3_CS,Wake Up Message Buffer 3 Register For C/S" bitfld.long 0x00 22. " SRR ,Substitute remote request" "0,1" bitfld.long 0x00 21. " IDE ,ID extended bit" "Standard,Extended" bitfld.long 0x00 20. " RTR ,Remote transmission request bit" "Data,Remote" bitfld.long 0x00 16.--19. " DLC ,Length of data in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WMB3_ID,Wake Up Message Buffer 3 Register For ID" hexmask.long 0x04 0.--28. 1. " ID ,Received ID under pretended networking mode" line.long 0x08 "WMB3_D03,Wake Up Message Buffer 3 Register For Data 3" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Received payload corresponding to the data byte 0 under pretended networking mode" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Received payload corresponding to the data byte 1 under pretended networking mode" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Received payload corresponding to the data byte 2 under pretended networking mode" hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Received payload corresponding to the data byte 3 under pretended networking mode" line.long 0x0C "WMB3_D47,Wake Up Message Buffer 3 Register Data 7" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Received payload corresponding to the data byte 4 under pretended networking mode" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Received payload corresponding to the data byte 5 under pretended networking mode" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Received payload corresponding to the data byte 6 under pretended networking mode" hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Received payload corresponding to the data byte 7 under pretended networking mode" if (((per.l(ad:0x40024000+0x00))&0x50000000)==0x50000000) group.long 0xC00++0x07 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" newline bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x04 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x04 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else group.long 0xC00++0x03 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" newline bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC04++0x03 line.long 0x00 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif rgroup.long 0xC08++0x03 line.long 0x00 "FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,Extended transmitted CRC value" width 0x0B tree.end tree "FCAN1" base ad:0x40025000 sif (cpu()=="MWCT1014S") width 16. if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40025000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x40025000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if (((per.l(ad:0x40025000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x40025000+0x00))&0x20000000)==0x20000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40025000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x40025000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x10000)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x00)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif else if ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x10000)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x00)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif endif if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" else rgroup.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" endif newline group.long 0x1C++0x03 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit error counter" newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x00 15. " BUFM[15] ,Message buffer 15 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Message buffer 14 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Message buffer 13 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Message buffer 12 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Message buffer 11 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Message buffer 10 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Message buffer 9 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Message buffer 8 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Message buffer 7 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Message buffer 6 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Message buffer 5 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Message buffer 4 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Message buffer 3 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Message buffer 2 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Message buffer 1 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Message buffer 0 interrupt mask" "Disabled,Enabled" if (((per.l(ad:0x40025000))&0x20000000)==0x20000000) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 15. " BUFM[15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,RX FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,RX FIFO warning flag" "No warning,Warning" eventfld.long 0x00 5. " [5] ,Frames available in RX FIFO flag" "No frames,Frames available" newline eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 15. " BUFM[15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Message buffer 7 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Message buffer 6 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Message buffer 5 in RX FIFO interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Message buffer 4 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Message buffer 3 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Message buffer 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Message buffer 1 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Message buffer 0 interrupt flag" "No interrupt,Interrupt" endif newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." bitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." rbitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority TX mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "Not inactive,Inactive" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value" newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40025000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x200) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif else if (((per.l(ad:0x40025000))&0x300)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x100) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x200) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "RXFIR,RX FIFO Information Register" in newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline group.long 0x880++0x03 line.long 0x00 "RXIMR0,RX Individual Mask Register 0" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR1,RX Individual Mask Register 1" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR2,RX Individual Mask Register 2" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR3,RX Individual Mask Register 3" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR4,RX Individual Mask Register 4" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR5,RX Individual Mask Register 5" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR6,RX Individual Mask Register 6" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR7,RX Individual Mask Register 7" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR8,RX Individual Mask Register 8" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR9,RX Individual Mask Register 9" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR10,RX Individual Mask Register 10" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR11,RX Individual Mask Register 11" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR12,RX Individual Mask Register 12" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR13,RX Individual Mask Register 13" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR14,RX Individual Mask Register 14" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR15,RX Individual Mask Register 15" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR16,RX Individual Mask Register 16" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR17,RX Individual Mask Register 17" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR18,RX Individual Mask Register 18" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR19,RX Individual Mask Register 19" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR20,RX Individual Mask Register 20" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR21,RX Individual Mask Register 21" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR22,RX Individual Mask Register 22" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR23,RX Individual Mask Register 23" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR24,RX Individual Mask Register 24" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR25,RX Individual Mask Register 25" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR26,RX Individual Mask Register 26" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR27,RX Individual Mask Register 27" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR28,RX Individual Mask Register 28" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR29,RX Individual Mask Register 29" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR30,RX Individual Mask Register 30" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR31,RX Individual Mask Register 31" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" newline width 0x0B else width 16. if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40025000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x40025000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if (((per.l(ad:0x40025000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x40025000+0x00))&0x20000000)==0x20000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40025000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x40025000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x10000)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x00)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif else if ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x10000)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x40025000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x40025000+0x34))&0x10000)==0x00)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif endif if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" else rgroup.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" endif newline group.long 0x1C++0x03 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit error counter" newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Message buffer 30 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Message buffer 29 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Message buffer 28 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Message buffer 27 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Message buffer 26 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Message buffer 25 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Message buffer 24 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Message buffer 23 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Message buffer 22 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Message buffer 21 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Message buffer 20 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Message buffer 19 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Message buffer 18 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Message buffer 17 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Message buffer 16 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Message buffer 15 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Message buffer 14 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Message buffer 13 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Message buffer 12 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Message buffer 11 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Message buffer 10 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Message buffer 9 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Message buffer 8 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Message buffer 7 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Message buffer 6 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Message buffer 5 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Message buffer 4 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Message buffer 3 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Message buffer 2 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Message buffer 1 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Message buffer 0 interrupt mask" "Disabled,Enabled" if (((per.l(ad:0x40025000))&0x20000000)==0x20000000) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Message buffer 30 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Message buffer 29 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Message buffer 28 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Message buffer 27 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Message buffer 26 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Message buffer 25 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Message buffer 24 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Message buffer 23 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Message buffer 22 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Message buffer 21 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Message buffer 20 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Message buffer 19 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Message buffer 18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Message buffer 17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Message buffer 16 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,RX FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,RX FIFO warning flag" "No warning,Warning" eventfld.long 0x00 5. " [5] ,Frames available in RX FIFO flag" "No frames,Frames available" newline eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Message buffer 30 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Message buffer 29 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Message buffer 28 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Message buffer 27 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Message buffer 26 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Message buffer 25 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Message buffer 24 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Message buffer 23 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Message buffer 22 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Message buffer 21 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Message buffer 20 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Message buffer 19 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Message buffer 18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Message buffer 17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Message buffer 16 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Message buffer 7 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Message buffer 6 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Message buffer 5 in RX FIFO interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Message buffer 4 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Message buffer 3 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Message buffer 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Message buffer 1 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Message buffer 0 interrupt flag" "No interrupt,Interrupt" endif newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." bitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." rbitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority TX mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "Not inactive,Inactive" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value" newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x40025000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x200) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif else if (((per.l(ad:0x40025000))&0x300)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x100) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x40025000))&0x300)==0x200) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "RXFIR,RX FIFO Information Register" in newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline group.long 0x880++0x03 line.long 0x00 "RXIMR0,RX Individual Mask Register 0" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR1,RX Individual Mask Register 1" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR2,RX Individual Mask Register 2" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR3,RX Individual Mask Register 3" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR4,RX Individual Mask Register 4" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR5,RX Individual Mask Register 5" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR6,RX Individual Mask Register 6" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR7,RX Individual Mask Register 7" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR8,RX Individual Mask Register 8" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR9,RX Individual Mask Register 9" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR10,RX Individual Mask Register 10" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR11,RX Individual Mask Register 11" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR12,RX Individual Mask Register 12" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR13,RX Individual Mask Register 13" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR14,RX Individual Mask Register 14" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR15,RX Individual Mask Register 15" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR16,RX Individual Mask Register 16" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR17,RX Individual Mask Register 17" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR18,RX Individual Mask Register 18" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR19,RX Individual Mask Register 19" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR20,RX Individual Mask Register 20" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR21,RX Individual Mask Register 21" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR22,RX Individual Mask Register 22" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR23,RX Individual Mask Register 23" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR24,RX Individual Mask Register 24" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR25,RX Individual Mask Register 25" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR26,RX Individual Mask Register 26" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR27,RX Individual Mask Register 27" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR28,RX Individual Mask Register 28" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR29,RX Individual Mask Register 29" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR30,RX Individual Mask Register 30" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR31,RX Individual Mask Register 31" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" newline if (((per.l(ad:0x40025000+0x00))&0x50000000)==0x50000000) group.long 0xC00++0x07 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" newline bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x04 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x04 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else group.long 0xC00++0x03 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" newline bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC04++0x03 line.long 0x00 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif rgroup.long 0xC08++0x03 line.long 0x00 "FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,Extended transmitted CRC value" width 0x0B endif tree.end tree "FCAN2" base ad:0x4002B000 sif (cpu()=="MWCT1016S") width 16. if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x4002B000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x4002B000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if (((per.l(ad:0x4002B000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x4002B000+0x00))&0x20000000)==0x20000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x4002B000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x4002B000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x10000)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x00)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif else if ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x10000)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x00)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif endif if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" else rgroup.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" endif newline group.long 0x1C++0x03 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit error counter" newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Message buffer 30 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Message buffer 29 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Message buffer 28 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Message buffer 27 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Message buffer 26 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Message buffer 25 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Message buffer 24 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Message buffer 23 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Message buffer 22 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Message buffer 21 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Message buffer 20 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Message buffer 19 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Message buffer 18 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Message buffer 17 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Message buffer 16 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Message buffer 15 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Message buffer 14 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Message buffer 13 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Message buffer 12 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Message buffer 11 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Message buffer 10 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Message buffer 9 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Message buffer 8 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Message buffer 7 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Message buffer 6 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Message buffer 5 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Message buffer 4 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Message buffer 3 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Message buffer 2 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Message buffer 1 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Message buffer 0 interrupt mask" "Disabled,Enabled" if (((per.l(ad:0x4002B000))&0x20000000)==0x20000000) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Message buffer 30 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Message buffer 29 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Message buffer 28 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Message buffer 27 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Message buffer 26 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Message buffer 25 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Message buffer 24 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Message buffer 23 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Message buffer 22 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Message buffer 21 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Message buffer 20 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Message buffer 19 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Message buffer 18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Message buffer 17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Message buffer 16 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,RX FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,RX FIFO warning flag" "No warning,Warning" eventfld.long 0x00 5. " [5] ,Frames available in RX FIFO flag" "No frames,Frames available" newline eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUFM[31] ,Message buffer 31 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Message buffer 30 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Message buffer 29 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Message buffer 28 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Message buffer 27 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Message buffer 26 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Message buffer 25 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Message buffer 24 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Message buffer 23 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Message buffer 22 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Message buffer 21 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Message buffer 20 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Message buffer 19 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Message buffer 18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Message buffer 17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Message buffer 16 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Message buffer 7 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Message buffer 6 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Message buffer 5 in RX FIFO interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Message buffer 4 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Message buffer 3 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Message buffer 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Message buffer 1 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Message buffer 0 interrupt flag" "No interrupt,Interrupt" endif newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." bitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." rbitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority TX mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "Not inactive,Inactive" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value" newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x4002B000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x200) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif else if (((per.l(ad:0x4002B000))&0x300)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x100) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x200) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "RXFIR,RX FIFO Information Register" in newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline group.long 0x880++0x03 line.long 0x00 "RXIMR0,RX Individual Mask Register 0" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR1,RX Individual Mask Register 1" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR2,RX Individual Mask Register 2" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR3,RX Individual Mask Register 3" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR4,RX Individual Mask Register 4" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR5,RX Individual Mask Register 5" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR6,RX Individual Mask Register 6" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR7,RX Individual Mask Register 7" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR8,RX Individual Mask Register 8" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR9,RX Individual Mask Register 9" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR10,RX Individual Mask Register 10" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR11,RX Individual Mask Register 11" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR12,RX Individual Mask Register 12" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR13,RX Individual Mask Register 13" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR14,RX Individual Mask Register 14" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR15,RX Individual Mask Register 15" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR16,RX Individual Mask Register 16" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR17,RX Individual Mask Register 17" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR18,RX Individual Mask Register 18" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR19,RX Individual Mask Register 19" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR20,RX Individual Mask Register 20" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR21,RX Individual Mask Register 21" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR22,RX Individual Mask Register 22" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR23,RX Individual Mask Register 23" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR24,RX Individual Mask Register 24" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR25,RX Individual Mask Register 25" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR26,RX Individual Mask Register 26" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR27,RX Individual Mask Register 27" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR28,RX Individual Mask Register 28" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR29,RX Individual Mask Register 29" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR30,RX Individual Mask Register 30" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR31,RX Individual Mask Register 31" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0xC00++0x07 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" newline bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x04 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x04 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else group.long 0xC00++0x03 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" newline bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC04++0x03 line.long 0x00 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif rgroup.long 0xC08++0x03 line.long 0x00 "FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,Extended transmitted CRC value" width 0x0B else width 16. if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x4002B000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x4002B000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if (((per.l(ad:0x4002B000+0x00))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x4002B000+0x00))&0x20000000)==0x20000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User mode,Supervisor mode" newline rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x4002B000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if (((per.l(ad:0x4002B000+0x00))&0x80000000)==0x80000000) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Oscillator clock,Peripheral clock" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,TX warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,RX warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x10000)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x00)) group.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif else if ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x10000)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "0,1" bitfld.long 0x00 30. ",RX mailboxes global mask bit 30" "0,1" bitfld.long 0x00 28. ",RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" elif ((((per.l(ad:0x4002B000+0x34))&0x20000)==0x20000)&&(((per.l(ad:0x4002B000+0x34))&0x10000)==0x00)) rgroup.long 0x10++0x03 line.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" bitfld.long 0x00 28. " MG[28] ,RX mailboxes global mask bit 28" "0,1" bitfld.long 0x00 27. ",RX mailboxes global mask bit 27" "0,1" bitfld.long 0x00 26. ",RX mailboxes global mask bit 26" "0,1" bitfld.long 0x00 25. ",RX mailboxes global mask bit 25" "0,1" bitfld.long 0x00 24. ",RX mailboxes global mask bit 24" "0,1" bitfld.long 0x00 23. ",RX mailboxes global mask bit 23" "0,1" bitfld.long 0x00 22. ",RX mailboxes global mask bit 22" "0,1" bitfld.long 0x00 21. ",RX mailboxes global mask bit 21" "0,1" bitfld.long 0x00 20. ",RX mailboxes global mask bit 20" "0,1" bitfld.long 0x00 19. ",RX mailboxes global mask bit 19" "0,1" bitfld.long 0x00 18. ",RX mailboxes global mask bit 18" "0,1" bitfld.long 0x00 17. ",RX mailboxes global mask bit 17" "0,1" bitfld.long 0x00 16. ",RX mailboxes global mask bit 16" "0,1" bitfld.long 0x00 15. ",RX mailboxes global mask bit 15" "0,1" bitfld.long 0x00 14. ",RX mailboxes global mask bit 14" "0,1" bitfld.long 0x00 13. ",RX mailboxes global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX mailboxes global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX mailboxes global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX mailboxes global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX mailboxes global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX mailboxes global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX mailboxes global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX mailboxes global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX mailboxes global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX mailboxes global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX mailboxes global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX mailboxes global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX mailboxes global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX mailboxes global mask bit 0" "0,1" else hgroup.long 0x10++0x03 hide.long 0x00 "RXMGMASK,RX Mailboxes Global Mask Register" endif endif if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" else rgroup.long 0x14++0x07 line.long 0x00 "RX14MASK,RX 14 Mask Register" bitfld.long 0x00 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x00 30. ",RX buffer 14 mask bit 30" "0,1" bitfld.long 0x00 29. ",RX buffer 14 mask bit 29" "0,1" bitfld.long 0x00 28. ",RX buffer 14 mask bit 28" "0,1" bitfld.long 0x00 27. ",RX buffer 14 mask bit 27" "0,1" bitfld.long 0x00 26. ",RX buffer 14 mask bit 26" "0,1" bitfld.long 0x00 25. ",RX buffer 14 mask bit 25" "0,1" bitfld.long 0x00 24. ",RX buffer 14 mask bit 24" "0,1" bitfld.long 0x00 23. ",RX buffer 14 mask bit 23" "0,1" bitfld.long 0x00 22. ",RX buffer 14 mask bit 22" "0,1" bitfld.long 0x00 21. ",RX buffer 14 mask bit 21" "0,1" bitfld.long 0x00 20. ",RX buffer 14 mask bit 20" "0,1" bitfld.long 0x00 19. ",RX buffer 14 mask bit 19" "0,1" bitfld.long 0x00 18. ",RX buffer 14 mask bit 18" "0,1" bitfld.long 0x00 17. ",RX buffer 14 mask bit 17" "0,1" bitfld.long 0x00 16. ",RX buffer 14 mask bit 16" "0,1" bitfld.long 0x00 15. ",RX buffer 14 mask bit 15" "0,1" bitfld.long 0x00 14. ",RX buffer 14 mask bit 14" "0,1" bitfld.long 0x00 13. ",RX buffer 14 mask bit 13" "0,1" bitfld.long 0x00 12. ",RX buffer 14 mask bit 12" "0,1" bitfld.long 0x00 11. ",RX buffer 14 mask bit 11" "0,1" bitfld.long 0x00 10. ",RX buffer 14 mask bit 10" "0,1" bitfld.long 0x00 9. ",RX buffer 14 mask bit 9" "0,1" bitfld.long 0x00 8. ",RX buffer 14 mask bit 8" "0,1" bitfld.long 0x00 7. ",RX buffer 14 mask bit 7" "0,1" bitfld.long 0x00 6. ",RX buffer 14 mask bit 6" "0,1" bitfld.long 0x00 5. ",RX buffer 14 mask bit 5" "0,1" bitfld.long 0x00 4. ",RX buffer 14 mask bit 4" "0,1" bitfld.long 0x00 3. ",RX buffer 14 mask bit 3" "0,1" bitfld.long 0x00 2. ",RX buffer 14 mask bit 2" "0,1" bitfld.long 0x00 1. ",RX buffer 14 mask bit 1" "0,1" bitfld.long 0x00 0. ",RX buffer 14 mask bit 0" "0,1" line.long 0x04 "RX15MASK,RX 15 Mask Register" bitfld.long 0x04 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x04 30. ",RX buffer 15 mask bit 30" "0,1" bitfld.long 0x04 29. ",RX buffer 15 mask bit 29" "0,1" bitfld.long 0x04 28. ",RX buffer 15 mask bit 28" "0,1" bitfld.long 0x04 27. ",RX buffer 15 mask bit 27" "0,1" bitfld.long 0x04 26. ",RX buffer 15 mask bit 26" "0,1" bitfld.long 0x04 25. ",RX buffer 15 mask bit 25" "0,1" bitfld.long 0x04 24. ",RX buffer 15 mask bit 24" "0,1" bitfld.long 0x04 23. ",RX buffer 15 mask bit 23" "0,1" bitfld.long 0x04 22. ",RX buffer 15 mask bit 22" "0,1" bitfld.long 0x04 21. ",RX buffer 15 mask bit 21" "0,1" bitfld.long 0x04 20. ",RX buffer 15 mask bit 20" "0,1" bitfld.long 0x04 19. ",RX buffer 15 mask bit 19" "0,1" bitfld.long 0x04 18. ",RX buffer 15 mask bit 18" "0,1" bitfld.long 0x04 17. ",RX buffer 15 mask bit 17" "0,1" bitfld.long 0x04 16. ",RX buffer 15 mask bit 16" "0,1" bitfld.long 0x04 15. ",RX buffer 15 mask bit 15" "0,1" bitfld.long 0x04 14. ",RX buffer 15 mask bit 14" "0,1" bitfld.long 0x04 13. ",RX buffer 15 mask bit 13" "0,1" bitfld.long 0x04 12. ",RX buffer 15 mask bit 12" "0,1" bitfld.long 0x04 11. ",RX buffer 15 mask bit 11" "0,1" bitfld.long 0x04 10. ",RX buffer 15 mask bit 10" "0,1" bitfld.long 0x04 9. ",RX buffer 15 mask bit 9" "0,1" bitfld.long 0x04 8. ",RX buffer 15 mask bit 8" "0,1" bitfld.long 0x04 7. ",RX buffer 15 mask bit 7" "0,1" bitfld.long 0x04 6. ",RX buffer 15 mask bit 6" "0,1" bitfld.long 0x04 5. ",RX buffer 15 mask bit 5" "0,1" bitfld.long 0x04 4. ",RX buffer 15 mask bit 4" "0,1" bitfld.long 0x04 3. ",RX buffer 15 mask bit 3" "0,1" bitfld.long 0x04 2. ",RX buffer 15 mask bit 2" "0,1" bitfld.long 0x04 1. ",RX buffer 15 mask bit 1" "0,1" bitfld.long 0x04 0. ",RX buffer 15 mask bit 0" "0,1" endif newline group.long 0x1C++0x03 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x00 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ,Transmit error counter" newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x00 15. " BUFM[15] ,Message buffer 15 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Message buffer 14 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Message buffer 13 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Message buffer 12 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Message buffer 11 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Message buffer 10 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Message buffer 9 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Message buffer 8 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Message buffer 7 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Message buffer 6 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Message buffer 5 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Message buffer 4 interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Message buffer 3 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Message buffer 2 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Message buffer 1 interrupt mask" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Message buffer 0 interrupt mask" "Disabled,Enabled" if (((per.l(ad:0x4002B000))&0x20000000)==0x20000000) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 15. " BUFM[15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,RX FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,RX FIFO warning flag" "No warning,Warning" eventfld.long 0x00 5. " [5] ,Frames available in RX FIFO flag" "No frames,Frames available" newline eventfld.long 0x00 0. " [0] ,Clear FIFO" "No effect,Clear" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 15. " BUFM[15] ,Message buffer 15 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " [14] ,Message buffer 14 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Message buffer 13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Message buffer 12 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Message buffer 11 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Message buffer 10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Message buffer 9 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Message buffer 8 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Message buffer 7 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Message buffer 6 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Message buffer 5 in RX FIFO interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Message buffer 4 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Message buffer 3 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Message buffer 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Message buffer 1 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Message buffer 0 interrupt flag" "No interrupt,Interrupt" endif newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." bitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,?..." rbitfld.long 0x00 19.--23. " TASD ,TX arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RX FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,?..." newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority TX mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "Not inactive,Inactive" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,Transmitted CRC value" newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x4002B000))&0x300)==0x00) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x100) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x200) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif else if (((per.l(ad:0x4002B000))&0x300)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 28" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 27" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 26" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 25" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 24" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 23" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 22" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 21" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 20" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 19" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 18" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 17" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 16" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 15" "0,1" bitfld.long 0x00 15. ",RX FIFO global mask bit 14" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x100) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 30. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 29. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 23. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " RTR ,RTR field mask" "Not checked,Checked" bitfld.long 0x00 14. " IDE ,IDE field mask" "Not checked,Checked" bitfld.long 0x00 13. " FGM ,RX FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 12" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 8" "0,1" bitfld.long 0x00 7. ",RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" elif (((per.l(ad:0x4002B000))&0x300)==0x200) rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 30. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 29. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 28. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 27. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 26. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 25. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 24. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 23. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 22. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 21. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 20. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 19. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 18. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 17. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 16. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 15. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 14. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 13. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 12. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 11. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 10. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 9. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 8. ",RX FIFO global mask bit 0" "0,1" newline bitfld.long 0x00 7. " FGM ,RX FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. ",RX FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. ",RX FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. ",RX FIFO global mask bit 4" "0,1" bitfld.long 0x00 3. ",RX FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. ",RX FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. ",RX FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. ",RX FIFO global mask bit 0" "0,1" else hgroup.long 0x48++0x03 hide.long 0x00 "RXFGMASK,RX FIFO Global Mask Register" endif endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "RXFIR,RX FIFO Information Register" in newline if (((per.l(ad:0x4002B000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif newline group.long 0x880++0x03 line.long 0x00 "RXIMR0,RX Individual Mask Register 0" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR1,RX Individual Mask Register 1" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR2,RX Individual Mask Register 2" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR3,RX Individual Mask Register 3" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR4,RX Individual Mask Register 4" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR5,RX Individual Mask Register 5" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR6,RX Individual Mask Register 6" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR7,RX Individual Mask Register 7" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR8,RX Individual Mask Register 8" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR9,RX Individual Mask Register 9" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR10,RX Individual Mask Register 10" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR11,RX Individual Mask Register 11" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR12,RX Individual Mask Register 12" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR13,RX Individual Mask Register 13" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR14,RX Individual Mask Register 14" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR15,RX Individual Mask Register 15" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR16,RX Individual Mask Register 16" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR17,RX Individual Mask Register 17" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR18,RX Individual Mask Register 18" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR19,RX Individual Mask Register 19" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR20,RX Individual Mask Register 20" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR21,RX Individual Mask Register 21" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR22,RX Individual Mask Register 22" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR23,RX Individual Mask Register 23" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR24,RX Individual Mask Register 24" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR25,RX Individual Mask Register 25" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR26,RX Individual Mask Register 26" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR27,RX Individual Mask Register 27" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR28,RX Individual Mask Register 28" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR29,RX Individual Mask Register 29" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR30,RX Individual Mask Register 30" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" group.long 0x880++0x03 line.long 0x00 "RXIMR31,RX Individual Mask Register 31" bitfld.long 0x00 31. " MI ,Individual mask bit 31" "0,1" bitfld.long 0x00 30. ",Individual mask bit 30" "0,1" bitfld.long 0x00 29. ",Individual mask bit 29" "0,1" bitfld.long 0x00 28. ",Individual mask bit 28" "0,1" bitfld.long 0x00 27. ",Individual mask bit 27" "0,1" bitfld.long 0x00 26. ",Individual mask bit 26" "0,1" bitfld.long 0x00 25. ",Individual mask bit 25" "0,1" bitfld.long 0x00 24. ",Individual mask bit 24" "0,1" bitfld.long 0x00 23. ",Individual mask bit 23" "0,1" bitfld.long 0x00 22. ",Individual mask bit 22" "0,1" bitfld.long 0x00 21. ",Individual mask bit 21" "0,1" bitfld.long 0x00 20. ",Individual mask bit 20" "0,1" bitfld.long 0x00 19. ",Individual mask bit 19" "0,1" bitfld.long 0x00 18. ",Individual mask bit 18" "0,1" bitfld.long 0x00 17. ",Individual mask bit 17" "0,1" bitfld.long 0x00 16. ",Individual mask bit 16" "0,1" bitfld.long 0x00 15. ",Individual mask bit 15" "0,1" bitfld.long 0x00 14. ",Individual mask bit 14" "0,1" bitfld.long 0x00 13. ",Individual mask bit 13" "0,1" bitfld.long 0x00 12. ",Individual mask bit 12" "0,1" bitfld.long 0x00 11. ",Individual mask bit 11" "0,1" bitfld.long 0x00 10. ",Individual mask bit 10" "0,1" bitfld.long 0x00 9. ",Individual mask bit 9" "0,1" bitfld.long 0x00 8. ",Individual mask bit 8" "0,1" bitfld.long 0x00 7. ",Individual mask bit 7" "0,1" bitfld.long 0x00 6. ",Individual mask bit 6" "0,1" bitfld.long 0x00 5. ",Individual mask bit 5" "0,1" bitfld.long 0x00 4. ",Individual mask bit 4" "0,1" bitfld.long 0x00 3. ",Individual mask bit 3" "0,1" bitfld.long 0x00 2. ",Individual mask bit 2" "0,1" bitfld.long 0x00 1. ",Individual mask bit 1" "0,1" bitfld.long 0x00 0. ",Individual mask bit 0" "0,1" newline width 0x0B endif tree.end tree.end newline