; --------------------------------------------------------------------------------
; @Title: PXA300 On-Chip Peripherals
; @Props: Released
; @Author: WRD
; @Changelog: 2007-01-09 WRD
; @Manufacturer: MARVELL - Marvell, Inc.
; @Core: Xscale
; @Chip: PXA300
; @Chiplist: MONAHANS, MONAHANS-L, MONAHANS-LV, MONAHANS-P, PXA290, PXA300,
;   PXA301, PXA302, PXA303, PXA310, PXA311, PXA312, PXA320, PXA322, PXA930,
;   PXA935, PXA940, PXA950
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permanzano.per 6547 2015-11-26 09:19:35Z askoncej $

config 16. 8.
width 8.
; --------------------------------------------------------------------------------
; CP15 for Manzano core
; --------------------------------------------------------------------------------
tree "CP15"
; --------------------------------------------------------------------------------
; *** Intel IXP2350 ***
; --------------------------------------------------------------------------------
if (d.l(c15:0x0)&0xffffe3f0)==0x69056200
group c15:0x0--0x0
line.long 0x0 "ID,ID Register (read only)"
bitfld.long  0x0 24.--24.    "Trademark ,Implementation Trademark" "Intel,Intel"
bitfld.long  0x0 16.--18.    "  Arch    ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
textline "                 "
bitfld.long  0x0 13.--15.    "CoreGen   ,Core Generation" "0,1,2,Manzano,4,5,6,7"
bitfld.long  0x0 10.--12.    " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
textline "                 "
bitfld.long  0x0  4.--4.     "ProdNum   ,Product Number" "IXP2350,IXP2350"
bitfld.long  0x0  0.--3.     "  ProdRev ,Product Revision" "A,res,res,res,res,res,res,res,res,?..."
; --------------------------------------------------------------------------------
; *** Intel PXA290, Marvell PXA320 ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69056020
group c15:0x0--0x0
line.long 0x0 "ID,ID Register (read only)"
bitfld.long  0x0 24.--24.    "Trademark ,Implementation Trademark" "Intel,Intel"
bitfld.long  0x0 16.--18.    "  Arch    ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
textline "                 "
bitfld.long  0x0 13.--15.    "CoreGen   ,Core Generation" "0,1,2,Manzano,4,5,6,7"
bitfld.long  0x0 10.--12.    " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
textline "                 "
bitfld.long  0x0  4.--4.     "ProdNum   ,Product Number" "PXA290/320,PXA290/320"
bitfld.long  0x0  0.--3.     "  ProdRev ,Product Revision" "A-0,A-1,res,res,B-0,res,res,res,res,?..."
; --------------------------------------------------------------------------------
; *** Intel/Marvell Tavor ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69056030
group c15:0x0--0x0
line.long 0x0 "ID,ID Register (read only)"
bitfld.long  0x0 24.--24.    "Trademark ,Implementation Trademark" "Intel,Intel"
bitfld.long  0x0 16.--18.    "  Arch    ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
textline "                 "
bitfld.long  0x0 13.--15.    "CoreGen   ,Core Generation" "0,1,2,Manzano,4,5,6,7"
bitfld.long  0x0 10.--12.    " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
textline "                 "
bitfld.long  0x0  4.--4.     "ProdNum   ,Product Number" "Tavor,Tavor"
bitfld.long  0x0  0.--3.     "  ProdRev ,Product Revision" "res,res,res,res,A-0,res,res,res,res,?..."
; --------------------------------------------------------------------------------
; *** other Intel XScale Manzano Core ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe000)==0x69056000
group c15:0x0--0x0
line.long 0x0 "ID,ID Register (read only)"
bitfld.long  0x0 24.--24.    "Trademark ,Implementation Trademark" "Intel,Intel"
bitfld.long  0x0 16.--18.    "  Arch    ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
textline "                 "
bitfld.long  0x0 13.--15.    "CoreGen   ,Core Generation" "0,1,2,Manzano,4,5,6,7"
bitfld.long  0x0 10.--12.    " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
textline "                 "
hexmask.long 0x0  4.--9.  1. "ProdNum   ,Product Number"
hexmask.long 0x0  0.--3.  1. "  ProdRev ,Product Revision"
; --------------------------------------------------------------------------------
; *** other Intel XScale V5TE ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffff0000)==0x69050000
group c15:0x0--0x0
line.long 0x0 "ID,ID Register (read only)"
bitfld.long  0x0 24.--24.    "Trademark ,Implementation Trademark" "Intel,Intel"
bitfld.long  0x0 16.--23.    "     Arch    ,Architecture Version" ",V4,V4T,V5,V5T,V5TE,?..."
textline "                 "
bitfld.long  0x0 13.--15.    "CoreGen   ,Core Generation" "0,1,2,Manzano,4,5,6,7"
bitfld.long  0x0 10.--12.    " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
textline "                 "
hexmask.long 0x0  4.--9.  1. "ProdNum   ,Product Number"
hexmask.long 0x0  0.--3.  1. "  ProdRev ,Product Revision"
; --------------------------------------------------------------------------------
; *** any else ***
; --------------------------------------------------------------------------------
else
group c15:0x0--0x0
line.long 0x0 "ID,ID Register (read only)"
; 0x41 = ARM, 0x44 = Digital, 0x69 = Intel
hexmask.long  0x0 24.--31. 1. "Implementor  ,Implementation Trademark"
hexmask.long  0x0 20.--23. 1. " Variant ,Implementation defined variant number"
textline "                 "
hexmask.long  0x0 16.--19. 1. "Architecture ,Architecture Version Code"
hexmask.long  0x0 13.--15. 1. " Primary part number ,Core Generation"
textline "                 "
hexmask.long  0x0  0.--3.  1. "Revision     ,Product Revision"
endif
; --------------------------------------------------------------------------------
group c15:0x100--0x100
line.long 0x0 "L1TYPE,L1 Cache Type Register"
bitfld.long 0x0 25.--28. "CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
bitfld.long 0x0 24.      "    H    ,Cache Havardness" "no,yes"
textline "                 "
bitfld.long 0x0 18.--20. "DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k"
bitfld.long 0x0 15.--17. "  DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
bitfld.long 0x0 12.--13. "  DLENGTH ,Data Cache Line Length" "2,4,8,16"
textline "                 "
bitfld.long 0x0 6.--8. "ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k"
bitfld.long 0x0 3.--5. "  IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
bitfld.long 0x0 0.--1. "  ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
group c15:0x1000--0x1000
line.long 0x0 "L2ID,L2 System ID"
hexmask.long  0x0 24.--31. 1. "Trademark ,Implementation Trademark"
group c15:0x1100--0x1100
line.long 0x0 "L2TYPE,L2 Cache Type Register"
bitfld.long 0x0 25.--28. "CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
bitfld.long 0x0 20.--23. " Way Size ,L2 Unified Cache Way Size" "res,res,32k,64k,res,res,res,res,res,?..."
bitfld.long 0x0 15.--19. " Associativity ,L2 Unified Cache Associativity" "not present,res,res,res,res,res,res,res,8-way,?..."
bitfld.long 0x0 12.--13. " Line Length ,L2 Unified Cache Line Length" "32b,res,res,res"
textline "                 "
bitfld.long 0x0  8.--11. "Way Size ,L2 Unified Cache Way Size" "res,res,32k,64k,res,res,res,res,res,?..."
bitfld.long 0x0  3.--7.  " Associativity ,L2 Unified Cache Associativity" "not present,res,res,res,res,res,res,res,8-way,?..."
bitfld.long 0x0  0.--1.  " Line Length ,L2 Unified Cache Line Length" "32b,res,res,res"
group c15:0x1--0x1
line.long 0x0 "CR,Control Register"
bitfld.long 0x0 26. "L2 ,L2 Unified Cache Enable" "disable,enable"
bitfld.long 0x0 13. " V ,Exception Vector Relocation" "0x00000000,0xffff0000"
bitfld.long 0x0 12. " I ,Instruction Cache" "disable,enable"
bitfld.long 0x0 11. " Z ,Branch Target Buffer" "disable,enable"
bitfld.long 0x0 9.  " R ,ROM Protection" "off,on"
bitfld.long 0x0 8.  " S ,System Protection" "off,on"
textline "                 "
bitfld.long 0x0 7.  "B ,Endianism" "little,big"
bitfld.long 0x0 2.  "      C ,Data Cache" "disable,enable"
bitfld.long 0x0 1.  "  A ,Alignment Fault" "disable,enable"
bitfld.long 0x0 0.  "  M ,Memory Management Unit" "disable,enable"
group c15:0x101--0x101
line.long 0x0 "AuxCR,Auxiliary Control Register"
bitfld.long 0x0 10.--11. "OC ,LLR Outer Cache Attributes" "non-cacheable,write back - write allocate,res,res"
bitfld.long 0x0  4.--5.  " IC ,LLR Inner (Data) Cache Attributes" "write back - read allocate,write back - read allocate,write through - read allocate,write back - read allocate"
bitfld.long 0x0  1.      "  P ,Page Table Memory Attribute" "0,1"
group c15:0x2--0x2
line.long 0x0 "TTB,Translation Table Base Register"
hexmask.long 0x0 14.--31. 0x4000 "TTBA ,Translation Table Base Address"
bitfld.long  0x0  3.--4.  " OC ,Table Walk Outer Cache Attributes" "non-cacheable,res,non-cacheable,write back"
bitfld.long  0x0  2.      " P ,Table Walk Memory Attribute" "0,1"
group c15:0x3--0x3
line.long 0x0 "DAC,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15 ,Domain Access 15" "no access,client,reserved,manager"
bitfld.long 0x0 28.--29. "  D14 ,Domain Access 14" "no access,client,reserved,manager"
bitfld.long 0x0 26.--27. "  D13 ,Domain Access 13" "no access,client,reserved,manager"
bitfld.long 0x0 24.--25. "  D12 ,Domain Access 12" "no access,client,reserved,manager"
textline "                 "
bitfld.long 0x0 22.--23. "D11 ,Domain Access 11" "no access,client,reserved,manager"
bitfld.long 0x0 20.--21. "  D10 ,Domain Access 10" "no access,client,reserved,manager"
bitfld.long 0x0 18.--19. "  D9  ,Domain Access 9" "no access,client,reserved,manager"
bitfld.long 0x0 16.--17. "  D8  ,Domain Access 8" "no access,client,reserved,manager"
textline "                 "
bitfld.long 0x0 14.--15. "D7  ,Domain Access 7" "no access,client,reserved,manager"
bitfld.long 0x0 12.--13. "  D6  ,Domain Access 6" "no access,client,reserved,manager"
bitfld.long 0x0 10.--11. "  D5  ,Domain Access 5" "no access,client,reserved,manager"
bitfld.long 0x0 8.--9. "  D4  ,Domain Access 4" "no access,client,reserved,manager"
textline "                 "
bitfld.long 0x0 6.--7. "D3  ,Domain Access 3" "no access,client,reserved,manager"
bitfld.long 0x0 4.--5. "  D2  ,Domain Access 2" "no access,client,reserved,manager"
bitfld.long 0x0 2.--3. "  D1  ,Domain Access 1" "no access,client,reserved,manager"
bitfld.long 0x0 0.--1. "  D0  ,Domain Access 0" "no access,client,reserved,manager"
group c15:0x5--0x5
line.long 0x0 "FSR,Fault Status Register"
bitfld.long 0x0 10.    "X ,Status Field Extension" "0,1"
bitfld.long 0x0 9.     "  D ,Debug event" "no,yes"
bitfld.long 0x0 4.--7. "  Domain ,Domain for Data Abort" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0.--3. "  Status ,Status X=0/X=1" "reserved/IMMU Exception,alignment/reserved,reserved,alignment/reserved,reserved/lock abort,transl_sect/reserved,reserved/external,transl_page,reserved/cache parity,domain_sect/reserved,reserved,domain_page,trans_lev_1/reserved,permission_sect/reserved,trans_lev_2/reserved,permission_page"
group c15:0x6--0x6
line.long 0x0 "FAR,Fault Address Registerr"
group c15:0x29--0x29
line.long 0x0 "DCLR, Data Cache Lock Register"
bitfld.long 0x0 0. "L ,Data Cache Lock Register" "no locking,fill with lock"
group c15:0xd--0xd
line.long 0x0 "PID,Process Identifier"
hexmask.long 0x0 25.--31. 0x2000000 "PID  ,Process Identifier"
group c15:0x8e--0x8e
line.long 0x0 "IBCR0,Inctruction Breakpoint Register 0"
hexmask.long 0x0 1.--31. 2. "MVA  ,Instruction Breakpoint MVA"
bitfld.long  0x0 0.         "  E ,Breakpoint Enable" "disable,enable"
group c15:0x9e--0x9e
line.long 0x0 "IBCR1,Inctruction Breakpoint Register 1"
hexmask.long 0x0 1.--31. 2. "MVA  ,Instruction Breakpoint MVA"
bitfld.long  0x0 0.         "  E ,Breakpoint Enable" "disable,enable"
group c15:0x0e--0x0e
line.long 0x0 "DBR0,Data Breakpoint Register 0"
group c15:0x3e--0x3e
line.long 0x0 "DBR1,Data Breakpoint Register 1"
group c15:0x4e--0x4e
line.long 0x0 "DBCON,Data Breakpoint Configuration Register"
bitfld.long 0x0 8.     "M ,DBR1 Mode" "Data Breakpoint Address,Data Address Mask"
bitfld.long 0x0 2.--3. " E1 ,DBR1 Breakpoint Enable" "disable,enable store,enable load/store,enable load"
bitfld.long 0x0 0.--1. " E0 ,DBR0 Enable" "disable,enable store,enable load/store,enable load"
; --------------------------------------------------------------------------------
; *** Intel 80200 ***
; --------------------------------------------------------------------------------
if (d.l(c15:0x0)&0xffffe3f0)==0x69052000
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0 13. "CP13 ,Coprocessor Access Rights" "denied,allowed"
bitfld.long 0x0  0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** Intel 80321 (IOP321) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0 13. "CP13 ,Coprocessor Access Rights" "denied,allowed"
bitfld.long 0x0  7. " CP7 ,Coprocessor Access Rights" "denied,allowed"
bitfld.long 0x0  6. " CP6 ,Coprocessor Access Rights" "denied,allowed"
bitfld.long 0x0  0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** Intel PXA210, PXA250 (Sabinal, Cotulla) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  7. "CP7 ,Coprocessor Access Rights" "denied,allowed"
bitfld.long 0x0  0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** Intel (Bulverde) ***
; --------------------------------------------------------------------------------
; wrong Product ID in developer's manual revision 0.1 (ID of PXA250!!!)
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** Intel (Manitoba) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** Intel IXP2400, IXP2800 (Sausolito, Castine) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffff41a0)==0x69052120
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  7. "CP7 ,Coprocessor Access Rights" "denied,allowed"
bitfld.long 0x0  0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** other Intel XScale V5TE ***
; *** includes XScale IXP425, because no product ID is available now ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe000)==0x69054000
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** other Intel XScale V5TE ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe000)==0x69052000
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
; *** any else ***
; --------------------------------------------------------------------------------
else
group c15:0x1f--0x1f
line.long 0x0 "CPAR,Coprocessor Access Register"
bitfld.long 0x0  0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
; --------------------------------------------------------------------------------
endif
tree.end
; --------------------------------------------------------------------------------
; IXP2325, IXP2350
; --------------------------------------------------------------------------------
tree "CP14"
group c14:0x10++0x00 "Performance Monitoring"
line.long 4.*0x00 "PMNC, Performance Monitor control Register"
bitfld.long 4.*0x00 20.--27. "EvtCnt1 ,Source of Events that PMN1 counts" "IC miss ext,IC no inst,Data stall,ITLB miss,DTLB miss,Branch,Branch mispr,Inst exec,DC full every,DC full once,DC acc,DC miss,DC wback,SW changed PC,res,res,BCU requ,BCU que full,BCU que drain,res,unlogged ECC,BCU 1-bit err,RMW,?..."
bitfld.long 4.*0x00 12.--19. " EvtCnt0 ,Source of Events that PMN0 counts" "IC miss ext,IC no inst,Data stall,ITLB miss,DTLB miss,Branch,Branch mispr,Inst exec,DC full every,DC full once,DC acc,DC miss,DC wback,SW changed PC,res,res,BCU requ,BCU que full,BCU que drain,res,unlogged ECC,BCU 1-bit err,RMW,?..."
textline "                 "
bitfld.long 4.*0x00 10.      "CCNT-OV ,Clock Counter Overflow Flag" "no,yes"
bitfld.long 4.*0x00  9.      "     PMN1-OV ,Performace Counter 1 Overflow Flag" "no,yes"
bitfld.long 4.*0x00  8.      "     PMN0-OV ,Performace Counter 0 Overflow Flag" "no,yes"
textline "                 "
bitfld.long 4.*0x00  6.      "CCNT-IE ,Clock Counter Interrupt" "disable,enable"
bitfld.long 4.*0x00  5.      " PMN1-IE ,Performace Counter 1 Interrupt" "disable,enable"
bitfld.long 4.*0x00  4.      " PMN0-IE ,Performace Counter 0 Interrupt" "disable,enable"
textline "                 "
bitfld.long 4.*0x00  3.      "D ,Clock Count Divider" "1,64"
bitfld.long 4.*0x00  2.      " C ,Clock Counter Reset" "no action,reset to 0"
bitfld.long 4.*0x00  1.      " P ,Performace Counter Reset (both)" "no action,reset to 0"
bitfld.long 4.*0x00  0.      " E ,Enable all 3 Counters" "disable,enable"
group c14:0x11++0x00
line.long 4.*0x00 "CCNT, 32-bit clock counter"
group c14:0x14++0x00
line.long 4.*0x00 "INTEN, 32-bit clock counter"
group c14:0x15++0x00
line.long 4.*0x00 "FLAG, 32-bit clock counter"
group c14:0x18++0x00
line.long 4.*0x00 "EVTSEL, 32-bit clock counter"
group c14:0x20++0x03
line.long 4.*0x00 "PMN0, 32-bit event counter"
line.long 4.*0x01 "PMN1, 32-bit event counter"
line.long 4.*0x02 "PMN2, 32-bit event counter"
line.long 4.*0x03 "PMN3, 32-bit event counter"
; --------------------------------------------------------------------------------
; *** Intel 80200 ***
; --------------------------------------------------------------------------------
if (d.l(c15:0x0)&0xffffe3f0)==0x69052000
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
bitfld.long 4.*0x00 0.--3. "CCLKCFG ,Core Clock Configuration" "res,3,4,5,6,7,8,9,res,?..."
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,IDLE,res,SLEEP"
; --------------------------------------------------------------------------------
; *** Intel 80321 or IOP321 (Verde) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
; --------------------------------------------------------------------------------
; *** Intel PXA210, PXA250 (Sabinal, Cotulla) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
bitfld.long 4.*0x00 1.--1. "FCS ,Frequency Change Sequence" "do not enter,enter"
bitfld.long 4.*0x00 0.--0. " TURBO ,Turbo Mode" "exit,enter"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "Run/Turbo,Idle,res,Sleep/Deep Sleep"
; --------------------------------------------------------------------------------
; *** Intel (Bulverde) ***
; --------------------------------------------------------------------------------
; wrong Product ID in developer's manual revision 0.1 (ID of PXA250!!!)
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
; --------------------------------------------------------------------------------
; *** Intel IXP2400, IXP2800 (Sausolito, Castine) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffffe3f0)==0x690541a0
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
; --------------------------------------------------------------------------------
; *** Intel (Manitoba) ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
; --------------------------------------------------------------------------------
; *** other Intel XScale V5TE ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe000)==0x69052000
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
; --------------------------------------------------------------------------------
; *** other Intel XScale V5TE ***
; *** includes XScale IXP425 ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xffffe000)==0x69054000
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
; --------------------------------------------------------------------------------
; *** Intel XScale PXA300 ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xfffffff0)==0x69056880
group c14:0x06--0x06 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
bitfld.long 0x00 1. " F ,Core Ferquency Change" "Not changed,Changed"
bitfld.long 0x00 0. "  T ,Turbo Mode" "Not changed,Changed"
group c14:0x07--0x07
line.long 4.*0x00 "PWRMODE,Power Management Register"
bitfld.long 0x00 0.--2. " M ,Mode" "S0/D0/C0,S0/D0/C1,S0/D1/C2,S0/D2/C2,Reserved,D0CS,S2/D3/C4,S3/D4/C4"
; --------------------------------------------------------------------------------
; *** Intel XScale PXA310 ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xfffffff0)==0x69056890
group c14:0x06--0x06 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
bitfld.long 0x00 1. " F ,Core Ferquency Change" "Not changed,Changed"
bitfld.long 0x00 0. "  T ,Turbo Mode" "Not changed,Changed"
group c14:0x07--0x07
line.long 4.*0x00 "PWRMODE,Power Management Register"
bitfld.long 0x00 0.--2. " M ,Mode" "S0/D0/C0,S0/D0/C1,S0/D1/C2,S0/D2/C2,Reserved,D0CS,S2/D3/C4,S3/D4/C4"
; --------------------------------------------------------------------------------
; *** Intel XScale PXA320 ***
; --------------------------------------------------------------------------------
elif (d.l(c15:0x0)&0xfffffffe)==0x69056824
group c14:0x06--0x06 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
bitfld.long 0x00 1. " F ,Core Ferquency Change" "Not changed,Changed"
bitfld.long 0x00 0. "  T ,Turbo Mode" "Not changed,Changed"
group c14:0x07--0x07
line.long 4.*0x00 "PWRMODE,Power Management Register"
bitfld.long 0x00 0.--2. " M ,Mode" "S0/D0/C0,S0/D0/C1,S0/D1/C2,S0/D2/C2,Reserved,D0CS,S2/D3/C4,S3/D4/C4"
; --------------------------------------------------------------------------------
; *** any other XScale ***
; --------------------------------------------------------------------------------
else
group c14:0x06--0x07 "Clock and Power Management"
line.long 4.*0x00 "CCLKCFG,Core Clock Configuration Register"
line.long 4.*0x01 "PWRMODE,Power Management Register"
bitfld.long 4.*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
endif
group c14:0x08--0x0d "Software Debug"
line.long 4.*0x02 "DCSR,Debug Control and Status Register"
bitfld.long 4.*0x02 31.     "GE ,Global Enable" "disable,enable"
bitfld.long 4.*0x02 30.     " H ,Halt Mode" "Monitor Mode,Halt Mode"
textline "                 "
bitfld.long 4.*0x02 23.     "TF ,Trap FIQ" "disable,enable"
bitfld.long 4.*0x02 22.     " TI ,Trap IRQ" "disable,enable"
bitfld.long 4.*0x02 20.     " TD ,Trap Data Abort" "disable,enable"
textline "                 "
bitfld.long 4.*0x02 19.     "TA ,Trap Prefetch Abort" "disable,enable"
bitfld.long 4.*0x02 18.     " TS ,Trap Software Interrupt" "disable,enable"
bitfld.long 4.*0x02 17.     " TU ,Trap Undefined Instruction" "disable,enable"
bitfld.long 4.*0x02 16.     " TR ,Trap Reset" "disable,enable"
textline "                 "
bitfld.long 4.*0x02  5.     "SA ,Sticky Abort" "no,yes"
bitfld.long 4.*0x02  2.--4. " MOE ,Method of Entry" "Reset,Inst Bkpt, Data Bkpt, BKPT Inst, Ext Debug Event, Vector Trap, Trace Buffer full, reserved"
bitfld.long 4.*0x02  1.     " M ,Trace Buffer Mode" "wrap around,fill-once"
bitfld.long 4.*0x02  0.     " E ,Trace Buffer Enable" "no,yes"
line.long 4.*0x04 "CHKPT0,Checkpoint 0 Register"
line.long 4.*0x05 "CHKPT1,Checkpoint 1 Register"
tree.end